MAX17036GTL+ [MAXIM]
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers; 1/2/ 3相Quick -PWM IMVP- 6.5 VID控制器
| 型号： | MAX17036GTL+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers |
| 文件： | 总38页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4577; Rev 0; 4/09
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
General Description
Features
o Triple/Dual-Phase Quick-PWM Controllers
o 2 Internal Drivers + 1 External Driver
The MAX17030/MAX17036 are 3/2-phase interleaved
Quick-PWM™ step-down VID power-supply controllers
for IMVP-6.5 notebook CPUs. Two integrated drivers and
the option to drive a third phase using an external driver
such as the MAX8791 allow for a flexible 3/2-phase con-
figuration depending on the CPU being supported.
o ±±0.5 ꢀ
Accuracy Over Line, Load, and
OUT
Temperature
o 7-Bit IMꢀP-60. DAC
o Dynamic Phase Selection Optimizes Active/Sleep
True out-of-phase operation reduces input ripple-current
requirements and output-voltage ripple while easing
component selection and layout difficulties. The Quick-
PWM control provides instantaneous response to fast
load-current steps. Active voltage positioning reduces
power dissipation and bulk output capacitance require-
ments and allows ideal positioning compensation for tan-
talum, polymer, or ceramic bulk output capacitors.
Efficiency
o Transient Phase Overlap Reduces Output
Capacitance
o Transient Suppression Feature (MAX17±36 Only)
o Integrated Boost Switches
o Active ꢀoltage Positioning with Adjustable Gain
o Accurate Lossless Current Balance and
The MAX17030/MAX17036 are intended for bucking
down the battery directly to create the core voltage.
The single-stage conversion method allows this device
to directly step down high-voltage batteries for the
highest possible efficiency.
Current Limit
o Remote Output and Ground Sense
o Adjustable Output Slew-Rate Control
o Power-Good (IMꢀPOK), Clock Enable (CLKEN),
and Thermal-Fault (VRHOT) Outputs
A slew-rate controller allows controlled transitions
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. An
output current monitor provides an analog current out-
put proportional to the sum of the inductor currents,
which in steady state is the same as the current con-
sumed by the CPU.
o IMꢀP-60. Power Sequencing and Timing
Compliant
o Output Current Monitor (IMON)
o Drives Large Synchronous Rectifier FETs
o 7ꢀ to 26ꢀ Battery Input Range
o Adjustable Switching Frequency (6±±kHz max)
Applications
o Undervoltage, Overvoltage, and Thermal-Fault
IMVP-6.5 SV and XE Core Power Supplies
Protection
High-Current Voltage-Positioned Step-Down
Converters
Pin Configuration
3 to 4 Li+ Cells Battery to CPU Core Supply
Converters
TOP VIEW
30 29 28 27 26 25 24 23 22 21
Notebooks/Desktops/Servers
20 PWM3
31
32
33
34
35
36
37
38
PGD_IN
D0
19
18
DRSKP
Ordering Information
D1
PWRGD
17 CLKEN
D2
D3
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
16
15
14
13
12
11
TON
MAX17030GTL+
MAX17036GTL+
MAX17030
MAX17036
D4
D5
PSI
DPRSLPVR
SHDN
CSP2
+Denotes a lead-free(Pb)/RoHS-compliant package.
*EP = Exposed pad.
D6
39
40
+
CSP1
CSN1
CSN2
1
2
3
4
5
6
7
8
9
10
THIN QFN
.mm x .mm
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www0maxim-ic0com0
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
, V
to GND .....................................................-0.3V to +6V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
CC DD
D0–D6, PGD_IN, PSI, DPRSLPVR to GND...............-0.3V to +6V
CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V
PWRGD, CLKEN, VR_HOT to GND..........................-0.3V to +6V
DH1 to LX1 ..............................................-0.3V to (V
DH2 to LX2 ..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
BST1
BST2
FB, FBAC, IMON, TIME to GND .................-0.3V to (V
+ 0.3V)
Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN)
Up to +70°C ..............................................................1778mW
Derating above +70°C ..........................................22.2mW/°C
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
SHDN to GND (Note 2)...........................................-0.3V to +30V
TON to GND ...........................................................-0.3V to +30V
GNDS to GND .......................................................-0.3V to +0.3V
DL1, DL2, PWM3, DRSKP to GND .............-0.3V to (V
BST1, BST2 to GND ...............................................-0.3V to +36V
+ 0.3V)
DD
BST1, BST2 to V .................................................-0.3V to +30V
DD
Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit.
Note 2: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal
BST switches are disabled as well. Use external BST diodes when SHDN is forced to 12V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
/MAX17036
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
CSN_
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
IN
CC
DD
1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = ±°C to +8.°C, unless otherwise noted.
FBAC
A
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
V
V
, V
4.5
7
5.5
26
CC DD
Input Voltage Range
V
IN
DAC codes from
0.8125V to 1.5000V
Measured at FB
with respect to
GNDS;
includes load-
regulation error
(Note 3)
-0.5
-7
+0.5
+7
%
DAC codes from
0.3750V to 0.8000V
FB Output Voltage Accuracy
V
FB
mV
DAC codes from
0 to 0.3625V
-20
+20
Boot Voltage
V
A
1.094
1.100
0.1
1.106
V
%
BOOT
Line Regulation Error
FB Input Bias Current
GNDS Input Range
GNDS Gain
V
= 4.5V to 5.5V, V = 4.5V to 26V
IN
CC
T
A
= +25°C
-0.1
-200
0.97
-0.5
+0.1
+200
1.03
µA
mV
V/V
µA
V
ꢀV
/ꢀV
GNDS
1.00
GNDS
GNDS
OUT
GNDS Input Bias Current
TIME Regulation Voltage
I
T
A
= +25°C
+0.5
2.015
+10
V
R
R
= 147kꢁ
1.985
-10
2.000
TIME
TIME
TIME
= 147kꢁ (6.08mV/µs nominal)
R
= 35.7kꢁ (25mV/µs nominal) to
TIME
-15
+15
178kꢁ (5mV/µs nominal)
TIME Slew-Rate Accuracy
%
Soft-start and soft-shutdown:
R
TIME
= 35.7kꢁ (6.25mV/µs nominal) to
-20
+20
178kꢁ (1.25mV/µs nominal)
2
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
CSN_
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
IN
CC
DD
1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = ±°C to +8.°C, unless otherwise noted.
FBAC
A
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= 96.75kꢀ (600kHz
MIN
TYP
MAX
UNITS
R
TON
V
V
= 10V,
= 1.0V,
-15
+15
IN
per phase), 167ns nominal
FB
measured at
DH1, DH2,
and PWM3
(Note 4)
R
= 200kꢀ (300kHz
TON
On-Time Accuracy
t
%
-10
-15
+10
ON
per phase), 333ns nominal
R
TON
= 303.25kꢀ (200kHz
+15
375
0.1
per phase), 500ns nominal
Minimum Off-Time
t
Measured at DH1, DH2, and PWM3 (Note 4)
300
ns
OFF(MIN)
SHDN = GND, V = 26V, V = V = 0
IN
CC
DD
TON Shutdown Input Current
BIAS CURRENTS
I
0.01
µA
TON,SDN
or 5V, T = +25°C
A
Measured at V , V
forced above the regulation point
= 5V, FB
CC DPRSLPVR
Quiescent Supply Current (V
)
I
I
3.5
7
1
mA
µA
CC
CC
Measured at V , V = 0, FB forced
DD DPRSLPVR
Quiescent Supply Current (V
)
0.02
DD
DD
above the regulation point, T = +25°C
A
Shutdown Supply Current (V
Shutdown Supply Current (V
FAULT PROTECTION
)
I
I
Measured at V , SHDN = GND, T = +25°C
0.01
0.01
1
1
µA
µA
CC
CC,SDN
CC
A
)
DD
Measured at V , SHDN = GND, T = +25°C
DD A
DD,SDN
Skip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250
300
350
mV
V
Output Overvoltage-Protection
Threshold
V
OVP
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45
1.50
1.55
Minimum OVP threshold; measured at FB
0.8
10
Output Overvoltage-
Propagation Delay
t
FB forced 25mV above trip threshold
µs
mV
µs
OVP
Output Undervoltage-
Protection Threshold
Measured at FB with respect to the voltage
target set by the VID code (see Table 4)
V
-450
20
-400
10
-350
100
UVP
Output Undervoltage-
Propagation Delay
t
FB forced 25mV below trip threshold
UVP
CLKEN Startup Delay and
Boot Time Period
Measured from the time when FB reaches
the boot target voltage (Note 3)
t
60
µs
BOOT
_______________________________________________________________________________________
3
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
CSN_
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
IN
CC
DD
1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = ±°C to +8.°C, unless otherwise noted.
FBAC
A
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured at startup from the time when
CLKEN goes low
PWRGD Startup Delay
3
6.5
10
ms
Lower threshold,
falling edge
(undervoltage)
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4), 20mV
hysteresis (typ)
-350
-300
-250
CLKEN and PWRGD Threshold
mV
Upper threshold,
rising edge
(overvoltage)
+150
+200
+250
FB forced 25mV outside the PWRGD trip
thresholds
CLKEN and PWRGD Delay
10
20
µs
µs
V
CLKEN and PWRGD Transition
Blanking Time (VID Transitions)
Measured from the time when FB reaches
the target voltage (Note 3)
t
BLANK
CLKEN, PWRGD Output
Low Voltage
Low state, I
= 3mA
0.4
1
SINK
/MAX17036
CLKEN, PWRGD Leakage
Current
High-Z state, pin forced to 5V, T = +25°C
µA
ꢀ
A
CSN1 Pulldown Resistance in
UVLO and Shutdown
SHDN = GND, measured after soft-
shutdown completed (DL = low)
8
V
Undervoltage-Lockout
Rising edge, 65mV typical hysteresis,
controller disabled below this level
CC
V
4.05
29
4.27
4.48
31
V
UVLO(VCC)
Threshold
THERMAL PROTECTION
Measured at THRM with respect to V
;
CC
VRHOT Trip Threshold
VRHOT Delay
30
%
falling edge, typical hysteresis = 75mV
THRM forced 25mV below the VRHOT trip
threshold, falling edge
t
10
2
µs
VRHOT
VRHOT Output On-Resistance
VRHOT Leakage Current
THRM Input Leakage
R
Low state
8
1
ꢀ
ON(VRHOT)
High-Z state, VRHOT forced to 5V, T = +25°C
µA
µA
°C
A
I
V
THRM
= 0 to 5V, T = +25°C
-0.1
+0.1
THRM
A
Thermal-Shutdown Threshold
T
Typical hysteresis = 15°C
+160
SHDN
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR
V
V
- V
- V
= 100mV
= 500mV
7
10
50
13
55
25
TIME
TIME
ILIM
ILIM
CC
Current-Limit Threshold Voltage
(Positive)
V
V
- V
mV
45
20
LIMIT
CSP_
CSN_
CSN_
ILIM = V
22.5
Current-Limit Threshold Voltage
(Negative) Accuracy
V
V
V
- V
, nominally -125% of V
LIMIT
-4
0
+4
mV
mV
V
LIMIT(NEG)
CSP_
Current-Limit Threshold Voltage
(Zero Crossing)
V
- V , V
= 5V
0
ZX
GND
LX_ DPRSLPVR
CSP_, CSN_ Common-Mode
Input Range
2
4
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
CSN_
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
IN
CC
DD
1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = 0°C to +85°C, unless otherwise noted.
FBAC
A
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
1
-
V
0.4
-
CC
Phases 2, 3 Disable Threshold
Measured at CSP2, CSP3
3
V
CSP_, CSN_ Input Current
ILIM Input Current
I
, I
T
T
= +25°C
= +25°C
-0.2
-0.1
+0.2
+0.1
μA
μA
CSP CSN
A
I
ILIM
A
(1/N) x ꢀ(V
-
CSP_
FBAC
V ) at I
CSN_
= 0;
T
T
= +25°C
-0.5
+0.5
A
ꢀ indicates
mV/
phase
summation over all
power-up enabled
phases from 1 to N,
N = 3
Droop Amplifier Offset
= 0°C to +85°C
-0.75
+0.75
A
ꢀI
FBAC
/ꢀ[ꢀ(V
- V )];
CSN_
CSP_
Droop Amplifier
Transconductance
ꢀ indicates summation over all power-up
enabled phases from 1 to N, N = 3,
G
393
-1.1
400
406
+1
μS
m(FBAC)
V
FBAC
= V
= 0.45V to 1.5V
CSN_
(1/N) x ꢀ(V
- V ) at I
CSN_
= 0,
IMON
CSP_
mV/
phase
ꢀ indicates summation over all power-up
enabled phases from 1 to N, N = 3
Current-Monitor Offset
ꢀI
/ꢀ[ꢀ(V
- V )];
CSN_
IMON
CSP_
Current-Monitor
Transconductance
ꢀ indicates summation over all power-up
enabled phases from 1 to N, N = 3,
G
1.552
1.6
1.648
mS
m(IMON)
V
CSN_
= 0.45V to 1.5V
GATE DRIVERS
High state (pullup)
Low state (pulldown)
High state (pullup)
Low state (pulldown)
0.9
0.7
2.5
2
BST_ - LX_ forced
to 5V
DH_ Gate-Driver On-Resistance
R
R
ꢁ
ꢁ
A
A
ON(DH)
0.7
2
DL_ Gate-Driver On-Resistance
DH_ Gate-Driver Source Current
DH_ Gate-Driver Sink Current
ON(DL)
0.25
0.7
DH_ forced to 2.5V,
I
2.2
2.7
DH(SOURCE)
BST_ - LX_ forced to 5V
DH_ forced to 2.5V,
I
DH(SINK)
BST_ - LX_ forced to 5V
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
I
DL_ forced to 2.5V
DL_ forced to 2.5V
2.7
8
A
A
DL(SOURCE)
I
DL(SINK)
DL_ falling, C
= 3nF
20
20
20
20
DL_
DL_ Transition Time
DH_ Transition Time
ns
ns
ꢁ
DL rising, C
= 3nF
DL_
DH_ falling, C
= 3nF
= 3nF
DH_
DH_
DH_ rising, C
Internal BST_ Switch
On-Resistance
R
I
= 10mA
10
20
ON(BST)
BST_
_______________________________________________________________________________________
5
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
CSN_
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
IN
CC
DD
1.0000V, FB = FBAC, R
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = ±°C to +8.°C, unless otherwise noted.
FBAC
A
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM3, DRSKP OUTPUTS
PWM3, DRSKP Output
High Voltages
V
0.4V
-
DD
I
I
= 3mA
V
V
SOURCE
PWM3, DRSKP Output
Low Voltages
= 3mA
0.4
1.0
SINK
LOGIC AND I/O
Logic-Input High Voltage
Logic-Input Low Voltage
V
SHDN, PGD_IN
SHDN, PGD_IN
2.3
V
V
IH
V
IL
Low-Voltage Logic-Input
High Voltage
V
PSI, D0–D6, DPRSLPVR
PSI, D0–D6, DPRSLPVR
0.67
V
V
IHLV
Low-Voltage Logic-Input
Low Voltage
V
0.33
+1
ILLV
/MAX17036
T
A
= +25°C; SHDN, DPRSLPVR, PGD_IN,
Logic Input Current
-1
µA
PSI, D0–D6 = 0 or 5V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
CSN_
IN
CC
DD
o
1.0000V, FB = FBAC, R
(Note 5)
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = -4± C to +1±.°C, unless otherwise noted.)
FBAC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
V
V
, V
4.5
7
5.5
26
CC DD
Input Voltage Range
V
IN
Measured at
FB with
respect to
GNDS,
includes load-
regulation
error (Note 3)
DAC codes from
0.8125V to 1.5000V
-0.75
-10
+0.75
+10
%
FB Output-Voltage Accuracy
DAC codes from
0.3750V to 0.8000V
V
FB
mV
DAC codes from
0 to 0.3625V
-25
+25
Boot Voltage
V
A
1.085
-200
0.95
1.985
-10
1.115
+200
1.05
V
BOOT
GNDS Input Range
GNDS Gain
mV
V/V
V
ꢀV
/ꢀV
GNDS
GNDS
OUT
TIME
TIME
TIME Regulation Voltage
V
R
R
R
= 147kꢀ
2.015
+10
TIME
= 147kꢀ (6.08mV/µs nominal)
= 35.7kꢀ (25mV/µs nominal) to
TIME
-15
+15
178kꢀ (5mV/µs nominal)
TIME Slew-Rate Accuracy
%
Soft-start and soft-shutdown:
-20
+20
R
TIME
= 35.7kꢀ (6.25mV/µs nominal) to
178kꢀ (1.25mV/µs nominal)
6
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
CSN_
IN
CC
DD
o
1.0000V, FB = FBAC, R
(Note 5)
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = -4± C to +1±.°C, unless otherwise noted.)
FBAC
A
PARAMETER
SYMBOL
CONDITIONS
= 96.75kꢁ (600kHz
MIN
TYP
MAX
UNITS
R
TON
V
V
= 10V,
= 1.0V,
-15
+15
IN
per phase), 167ns nominal
FB
measured at
DH1, DH2,
and PWM3
(Note 4)
R
= 200kꢁ (300kHz
TON
On-Time Accuracy
t
%
-10
-15
+10
ON
per phase), 333ns nominal
R
TON
= 303.25kꢁ (200kHz
+15
400
per phase), 500ns nominal
Minimum Off-Time
t
Measured at DH1, DH2, and PWM3 (Note 4)
ns
OFF(MIN)
BIAS CURRENTS
Measured at V , DPRSLPVR = 5V, FB
CC
forced above the regulation point
Quiescent Supply Current (V
)
CC
I
7
mA
CC
FAULT PROTECTION
Skip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250
350
mV
V
Output Overvoltage-Protection
Threshold
V
OVP
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45
1.55
Output Undervoltage-Protection
Threshold
Measured at FB with respect to the voltage
target set by the VID code (see Table 4)
V
-450
20
-350
100
10
mV
µs
UVP
CLKEN Startup Delay and Boot
Time Period
Measured from the time when FB reaches
the boot target voltage (Note 3)
t
BOOT
Measured at startup from the time when
CLKEN goes low
PWRGD Startup Delay
3
ms
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4),
20mV hysteresis
(typ)
Lower threshold,
falling edge
(undervoltage)
-350
-250
CLKEN and PWRGD Threshold
mV
Upper threshold,
rising edge
(overvoltage)
+150
+250
CLKEN, PWRGD Output
Low Voltage
Low state, I
= 3mA
0.4
4.5
V
V
SINK
V
CC
Undervoltage-Lockout
Rising edge, 65mV typical hysteresis,
controller disabled below this level
V
4.05
29
UVLO(VCC)
Threshold
THERMAL PROTECTION
Measured at THRM with respect to V
falling edge, typical hysteresis = 75mV
,
CC
VRHOT Trip Threshold
31
8
%
VRHOT Output On-Resistance
R
Low state
ꢁ
ON(VRHOT)
_______________________________________________________________________________________
7
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 10V, V
= V = V
= V
= V
= V
= 5V, V
= V
= 0, V
= V
=
SHDN
PGD_IN
PSI
ILIM
DPRSLPVR
GNDS
CSP_
CSN_
IN
CC
DD
o
1.0000V, FB = FBAC, R
(Note 5)
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; T = -40 C to +105°C, unless otherwise noted.)
FBAC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR
V
V
- V
- V
= 100mV
= 500mV
7
13
55
25
TIME
ILIM
ILIM
CC
Current-Limit Threshold Voltage
(Positive)
V
V
V
- V
- V
mV
45
20
LIMIT
CSP_
CSN_
TIME
ILIM = V
Current-Limit Threshold Voltage
(Negative) Accuracy
V
, nominally -125% of V
-4
0
+4
2
mV
V
LIMIT(NEG)
CSP_
CSN_
LIMIT
CSP_, CSN_ Common-Mode
Input Range
V
0.4
-
CC
Phases 2, 3 Disable Threshold
Measured at CSP2, CSP3
(1/N) x ꢀ(V - V ) at I = 0;
FBAC
ꢀ indicates summation over all power-up
enabled phases from 1 to N, N = 3
3
V
CSP_
CSN_
mV/
phase
Droop Amplifier Offset
-1
+1
ꢀI
FBAC
/ꢀ[ꢀ(V
- V )]; ꢀ indicates
CSN_
/MAX17036
CSP_
summation over all power-up enabled
phases from 1 to N, N = 3,
Droop Amplifier
Transconductance
G
390
407
μS
m(FBAC)
V
FBAC
= V
= 0.45V to 1.5V
CSN_
(1/N) x ꢀ(V
ꢀ indicates summation over all power-up
enabled phases from 1 to N, N = 3
- V
) at I
= 0;
CSP_
CSN_
FBAC
mV/
phase
Current-Monitor Offset
-1.5
+1.5
ꢀI
/ꢀ[ꢀ(V
- V
)]; ꢀ indicates
IMON
CSP_ CSN_
Current-Monitor
Transconductance
summation over all power-up enabled phases
from 1 to N, N = 3, V = 0.45V to 1.5V
G
1.536
1.664
mS
m(IMON)
CSN_
GATE DRIVERS
High state (pullup)
2.5
2
BST_ – LX_
forced to 5V
DH_ Gate-Driver On-Resistance
R
R
ꢁ
ON(DH)
Low state (pulldown)
High state (pullup)
2
DL_ Gate-Driver On-Resistance
ꢁ
ꢁ
ON(DL)
Low state (pulldown)
0.7
Internal BST_ Switch
On-Resistance
R
I
= 10mA
20
ON(BST)
BST-
PWM3, DRSKP OUTPUTS
PWM3, DRSKP Output
High Voltages
V
0.4V
-
DD
I
I
= 3mA
V
V
SOURCE
PWM3, DRSKP Output
Low Voltages
= 3mA
0.4
SINK
LOGIC AND I/O
Logic-Input High Voltage
Logic-Input Low Voltage
V
SHDN, PGD_IN
SHDN, PGD_IN
2.3
V
V
IH
V
1.0
IL
Low-Voltage Logic-Input
High Voltage
V
PSI, D0–D6, DPRSLPVR
PSI, D0–D6, DPRSLPVR
0.67
V
V
IHLV
Low-Voltage Logic-Input
Low Voltage
V
0.33
ILLV
8
_______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
ELECTRICAL CHARACTERISTICS (continued)
Note 3: The equation for the target voltage V
is:
TARGET
V
V
V
= The slew-rate-controlled version of V
, where V
= 0 for shutdown
DAC
TARGET
DAC
DAC
DAC
= V
= V
during IMVP-6.5 startup
BOOT
VID
otherwise (the V
voltages for all possible VID codes are given in Table 4).
VID
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times
might be different due to MOSFET switching speeds.
Note .: Specifications to -40°C and +105°C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 0.95V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
EFFICIENCY vs. LOAD CURRENT
OUTPUT VOLTAGE vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V
= 0.95V)
(V
= 0.95V)
(V
= 0.875V)
OUT(HFM)
OUT(HFM)
OUT(LFM)
100
1.00
90
7V
90
80
70
60
50
40
30
20
7V
0.95
0.90
80
70
12V
12V
20V
20V
0.85
0.80
60
50
SKIP MODE
PWM MODE
0.1
1
10
100
0
10
20
30
40
50
60
70
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
(V = 0.875V)
SWITCHING FREQUENCY
vs. LOAD CURRENT
V
= 0.95V NO-LOAD
OUT(HFM)
SUPPLY CURRENT vs. INPUT VOLTAGE
OUT(LFM)
0.90
0.89
400
350
300
250
200
150
100
50
1000
100
10
DPRSLPVR = V
DPRSLPVR = GND
CC
V
= 0.875V
OUT(LFM)
I
IN
V
= 0.95V
OUT(HFM)
0.88
0.87
0.86
I
+ I
1-PHASE SKIP MODE
CC DD
I + I
CC DD
1
0.1
0.85
0.84
0.83
2-PHASE PWM MODE
I
IN
DPRSLPVR = V
DPRSLPVR = GND
CC
0
0.01
0
5
10
LOAD CURRENT (A)
15
20
0
10
20
30 40
50
6
9
12
15
18
21
LOAD CURRENT (A)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 0.95V, T = +25°C, unless otherwise specified.)
DD CC A
IN
CC
CURRENT BALANCE
vs. LOAD CURRENT
I
IMON
vs. LOAD CURRENT
MAX17030 toc07
20
15
0.2
0.1
100
80
V
= 0.95V
V
OUT
= 0.95V
OUT
CS2
V
- V
CSN1
CSP1
V
-
CSP3
60
40
20
V
CSN3
V
- V
CS1
DPRSLPVR = GND
10
5
0
V
- V
CSN2
CSP2
-0.1
-0.2
V
- V
CS1
CS3
0
0
0
10
20
30
40
50
60
70
0
10
20
30
40
(mV)
50
60
∑
LOAD CURRENT (A)
V
CSP - CSN
0.8125V OUTPUT
VOLTAGE DISTRIBUTION
G
m(FB)
TRANSCONDUCTANCE
DISTRIBUTION
0
70
60
50
40
70
60
50
40
+85°C
+25°C
+85°C
+25°C
SAMPLE SIZE = 100
SAMPLE SIZE = 100
30
20
30
20
10
0
10
0
TRANCONDUCTANCE (µs)
OUTPUT VOLTAGE (V)
G TRANSCONDUCTANCE
m(IMON)
DISTRIBUTION
40
SAMPLE SIZE = 100
35
30
25
20
15
10
5
0
+85°C
+25°C
TRANCONDUCTANCE (µs)
1± ______________________________________________________________________________________
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Typical Operating Characteristics (continued)
(Circuit of Figure 1. V = 12V, V
= V
= 5V, SHDN = V , D0–D6 set for 0.95V, T = +25°C, unless otherwise specified.)
IN
CC
DD
CC
A
SOFT-START WAVEFORM
(UP TO CLKEN)
SOFT-START WAVEFORM
(UP TO PWRGD)
MAX17030 toc12
MAX17030 toc13
3.3V
3.3V
A
B
C
0
3.3V
0
A
B
0
3.3V
0
0.95V
0
3.3V
0
C
0.95V
D
E
0
0
D
E
0
0
0
F
0
0
F
G
200µs/div
1ms/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
D. I , 10A/div
A. SHDN, 5V/div
B. CLKEN, 6.6V/div
C. PWRGD, 10V/div
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
LX1
E. I , 10A/div
LX2
C. V , 500mV/div
F. I , 10A/div
LX3
OUT
I , 15A
OUT
D. V , 1V/div
I , 15A
OUT
OUT
SHUTDOWN WAVEFORM
LOAD-TRANSIENT RESPONSE
(HFM MODE)
MAX17030 toc14
MAX17030 toc15
3.3V
0
A
59A
3.3V
A
B
C
0
7A
3.3V
0
0.95V
0.935V
D
E
B
0
0
0.84V
C
F
0
0
D
E
G
200µs/div
A. SHDN, 5V/div
B. PWRGD, 10V/div
C. CLKEN, 10V/div
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
20µs/div
A. I
= 7A - 59A
OUT
C. I , 20A/div
LX1
OUT
B. V , 50mV/div
D. I , 20A/div
LX2
D. V , 500mV/div
OUT
E. I , 20A/div
LX3
______________________________________________________________________________________ 11
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description
PIN
NAME
FUNCTION
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
1
CSN3
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
2
3
CSP3
To disable phase 3, connect CSP3 to V and CSN3 to GND.
CC
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V
CC
and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of
) at the desired high temperature.
THRM
V
CC
Current Monitor Output Pin. The output current at this pin is:
= G x ꢀV(CSP_,CSN_)
I
IMON
M(IMON)
where G
= 1.6mS typical and ꢀ denotes summation over all enabled phases.
M(IMON)
An external resistor R
between IMON and GNDS sets the current-monitor output voltage:
IMON
4
5
IMON
V
= I
x R
x G
x R
M(IMON) IMON
IMON
LOAD
SENSE
where R
is the value of the effective current-sense resistance.
SENSE
/MAX17036
Choose R
such that V
does not exceed 900mV at the maximum expected load current I
.
IMON
IMON
MAX
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are
precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
ILIM
current-limit thresholds. Connect ILIM to V to get the default current-limit threshold setting of
CC
22.5mV typ.
Slew-Rate Adjustment Pin. The total resistance R
from TIME to GND sets the internal slew rate:
TIME
Slew rate = (12.5mV/µs) x (71.5kꢁ/R
)
TIME
where R
is between 35.7kꢁ and 178kꢁ.
TIME
This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
6
7
8
TIME
V
CC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
of the inductor currents is essential for cycle-by-cycle stability.
The external connections and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
FB
12 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Pin Description (continued)
PIN
NAME
FUNCTION
Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor R
between
FBAC
FBAC and the positive side of the feedback remote sense to set the transient (AC) droop based on
the stability, load-transient response, and voltage-positioning gain requirements:
R
FBAC
= R /[R
DROOP,AC
x G
]
m(FBAC)
SENSE
where R
is the transient (AC) voltage-positioning slope that provides an acceptable
DROOP,AC
tradeoff between stability and load-transient response, G
= 400µS typ, and R
is the
SENSE
m(FBAC)
9
FBAC
effective current-sense resistance that is used to provide the (CSP_, CSN_) current-sense voltages.
A minimum R value is required for stability, but if there are no ceramic output capacitors
DROOP,AC
used, then the minimum requirement applies to R
ESR of the output capacitors.
+ R , where R
DROOP,AC
is the effective
ESR
ESR
If lossless sensing (inductor DCR sensing) is used, use a thermistor-resistor network to minimize
the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load.
GNDS internally connects to a transconductance amplifier that fine tunes the output voltage
compensating for voltage drops from the regulator ground to the load ground.
10
11
GNDS
CSN2
Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
inductor is utilized for current sensing.
12
13
CSP2
To disable phase 2, connect CSP2 to V and CSN2 to GND.
CC
Shutdown Control Input. Connect to V for normal operation. Connect to ground to put the IC into
CC
the 1µA (max at T = +25°C) shutdown state. During startup, the output voltage is ramped up at 1/4
A
the slew rate set by the TIME resistor to the boot voltage or to the target voltage.
During the transition from normal operation to shutdown, the output voltage is ramped down at 1/6
the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V to enter no-fault test mode clears
SHDN
the fault latches, disables transient phase overlap, and turns off the internal BST_-to-V switches.
DD
However, internal diodes still exist between BST_ and V in this state.
DD
Deeper Sleep VR Control Input. This low-voltage logic input indicates power usage and sets the
operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the
controller is immediately set to 1-phase automatic pulse-skipping mode. The controller returns to forced-
PWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold
is blanked during any downward output-voltage transition that happens when the controller is in skip
mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period
is complete and the output reaches regulation. During this blanking period, the overvoltage fault
threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.5V threshold.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by
14
DPRSLPVR
connecting CSP2, CSP3 to V , then only phase 1 is active in the above modes.
CC
DPRSLPVR
PSI
MODE
1
0
0
X
0
1
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
______________________________________________________________________________________ 13
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
This low-voltage logic input indicates power usage and sets the operating mode together
with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when PSI is forced high.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by
connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes.
15
PSI
DPRSLPVR
PSI
MODE
Very low current (1-phase skip)
1
0
0
X
0
1
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency according to the following equation:
f
= 1/(C
x (R
+ 6.5kꢁ))
SW
TON
TON
/MAX17036
16
17
TON
where C
= 16.26pF.
TON
The external resistor must also satisfy the requirement [V
the minimum V value expected in the application.
IN
TON is high impedance in shutdown.
/R
] ꢀ 10µA where V
is
IN(MIN)
IN(MIN) TON
Clock Enable CMOS Push-Pull Logic Output Powered by V . This inverted logic output indicates
3P3
when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during
soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an
additional 20µs after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms
PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The
CLKEN upper threshold is blanked during any downward output-voltage transition that happens when
the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
CLKEN
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes
high if FB is within the PWRGD threshold window.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high
impedance whenever the slew-rate controller is active (output-voltage transitions), and continues
to be forced high impedance for an additional 20µs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that
happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled
internal-transition-related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
18
PWRGD
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-
mode driver IC. DRSKP swings from V to GND. When DRSKP is high, the driver ICs operate in
DD
19
DRSKP
forced-PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and
operate in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence,
instructing the external drivers to shut down.
14 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Pin Description (continued)
PIN
NAME
FUNCTION
PWM Signal Output for Phase 3. Swings from GND to V . Three-state whenever phase 3 is disabled
(in shutdown, when CSP3 is connected to V , and when operating with fewer than all phases).
CC
DD
20
PWM3
Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-
side gate driver. An internal switch between V and BST2 charges the BST2-LX2 flying capacitor
DD
21
BST2
while the low-side MOSFET is on (DL2 pulled high).
Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to phase 2’s zero-crossing comparator.
22
23
LX2
DH2
Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
Phase 2 Low-Side Gate-Driver Output. DL2 swings from GND to V . DL2 is forced low in shutdown.
DD
DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor
current zero crossing.
24
DL2
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes
25
26
VRHOT
below 1.5V (30% of V ). VRHOT is high impedance in shutdown.
CC
Supply Voltage Input for the DL_ Drivers. V is also the supply voltage used to internally recharge
DD
V
DD
the BST_-LX_ flying capacitor during the times the respective DL_s are high. Connect V
to the
DD
4.5V to 5.5V system supply voltage. Bypass V
to GND with a 1µF or greater ceramic capacitor.
DD
Phase 1 Low-Side Gate-Driver Output. DL1 swings from GND to V . DL1 is forced low in shutdown.
DD
DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor
current zero crossing.
27
DL1
28
29
DH1
LX1
Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to phase 1’s zero-crossing comparator.
Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-
side gate driver. An internal switch between V and BST1 charges the BST1-LX1 flying capacitor
DD
30
BST1
while the low-side MOSFET is on (DL1 pulled high).
Power-Good Logic Input Pin that Indicates the Power Status of Other System Rails and Used for Supply
Sequencing. During startup, after soft-starting to the boot voltage, the output voltage remains at V
,
BOOT
and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGD_IN input
stays low. When PGD_IN later goes high, the output is allowed to transition to the voltage set by the VID
code, and CLKEN is allowed to go low. During normal operation, if PGD_IN goes low, the controller
immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in skip
mode at 1/4 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until
the controller is turned off or power cycled, or until PGD_IN goes high again.
31
PGD_IN
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups. These
1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID
code indicated by the logic-level voltages on D0–D6 (see Table 4).
The 1111111 code corresponds to a shutdown mode. When this code is detected, The
MAX17030/MAX17036 initiate a soft-shutdown transition identical to the shutdown transition for a
SHDN falling edge. After slewing the output to 0V, it forces DH_, DL_, and DRSKP low, and three-states
PWM3. The IC remains active and its V quiescent current consumption stays the same as in normal
CC
operation. If D6–D0 is changed from 1111111 to a different code, the MAX17030/MAX17036 initiate a
32–38
D0–D6
CSP1
startup sequence identical to the startup sequence for a SHDN rising edge.
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
inductor is utilized for current sensing.
39
______________________________________________________________________________________ 1.
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing. A 10ꢀ discharge FET is turned on in UVLO event
or thermal shutdown, or at the end of soft-shutdown.
40
CSN1
Exposed Backplate (Pad) of Package. Internally connected to both analog ground and power
(driver) grounds. Connect to the ground plane through a thermally enhanced via.
—
PAD (GND)
R
TON
200kΩ
16
8V TO 20V
PWR INPUT
32
33
34
35
36
37
38
13
TON
D0
30
28
BST1
DH1
C
IN
D1
N
N
H
D2
C
L1
BST
29
OUTPUT
VID INPUTS
D3
LX1
(IMVP-6.5 CORE)
D4
R3
27
39
C
OUT
R1
D5
L
DL1
D6
CSP1
ON OFF (VRON)
DPRSLPVR
PGDIN
SHDN
2Ω
R2
R
NTC1
14
31
15
/MAX17036
DPRSLPVR
PGDIN
PSI
C
CS1
40
CSN1
8V TO 20V
PWR INPUT
PSI
21
23
BST2
DH2
C
IN
26
N
5V BIAS
V
DD
H
C
2.2µF
C
VDD
L2
BST
R
20Ω
VCC
22
LX2
MAX17030
MAX17036
7
R6
V
CC
24
12
C
OUT
N
R4
C
L
VCC
DL2
1.0µF
5
6
CSP2
ILIM
2Ω
R
NTC2
R5
R
R
ILIM2
ILIM1
TIME
C
CS2
11
CSN2
8V TO 20V
PWR INPUT
5V BIAS
3.3V
C
IN
V
BST
DH
CC
V
CCP
C
1.0µF
VCC1
N
R
R
PWRGD
1.9kΩ
H
CLKEN
R
1.9kΩ
C
BST
L3
VRHOT
56Ω
LX
DL
MAX8791
18
25
PWRGD
VRHOT
20
R9
C
PWM3
PWM
SKIP
OUT
R7
N
L
19
2
17
4
DRSKP
CSP3
GND
CLKEN
IMON
R
NTC3
IMON
R8
2Ω
R
IMON
NTC
C
CS3
1
CSN3
V
SS_SENSE
R
10Ω
9
8
FBS
FBAC
FB
R
FB
3
R
CATCHCORE
10Ω
V
CC
THRM
V
CC_SENSE
C
FBS
R
THRM
1000pF
13kΩ
CPU REMOTE
SENSE
R
GNDS
10
100kΩ
β = 4250
GNDS
10Ω
V
SS_SENSE
PAD
C
GNDS
R
10Ω
4700pF
CATCHGND
Figure 1. Standard 3-Phase IMVP-6.5 Application Circuit
16 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Table 10 Component Selection for Standard Applications
IMVP-6.5 XE CORE
3-PHASE
IMVP-6.5 SV CORE
3-PHASE
IMVP-6.5 SV CORE
2-PHASE
DESIGN PARAMETERS
Circuit
Figure 1
Figure 1
Figure 2
Input Voltage Range
8V to 20V
8V to 20V
8V to 20V
Maximum Load Current
65A (48A TDC)
52A (38A TDC)
52A (38A TDC)
49A
(100A/µs)
39A
(100A/µs)
39A
(100A/µs)
Transient Load Current
Load Line
-1.9mV/A
110
-1.9mV/A
101
-1.9mV/A
101
POC Setting
TON Resistance (R
)
200kꢁ (f
= 300kHz)
200kꢁ (f
= 300kHz)
200kꢁ (f
= 300kHz)
SW
TON
SW
SW
0.36µH, 36A, 0.82mꢁ
(10mm x 10mm)
0.42µH, 20A, 1.55mꢁ
(7mm x 7mm)
0.36µH, 36A, 0.82mꢁ
(10mm x 10mm)
Inductance (L)
Panasonic ETQP4LR36ZFC
NEC/TOKIN MPC0740LR42C
Panasonic ETQP4LR36ZFC
Fairchildsemi
Fairchildsemi
Fairchildsemi
1x FDS6298
1x FDS6298
1x FDS6298
9.4mꢁ/12mꢁ (typ/max)
Toshiba
9.4mꢁ/12mꢁ (typ/max)
Toshiba
9.4mꢁ/12mꢁ (typ/max)
Toshiba
High-Side MOSFET (N )
H
1x TPCA8030-H
9.6mꢁ/13.4mꢁ (typ/max)
1x TPCA8030-H
9.6mꢁ/13.4mꢁ (typ/max
1x TPCA8030-H
9.6mꢁ/13.4mꢁ (typ/max)
Fairchildsemi
2x FDS8670
Fairchildsemi
1x FDS8670
Fairchildsemi
2x FDS8670
Low-Side MOSFET (N )
L
4.2mꢁ/5mꢁ (typ/max)
Toshiba
4.2mꢁ/5mꢁ (typ/max)
Toshiba
4.2mꢁ/5mꢁ (typ/max)
Toshiba
2x TPCA8019-H
1x TPCA8019-H
2x TPCA8019-H
4x 330µF, 2V, 4.5mꢁ
3x 330µF, 2V, 4.5mꢁ
Output Capacitors (C
(MAX17030 Only)
Contact Maxim for MAX17036
reference design
)
OUT
Panasonic EEFSXOD331E4 or Panasonic EEFSXOD331E4 or 4x 330µF, 6mꢁ, 2.5V
NEC/Tokin PSGVOE337M4.5
27x 22µF, 6.3V X5R
NEC/Tokin PSGVOE337M4.5
27x 22µF, 6.3V X5R
ceramic capacitor (0805)
Panasonic EEFSX0D0D331XR
28x 10µF, 6V ceramic (0805)
ceramic capacitor (0805)
Input Capacitors (C
)
IN
6x 10µF 25V ceramic (1210)
4x 10µF 25V ceramic (1210)
4x 10µF 25V ceramic (1210)
TIME-ILIM Resistance (R
)
14kꢁ
14kꢁ
16.9kꢁ
ILIM2
ILIM-GND Resistance (R
)
137kꢁ
137kꢁ
133kꢁ
ILIM1
FB Resistance (R
)
FB
6.04kꢁ
453kꢁ
6.04kꢁ
IMON Resistance (R
LX-CSP Resistance
)
12.1kꢁ
10.2kꢁ
14kꢁ
IMON
2.21kꢁ (R1, R4, R7)
1.4kꢁ (R1, R4, R7)
2.21kꢁ (R1, R7)
3.24kꢁ (R2, R5, R8)
40.2kꢁ (R3, R6, R9)
2kꢁ (R2, R5, R8)
40.2kꢁ (R3, R6, R9)
3.24kꢁ (R2, R8)
40.2kꢁ (R3, R9)
CSP-CSN Resistance
10kꢁ NTC B = 3380
TDK NTCG163JH103F
10kꢁ NTC B = 3380
TDK NTCG163JH103F
10kꢁ NTC B = 3380
TDK NTCG163JH103F
DCR Sense NTC (R
)
NTC
DCR Sense Capacitance
(C
0.22µF, 6V ceramic (0805)
0.22µF, 6V ceramic (0805)
0.22µF, 6V ceramic (0805)
)
SENSE
______________________________________________________________________________________ 17
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Table 20 Component Suppliers
MANUFACTURER
WEBSITE
MANUFACTURER
Siliconix (Vishay)
WEBSITE
www.vishay.com
AVX Corp.
www.avxcorp.com
Fairchild Semiconductor
NEC/TOKIN America, Inc.
Panasonic Corp.
www.fairchildsemi.com
www.nec-tokinamerica.com
www.panasonic.com
www.sanyodevice.com
Taiyo Yuden
www.t-yuden.com
TDK Corp.
www.component.tdk.com
www.tokoam.com
TOKO America, Inc.
SANYO Electric Co., Ltd.
Toshiba America Electronic
Components, Inc.
www.toshiba.com/taec
R
TON
200kΩ
32
D0
D1
D2
D3
D4
D5
D6
16
30
8V TO 20V
PWR INPUT
TON
33
34
35
36
37
38
13
BST1
C
IN
28
29
N
N
DH1
LX1
H
VID INPUTS
C
L1
BST
OUTPUT
(IMVP-6.5 CORE)
R3
27
39
C
OUT
R1
DL1
L
ON OFF (VRON)
DPRSLPVR
PGDIN
SHDN
14
31
/MAX17036
DPRSLPVR
PGDIN
PSI
CSP1
R
R2
NTC1
2Ω
15
26
C
PSI
CS1
40
CSN1
5V BIAS
V
DD
8V TO 20V
C
2.2µF
VDD
R
20Ω
VCC
PWR INPUT
21
23
22
BST2
DH2
LX2
C
IN
7
V
CC
N
H
MAX17030
MAX17036
C
1.0µF
VCC
C
L2
BST
5
6
ILIM
R9
R
R
ILIM1
24
ILIM2
R7
C
OUT
N
DL2
L
TIME
12
R
NTC3
R8
3.3V
CSP2
2Ω
V
CCP
R
R
PWRGD
CLKEN
R
1.9kΩ
1.9kΩ
VRHOT
56Ω
C
CS2
11
CSN2
18
25
PWRGD
VRHOT
20
19
PWM3
DRSKP
17
4
CLKEN
IMON
IMON
2
1
5V BIAS
CSP3
CSN3
R
IMON
R
CATCHCORE
10Ω
V
SS_SENSE
9
8
R
FBS
10Ω
3
FBAC
FB
V
CC
THRM
R
FB
R
THRM
V
V
CC_SENSE
SS_SENSE
C
NTC
13kΩ
FBS
CPU REMOTE
SENSE
1000pF
100kΩ
β = 4250
10
GNDS
R
10Ω
GNDS
PAD
R
10Ω
CATCHGND
Figure 2. Standard 2-Phase IMVP-6.5 Application Circuit
18 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
THRM
PWM3
VRHOT
PHASE 3 DRIVER
CONTROL
DRSKP
CSN3
0.3 x V
CC
CSP3
CSP1
Q
TRIG
TRIG3
G
G
m(CCI)
CSP3
CSN3
TON
CC13
ONE-SHOT
PHASE 3
ON-TIME
10x
CSN1
m(CCI)
BST2
DH2
LX2
DL2
GND
CSP2
CSN2
10x
10x
PHASE 2 DRIVERS
CSP1
CSN1
Q
TRIG
ONE-SHOT
PHASE 2
ON-TIME
CC12
ILIM
MINIMUM
OFF-TIME
CSN2
TIME
Q
TRIG
TRIG 3
CSP2
CSP1
G
G
m(CCI)
ONE SHOT
V
CC
PHASE 1
ON-TIME
ONE-SHOT
FB
REF
(2.0V)
CSN1
m(CCI)
Q
TRIG
GND
SLEW
TON
D0–D6
PGDIN
R-TO-I
CONVERTER
DAC
MAIN PHASE
DRIVERS
R
BST1
DH1
LX1
Q
S
SHDN
S
R
PGND1
LX1
Q
TARGET
PHASE
SEL
0mV
FAULT
V
DD
SKIP
DL1
GND
TARGET
- 300mV
TARGET
+ 200mV
FB
PWRGD
5ms
STARTUP
DELAY
GNDS
SKIP
CLKEN
IMON
60µs
x3
CSP
CSN
CSP
CSN
x3
BLANK
MODE/PHASE/SLEW-
RATE CONTROL
MAX17030
MAX17036
FBAC
G
m(FB)
G
m(IMON)
PGDIN DPRSLPVR
PSI
Figure 3. Functional Diagram
______________________________________________________________________________________ 19
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
V
and V
can be connected together if the input
DD
IN
Detailed Description
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
power source is a fixed +4.5V to +5.5V supply. If the
+5V bias supply is powered up prior to the battery sup-
ply, the enable signal (SHDN going from low to high)
must be delayed until the battery voltage is present to
ensure startup.
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator with
voltage feed-forward (Figure 3). This architecture relies on
the output filter capacitor’s ESR to act as the current-
sense resistor, so the output ripple voltage provides the
PWM ramp signal. The control algorithm is simple: the
high-side switch on-time is determined solely by a one-
shot whose period is inversely proportional to input volt-
age, and directly proportional to output voltage or the
difference between the main and secondary inductor cur-
rents (see the On-Time One-Shot section). Another one-
shot sets a minimum off-time. The on-time one-shot
triggers when the error comparator goes low, the inductor
current of the selected phase is below the valley current-
limit threshold, and the minimum off-time one-shot times
out. The controller maintains 120° out-of-phase operation
by alternately triggering the three phases after the error
comparator drops below the output-voltage set point.
Switching Frequency (TON)
Connect a resistor (R
the switching period T
) between TON and V to set
TON
SW
IN
= 1/f , per phase:
SW
T
SW
= 16.26pF x (R
+ 6.5kΩ)
TON
A 96.75kΩ to 303.25kΩ corresponds to switching peri-
ods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the appli-
cation for the smallest component size, trading off effi-
ciency due to higher switching losses. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an over-
voltage condition on the output. The MAX17030/
MAX17036 detect an open-circuit fault if the TON current
drops below 10µA for any reason—the TON resistor
/MAX17036
Triple 120° Out-of-Phase Operation
The three phases in the MAX17030/MAX17036 operate
120° out-of-phase to minimize input and output filtering
requirements, reduce electromagnetic interference (EMI),
and improve efficiency. This effectively lowers component
count—reducing cost, board space, and component
power requirements—making the MAX17030/MAX17036
ideal for high-power, cost-sensitive applications.
(R
) is unpopulated, a high resistance value is used,
TON
the input voltage is low, etc. Under these conditions, the
MAX17030/MAX17036 stop switching (DH and DL pulled
low) and immediately set the fault latch. Toggle SHDN or
cycle the V
latch and reactivate the controller.
power supply below 0.5V to clear the fault
CC
The MAX17030/MAX17036 share the current between
three phases that operate 120° out-of-phase, so the
high-side MOSFETs never turn on simultaneously dur-
ing normal operation. The instantaneous input current
of each phase is effectively reduced, resulting in
reduced input voltage ripple, ESR power loss, and RMS
ripple current (see the Input Capacitor Selection sec-
tion). Therefore, the same performance can be
achieved with fewer or less-expensive input capacitors.
On-Time One-Shot
The MAX17030/MAX17036 contain a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. It is shared among the three phases. The one-
shot for the main phase varies the on-time in response
to the input and feedback voltages. The main high-side
switch on-time is inversely proportional to the input volt-
age as measured by the V+ input, and proportional to
the feedback voltage (V ):
FB
+5V Bias Supply (V
and V )
DD
CC
T
V
+ 0.075V
(
)
SW FB
The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
t
=
ON
V
IN
The one-shot for the second phase and third phase
varies the on-time in response to the input voltage and
the difference between the main and the other inductor
currents. Two identical transconductance amplifiers
integrate the difference between the master and each
slave’s current-sense signals. The summed output is
connected to an internal integrator for each master-
slave pair, which serves as the input to the respective
slave’s high-side MOSFET TON timer.
system supply. The +5V bias supply must provide V
CC
(PWM controller) and V
(gate-drive power), so the
DD
maximum current drawn is:
I
= I
+ f
Q
+ Q
G(LOW) G(HIGH)
(
)
BIAS
CC
SW
where I
is provided in the Electrical Characteristics
CC
SW
G(HIGH)
table, f
is the switching frequency, and Q
and
G(LOW)
Q
are the MOSFET data sheet’s total gate-
charge specification limits at V = 5V.
GS
2± ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
When the main and other phase current-sense signals
(V = V - V and V = V - V ) become
unbalanced, the transconductance amplifiers adjust the
other phase’s on-time, which increases or decreases
the phase inductor current until the current-sense sig-
nals are properly balanced:
including MOSFET, inductor, and PCB resistances;
V is the sum of the parasitic voltage drops in the
CHG
CM
CMP
CMN
CS
CSP
CSM
inductor charge path, including high-side switch,
inductor, and PCB resistances; and t
as determined above.
is the on-time
ON
Current Sense
⎛
⎝
⎞
⎠
V
+ 0.075V
CCI
The MAX17030/MAX17036 sense the output current of
each phase allowing the use of current-sense resistors
on inductor DCR as the current-sense element. Low-
offset amplifiers are used for current balance, voltage-
positioning gain, and current limit.
t
= T
ON(SEC)
SW
⎜
⎟
V
IN
⎛
⎝
⎞
⎠
⎛
⎝
⎞
⎠
V
+ 0.075V
I
Z
FB
CCI CCI
= T
+ T
SW
SW
⎜
⎟
⎜
⎟
V
V
IN
IN
= Main On-time + Secondary Current Balance Correction
(
)
(
)
Using the DC resistance (R
) of the output inductor
DCR
where V
is the internal integrator node for each
allows higher efficiency. The initial tolerance and tem-
perature coefficient of the inductor’s DCR must be
accounted for in the output-voltage droop-error budget
and current monitor. This current-sense method uses
an RC filtering network to extract the current information
from the output inductor (see Figure 4). The RC network
CCI
slave’s current-balance integrator, and Z
effective impedance at that node.
is the
CCI
During phase overlap, tON is calculated based on
phase 1’s on-time requirements, but reduced by 33%
when operating with three phases.
should match the inductor’s time constant (L/R
):
DCR
For a 3-phase regulator, each phase cannot be
enabled until the other 2 phases have completed their
on-time and the minimum off-times have expired. As
R2
R1+ R2
⎛
⎞
R
=
=
R
DCR
⎜
⎝
⎟
⎠
CS
such, the minimum period is limited by 3 x (t
+
IN
ON
t
). Maximum t
is dependent on minimum V
and:
OFF(MIN)
ON
and maximum output voltage:
L
1
1
⎡
⎤
R
+
CS
⎢
⎣
⎥
⎦
TSW(MIN) = NPH x (t
+ t
)
ON(MAX)
OFF(MIN)
C
R1 R2
EQ
where:
where R
is the required current-sense resistance,
is the inductor’s series DC resistance. Use
CS
t
= V
/V
x T
ON(MAX)
FB(MAX) IN(MIN
SW(MIN)
and R
DCR
so:
T
the typical inductance and R
values provided by
DCR
= t
/[1/N – V
/V
]
the inductor manufacturer. To minimize the current-
sense error due to the current-sense inputs’ bias current
SW(MIN)
OFF(MIN)
PH
IN(MAX) IN(MIN)
Hence, for a 7V input and 1.1V output, 500kHz is the
maximum switching frequency. Running at this limit is
not desirable as there is no room to allow the regulator
to make adjustments without triggering phase overlap.
For a 3-phase, high-current application with minimum
8V input, the practical switching frequency is 300kHz.
(I
CSP_
and I
), choose R1//R2 to be less than 2kΩ
CSN_
and use the above equation to determine the sense
capacitance (C ). Choose capacitors with 5% toler-
EQ
ance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the Voltage Positioning and
Loop Compensation section for detailed information.
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the Electrical
Characteristics are influenced by parasitics in the con-
duction paths and propagation delays. For loads above
the critical conduction point, where the dead-time effect
(LX flying high and conducting through the high-side
FET body diode) is no longer a factor, the actual
switching frequency (per phase) is:
When using a current-sense resistor for accurate out-
put-voltage positioning, the circuit requires a differential
RC filter to eliminate the AC voltage step caused by the
equivalent series inductance (L
) of the current-
ESL
sense resistor (see Figure 4). The ESL induced voltage
step might affect the average current-sense voltage.
The RC filter’s time constant should match the L
/
ESL
R time constant formed by the current-sense
V
+ V
SENSE
(
)
OUT
+ V
DIS
f
=
SW
resistor’s parasitic inductance:
t
V
− V
(
)
ON IN
DIS CHG
L
ESL
= C
R
EQ EQ
where V
and V
are the sum of the parasitic volt-
CHG
DIS
R
SENSE
age drops in the inductor discharge and charge paths,
______________________________________________________________________________________ 21
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
INPUT (V )
IN
C
IN
N
H
DH_
LX_
SENSE RESISTOR
L
R
SENSE
ESL
L
MAX17030
MAX17036
L
C
OUT
ESL
DL_
D
L
C
R
=
EQ EQ
N
L
R
SENSE
R
EQ
C
EQ
CSP_
CSN_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (V )
IN
C
IN
/MAX17036
N
H
DH_
LX_
INDUCTOR
R
DCR
R2
L
R2
R
CS
=
R
DCR
R1 + R2
MAX17030
MAX17036
C
OUT
DL_
D
L
N
L
R1
L
1
1
+
R
DCR
=
C
R1 R2
EQ[ ]
C
EQ
CSP_
CSN_
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR
B) LOSSLESS INDUCTOR SENSING
Figure 4. Current-Sense Methods
where L
is the equivalent series inductance of the cur-
ESL
V
OS(IBAL)
rent-sense resistor, R
is current-sense resistance
SENSE
I
= I
−I
=
OS(IBAL)
LMAIN LSEC
R
value, and C
components.
and R
are the time-constant matching
EQ
EQ
SENSE
where R
= R
= R
and V
is the
OS(IBAL)
SENSE
CM
CS
Current Balance
current balance offset specification in the Electrical
Characteristics table.
The MAX17030/MAX17036 integrate the difference
between the current-sense voltages and adjust the on-
time of the secondary phase to maintain current bal-
ance. The current balance relies on the accuracy of the
current-sense signals across the current-sense resistor
or inductor DCR. With active current balancing, the cur-
rent mismatch is determined by the current-sense resis-
tor or inductor DCR values and the offset voltage of the
transconductance amplifiers:
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
22 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Current Limit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that senses the voltage across
the current-sense resistors or inductor DCR at the cur-
rent-sense inputs (CSP_ to CSN_). If the current-sense
signal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
any one phase exceeds the current limit, all phases are
effectively current limited since the interleaved con-
troller does not initiate a cycle with the next phase.
amplifier’s output current (I ) is determined by the
FB
sum of the current-sense voltages:
η
I
= G
PH V
∑
FB
m(FB)
CSX
X=1
where V
= V
- V
is the differential current-
CSN
m(FB)
CSX
CSP
sense voltage, and G
is typically 400µS as
defined in the Electrical Characteristics.
Differential Remote Sense
The MAX17030/MAX17036 include differential, remote-
sense inputs to eliminate the effects of voltage drops
along the PCB traces and through the processor’s
power pins. The feedback-sense node connects to the
Since only the valley current is actively limited, the actu-
al peak current is greater than the current-limit thresh-
old by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the current-
sense resistance, inductor value, and battery voltage.
voltage-positioning resistor (R ). The ground-sense
FB
(GNDS) input connects to an amplifier that adds an off-
set directly to the target voltage, effectively adjusting
the output voltage to counteract the voltage drop in the
ground path. Connect the voltage-positioning resistor
The positive valley current-limit threshold voltage at
CSP to CSN equals precisely 1/10 of the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
(R ) and ground sense (GNDS) input directly to the
FB
processor’s remote sense outputs as shown in Figure 1.
V
to set the default current-limit threshold setting of
Integrator Amplifier
An internal integrator amplifier forces the DC average of
the FB voltage to equal the target voltage, allowing
accurate DC output-voltage regulation regardless of the
output ripple voltage.
CC
22.5mV (typ).
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immedi-
ately activates an on-time pulse—DL turns off, and DH
turns on—allowing the inductor current to remain above
the negative current threshold.
The MAX17030/MAX17036 disable the integrator by
connecting the amplifier inputs together at the begin-
ning of all VID transitions done in pulse-skipping mode
(DPRSLPVR = high). The integrator remains disabled
until 20µs after the transition is completed (the internal
target settles) and the output is in regulation (edge
detected on the error comparator).
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP_, CSN_).
Transient Overlap Operation
When a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 120° out-of-
phase when a transient occurs actually respond slower
than an equivalent single-phase controller. In order to
provide fast transient response, the MAX17030/
MAX17036 support a phase overlap mode, which
allows the triple regulators to operate in-phase when
heavy load transients are detected, effectively reducing
the response time. After any high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the con-
troller simultaneously turns on all high-side MOSFETs
with the same on-time during the next on-time cycle.
The phases remain overlapped until the output voltage
exceeds the regulation voltage after the minimum
Feedback Adjustment Amplifiers
ꢀoltage-Positioning Amplifier
(Steady-State Droop)
The MAX17030/MAX17036 include a transconductance
amplifier for adding gain to the voltage-positioning sense
path. The amplifier’s input is generated by summing the
current-sense inputs, which differentially sense the volt-
age across either current-sense resistors or the induc-
tor’s DCR. The amplifier’s output connects directly to the
regulator’s voltage-positioned feedback input (FB), so
the resistance between FB and the output-voltage sense
point determines the voltage-positioning gain:
V
= V
− R I
FB FB
OUT
TARGET
where the target voltage (V
) is defined in the
TARGET
Nominal Output Voltage Selection section, and the FB
______________________________________________________________________________________ 23
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
off-time expires. The on-time for each phase is based
on the input voltage to FB ratio (i.e., follows the master
on-time), but reduced by 33% in a 3-phase configura-
tion, and not reduced in a 2-phase configuration. This
maximizes the total inductor current slew rate.
DAC Inputs (D±–D6)
The digital-to-analog converter (DAC) programs the out-
put voltage using the D0–D6 inputs. D0–D6 are low-volt-
age (1.0V) logic inputs, designed to interface directly with
the CPU. Do not leave D0–D6 unconnected. Changing
D0–D6 initiates a transition to a new output-voltage level.
Change D0–D6 together, avoiding greater than 20ns
skew between bits. Otherwise, incorrect DAC readings
might cause a partial transition to the wrong voltage level
followed by the intended transition to the correct voltage
level, lengthening the overall transition time. The available
DAC codes and resulting output voltages are compatible
with the IMVP-6.5 (Table 4) specifications.
After the phase-overlap mode ends, the controller auto-
matically begins with the next phase. For example, if
phase 2 provided the last on-time pulse before overlap
operation began, the controller starts switching with
phase 3 when overlap operation ends.
Nominal Output Voltage Selection
The nominal no-load output voltage (V
) is
TARGET
defined by the selected voltage reference (VID DAC)
OFF Code
VID = 1111111 is defined as an OFF code. When the
OFF code is set, the MAX17030/MAX17036 go through
the same shutdown sequence as though SHDN has
been pulled low—output discharged to zero, CLKEN
high, and PWRGD low. Only the IC supply currents
remain at the operating levels rather than the shutdown
level. When exiting from the OFF code, the MAX17030/
MAX17036 go through the boot sequence, similar to the
sequence when SHDN is first pulled high.
plus the remote ground-sense adjustment (V
defined in the following equation:
) as
GNDS
V
= V = V
+ V
TARGET
FB
DAC GNDS
where V
is the selected VID voltage. On startup, the
DAC
MAX17030/MAX17036 slew the target voltage from
ground to the preset boot voltage. Table 3 is the operating
mode truth table.
/MAX17036
Table 30 Operating Mode Truth Table
INPUTS
PHASE
OPERATION*
OPERATING MODE
SHDN DPRSLPVR
PSI
Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1µA (max).
GND
Rising
High
X
X
Disabled
Startup/Boot. When SHDN is pulled high, the MAX17030/
MAX17036 begin the startup sequence. Once the REF is above
1.84V, the controller enables the PWM controller and ramps the
output voltage up to the boot voltage. See Figure 9.
Multiphase Pulse
Skipping
X
X
1/4 R
Slew Rate
TIME
Multiphase Forced-PWM Full Power. The no-load output voltage is determined by the selected
Nominal R Slew Rate VID DAC code (D0–D6, Table 4).
Low
Low
High
Low
TIME
Intermediate Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When PSI is pulled low,
Slew Rate the MAX17030/MAX17036 immediately disable phase 3, PWM3 is
(N-1)-Phase Forced-PWM
High
Nominal R
TIME
three-state, and DRSKP is low.
Deeper Sleep Mode. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When DPRSLPVR is pulled
1-Phase Pulse Skipping high, the MAX17030/MAX17036 immediately enter 1-phase pulse-
High
High
X
Nominal R
Slew Rate skipping operation allowing automatic PWM/PFM switchover under
light loads. The PWRGD and CLKEN upper thresholds are blanked.
DH2 and DL2 are pulled low, PWM3 is three-state and DRSKP is low.
TIME
*Multiphase operation = All enabled phases active.
24 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Table 30 Operating Mode Truth Table (continued)
INPUTS
PHASE
OPERATION*
OPERATING MODE
SHDN DPRSLPVR
PSI
Shutdown. When SHDN is pulled low, the MAX17030/MAX17036
immediately pull PWRGD low, CLKEN becomes high impedance, all
enabled phases are activated, and the output voltage is ramped
down to 12.5mV; then DH and DL are pulled low and CSNI discharge
FET is turned on.
Multiphase Forced-PWM
Falling
High
X
X
X
1/4 R
Slew Rate
TIME
Fault Mode. The fault latch has been set by the MAX17030/MAX17036
UVP or thermal-shutdown protection, or by the OVP protection. The
X
Disabled
controller remains in fault mode until V power is cycled or SHDN
CC
toggled.
*Multiphase operation = All enabled phases active.
Table 40 IMꢀP-60. Output ꢀoltage ꢀID DAC Codes
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
______________________________________________________________________________________ 2.
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Table 40 IMꢀP-60. Output ꢀoltage ꢀID DAC Codes (continued)
OUTPUT
VOLTAGE
(V)
OUTPUT
VOLTAGE
(V)
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3750
0.3625
0.3500
0.3375
0.3250
0.3125
0.3000
0.2875
0.2750
0.2625
0.2500
0.2375
0.2250
0.2125
0.2000
0.1875
0.1750
0.1625
0.1500
0.1375
0.1250
0.1125
0.1000
0.0875
0.0750
0.0625
0.0500
0.0375
0.0250
0.0125
0
/MAX17036
0
0
0
0
0
0
Off
26 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6.5 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17030/MAX17036 respond by slewing the internal
target voltage to the new DAC code, switching to single-
phase operation, and letting the output voltage gradual-
ly drift down to the deeper sleep voltage. During the
transition, the MAX17030/MAX17036 blank both the
upper and lower PWRGD and CLKEN thresholds until
20µs after the internal target reaches the deeper sleep
voltage. Once the 20µs timer expires, the MAX17030/
MAX17036 reenable the lower PWRGD and CLKEN
threshold, but keep the upper threshold blanked.
The average inductor current per phase required to
make an output-voltage transition is:
C
OUT
I
≅
× dV
(
dt
TARGET
)
L
η
TOTAL
where dV
/dt is the required slew rate, C
is
OUT
TARGET
the total output capacitance, and ηTOTAL is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17030/MAX17036
immediately disable phases 2 and 3 (DH2, DL2 forced
low, PWM3 three-state, DRSKP low), and enter pulse-
skipping operation (see Figures 5 and 6). If the VIDs are
set to a lower voltage setting, the output drops at a rate
determined by the load and the output capacitance. The
internal target still ramps as before, and PWRGD
remains blanked high impedance until 20µs after the
output voltage reaches the internal target. Once this
time expires, PWRGD monitors only the lower threshold:
Output-Voltage-Transition Timing
At the beginning of an output-voltage transition, the
MAX17030/MAX17036 blank both PWRGD thresholds,
preventing the PWRGD open-drain output from chang-
ing states during the transition. The controller enables
the lower PWRGD threshold approximately 20µs after
the slew-rate controller reaches the target output volt-
age, but the upper PWRGD threshold is enabled only if
the controller remains in forced-PWM operation. If the
controller enters pulse-skipping operation, the upper
PWRGD threshold remains blanked. The slew rate (set
•
Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX17030/MAX17036 quickly slew (50mV/µs min
regardless of R
setting) the internal target volt-
TIME
by resistor R
) must be set fast enough to ensure
TIME
age to the DAC code provided by the processor as
long as the output voltage is above the new target.
The controller remains in skip mode until the output
voltage equals the internal target. Once the internal
target reaches the output voltage, phase 2 is
enabled. The controller blanks PWRGD and CLKEN
(forced high impedance) until 20µs after the transi-
tion is completed. See Figure 5.
that the transition can be completed within the maxi-
mum allotted time.
The MAX17030/MAX17036 automatically control the cur-
rent to the minimum level required to complete the transi-
tion. The total transition time depends on R
, the
TIME
voltage difference, and the accuracy of the slew-rate
controller (C accuracy). The slew rate is not depen-
SLEW
dent on the total output capacitance, as long as the
surge current is less than the current limit. For all dynam-
•
Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the out-
put voltage is regulating to the deeper sleep volt-
age, the MAX17030/MAX17036 immediately
activate all enabled phases and ramp the output
voltage to the LFM DAC code provided by the
ic VID transitions, the transition time (t ) is given by:
TRAN
V
− V
NEW
OLD
t
=
TRAN
dV
dt
(
)
TARGET
processor at the slew rate set by R
. The con-
TIME
where dV
/dt = 12.5mV/µs × 71.5kΩ/R
is the
TIME
TARGET
troller blanks PWRGD and CLKEN (forced high
impedance) until 20µs after the transition is com-
pleted. See Figure 6.
slew rate, V
is the original output voltage, and V
OLD
is the new target voltage. See TIME Slew-RNaEtWe
Accuracy in the Electrical Characteristics for slew-rate
limits. For soft-start and shutdown, the controller auto-
matically reduces the slew rate to 1/4.
______________________________________________________________________________________ 27
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ACTUAL V
OUT
CPU CORE
VOLTAGE
INTERNAL TARGET
DEEPER SLEEP VID
VID (D0–D6)
DPRSLPVR
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE)
FORCED-PWM
DH1
DH2
NO PULSES: V
> V
TARGET
OUT
PWM3
PWRGD
CLKEN
OVP
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK HIGH THRESHOLD ONLY
BLANK HI-Z
BLANK LO
SET TO 1.5V MIN
TRACKS INTERNAL TARGET
/MAX17036
t
t
BLANK
BLANK
20µs typ
20µs typ
Figure 5. C4E (C4 Early Exit) Transition
ACTIVE VID
CPU CORE
ACTUAL V
OUT
LFM VID
INTERNAL
VOLTAGE
TARGET
DPRSLP VID
VID (D0–D6)
LFM VID
DEEPER SLEEP VID
DPRSLPVR
DO NOT CARE (DPRSLPVR DOMINATES STATE)
1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE)
NO PULSES: V > V
PSI
INTERNAL
PWM CONTROL
FORCED-PWM
DH1
OUT
TARGET
DH2
PWM3
PWRGD
CLKEN
OVP
BLANK HIGH-Z
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
SET TO 1.5V MIN
TRACKS INTERNAL TARGET
t
t
BLANK
BLANK
20µs TYP
20µs TYP
Figure 6. Standard C4 Transition
28 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Forced-PWM operation comes at a cost: the no-load
+5V bias supply current remains between 10mA to
50mA per phase, depending on the external MOSFETs
and switching frequency. To maintain high efficiency
under light-load conditions, the processor can switch
the controller to a low-power pulse-skipping control
scheme by entering suspend mode.
PSI Transitions
When PSI is pulled low, the MAX17030/MAX17036
immediately disable phase 3 (PWM3 three-state,
DRSKP forced low) and enter 2-phase PWM operation
(see Figure 7). When PSI is pulled high, the MAX17030/
MAX17036 enable phase 3.
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation—when the
CPU is actively running (DPRSLPVR = low, Table 5)—
the MAX17030/MAX17036 operate with the low-noise,
forced-PWM control scheme. Forced-PWM operation
disables the zero-crossing comparators of all active
phases, forcing the low-side gate-drive waveforms to
constantly be the complement of the high-side gate-
drive waveforms. This keeps the switching frequency
constant and allows the inductor current to reverse
under light loads, providing fast, accurate negative out-
put-voltage transitions by quickly discharging the output
capacitors.
PSI determines how many phases are active when oper-
ating in forced-PWM mode (DPRSLPVR = low). When PSI
is pulled low, phases 1 and 2 remain active but phase 3
is disabled (PWM3 three-state, DRSKP forced low).
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
During soft-start and normal operation when
DPRSLPVR is pulled high, the MAX17030/MAX17036
operate with a single-phase pulse-skipping mode. The
pulse-skipping mode enables the driver’s zero-crossing
comparator, so the controller pulls DL1 low when its cur-
rent-sense inputs detect “zero” inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output.
CPU FREQ
CPU LOAD
VID (D0–D6)
CPU CORE
VOLTAGE
PSI
DH1
DH2
PWM3 THREE-STATE
PWM3
BLANK HIGH-Z
BLANK LOW
BLANK HIGH-Z
PWRGD
CLKEN
BLANK LOW
180° OUT-OF-PHASE
t
t
BLANK
BLANK
20µs typ
20µs typ
Figure 7. PSI Transition
______________________________________________________________________________________ 29
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
When pulse-skipping, the controller blanks the upper
PWRGD and CLKEN thresholds. Upon entering pulse-
skipping operation, the controller temporarily sets the
OVP threshold to 1.5V, preventing false OVP faults
when the transition to pulse-skipping operation coin-
cides with a VID code change. Once the error amplifier
detects that the output voltage is in regulation, the OVP
threshold tracks the selected VID DAC code. The
MAX17030/MAX17036 automatically use forced-PWM
operation during soft-start and soft shutdown, regard-
less of the DPRSLPVR and PSI configuration.
low duty cycles. The total load-current at the PFM/PWM
crossover threshold (I ) is approximately:
LOAD(SKIP)
⎛
⎞
T
V
L
V
- V
⎛
⎞
SW OUT
IN OUT
I
=
LOAD(SKIP)
⎜
⎝
⎟
⎠
⎜
⎟
2 × V
IN
⎝
⎠
Power-Up Sequence (POR, UVLO)
The MAX17030/MAX17036 are enabled when SHDN is
driven high (Figure 9). The reference powers up first.
Once the reference exceeds its undervoltage-lockout
(UVLO) threshold, the internal analog blocks are turned
on and masked by a 150µs one-shot delay. The PWM
controller then begins switching.
Automatic Pulse-Skipping Switchover
In skip mode (DPRSLPVR = high), an inherent automatic
switchover to PFM takes place at light loads (Figure 8).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
senses the inductor current across the low-side
VIN – VOUT
L
∆I
∆t
=
MOSFETs. Once V drops below the zero-crossing
LX
comparator threshold (see the Electrical Characteristics),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation. The PFM/PWM crossover occurs when the
load current of each phase is equal to 1/2 the peak-to-
peak ripple current, which is a function of the inductor
value (Figure 8). For a battery input range of 7V to 20V,
this threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
/MAX17036
I
PEAK
= I
I
/2
LOAD PEAK
0
ON-TIME
TIME
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
V
CC
SHDN
IGNORE
VID
IGNORE
VID
VID (D0–D6)
SOFT-START
1/4 SLEW RATE SET
BY R
SOFT-SHUTDOWN
1/4 SLEW RATE SET
TIME
BY R
TIME
V
CORE
INTERNAL
PWM CONTROL
PULSE-SKIPPING
FORCED-PWM
CLKEN
IMVPOK
t
t
BLANK
5ms TYP
BLANK
t
BLANK
60µs TYP
t
20µs TYP
BLANK
20µs TYP
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
3± ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
Power-on reset (POR) occurs when V
rises above
Current Monitor (IMON)
The MAX17030/MAX17036 include a unidirectional
transconductance amplifier that sources current pro-
portional to the positive current-sense voltage. The
IMON output current is defined by:
CC
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The V UVLO circuitry
CC
inhibits switching until V
rises above 4.25V. The con-
CC
troller powers up the reference once the system
enables the controller, V is above 4.25V, and SHDN
CC
I
= G
x Σ(V
- V
)
CSN
IMON
m(IMON)
CSP
driven high. With the reference in regulation, the con-
troller ramps the output voltage to the boot voltage
where Gm(IMON) = 1.6mS (typ) and the IMON current is
unidirectional (sources current out of IMON only) for
positive current-sense values. For negative current-
sense voltages, the IMON current is zero.
(1.1V) at 1/4 the slew rate set by R
:
TIME
4V
BOOT
t
=
TRAN(START)
dV
dt
Connect an external resistor between IMON and GNDS
to create the desired IMON gain based on the following
equation:
(
)
TARGET
where dV
/dt = 12.5mV/µs x 71.5kΩ/R
is the
TARGET
slew rate. The soft-start circuitry does not useTaIMvEariable
current limit, so full output current is available immedi-
ately. CLKEN is pulled low approximately 60µs after the
MAX17030/MAX17036 reach the boot voltage. At the
same time, the MAX17030/MAX17036 slew the output
to the voltage set at the VID inputs at the programmed
slew rate. PWRGD becomes high impedance approxi-
mately 5ms after CLKEN is pulled low. The MAX17030/
MAX17036 automatically operate in pulse-skipping
mode during soft-start, and use forced-PWM operation
during soft-shutdown, regardless of the DPRSLPVR and
PSI configuration.
R
= 0.9V/(I
x R
x G
)
m(IMON_MIN)
IMON
MAX
SENSE(MIN)
where I
is defined in the Current Monitor section of
MAX
the Intel IMVP-6.5 specification and based on discrete
increments (10A, 20A, 30A, 40A, etc.), R
is
SENSE(MIN)
the minimum effective value of the current-sense ele-
ment (sense resistor or inductor DCR) that is used to
provide the current-sense voltage, and G
m(IMON_MIN)
is the minimum transconductance amplifier gain as
defined in the Electrical Characteristics.
The IMON voltage is internally clamped to a maximum
of 1.1V (typ), preventing the IMON output from exceed-
ing the IMON voltage rating even under overload or
short-circuit conditions. When the controller is disabled,
IMON is pulled to ground.
If the V
voltage drops below 4.25V, the controller
CC
assumes that there is not enough supply voltage to make
valid decisions, and shuts down immediately. DH and DL
are forced low, and CSNI 10Ω discharge FET is enabled.
The transconductance amplifier and voltage clamp are
internally compensated, so IMON cannot directly drive
large capacitance values. To filter the IMON signal, use
an RC filter as shown in Figure 1.
Shutdown
When SHDN goes low, the MAX17030/MAX17036
enters low-power shutdown mode. PWRGD is pulled
low immediately, and the output voltage ramps down at
Temperature Comparator (VRHOT)
The MAX17030/MAX17036 also feature an independent
1/4 the slew rate set by RTIME
:
comparator with an accurate threshold (V
) that
HOT
4V
OUT
tracks the analog supply voltage (V
= 0.3V ). This
HOT
CC
t
=
TRAN(SHDN)
makes the thermal trip threshold independent of the V
dV
dt
(
)
CC
TARGET
supply voltage tolerance. Use a resistor- and thermistor-
divider between V and GND to generate a voltage-
where dV
/dt = 12.5mV/µs x 71.5kΩ/R
TARGET
is the
TIME
CC
slew rate. After the output voltage drops to 12.5mV, the
MAX17030/MAX17036 shut down completely—the dri-
vers are disabled (DL1 and DL2 driven low, PWM3 is
three-state, and DRSKP low), the reference turns off,
10Ω CSNI discharge FET is turned on, and the supply
current drops below 1µA.
regulator overtemperature monitor. Place the thermistor
as close to the MOSFETs and inductors as possible.
Fault Protection (Latched)
Output Overvoltage Protection
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17030/MAX17036 continuously monitor the
output for an overvoltage fault. An OVP fault is detected
if the output voltage exceeds the set VID DAC voltage
by more than 300mV, or the fixed 1.5V (typ) threshold
When an undervoltage fault condition activates the shut-
down sequence, the protection circuitry sets the fault
latch to prevent the controller from restarting. To clear
the fault latch and reactivate the controller, toggle SHDN
or cycle V
power below 0.5V.
CC
______________________________________________________________________________________ 31
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
during a downward VID transition in skip mode. During
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold tracks the VID DAC voltage as soon as the
output is in regulation; otherwise, the fixed 1.5V (typ)
threshold is used.
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—over-
voltage protection, undervoltage protection, and ther-
mal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
When the OVP circuit detects an overvoltage fault while
in multiphase mode (DPRSLPVR = low, PSI = high), the
MAX17030/MAX17036 immediately force DL1 and DL2
high, PWM3 low, and DRSKP high; and pull DH1 and
DH2 low. This action turns on the synchronous-rectifier
MOSFETs with 100% duty and, in turn, rapidly dis-
charges the output filter capacitor and forces the output
low. If the condition that caused the overvoltage (such
as a shorted high-side MOSFET) persists, the battery
fuse blows. Toggle SHDN or cycle the VCC power supply
below 0.5V to clear the fault latch and reactivate the con-
troller.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
OUT
-
IN
V
differential exists. The high-side gate drivers (DH)
source 2.7A and sink 2.2A, and the low-side gate dri-
vers (DL) source 2.7A and sink 8A. This ensures robust
gate drive for high-current applications. The DH_ float-
ing high-side MOSFET drivers are powered by internal
boost switch charge pumps at BST_, while the DL_ syn-
chronous-rectifier drivers are powered directly by the
When an overvoltage fault occurs while in 1-phase
operation (DPRSLPVR = high, or PSI = low), the
MAX17030/MAX17036 immediately force DL1 high and
pull DH1 low. DL2 and DH2 remain low as phase 2 was
disabled. DL2 does not react.
/MAX17036
5V bias supply (V ).
DD
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
Output Undervoltage Protection
If the MAX17030/MAX17036 output voltage is 400mV
below the target voltage, the controller activates the
shutdown sequence and sets the fault latch. Once the
output voltage ramps down to 12.5mV, it forces the DL1
and DL2 low and pulls DH1 and DH2 low, three-states
PWM3, and sets DRSKP low 10Ω CSNI discharge FET
A low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates is required for the
adaptive dead-time circuits to work properly; otherwise,
the sense circuitry in the MAX17030/MAX17036 inter-
prets the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
is turned on. Toggle SHDN or cycle the V
power
CC
supply below 0.5V to clear the fault latch and reactivate
the controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
The DL low on-resistance of 0.25Ω (typ) helps prevent
DL from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
inductor node (LX) quickly switches from ground to VIN.
The capacitive coupling between LX and DL created by
Thermal-Fault Protection
The MAX17030/MAX17036 feature a thermal fault-pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor sets the fault latch and
forces the DL1 and DL2 low and pulls DH1 and DH2
low, three-states PWM3, sets DRSKP low, and enables
10Ω CSNI discharge FET on. Toggle SHDN or cycle the
the MOSFET’s gate-to-drain capacitance (C
), gate-
RSS
to-source capacitance (C
- C
), and additional
ISS
RSS
board parasitics should not exceed the following mini-
mum threshold to prevent shoot-through currents:
V
power supply below 0.5V to clear the fault latch
CC
⎛
⎞
C
C
and reactivate the controller after the junction tempera-
ture cools by 15°C.
RSS
V
> V
IN(MAX)
GS(TH)
⎜
⎟
⎝
⎠
ISS
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
Adding a 4700pF between DL and power ground (CNL
in Figure 10), close to the low-side MOSFETs, greatly
reduces coupling. Do not exceed 22nF of total gate
capacitance to prevent excessive turn-off delays.
32 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
•
Maximum load current: There are two values to
consider. The peak load current (I ) deter-
(R )*
BST
LOAD(MAX)
BST_
INPUT (V
)
mines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
IN
C
BST
DH_
LX_
N
H
L
ous load current (I
) determines the thermal
LOAD
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
C
BYP
V
DD
erally exhibit I
= I
x 80%.
LOAD
LOAD(MAX)
For multiphase systems, each phase supports a
fraction of the load, depending on the current bal-
ancing. When properly balanced, the load current is
evenly distributed among each phase:
DL_
N
L
(C )*
NL
PGND
I
η
LOAD
I
=
MAX17030/MAX17036
LOAD(PHASE)
TOTAL
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
BST
SWITCHING NODE RISE TIME.
(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
NL
η
TOTAL
where
is the total number of active phases.
•
•
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENT.
Figure 10. Gate Drive Circuit
are proportional to frequency and V 2. The opti-
IN
Shoot-through currents can also be caused by a com-
bination of fast high-side MOSFETs and slow low-side
MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading the
mum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 30% and 50% ripple current. for a multi-
phase core regulator, select an LIR value of ~0.4.
turn-off time (R
in Figure 10). Slowing down the
BST
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple-current ratio). The pri-
mary design trade-off lies in choosing a good switching
frequency and inductor operating point, and the following
four factors dictate the rest of the design:
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
•
Input voltage range: The maximum value
(V ) must accommodate the worst-case high
⎛
⎞
⎛
⎝
⎞
⎠
V
− V
V
OUT
IN(MAX)
IN
OUT
L = η
⎜
⎟
TOTAL
⎜
⎟
AC adapter voltage. The minimum value (V
)
IN(MIN)
f
I
LIR
V
⎝
⎠
SW LOAD(MAX)
IN
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
η
where
is the total number of phases.
TOTAL
______________________________________________________________________________________ 33
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The core
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
must not to saturate at the peak inductor current (I
):
PEAK
I
⎛
⎞
LIR
2
⎛
⎞
LOAD(MAX)
I
=
1+
⎜
⎝
⎟
⎠
PEAK
⎜
⎟
η
⎝
⎠
TOTAL
f
SW
π
f
≤
ESR
Output Capacitor Selection
Output capacitor selection is determined by the con-
troller stability requirements, and the transient soar and
sag requirements of the application.
where:
1
f
=
ESR
2πR
C
Output Capacitor ESR
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
EFF OUT
and:
R
= R
+ R
+ R
DROOP PCB
EFF
ESR
In CPU V
converters and other applications where
CORE
where C
is the total output capacitance, R
is the
OUT
ESR
is the volt-
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance:
total equivalent series resistance, R
DROOP
age-positioning gain, and R
resistance between the output capacitors and sense
resistors.
is the parasitic board
PCB
/MAX17036
V
STEP
LOAD(MAX)
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
R
(
+ R
≤
PCB
)
ESR
∆I
The output ripple voltage of a step-down controller
equals the total inductor ripple current multiplied by the
output capacitor’s ESR. When operating multiphase
systems out-of-phase, the peak inductor currents of
each phase are staggered, resulting in lower output rip-
ple voltage by reducing the total inductor ripple current.
For multiphase operation, the maximum ESR to meet
ripple requirements is:
a 30mV
ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four
P-P
330µF/2.5V Panasonic SP (type SX) capacitors in paral-
lel provide 1.5mΩ (max) ESR. With a 2mΩ droop and
0.5mΩ PCB resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high ESR zero frequency, but
applications with significant voltage positioning can take
advantage of their size and low ESR. When using only
⎡
⎢
⎤
⎥
V f
L
IN SW
R
≤
V
RIPPLE
ESR
V
− η
V V
(
)
⎢
⎣
⎥
⎦
IN
TOTAL OUT OUT
ceramic output capacitors, output overshoot (V
)
SOAR
η
where
is the total number of active phases and
TOTAL
typically determines the minimum output capacitance
requirement. Their relatively low capacitance value
favors high switching-frequency operation with small
inductor values to minimize the energy transferred from
inductor to capacitor during load-step recovery.
fSW is the switching frequency per phase. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usu-
ally selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent VSAG and VSOAR from causing prob-
lems during load transients. Generally, once enough
capacitance is added to meet the overshoot require-
ment, undershoot at the rising load edge is no longer a
problem (see the V
Transient Response section).
and V
equations in the
SOAR
SAG
34 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
The multiphase Quick-PWM controllers operate out-of-
phase, reducing the RMS input. For duty cycles less
η
than 100%/
per phase, the IRMS requirements
OUTPH
can be determined by the following equation:
The easiest method for checking stability is to apply a
very fast 10% to 90% max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
⎛
⎞
I
LOAD
I
=
η
V
V
− η V
TOTAL OUT
(
)
RMS
TOTAL OUT IN
⎜
⎟
η
V
⎝
⎠
TOTAL IN
η
where
is the total number of out-of-phase
switching regulators. The worst-case RMS current
TOTAL
requirement occurs when operating with VIN
=
Transient Response
η
2
V
RMS
. At this point, the above equation simpli-
TOTAL OUT
The inductor ripple current impacts transient-response
η
fies to I
= 0.5 x I
/
. Choose an input
LOAD TOTAL
performance, especially at low V - V
differentials.
IN
OUT
capacitor that exhibits less than +10°C temperature rise
at the RMS input current for optimal circuit longevity.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac-
tor, which can be calculated from the on-time and mini-
mum off-time. For a dual-phase controller, the
worst-case output sag voltage can be determined by:
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters.
High-Side MOSFET Power Dissipation
The conduction loss in the high-side MOSFET (NH) is a
function of the duty factor, with the worst-case power
dissipation occurring at the minimum input voltage:
2
L ∆I
(
)
T
LOAD(MAX)
MIN
V
≈
×
SAG
2η
C
V
KT − T
⎡
⎣
⎤
TOTAL OUT OUT
SW MIN ⎦
2
and:
where t
⎛
⎜
⎞
⎛
⎝
⎞
⎟
V
V
I
η
OUT
LOAD
T
= t
+ t
ON OFF(MIN)
MIN
PD (NH Resistive) =
R
DS(ON)
⎟
⎜
⎠ ⎝
⎠
IN
TOTAL
is the minimum off-time (see the
OFF(MIN)
Electrical Characteristics), T
η
is the programmed
where
is the total number of phases.
SW
TOTAL
η
switching period, and
active phases. K = 66% when N
is the total number of
TOTAL
Calculating the switching losses in the high-side
MOSFET (N ) is difficult since it must allow for difficult
H
= 3, and K = 100%
PH
when N
= 2. V
must be less than the transient
.
DROOP
PH
droop ∆I
SAG
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PCB layout characteristics. The follow-
ing switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on NH:
x R
LOAD(MAX)
The capacitive soar voltage due to stored inductor
energy can be calculated as:
2
∆I
L
(
)
LOAD(MAX)
V
≈
SOAR
2η
C
V
TOTAL OUT OUT
η
where
is the total number of active phases. The
Q
I
⎛
⎞ ⎛
⎞
TOTAL
V I
f
G(SW)
IN LOAD SW
PD (NH Switching) =
actual peak of the soar voltage is dependent on the
time where the decaying ESR step and rising capaci-
tive soar is at its maximum. This is best simulated or
measured. For the MAX17036 with transient suppres-
sion, contact Maxim directly for application support to
determine the output capacitance requirement.
⎜
⎟ ⎜
⎟
η
⎝
⎠ ⎝
⎠
TOTAL
GATE
2
C
V
f
OSS IN SW
2
+
where COSS is the N MOSFET’s output capacitance,
H
Q
is the charge needed to turn on the N
G(SW)
H
MOSFET, and I
is the peak gate-drive source/sink
GATE
current (2.2A typ).
______________________________________________________________________________________ 3.
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
The optimum high-side MOSFET trades the switching
where N is the number of high-side MOSFETs used for
one regulator, and Q is the gate charge specified
in the MOSFET’s data sheet. For example, assume (1)
FDS6298 n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6298 has a maximum gate charge of 19nC
losses with the conduction (R
) losses over the
DS(ON)
GATE
input voltage range. Ideally, the losses at V
IN(MIN)
, with
should be roughly equal to losses at V
IN(MAX)
lower losses in between. If V does not vary over a
IN
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
(V
= 5V). Using the above equation, the required
GS
boost capacitance would be:
Low-Side MOSFET Power Dissipation
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
1×10nC
200mV
C
=
= 0.05µF
BST
2
⎡
⎤
⎥
⎛
⎞
⎛
⎞
V
I
η
Selecting the closest standard value; this example
requires a 0.1µF ceramic capacitor.
OUT
LOAD
PD (NL Resistive) =⎢1−
R
DS(ON)
⎜
⎟
⎜
⎟
V
⎝
⎠
⎢
⎣
⎥
⎦
⎝
⎠
IN(MAX)
TOTAL
Current Limit and Slew-Rate Control
(TIME and ILIM)
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than I
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, the circuit can be overdesigned to tolerate:
LOAD(MAX)
TIME and ILIM are used to control the slew rate and
current limit. TIME regulates to a fixed 2.0V. The
MAX17030/MAX17036 use the TIME source current to
set the slew rate (dV
/dt). The higher the source
TARGET
∆I
⎛
⎝
⎞
current, the faster the output-voltage slew rate:
INDUCTOR
2
/MAX17036
I
= η
I
+
LOAD
TOTAL ⎜ VALLEY(MAX)
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
71.5kΩ
dV
dt = 12.5mV µs ×
I
LIR
TARGET
⎛
⎞
LOAD(MAX)
2
R
TIME
= η
I
+
TOTAL VALLEY(MAX)
⎜
⎟
⎝
⎠
where R
is the sum of resistance values between
TIME
where I
is the maximum valley current
VALLEY(MAX)
TIME and ground.
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
The ILIM voltage determines the valley current-sense
threshold. When ILIM = V , the controller uses the
CC
22.5mV preset current-limit threshold. In an adjustable
design, ILIM is connected to a resistive voltage-
divider connected between TIME and ground. The dif-
ferential voltage between TIME and ILIM sets the cur-
rent-limit threshold (VLIMIT), so the valley current-sense
threshold:
Choose a low-side MOSFET that has the lowest possible
on-resistance (R
), comes in a moderate-sized
DS(ON)
package (i.e., one or two thermally enhanced 8-pin SOs),
and is reasonably priced. Make sure that the DL gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-to-
drain capacitor caused by the high-side MOSFET turning
on; otherwise, cross-conduction problems might occur
(see the MOSFET Gate Drivers section).
V
− V
ILIM
10
TIME
V
=
LIMIT
This allows design flexibility since the DCR sense circuit
or sense resistor does not have to be adjusted to meet
the current limit as long as the current-sense voltage
never exceeds 50mV. Keeping VLIMIT between 20mV to
40mV leaves room for future current-limit adjustment.
The optional Schottky diode (D ) should have a low for-
L
ward voltage and be able to handle the load current
per phase during the dead times.
Boost Capacitors
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
The boost capacitors (C
) must be selected large
BST
enough to handle the gate-charging requirements of
the high-side MOSFETs. Select the boost capacitors to
avoid discharging the capacitor more than 200mV while
charging the high-side MOSFETs’ gates:
ley of the inductor current occurs at I
half the ripple current; therefore:
minus
LOAD(MAX)
LIR
2
⎛
⎞
N× Q
I
> I
1−
GATE
200mV
⎜
⎝
⎟
⎠
VALLEY
LOAD(MAX)
C
=
BST
36 ______________________________________________________________________________________
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
/MAX17036
where:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
V
LIMIT
I
=
VALLEY
R
SENSE
2) Connect all analog grounds to a separate solid cop-
per plane, which connects to the ground pin of the
Quick-PWM controller. This includes the VCC bypass
capacitor, FB, and GNDS bypass capacitors.
where R
tor DCR.
is the sensing resistor or effective induc-
SENSE
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCB (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The MAX17030/MAX17036 use a
transconductance amplifier to set the transient and DC
output voltage droop (Figure 3) as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and
allows smaller current-sense resistance to be used,
reducing the overall power dissipated.
4) Keep the high current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
Steady-State ꢀoltage Positioning
5) CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
Connect a resistor (R ) between FB and V
to set
FB
OUT
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R ):
DROOP
R
DROOP
R
=
6) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
FB
R
G
SENSE m(FB)
where the effective current-sense resistance (R
)
SENSE
depends on the current-sense method (see the Current
Sense section), and the voltage positioning amplifier’s
transconductance (G
) is typically 400µS as
m(FB)
defined in the Electrical Characteristics table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
7) Route high-speed switching nodes away from sen-
sitive analog areas (FB, CSP_, CSN_, etc.).
When the inductors’ DCR is used as the current-sense
Layout Procedure
1) Place the power components first, with ground ter-
element (R
= R
), each current-sense input
DCR
SENSE
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
minals adjacent (low-side MOSFET source, C
OUT
,
IN
C
, and D1 anode). If possible, make all these
Applications Information
connections on the top layer with wide, copper-
filled areas.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17030 Evaluation Kit specifi-
cation for a layout example and follow these guidelines
for good PCB layout:
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50mils to 100mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST diodes and
capacitors, V
bypass capacitor) together near
DD
the controller IC.
______________________________________________________________________________________ 37
1/2/3 Phase-Quick-PWM
IMVP-6.5 VID Controllers
4) Make the DC-DC controller ground connections as
shown in the standard application circuits. This dia-
gram can be viewed as having four separate ground
planes: input/output ground, where all the high-
power components go; the power ground plane,
Chip Information
PROCESS: BiCMOS
where the GND pin and V
bypass capacitor go;
DD
the master’s analog ground plane, where sensitive
analog components, the master’s GND pin and V
CC
Package Information
bypass capacitor go; and the slave’s analog ground
plane, where the slave’s GND pin and V bypass
For the latest package outline information and land patterns, go
CC
to www0maxim-ic0com/packages.
capacitor go. The master’s GND plane must meet
the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the high-
power output ground with a short metal trace from
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO0
40 TQFN-EP
T4055-2
21-±14±
5) Connect the output power planes (V
and sys-
CORE
/MAX17036
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明