MAX17201X+ [MAXIM]
Power Supply Support Circuit,;
| 型号： | MAX17201X+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Support Circuit, |
| 文件： | 总115页 (文件大小：4657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
General Description
Benefits and Features
The MAX1720x/MAX1721x are ultra-low power stand-alone
fuel gauge ICs that implement the Maxim ModelGauge™
m5 algorithm without requiring host interaction for configura-
tion. This feature makes the MAX1720x/MAX1721x excellent
pack-side fuel gauges. The MAX17201/MAX17211 monitor a
single cell pack. The MAX17205/MAX17215 monitor and bal-
ance a 2S or 3S pack or monitor a multiple-series cell pack.
● ModelGauge m5 Algorithm
• Eliminates Error when Approaching Empty Voltage
• Eliminates Coulomb-Counter Drift
• Current, Temperature, and Age Compensated
• Does Not Require Empty, Full, or Idle States
• No Characterization Required for EZ Performance
(See the ModelGauge m5 EZ Performance Section)
• Cycle+ Age Forecasting Observes Lifespan
To prevent battery pack cloning, the ICs integrate SHA-
256 authentication with a 160-bit secret key. Each IC
incorporates a unique 64-bit ID.
● Nonvolatile Memory for Stand-Alone Operation
• Learned Parameters and History Logging
• Up to 75 Words Available for User Data
The ModelGauge™ m5 algorithm combines the short-term
accuracy and linearity of a coulomb counter with the long-
term stability of a voltage-based fuel gauge, along with
temperature compensation to provide industry-leading
fuel gauge accuracy. The IC automatically compensates
for cell aging, temperature, and discharge rate, and pro-
vides accurate state of charge (SOC) in milliampere-hours
(mAh) or percentage (%) over a wide range of operating
conditions. As the battery approaches the critical region
near empty, the ModelGauge m5 algorithm invokes a spe-
cial error correction mechanism that eliminates any error.
The ICs provide accurate estimation of time-to-empty and
time-to-full, Cycle+™ age forecast, and three methods
for reporting the age of the battery: reduction in capacity,
increase in battery resistance, and cycle odometer.
● Precision Measurement System
• No Calibration Required
● Time-to-Empty and Time-to-Full Estimation
● Temperature Measurement
• Die Temperature
• Up to Two External Thermistors
● Multiple Series Cell Pack Operation
● Low Quiescent Current
• MAX172x1: 18µA Active, 9µA Hibernate
• MAX172x5: 25µA Active, 12µA Hibernate
● Alert Indicator for Voltage, SOC, Temperature,
Current, and 1% SOC Change
● High-Speed Overcurrent Comparators
● Predicts Remaining Capacity Under Theoretical Load
● SHA-256 Authentication
The ICs provide precision measurements of current, voltage,
and temperature. Temperature of the battery pack is mea-
sured using an internal temperature measurement and up to
two external thermistors supported by ratiometric measure-
2
● Maxim 1-Wire or 2-Wire (I C) Interface
®
ments on auxiliary inputs. A Maxim 1-Wire (MAX17211/
2
● SBS 1.1 Compatible Register Set
MAX17215) or 2-wire I C (MAX17201/MAX17205) inter-
face provides access to data and control registers. The ICs
are available in lead-free, 3mm x 3mm, 14-pin TDFN and
1.6mm x 2.4mm 15-bump WLP packages.
Applications
● Smartphones and Tablets
● Portable Game Players
● e-Readers
Ordering Information appears at end of data sheet.
● Digital Still and Video Cameras
● Handheld Computers and Terminals
● Portable Medical Equipment
● Handheld Radios
ModelGauge and Cycle+ are trademarks and 1-Wire is a regis-
tered trademark of Maxim Integrated Products, Inc.
19-8424; Rev 2; 8/16
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Simplified Block Diagram
PACK+
10Ω
V
BATT
REG3
CELL1
CELL2
CELLx
0.1µF
DQ/SDA
COMMUNICATION
INTERFACE
OD/SCL
+
REG2
0.47µF
SINGLE-CELL
EXAMPLE
MAX17201
GND (WLP)
PACK PROTECTOR
CSP
CSN
EP (TDFN)
PACK-
R
SENSE
Maxim Integrated
│ 2
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings (TDFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings (WLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin/Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Description Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Standard Register Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Nonvolatile Backup and Initial Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Alternate Initial and Factory Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical Operating Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Single-Cell Typical Operating Circuit (MAX17201/MAX17211 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Multicell Typical Operating Circuits (MAX17205/MAX17215 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Cell Balancing Typical Operating Circuits (MAX17205/MAX17215 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ModelGauge m5 Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
ModelGauge m5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
ModelGauge m5 Algorithm Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RepCap Register (005h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RepSOC Register (006h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
FullCapRep Register (035h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
TTE Register (011h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
TTF Register (020h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Age Register (007h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Cycles Register (017h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
TimerH Register (0BEh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
FullCap Register (010h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
nFullCapNom Register (1A5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
RCell Register (014h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
VRipple Register (0BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
nSOC Register (1AEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
nVoltTemp Register (1AAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Maxim Integrated
│ 3
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
ModelGauge m5 EZ Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
OCV Estimation and Coulomb Count Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Empty Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
End-of-Charge Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fuel Gauge Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Converge-to-Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Determining Fuel Gauge Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Initial Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Cycle+ Age Forecasting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
nAgeFcCfg Register (1D2h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
AgeForecast Register (0B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Age Forecasting Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Enabling Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Battery Life Logging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Life-Logging Data Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Determining Number of Valid Logging Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reading History Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
History Data Reading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
ModelGauge m5 Algorithm Model Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nXTable0 (180h) to nXTable11 (18Bh) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nOCVTable0 (190h) to nOCVTable11 (19Bh) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nQRTable00 (1A0h) to nQRTable30 (1A3h) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nFullSOCThr Register (1C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nVEmpty Register (19Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nDesignCap Register(1B3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
nRFastVShdn Register (1D5h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
nIChgTerm Register (19Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
nRComp0 Register (1A6h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
nTempCo Register (1A7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
nIAvgEmpty Register (1A8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ModelGauge m5 Algorithm Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
nFilterCfg Register (19Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
nRelaxCfg Register (1B6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
nLearnCfg Register (19Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
nMiscCfg Register (1B2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
nTTFCfg Register (1C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
nConvgCfg Register (1B7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
nRippleCfg Register (1B1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Maxim Integrated
│ 4
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
ModelGauge m5 Algorithm Additional Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Timer Register (03Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
dQAcc Register (045h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
dPAcc Register (046h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
QResidual Register (00Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
VFSOC Register (0FFh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
VFOCV Register (0FBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
QH Register (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
AvCap Register (01Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
AvSOC Register (00Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
MixSOC Register (00Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
MixCap Register (00Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
VFRemCap Register (04Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
FStat Register (03Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Status and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
DevName Register (021h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
nROMID0 (1BCh)/nROMID1 (1BDh)/nROMID2 (1BEh)/nROMID3 (1BFh) Registers . . . . . . . . . . . . . . . . . . . . . 58
nRSense Register (1CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
nPackCfg Register (1B5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
nNVCfg0 Register (1B8h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
nNVCfg1 Register (1B9h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
nNVCfg2 Register (1BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
ShdnTimer Register (03Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
nConfig Register (1B0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Status Register (000h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Status2 Register (0B0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
nHibCfg Register (1B4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CommStat Register (061h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Cell Balancing (MAX17205/MAX17215 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Cell Balancing Window of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Cell Balancing Order and Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Cell Balancing Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Cell Balancing Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Analog Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Voltage Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
VCell Register (009h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maxim Integrated
│ 5
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
AvgVCell Register (019h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MaxMinVolt Register (01Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Cell1 (0D8h)/Cell2 (0D7h)/Cell3 (0D6)/Cell4 (0D5h) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AvgCell1 (0D4h)/AvgCell2 (0D3h)/AvgCell3 (0D2h)/AvgCell4 (0D1h) Registers. . . . . . . . . . . . . . . . . . . . . . . . . 71
CellX Register (0D9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Batt Register (0DAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Current Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MaxMinCurr Register (01Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
nCGain Register (1C8h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
CGTempCo Register (16Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Copper Trace Current Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Temperature Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Temperature Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
AvgTA Register (016h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MaxMinTemp Register (01Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
nTCurve Register (1C9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
nTGain (1CAh) Register/nTOff (1CBh) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Temp1 (134h)/Temp2 (13Bh)/IntTemp (135h) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AvgTemp1 (137h)/AvgTemp2 (139h)/AvgIntTemp (138h) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AIN0 Register (027h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
At-Rate Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AtRate Register (004h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AtQResidual Register (0DCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AtTTE Register (0DDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AtAvSOC Register (0CEh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AtAvCap Register (0DFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Overcurrent Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
nODSCTh Register (18Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
nODSCCfg Register (18Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Alert Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
nVAlrtTh Register (1C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
nTAlrtTh Register (1C1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
nSAlrtTh Register (1C2h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
nIAlrtTh Register (1C3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ModelGauge m5 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Maxim Integrated
│ 6
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
Shadow RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Nonvolatile Memory Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
COPY NV BLOCK [E904h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
NV RECALL [E001h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
HISTORY RECALL [E2XXh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Nonvolatile Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Determining the Number of Remaining Updates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
General-Purpose Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Memory Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
NV LOCK [6AXXh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Locking Memory Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Reading Lock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Smart Battery Compliant Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
SBS Compliant Memory Space (MAX1720x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
sFirstUsed Register (136h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
sCell1 (13Fh)/sCell2 (13Eh)/sCell3 (13Dh)/sCell4 (13Ch) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
sAvgCell1 (14Fh)/sAvgCell2 (14Eh)/sAvgCell3 (14Dh)/sAvgCell4 (14Ch) Registers . . . . . . . . . . . . . . . . . . . . . . 91
sAvCap Register (167h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
sMixCap Register (168h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
sManfctInfo Register (170h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Nonvolatile SBS Register Back-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
nSBSCfg Register (1BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
nDesignVoltage Register (1D3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
nCGain and Sense Resistor Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
SHA-256 Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Authentication Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Alternate Authentication Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Secret Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Single Step Secret Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Multistep Secret Generation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
All OEMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Determining the Number of Remaining Updates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Authentication Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Compute MAC Without ROM ID [3600h]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Compute MAC with ROM ID [3500h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Compute Next Secret Without ROM ID [3000h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Compute Next SECRET WITH ROM ID [3300h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Maxim Integrated
│ 7
www.maximintegrated.com
MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
CLEAR SECRET [5A00h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
LOCK SECRET [6000h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Reset Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Hardware Reset [000Fh to Address 060h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Fuel Gauge Reset [0001h to Address 0BBh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
2-Wire Bus System (MAX17201/MAX17205 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Hardware Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
I/O Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Bus Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Acknowledge Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Read/Write Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
2
I C Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
I C Write Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
I C Read Data Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SBS Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SBS Write Word Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SBS Read Word Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SBS Write Block Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SBS Read Block Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Packet Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
1-Wire Bus System (MAX17211/MAX17215 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Hardware Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
64-Bit Net Address (ROM ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
I/O Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Reset Time Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Write Time Slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Read Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Transaction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Net Address Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Read Net Address [33h]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Match Net Address [55h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
TABLE OF CONTENTS (CONTINUED)
Skip Net Address [CCh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Search Net Address [F0h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
1-Wire Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Read Data [69h, LL, HH] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Write Data [6Ch, LL, HH]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Summary of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Appendix A: Reading History Data
Psuedo-Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
LIST OF FIGURES
Figure 1. Single-Cell Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2. Multicell Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. Cell-Balancing Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. Merger of Coulomb Counter and Voltage-Based Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5. ModelGauge m5 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. ModelGauge m5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. nSOC (1AEh) Format When nNVCfg2.enSOC = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. nVoltTemp (1AAh) Format When nNVCfg2.enVT = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. EZ Configuration Performance Histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. EZ Configuration Performance vs. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Voltage and Coulomb Count Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. ModelGauge m5 Typical Accuracy Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Handling Changes in Empty Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Blocking False End of Charge Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15. FullCapRep Learning at End of Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. FullCapNom Learning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 17. Converge to Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. nAgeFcCfg Register (1D2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. Benefits of Age Forecasting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20. Sample Life-Logging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. Write Flag Register and Valid Flag Register Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. nFullSOCThr (1C6h)/FullSOCThr (013h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. VEmpty (03Ah)/nVEmpty (19Eh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
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LIST OF FIGURES (CONTINUED)
Figure 24. nRFastVshdn (1D5h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 25. FilterCfg (029h)/nFilterCfg (19Dh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. RelaxCfg (02Ah)/nRelaxCfg (1B6h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 27. LearnCfg (028h)/nLearnCfg (19Fh) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28. MiscCfg (02Bh)/nMiscCfg (1B2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29. nTTFCfg (1C7h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30. nConvgCfg (1B7h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 31. nRippleCfg (1B1h) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 32. FStat (03Dh) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. Cell Relaxation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 34. Flowchart of Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 35. DevName (021h) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 36. nROMID (1BCh to 1BFh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 37. PackCfg (0BDh)/nPackCfg (1B5h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 38. nNVCfg0 (1B8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 39. nNVCfg1 (1B9h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 40. nNVCfg2 (1BAh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 41. ShdnTimer (03Fh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 42. nConfig (1B0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 43. Config (01Dh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 44. Config2 (0BBh) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 45. Status (000h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 46. Status2 (0B0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 47. HibCfg (0BAh)/nHibCfg (1B4h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 48. CommStat (061h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 49. Cell Balancing Window of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 50. 2S and 3S Balancing Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 51. Cell Balancing Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 52. MaxMinVolt (01Bh)/nMaxMinVolt (1ACh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 53. MaxMinCurr (01Ch)/nMaxMinCurr (1ABh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 54. nCGain Register (1C8h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 55. MaxMinTemp (01Ah)/nMaxMinTemp (1ADh) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 56. Overcurrent Comparator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 57. ODSCTh Register (0F2h) and nODSCTh Register (18Eh) Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 58. ODSCCfg Register (0F3h) and nODSCCfg Register (18Fh) Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 59. VAlrtTh (001h)/nVAlrtTh (1C0h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 60. TAlrtTh (002h)/nTAlrtTh (1C1h) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 61. SAlrtTh (003h)/nSAlrtTh (1C2h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Maxim Integrated
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
LIST OF FIGURES (CONTINUED)
Figure 62. IAlrtTh (0B4h)/nIAlrtTh (1C3h) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 63. Shadow RAM and Nonvolatile Memory Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 64. Format of LOCK Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 65. Format of Lock Register (07Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 66. nSBSCfg (1BBh) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 67. Procedure to Verify a Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 68. Battery Authentication Without a Host-Side Secret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 69. Single Step Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 70. Multistep Secret Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 71. 2-Wire Bus Interface Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 72. 2-Wire Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 73. Example I2C Write Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 74. Example I2C Read Data Communication Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 75. Example SBS Write Word Communication Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 76. Example SBS Read Word Communication Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 77. Example SBS Read Block Communication Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 78. PEC CRC Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 79. 1-Wire Bus Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 80. 1-Wire Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 81. 1-Wire Write and Read Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 82. Example 1-Wire Communication Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LIST OF TABLES
Table 1. ModelGauge Register Standard Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2. Minimum and Maximum Cell Sizes for Age Forecasting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 3. Life Logging Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 4. Decoding History Page Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5. Reading History Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 6. Reading History Page Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 7. Recommended nRSense Register Values for Common-Sense Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 8. Fuel Gauge Temperature Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 9. Cell Balancing Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 10. Voltage Measurement Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 11. Current Measurement Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 12. Current Measurement Range and Resolution vs. Sense Resistor Value . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Stand-Alone ModelGauge m5 Fuel Gauge
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LIST OF TABLES (CONTINUED)
Table 13. Copper Trace Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 14. Temperature Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 15. Register Settings for Common Thermistor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 16. Top-Level Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 17. Individual Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 18. ModelGauge m5 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 19. Nonvolatile Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 20. History Recall Command Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 21. Number of Remaining Config Memory Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 22. Nonvolatile Memory Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 23. SBS Register Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 24. SBS to Nonvolatile Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 25. nCGain Register Settings to Meet SBS Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. Number of Remaining Secret Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 27. 2-Wire Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 28. Valid SBS Read Block Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 29. 1-Wire Net Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 30. All Function Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
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MAX17201/MAX17205/
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Stand-Alone ModelGauge m5 Fuel Gauge
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Absolute Maximum Ratings (TDFN)
V
to CSN (MAX17201/MAX17211)..................-0.3V to +6V
CSP to CSN ...............................................................-2V to +2V
DQ/SDA, OD/SCL to CSN.......................................-0.3V to +6V
Continuous Source Current for THRM...............................20mA
Continuous Sink Current for DQ/SDA, ALRT1...................20mA
Continuous Sink Current for BATT, CELL1, CELL2...........50mA
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -55°C to +125°C
Lead Temperature (soldering 10s) ..................................+300°C
Soldering Temperature (reflow).......................................+260°C
BATT
V
to CSN (MAX17205/MAX17215) ...............-0.3V to +22V
BATT
ALRT1 to CSN.......................................................-0.3V to +17V
CELL1 to CSN....................................... -0.3V to V
+ 0.3V
+ 0.3V
CELL2
CELL2 to CELL1 ..................................... -0.3V to V
BATT
REG3 to V
(MAX17201/MAX17211) .....................0V to 0V
BATT
REG3 to CSN (MAX17205/MAX17215)..................-0.3V to +6V
AIN1, AIN2 to CSN..................................................-0.3V to +6V
THRM, CELLx to CSN .......................... -0.3V to V
REG2 to CSN.......................................................-0.3V to +2.2V
+ 0.3V
REG3
Absolute Maximum Ratings (WLP)
V
to GND (MAX17201/MAX17211) .................-0.3V to +6V
CSP to GND...............................................................-2V to +2V
DQ/SDA, OD/SCL to GND ......................................-0.3V to +6V
Continuous Source Current for THRM...............................20mA
Continuous Sink Current for DQ/SDA, ALRT1...................20mA
Continuous Sink Current for BATT, CELL1, CELL2...........50mA
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -55°C to +125°C
Lead Temperature (soldering 10s) ..................................+300°C
Soldering Temperature (reflow).......................................+260°C
BATT
V
to GND (MAX17205/MAX17215)...............-0.3V to +22V
BATT
ALRT1 to GND ......................................................-0.3V to +17V
CELL1 to GND ...................................... -0.3V to V
+ 0.3V
+ 0.3V
CELL2
CELL2 to CELL1 ..................................... -0.3V to V
BATT
REG3 to V
(MAX17201/MAX17211) .....................0V to 0V
BATT
REG3 to GND (MAX17205/MAX17215) .................-0.3V to +6V
AIN1, AIN2 to GND .................................................-0.3V to +6V
THRM, CELLx to GND.......................... -0.3V to V
+ 0.3V
REG2 to GND.......................................................-0.3V to +2.2V
REG3
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
14 TDFN-EP
Package Code
Outline Number
T1433+2C
21-0137
Land Pattern Number
90-0063
Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θ
)
54°C/W
8°C/W
JA
Junction-to-Case Thermal Resistance (θ
)
)
JC
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θ
)
41°C/W
8°C/W
JA
Junction-to-Case Thermal Resistance (θ
15 WLP
JC
Package Code
W151F2+1
21-100072
Outline Number
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θ
)
62°C/W
JA
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Electrical Characteristics
(V
= 2.3V to 4.9V (MAX17201/MAX17211) 4.2V to 20V (MAX17205/MAX17215), T = -40°C to 85°C, unless otherwise noted.
BATT
A
Typical values are T = +25°C. See Figure 1, Figure 2, and Figure 3. Limits are 100% tested at T = +25°C. Limits over the operating
A
A
temperature range and relevant supply voltage range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
MAX17201/MAX17211 (Notes 1, 2)
MAX17205/MAX17215 (Notes 1, 2)
MAX17201/MAX17211 (Note 1)
2.3
4.2
4.9
20
Supply Voltage
Startup Voltage
V
V
I
V
V
BATT
BATT
DD0
2.85
0.7
3.0
1.5
3.0
Single cell, shutdown mode (Note 3)
Multiple cell, shutdown mode (Note 3)
Shutdown Supply
Current
μA
1.5
Hibernate mode average current,
single cell (Note 3)
9
20
25
35
40
Hibernate Supply
Current
I
I
μA
DD1
DD2
Hibernate mode average current,
multiple cell (Note 3)
12
18
25
MAX17201/MAX17211, not including
thermistor measurement current (Note 3)
Active Supply Current
Regulation Voltage
μA
MAX17205/1MAX17215, not including
thermistor measurement current (Note 3)
V
V
1.8
3.4
REG2
V
MAX17205/MAX17215 only
REG3
ANALOG-TO-DIGITAL CONVERSION
T
= +25°C (Note 4)
-12.5
-25
+12.5
+25
A
(Note 4)
= +25°C (Note 5)
V
GERR
T
-12.5
-25
+12.5
+25
A
mV
(Note 5)
= +25°C (Note 6)
Voltage Measurement
Error
T
-30
+30
A
VB
VX
GERR
(Note 6)
= +25°C (Note 7)
-100
-0.2
-0.5
+100
+0.2
+0.5
T
% of
Reading
A
GERR
(Note 7)
V
Individual cell
78.125
1.25
μV
mV
μV
LSB
Voltage Measurement
Resolution
VB
V
pin
LSB
LSB
FS
BATT
VX
CELLx pin
78.125
V
Individual cell
2.3
4.2
4.9
20.0
2.0
Voltage Measurement
Range
VB
V
pin
V
FS
FS
BATT
VX
CELLx pin
0.92
Current Measurement
Offset Error
I
V
= 0V, long-term average (Note 2)
-2.0
-1
-0.7
+0.5
+1
μV
OERR
GERR
CSP
Current Measurement
Gain Error
% of
reading
I
CSP between -50mV and +50mV
Current Measurement
Resolution
I
1.5625
μV
LSB
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
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Electrical Characteristics (continued)
(V
= 2.3V to 4.9V (MAX17201/MAX17211) 4.2V to 20V (MAX17205/MAX17215), T = -40°C to 85°C, unless otherwise noted.
BATT
A
Typical values are T = +25°C. See Figure 1, Figure 2, and Figure 3. Limits are 100% tested at T = +25°C. Limits over the operating
A
A
temperature range and relevant supply voltage range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current Measurement
Range
I
±51.2
mV
FS
Internal Temperature
Measurement Error
TI
±1
°C
°C
GERR
Internal Temperature
Measurement Resolution
TI
AIN1, AIN2 (Note 1)
0.00391
LSB
Auxiliary Ratiometric
Measurement Error
% of
reading
TE
-0.5
+0.5
GERR
Auxiliary Ratiometric
Measurement Resolution
TE
0.001526
%
LSB
INPUT/OUTPUT
Output Drive High,
THRM
V
REG3
0.1
-
V
I
I
= -1mA, V
= 2.3V
V
V
OH
OH
REG3
Output Drive Low,
ALRT1, SDA/DQ
V
= 4mA, V
= 2.3V
0.4
OL
OL
REG3
Input Logic-High,
SCL/OD, SDA/DQ
V
1.5
91
V
IH
Input Logic-Low,
SCL/OD, SDA/DQ
V
0.44
99
V
IL
Battery-Detach Detection
Threshold
AIN1 as a fraction of the voltage of THRM,
AIN1 rising (Note 1)
V
95
1
%
%
DET
Battery-Detach Detection
Threshold Hysteresis
V
AIN1 falling
DET-HYS
AIN1 step from 70% to 100% of THRM
voltage to ALRT1 falling, Config register
Alrtp = 0, Ber = 1, FTHRM = 1
Battery-Detach
Comparator Delay
t
100
μs
TOFF
COMPARATORS
Overcurrent Threshold
Offset Error
OC
OC
OD or SC comparator
OD or SC comparator
-2.5
-5.0
+2.5
+5.0
mV
OE
Overcurrent Threshold
Gain Error
% of
threshold
GE
OD or SC comparator, 20mV minimum
input overdrive, delay configured to
minimum
Over Current
Comparator Delay
OC
2
µs
DLY
RESISTANCE AND LEAKAGE
Leakage Current, AIN1,
AIN2
I
I
AIN1, AIN2 < REG3
-0.2
-60
0.2
μA
LEAK
LEAK
Leakage Current,
CELLx
V
< 2.0V (Note 2)
±5
+60
nA
CELLx
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
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Electrical Characteristics (continued)
(V
= 2.3V to 4.9V (MAX17201/MAX17211) 4.2V to 20V (MAX17205/MAX17215), T = -40°C to 85°C, unless otherwise noted.
BATT
A
Typical values are T = +25°C. See Figure 1, Figure 2, and Figure 3. Limits are 100% tested at T = +25°C. Limits over the operating
A
A
temperature range and relevant supply voltage range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Leakage Current,
CELL1, CELL2, CSN,
CSP, ALRT1, THRM
I
V
< 15V, THRM < REG3
-1
+1
μA
LEAK
ALRT1
Input Resistance,
CELL2, CELL1, CSP
Resistance during voltage sampling
(Note 15)
R
1
MΩ
MΩ
VAD
Input Resistance,
CELLx
R
400
CELLx
V
V
= 12.6V, I
-CELL2, CELL2-CELL1, and
= 50mA, between
BATT
BAL
Cell-Balancing
Resistance
BATT
R
3
9
20
Ω
BAL
CELL1-CSN (TDFN) or CELL1-GND
(WLP)
Input Pulldown Current
TIMING
I
V
, V
pins = 0.4V
0.05
-1
0.2
0.4
μA
PD
SDA SCL
Time-Base Accuracy
SHA Calculation Time
t
T = +25°C
+1
10
%
ERR
A
t
4.5
ms
SHA
PRE
POR
Time between turning on the THRM pullup
and AIN1 or AIN2 analog-to-digital
conversions
THRM Precharge Time
t
8.48
ms
Power-on-Reset Time
Task Period
t
(Note 2)
10
ms
ms
t
351.5
TP
NONVOLATILE MEMORY
For block programming and recalling,
3.0
4.2
applied on V
(MAX17201/MAX17211)
Nonvolatile Access
Voltage
BATT
V
V
NVM
For block programming and recalling,
applied on V (MAX17205/MAX17215)
BATT
Programming Supply
Current
I
Current from V
for block programming
4
10
7360
1280
5
mA
ms
PROG
BATT
Block Programming
Time
t
368
64
BLOCK
Page Programming
Time
SHA secret update or learned parameters
update
t
ms
UPDATE
Nonvolatile Memory
Recall Time
t
ms
RECALL
Write Capacity,
Configuration Memory
n
(Notes 2, 8, 9)
(Notes 2, 8, 9)
7
5
writes
writes
CONFIG
Write Capacity,
SHA Secret
n
SECRET
Write Capacity,
Learned Parameters
n
(Notes 2, 8, 9)
(Note 2)
202
writes
years
LEARNED
Data Retention
t
10
NV
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
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Electrical Characteristics (continued)
(V
= 2.3V to 4.9V (MAX17201/MAX17211) 4.2V to 20V (MAX17205/MAX17215), T = -40°C to 85°C, unless otherwise noted.
BATT
A
Typical values are T = +25°C. See Figure 1, Figure 2, and Figure 3. Limits are 100% tested at T = +25°C. Limits over the operating
A
A
temperature range and relevant supply voltage range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1-WIRE INTERFACE, REGULAR SPEED
Time Slot
t
60
1
120
µs
µs
µs
µs
µs
µs
µs
µs
µs
SLOT
Recovery Time
t
REC
Write-0 Low Time
Write-1 Low Time
Read-Data Valid
Reset-Time High
Reset-Time Low
Presence-Detect High
Presence-Detect Low
t
t
60
1
120
15
LOW0
LOW1
t
15
RDV
t
480
480
15
RSTH
t
RSTL
t
60
PDH
t
60
240
PDL
1-WIRE INTERFACE, OVERDRIVE SPEED
Time Slot
t
6
1
6
1
16
µs
µs
µs
µs
µs
µs
µs
µs
µs
SLOT
Recovery Time
t
REC
Write-0 Low Time
Write-1 Low Time
Read-Data Valid
Reset-Time High
Reset-Time Low
Presence-Detect High
Presence-Detect Low
2-WIRE INTERFACE
SCL Clock Frequency
t
t
16
2
LOW0
LOW1
t
2
RDV
t
48
48
2
RSTH
t
RSTL
t
6
PDH
t
8
24
PDL
f
(Note 10)
(Note 11)
0
400
kHz
µs
SCL
Bus Free Time Between
a STOP and START
Condition
t
1.3
BUF
Hold Time (Repeated)
START Condition
t
t
0.6
1.3
0.6
0.6
µs
µs
µs
µs
HD:STA
Low Period of SCL
Clock
t
LOW
High Period of SCL
Clock
t
HIGH
Setup Time for a Repeated
START Condition
SU:STA
HD:DAT
Data Hold Time
Data Setup Time
t
(Notes 12, 13)
(Note 12)
0
0.9
us
ns
t
100
SU:DAT
Rise Time of Both SDA
and SCL Signals
t
5
300
ns
R
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Electrical Characteristics (continued)
(V
= 2.3V to 4.9V (MAX17201/MAX17211) 4.2V to 20V (MAX17205/MAX17215), T = -40°C to 85°C, unless otherwise noted.
BATT
A
Typical values are T = +25°C. See Figure 1, Figure 2, and Figure 3. Limits are 100% tested at T = +25°C. Limits over the operating
A
A
temperature range and relevant supply voltage range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fall Time of Both SDA
and SCL Signals
t
5
300
ns
F
Setup Time for STOP
Condition
t
0.6
µs
ns
SU:STO
Spike Pulse Width
Suppressed by Input
Filter
t
(Note 14)
50
SP
Capacitive Load for
Each Bus Line
C
400
pF
pF
B
SCL, SDA Input
Capacitance
C
6
BIN
Note 1: All voltages are referenced to CSN in the TDFN package. All voltages are referenced to GND in the WLP package.
Note 2: Specification is guaranteed by design (GBD), and not production tested.
Note 3: T < +50°C, V
= 4.9V for single cell or 20V for multiple cell.
A
BATT
Note 4: Single cell, CELL1 to CSP cell voltage between 2.3V and 4.9V.
Note 5: Multiple cell, V to CELL2, CELL2 to CeLL1, or CELL1 to CSP, cell voltages between 2.3V and 4.9V; for voltages
BATT
between 2.3V and 4.9V; for two cells, CELL2 must be shorted to CELL1.
Note 6: Multiple cell, total V voltage, V = 4.2V to 20V.
BATT
BATT
Note 7: The MAX17205/MAX17215 only CELLx to CSP, per cell voltage of 2.3V to 4.9V.
Note 8: Write capacity numbers shown have one write subtracted for the initial write performed during manufacturing test to set
nonvolatile memory to a known value.
Note 9: Due to the nature of one-time programmable memory, write capacity cannot be production tested. Follow the nonvolatile
memory and SHA secret update procedures detailed in the data sheet.
Note 10: Timing must be fast enough to prevent the IC from entering shutdown mode due to bus low for a period greater than the
shutdown timer setting.
Note 11: f
must meet the minimum clock low time plus the rise/fall times.
SCL
Note 12: The maximum t
has only to be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 13: This device internally provides a hold time of at least 100ns for the SDA signal (referred to the minimum V of the SCL
IH
signal) to bridge the undefined region of the falling edge of SCL.
Note 14: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 15: Resistance is measured to CSN in the TDFN package. Resistance is measured to GND in the WLP package.
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Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
HIBERNATE CURRENT vs. SUPPLY VOLTAGE
(MAX17201/MAX17211)
(MAX17205/MAX17215)
(MAX17201/MAX17211)
toc01
toc02
toc03
1.0
2
1.6
1.2
0.8
0.4
0
15
10
5
+25°C
+50°C
+50°C
0.8
+50°C
0.6
+25°C
+25°C
0.4
-20°C
-20°C
-20°C
0.2
0.0
0
1
2
3
4
5
10
VOLTAGE (V)
15
20
1
2
3
4
VOLTAGE (V)
VOLTAGE (V)
HIBERNATE CURRENT vs. SUPPLY VOLTAGE
ACTIVE CURRENT vs. SUPPLY VOLTAGE
ACTIVE CURRENT vs. SUPPLY VOLTAGE
(MAX17205/MAX17215)
(MAX17201/MAX17211)
(MAX17205/MAX17215)
toc04
toc05
toc06
20
15
10
5
30
20
10
0
40
30
20
10
0
+50°C
+50°C
+50°C
+25°C
+25°C
+25°C
-20°C
-20°C
2S OPERATION
-20°C
2S OPERATION
3S OPERATION
4S OPERATION
3S OPERATION
4S OPERATION
0
5
10
15
20
1
2
3
4
5
10
15
20
VOLTAGE (V)
VOLTAGE (V)
VOLTAGE (V)
CELL1 VOLTAGE ADC ERROR
(MAX17201/MAX17211)
CELL1 VOLTAGE ADC ERROR
(MAX17205/MAX17215)
CELL2 VOLTAGE ADC ERROR
(MAX17205/MAX17215)
toc07
toc08
toc09
10
5
10
5
10
5
-20°C
-20°C
+50°C
-20°C
+50°C
0
0
0
+25°C
+50°C
+25°C
+25°C
-5
-5
-5
-10
-10
-10
2.4
3.2
4.0
4.8
2.4
3.2
4.0
4.8
2.4
3.2
VOLTAGE (V)
4.0
4.8
VOLTAGE (V)
VOLTAGE (V)
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Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
CELL3 VOLTAGE ADC ERROR
(MAX17205/MAX17215)
VBATT VOLTAGE ADC ERROR
CELLx VOLTAGE ADC ERROR
toc10
toc11
toc12
10
5
10
5
10
5
+50°C
+50°C
+25°C
-20°C
+50°C
+25°C
0
0
0
+25°C
2S OPERATION
3S OPERATION
4S OPERATION
-20°C
-20°C
-5
-5
-5
-10
-10
-10
2.4
3.2
4.0
4.8
2.4
3.2
4.0
4.8
5
10
15
20
VOLTAGE (V)
CELLX SCALED VOLTAGE (V)
VOLTAGE (V)
CURRENT ADC ERROR
(MAX17201/MAX17211)
CURRENT ADC ERROR
(MAX17205/MAX17215)
METAL TRACE CURRENT SENSE
ADC ERROR
toc15
toc13
toc14
5.0
2.5
5.0
2.5
100
50
10mΩ SENSE RESISTOR
10mΩ SENSE RESISTOR
CALIBRATED CGAIN
(SEE THE METAL SENSING
SECTION AND EV KIT LAYOUT)
+50°C
+50°C
-20°C
0.0
0.0
0
+50°C
+25°C
-20°C
+25°C
+25°C
-2.5
-5.0
-2.5
-5.0
-50
-100
RECOMMENDED
OPERATION
-20°C
-5000
-2500
0
2500
5000
-5000
-2500
0
2500
5000
-5000
-2500
0
2500
5000
CURRENT (mA)
CURRENT (mA)
CURRENT (mA)
RESPONSE TO TEMPERATURE TRANSIENT
AT CONSTANT CURRENT LOAD
toc17
DIE TEMPERATURE AND THERMISTOR
MEASUREMENT ERROR
COLD DISCHARGE (0°C)
toc18
toc16
100
90
80
70
60
50
40
30
20
10
0
4.4
3.9
3.4
2.9
2.4
100
90
80
70
60
50
40
30
20
10
0
10
10
5
NCP15XH103F03RC THERMISTOR
8
6
BATTERY
VOLTAGE
4
THERMISTOR
2
0
0
AvSOC
EMPTY VOLTAGE
REFERENCE
SOC
-2
-4
-6
-8
-10
-5
DIE TEMP
10
RepSOC
RepSOC
TEMPERATURE
-10
-40
-15
35
60
85
0
1
2
3
4
0
4
8
12
16
TEMPERATURE (°C)
TIME (HOURS)
TIME (HOURS)
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Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
CHARGE AND DISCHARGE (+20°C)
HOT DISCHARGE (40°C)
toc20
toc19
100
90
80
70
60
50
40
30
20
10
0
10
8
100
90
80
70
60
50
40
30
20
10
0
10
8
6
6
4
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
RepSOC
RepSOC
4
0
4
8
12
16
0
8
12
16
20
TIME (HOURS)
TIME (HOURS)
ZIGZAG PATTERN SOC ACCURACY (1/2)
REFERENCE SOC FUELGAUGE SOC ERROR
CHARGE AND DISCHARGE IN ACTUAL SYSTEM
toc22
toc21
100
4.5
4.3
4.1
3.9
3.7
3.5
3.3
100
90
80
70
60
50
40
30
20
10
0
10
8
90
80
70
60
50
40
30
20
10
0
6
4
2
VCELL
0
TEMPERATURE
-2
-4
-6
-8
-10
SOCREP
ACCURATE PREDICTION
TO EMPTY
0
4
8
12
16
0
20
40
60
80
100
TIME (HOURS)
TIME (HOURS)
ZIGZAG PATTERN SOC ACCURACY (2/2)
REFERENCE SOC FUELGAUGE SOC ERROR
CELL BALANCING
toc23
toc24
100
90
80
70
60
50
40
30
20
10
0
10
8
60
50
40
30
20
10
0
START OF BALANCING
6
2 SERIES 600mAh BATTERY
FIGURE 3 CIRCUIT
4
2
0
-2
-4
-6
-8
-10
END OF BALANCING
(BALCFG = 10mV)
ACCURATE PREDICTION
TO EMPTY
81
85
89
93
97
101
0.0
0.5
1.0
TIME (HOURS)
1.5
2.0
TIME (HOURS)
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Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
TIME TO FULL PERFORMANCE
AGE FORECAST
toc26
toc25
3.0
2.5
2.0
1.5
1.0
0.5
0.0
600
500
400
300
200
100
0
2400
2200
2000
1800
1600
1400
1200
START OF CHARGE
CYCLE LIFE
FORECAST
TTF
REGISTER
ACTUAL
TIME TO
FULL
DISCHARGE
CAPACITY
BATTERY
AGED
FULL
0
100
200
300
400
-3
-2
-1
0
BATTERY CYCLES
ACTUAL TIME FROM FULL (HOURS)
TIME TO EMPTY PERFORMANCE
toc27
3.0
2.5
2.0
1.5
1.0
0.5
0.0
START OF DISCHARGE
TTE
REGISTER
ACTUAL TIME
TO EMPTY
EMPTY
-3
-2
-1
0
ACTUAL TIME FROM EMPTY (HOURS)
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Pin Configurations
TOP VIEW
(PAD SIDE DOWN)
REG3
CSP
1
2
3
4
5
6
7
14
13
12
11
10
9
THRM
CELLx
DQ/SDA
OD/SCL
AIN2
REG2
CSN
MAX17201
MAX17205
MAX17211
MAX17215
V
BATT
CELL2
CELL1
AIN1
EP
8
ALRT1
TDFN
TOP VIEW
MAX17201/MAX17205/MAX17211/MAX17215
+
ALRT1
A5
REG2
A1
GND
A2
CSN
A3
CSP
A4
CELL2
B2
CELL1
B3
AIN2
B4
THRM
B5
V
BATT
B1
REG3
C1
CELLx
C2
DQ/SDA OD/SCL
AIN1
C5
C3
C4
15 WLP
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Pin/Bump Description
PIN/BUMP
NAME
FUNCTION
TDFN
WLP
Internal 3.4V Regulator Output. For the MAX17205/MAX17215, bypass with an external 0.47μF
1
2
3
C1
REG3
CSP
capacitor. For the MAX17201/MAX17211, connect REG3 to V
.
BATT
A4
Current Measurement Positive Sense Point. Kelvin connect to cell side of sense resistor.
Internal 1.8V Regulator Output. Bypass with an external 0.47μF capacitor to CSN (TDFN) or
GND (WLP).
A1
REG2
Device Ground and Current Measurement Negative Sense Point. Kelvin connect to load side of
sense resistor.
4
5
A3
B1
CSN
Power-Supply and Battery Voltage Sense Input. Connect to positive terminal of cell stack.
Bypass with RC filter to CSN (TDFN) or GND (WLP).
V
BATT
Voltage Sense Input for Measuring Cell Voltage of Second or Middle Cell. Series resistance
determines balancing current. Also acts as the external divider gate drive when measuring pack
voltage on CELLx pin.
6
7
B2
B3
CELL2
CELL1
Voltage Sense Input for Measuring Voltage of Bottom Cell. Series resistance determines balanc-
ing current.
8
9
A5
C5
B4
ALRT1
AIN1
Programmable Alert Output
Auxiliary Voltage Input 1. Auxiliary voltage input from external thermal-measurement network.
Auxiliary Voltage Input 2. Auxiliary voltage input from external thermal-measurement network.
10
AIN2
2
Serial Clock Input for I C Communication or Speed Selection for 1-Wire Communication. Input
2
only. For I C communication, connect to the clock terminal of the battery pack. Connect to CSN
11
12
C4
C3
OD/SCL
DQ/SDA
for standard speed 1-wire communication. Connect to REG3 pin for overdrive 1-wire communica-
tion. OD/SCL has an internal pulldown (IPD) for sensing pack disconnection.
2
Serial Data Input/Output for Both 1-Wire and I C communication modes. Open-drain output
driver. Connect to the DATA terminal of the battery pack. DQ/SDA has an internal pulldown (IPD)
for sensing pack disconnection.
High-Impedance Voltage Measurement Channel. Connect to an external voltage divider for mea-
suring cell stacks larger than 4S.
13
14
C2
B5
CELLx
THRM
Thermistor Bias Connection. Connect to the high side of the thermistor resistor-divider circuit.
THRM biases to REG3 voltage during AIN1 and AIN2 measurement.
—
—
A2
—
GND
EP
IC Ground (WLP Only). Connect to PACK-. Keep isolated from CSN.
Exposed Pad (TDFN Only). Connect directly to CSN.
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Functional Diagram
PACK+
PROTECTION
CIRCUIT
1.8V LDO
MAX17201
REG2
IN
IN
OUT
MAX17205
MAX17211
MAX17215
0.47µF
0.47µF
3.4V LDO
MAX17205/
MAX17215 ONLY
50Ω
0.1µF
V
BATT
REG3
OUT
OPTIONAL
CELL
BALANCING
RESISTORS
32kHz
OSCILLATOR
1nF
10Ω
ALRT1
50Ω
CELL2
MODELGAUGE m5 CORE
SHA-256
2
1nF
1nF
150Ω
150Ω
10Ω
DQ/SDA
OD/SCL
REF
REG3
I
C/1-WIRE
50Ω
CELL1
INTERFACE
MUX
INTERNAL
TEMPERATURE
SENSOR
4.7V
4.7V
10Ω
CSN (TDFN)
GND (WLP)
REG3
THRM
THRM ENABLE
PACK
CELLx
OPTIONAL 2ND
THERMISTOR
VOLTAGE
DIVIDER
CIRCUIT
CURRENT
COMPARATORS
AIN2
AIN1
GND
CSP
CSN
(WLP ONLY)
OPTIONAL STACK
MEASUREMENT
PACK-
R
SENSE
The ModelGauge m5 algorithm combines the short-term
accuracy and linearity of a coulomb-counter with the long-
term stability of a voltage-based fuel gauge, along with
temperature compensation to provide industry-leading fuel
gauge accuracy. Additionally, the algorithm does not suffer
from abrupt corrections that normally occur in coulomb-
counter algorithms, since tiny continual corrections are
distributed over time. The MAX1720x automatically com-
pensates for aging, temperature, and discharge rate and
provides accurate state of charge (SOC) in milliampere-
hours (mAh) or percentage (%) over a wide range of oper-
ating conditions. Fuel gauge error always converges to 0%
as the cell approaches empty. The ICs provide accurate
estimation of time-to-empty and time-to-full and provide
three methods for reporting the age of the battery: reduc-
tion in capacity, increase in battery resistance, and cycle
odometer. In addition, age forecasting allows the user to
estimate the expected lifespan of the cell.
Detailed Description
The MAX1720x/MAX1721x ultra-low power stand-alone
fuel gauge ICs that implement the ModelGauge m5 algo-
rithm without requiring host interaction for configuration.
This feature makes the MAX1720x/MAX1721x an excellent
pack-side fuel gauge. Voltage of the battery pack is mea-
sured at the BATT, CELL2, CELL1, CELLx, and CSP con-
nections. Current is measured by an external sense resis-
tor placed between the CSP and CSN pins. An external
resistive voltage-divider network allows the IC to measure
temperature of the battery pack by monitoring the AIN1 and
AIN2 pins. The THRM pin provides a strong pullup for the
resistor-divider that is disabled internally when temperature
is not being measured. Internal die temperature of the ICs
is also measured. The MAX17201/MAX17211 monitor a
single-cell pack. The MAX17205/MAX17215 monitor indi-
vidual cells of a 2S or 3S pack or the entire stack voltage
of any number of multiple-series cells.
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To prevent battery clones, the ICs integrate SHA-256
authentication with a 160-bit secret key. Every IC also incor-
porates a 64-bit unique identification number (ROM ID).
must be divided by the sense resistor to determine amps
or amp-hours. It is strongly recommended to use the
nRSense (1CFh) register to store the sense resistor value
for use by host software.
Communication to the host occurs over a Maxim 1-wire
2
(MAX17211/MAX17215) or standard I C interface
Device Reset
(MAX17201/MAX17205). OD/SCL is an input from the
host, and DQ/SDA is an open-drain I/O pin that requires
an external pullup. The ALRT1 pin is an output that can
be used as an external interrupt to the host processor if
certain application conditions are detected.
Device reset refers to any condition that would cause the
ICs to recall nonvolatile memory into RAM locations and
restart operation of the fuel gauge. Device reset refers to
initial power up of the IC, temporary power loss, or reset
through the software power-on-reset command.
For additional reference material, refer to the following
application notes:
Nonvolatile Backup and Initial Value
All configuration register locations have nonvolatile mem-
ory backup that can be enabled with control bits in the
nNVCfg0, nNVCfg1, and nNVCfg2 registers. If enabled,
the associated registers are initialized to their corre-
sponding nonvolatile register value after device reset. If
nonvolatile backup is disabled, the register restores to an
alternate initial value instead. See each register descrip-
tion for details.
Application Note 6258: MAX1720x/MAX1721x Battery
Pack Implementation Guide
Application Note 6259: MAX1720x/MAX1721x System
Side Implementation Guide
Application Note 6260: MAX1720x/MAX1721x Host
Software Implementation Guide
Register Description Conventions
Register Naming Conventions
The following sections define standard conventions used
throughout the data sheet to describe register functions and
device behavior. Any register that does not match one of
the following data formats is described as a special register
Register addresses are described throughout the doc-
ument as 9-bit internal values from 000h to 1FFh.
These addresses must be translated to 8-bit values for
2
the MAX1720x (I C) or 16-bit external values for the
Standard Register Formats
MAX1721x (1-Wire). See the Memory section for details.
Unless otherwise stated during a given register's descrip-
tion, all IC registers follow the same format depending
on the type of register. See Table 1 for the resolution and
range of any register described hereafter. Note that cur-
rent and capacity values are displayed as a voltage and
Register names that start with a lower case n, such as
nPackCfg for example, indicate the register is a nonvolatile
memory location. Register names that start with a lower
case s indicate the register is part of the SBS compliant
register block.
Table 1. ModelGauge Register Standard Resolutions
REGISTER
TYPE
MINIMUM
VALUE
MAXIMUM
VALUE
LSB SIZE
NOTES
327.675mVh/
Capacity
5.0μVh/R
0.0μVh
Equivalent to 0.5mA with a 0.010Ω sense resistor.
SENSE
R
SENSE
Percentage
Voltage
1/256%
0.078125mV
1.5625μV/
0.0%
0.0V
255.9961%
5.11992V
1% LSb when reading only the upper byte.
—
-51.2mV/
51.1984mV/
R
SENSE
Signed 2's complement format. Equivalent to
Current
R
R
156.25μA with a 0.010Ω sense resistor.
SENSE
SENSE
Signed 2's complement format. 1°C LSb when
reading only the upper byte.
Temperature
1/256°C
-128.0°C
127.996°C
Resistance
Time
1/4096Ω
0.0 Ω
15.99976Ω
—
—
5.625s
0.0s
102.3984h
Format details are included with the
register description.
Special
—
—
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Single-Cell Typical Operating Circuit
(MAX17201/MAX17211 Only)
Alternate Initial and Factory Default Values
If nonvolatile backup of a memory location is disabled,
that location initializes to its alternate initial value after
reset. The factory default value is the initial value stored
in nonvolatile memory at the factory. See Table 22.
In the single-cell operating circuit example shown in
Figure 1, the MAX17201/MAX17211 is mounted outside
of the protector circuit to allow communication to the pack
even when the protection FETs are disabled. Take care
to avoid exceeding the maximum operating voltage on
any pin under fault conditions. The single-cell versions of
the ICs do not contain a 3.4V regulator. REG3 must be
Typical Operating Circuits
The typical operating circuit for the MAX1720x/MAX1721x
depends on the series cell count of the cell stack to be
monitored and which features of the ICs are desired. The
following sections show the five most common typical
operating circuits when mounted inside of a cell pack.
connected directly to the V
pin. A single thermistor
BATT
circuit measures cell temperature leaving the AIN2 input
available for additional ADC measurements if desired.
Resistors and clamping diodes protect all input pins from
ESD. Connect the exposed pad (TDFN only) directly to
the CSN pin.
PACK+
10Ω
ALRT1
V
BATT
1kΩ
0.1µF
4.7V
REG3
CELLx
CELL2
DQ/SDA
150Ω
4.7V
CELL1
MAX17201
MAX17211
OD/SCL
150Ω
THRM
4.7V
10kΩ
AIN1
AIN2
REG2
10kΩ NTC
EP
(TDFN)
GND
(WLP)
CSP
CSN
0.47µF
PACK-
PROTECTION
CIRCUIT
RSENSE
PackCfg = 0x1C01
0.010Ω
Figure 1. Single-Cell Schematic
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current drain. Set PackCfg.CxEn = 1, BtEn = 0, ChEn =
0 for operation with this schematic. For cell stacks larger
than 4S, a simple regulator circuit clamps the voltage on
Multicell Typical Operating Circuits
(MAX17205/MAX17215 Only)
The MAX17205/MAX17215 is designed for use in multi-
cell packs as shown in Figure 2. When used in con-
junction with a low-side protection circuit, individual cell
measurements and cell balancing are not available. For
2S to 4S configuration packs, the ICs monitor the entire
V
below the maximum allowed. Take care to avoid
BATT
exceeding the maximum operating voltage on any pin
under fault conditions.
The resistor divider on CELLx should be calculated as
follows:
stack voltage from the V
pin. Set PackCfg.BtEn = 1,
BATT
CxEn = 0 and ChEn = 0 for operation with this schematic.
Resistor from CELLx to PACK-: 200kΩ
For packs that are larger than 4S, a resistor divider cir-
cuit is used. The CELLx pin measures the divided stack
voltage and CELL2 controls the divider circuit to limit
Resistor from CELLx to V
x 200kΩ
: (2.5 * number of cells - 1)
BATT
2S TO 4S CELL PACK CONFIGURATIONS
PACK+
CELL PACK CONFIGURATIONS MORE THAN 4S
PACK+
500kΩ
50Ω
(2.5N - 1)
x 200kΩ
V
V
BATT
BATT
ALRT1
ALRT1
0.1µF
1kΩ
18V
1µF
1kΩ
150Ω
150Ω
4.7V
4.7V
4.7V
4.7V
4.7V
4.7V
CELL1
DQ/SDA
DQ/SDA
CELLx
CELL2
CELL N
CELL2
CELLx
150Ω
150Ω
CELL1
OD/SCL
OD/SCL
CELL N
200kΩ
MAX17205
MAX17215
MAX17205
MAX17215
THRM
THRM
AIN1
10kΩ
10kΩ
10kΩ
REG3
REG2
REG3
REG2
CELL 2
CELL 1
AIN1
AIN2
0.47µF
0.47µF
0.47µF
0.47µF
10kΩ
NTC
10kΩ
NTC
CELL 1
AIN2
10kΩ
NTC
10kΩ
NTC
EP
GND
EP
GND
(TDFN)
CSP
CSN
(WLP)
CSP
(TDFN)
CSN
(WLP)
PACK-
PACK-
PROTECTION
CIRCUIT
PROTECTION
CIRCUIT
R
R
SENSE
SENSE
0.010Ω
0.010Ω
PackCfg = 0x390N
N = NUMBER OF CELLS
PackCfg = 0x3A0N
N = NUMBER OF CELLS
Figure 2. Multicell Schematics
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and requires periodic corrections. Corrections are usually
performed at full or empty. Some other systems also use
the relaxed battery voltage to perform corrections. These
systems determine the true state of charge (SOC) based
on the battery voltage after a long time of no current flow.
Both have the same limitation: if the correction condition
is not observed over time in the actual application, the
error in the system is boundless. The performance of
classic coulomb counters is dominated by the accuracy
of such corrections. Voltage measurement based SOC
estimation has accuracy limitations due to imperfect cell
modeling, but does not accumulate offset error over time.
Cell Balancing Typical Operating Circuits
(MAX17205/MAX17215 Only)
In multicell configuration packs, if the MAX17205/
MAX17215 is used in conjunction with a high-side protec-
tion circuit, the ICs can monitor the individual cell voltages
and perform cell balancing as shown in Figure 3. In the
following 2S and 3S examples, the voltage of each cell is
monitored independently. External 100Ω resistors on the
CELL1 and CELL2 pins limit current through the balanc-
ing circuits to approximately 30mA. Balancing resistors are
added to every other pin so that each balancing loop con-
tains a single limiting resistor. Leave the CELLx pin open.
Set PackCfg.ChEn = 1 for operation with this schematic.
The ICs include an advanced voltage fuel gauge (VFG)
that estimates open-circuit voltage (OCV), even during
current flow, and simulates the nonlinear internal dynam-
ics of a Li+ battery to determine the SOC with improved
accuracy. The model considers the time effects of a bat-
tery caused by the chemical reactions and impedance in
the battery to determine SOC. This SOC estimation does
not accumulate offset error over time.
ModelGauge m5 Algorithm
Classical coulomb-counter-based fuel gauges have
excellent linearity and short-term performance. However,
they suffer from drift due to the accumulation of the offset
error in the current-sense measurement. Although the
offset error is often very small, it cannot be eliminated,
causes the reported capacity error to increase over time,
2S BALANCING CONFIGURATION WITH HIGH-SIDE PROTECTOR
PACK+
3S BALANCING CONFIGURATION WITH HIGH-SIDE PROTECTOR
PACK+
REG3
REG2
REG3
REG2
ALRT1
ALRT1
1kΩ
1kΩ
150Ω
150Ω
4.7V
4.7V
4.7V
4.7V
4.7V
4.7V
0.47µF
0.47µF
0.47µF
0.47µF
PROTECTION
CIRCUIT
PROTECTION
CIRCUIT
DQ/SDA
DQ/SDA
150Ω
OD/SCL
THRM
AIN1
OD/SCL
THRM
AIN1
CELLx
10Ω
150Ω
10kΩ
CELLx
BATT
MAX17205
MAX17215
V
MAX17205
MAX17215
BATT
10Ω
0.1µF
1nF
10kΩ
10kΩ
10kΩ
0.1µF
100Ω
1nF
CELL2
CELL1
10kΩ
NTC
10kΩ
NTC
100Ω
1nF
CELL2
CELL1
100Ω
AIN2
AIN2
1nF
GND
(WLP)
10kΩ
NTC
GND
(WLP)
10kΩ
NTC
EP
(TDFN)
EP
(TDFN)
CSN
CSN
CSP
CSP
1nF
PACK-
PACK-
PackCfg = 0x3C62
PackCfg = 0x3C63
R
R
SENSE
SENSE
0.010Ω
0.010Ω
Figure 3. Cell-Balancing Circuit Schematics
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The ModelGauge m5 algorithm combines a high-accuracy
coulomb counter with a VFG. See Figure 4 and Figure 5.
The complementary combined result eliminates the weak-
nesses of both the coulomb counter and the VFG while
providing the strengths of both. A mixing algorithm weighs
and combines the VFG capacity with the coulomb counter
and weighs each result so that both are used optimally to
determine the battery state. In this way, the VFG capacity
result is used to continuously make small adjustments to
the battery state, canceling the coulomb-counter drift.
inputs and outputs to the algorithm grouped by category.
Analog input registers are the real-time measurements of
voltage, temperature, and current performed by the IC.
Application-specific registers are programmed by the cus-
tomer to reflect the operation of the application. The Cell
Characterization Information registers hold characteriza-
tion data that models the behavior of the cell over the oper-
ating range of the application. The Algorithm Configuration
registers allow the host to adjust performance of the IC for
its application. The Learned Information registers allow an
application to maintain accuracy of the fuel gauge as the
cell ages. The register description sections describe each
register function in detail.
The ModelGauge m5 algorithm uses this battery state
information and accounts for temperature, battery cur-
rent, age, and application parameters to determine
the remaining capacity available to the system. As the
battery approaches the critical region near empty, the
ModelGauge m5 algorithm invokes a special error correc-
tion mechanism that eliminates any error.
ModelGauge m5 Algorithm Output Registers
The following registers are outputs from the ModelGauge
m5 algorithm. The values in these registers become valid
480ms after the ICs are reset.
The ModelGauge m5 algorithm continually adapts to the
cell and application through independent learning rou-
tines. As the cell ages, its change in capacity is monitored
and updated and the voltage-fuel-gauge dynamics adapt
based on cell-voltage behavior in the application.
RepCap Register (005h)
Register Type: Capacity
Nonvolatile Backup: None
RepCap or reported capacity is a filtered version of the
AvCap register that prevents large jumps in the reported
value caused by changes in the application such as
abrupt changes in temperature or load current. See the
Fuel-Guage Empty Compensation section for details.
ModelGauge m5 Registers
For accurate results, ModelGauge m5 uses information
about the cell and the application as well as the real-
time information measured by the IC. Figure 6 shows
COULOMB COUNTER
MODELGAUGE
VERY SLOW INFLUENCE
Δ% SOC
Ʃ
ΔQ
CAPACITY
MICROCORRECTIONS
FULL, EMPTY, AND STANDBY STATE DETECTION UNNECESSARY
Figure 4. Merger of Coulomb Counter and Voltage-Based Fuel Gauge
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VOLTAGE
CURRENT
OCV CALCULATION
(OCV OUTPUT)
OCV TABLE LOOKUP
(% REMAINING OUTPUT)
COULOMB COUNTER
(mAh OUTPUT)
OCV TEMPERATURE
COMPENSATION
LEARN
TIME
RELAXED CELL
DETECTION
CAPACITY LEARN
(mAh PER PERCENT)
×
MIXING ALGORITHM
(mAh OUTPUT)
EMPTY DETECTION
M
IX
C
AP REGISTER
M
IXSOC REGISTER
+
APPLICATION EMPTY COMPENSATION
BASED ON APPLICATION TEMPERATURE
AND DISCHARGE RATE
+
-
END-OF-CHARGE DETECTION
APPLICATION OUTPUTS:
C
ELL CHEMISTRY OUTPUTS:
R
R
EPSOC REGISTER
AP REGISTER
SOC REGISTER
AP REGISTER
TTE/TTF REGISTERS
AP REGISTER
VFOCV REGISTER
YCLES REGISTER
RFAST REGISTER
ULL AP OM RESGISTER
GE REGISTER
EP
C
C
A
A
V
V
C
F
A
C N
TTE/A
T
F
ULL
C
Figure 5. ModelGauge m5 Block Diagram
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VCELL
A
V
C
C
C
AP/A
V
SOC
C
URRENT
R
EP
AP/REPSOC
AP/MIXSOC
T
EMPERATURE
M
IX
A
VGVCELL
F
ULLCAP
AVGCURRENT
FULLCAPREP
AVGTEMPERATURE
F
ULLCAPNOM
RCell
TTE/TTF/A
TTTE
NDESIGNVOLTAGE
VFOCV/VFSOC
VRIPPLE
NDESIGNCAP
N
ICHGTERM
Age
MODELGAUGE m5
ALGORITHM
AGEFORECAST
Cycles
NRIPPLECFG
CHARACTERIZATION TABLES
N
CONVGCFG
F
ULLCAPNOM
N
CVCFG
Cycles
N
QRTABLE00,10,20,30
ULLSOCTHR
RCOMP
N
A
GE
F
C
C
FG
T
IMERH
N
F
NLEARNC
FG
N
QRTABLE00,10,20,30
N
0
N
F
ILTERC
FG
N
IAVGE
MPTY
NFULLCAPNOM
NRELAXC
FG
RCOMP
0
N
VEMPTY
NMISCCFG
T
EMPCO
NTEMPCO
ATRATE
F
ULLCAPREP
N
IAVGEMPTY
Figure 6. ModelGauge m5 Registers
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expected capacity. The result can be used by the host to
gauge the battery pack health as compared to a new pack
of the same type. The equation for the register output is:
RepSOC Register (006h)
Register type: Percentage
Nonvolatile backup: None
Age register = 100% x (FullCapNom register/DesignCap
register)
RepSOC is a filtered version of the AvSOC register
that prevents large jumps in the reported value caused
by changes in the application such as abrupt changes
in load current. RepSOC corresponds to RepCap and
FullCapRep. RepSOC is intended to be the final state of
charge percentage output for use by the application. See
the Empty Compensation section for details.
Cycles Register (017h)
Register Type: Special
Nonvolatile Backup and Restore: nCycles (1A4h)
The Cycles register maintains a total count of the number
of charge/discharge cycles of the cell that have occurred.
The result is stored as a percentage of a full cycle. For
example, a full charge/discharge cycle results in the
Cycles register incrementing by 100%. The Cycles regis-
ter has a full range of 0 to 10485 cycles with a 16.0% LSb.
Cycles is periodically saved to nCycles to provide a long
term nonvolatile cycle count.
FullCapRep Register (035h)
Register Type: Capacity
Nonvolatile Backup and Restore From: nFullCapRep
(1A9h) or nFullCapNom (1A5h). See nNVCfg2.EnFC.
This register reports the full capacity that goes with
RepCap, generally used for reporting to the user. A new
full-capacity value is calculated at the end of every charge
cycle in the application.
TimerH Register (0BEh)
Register Type: Special
Nonvolatile Backup and Restore: nTimerH (1AFh) if
nNVCfg2.enT is set
TTE Register (011h)
Register Type: Time
Alternate Initial Value: 0x0000
Nonvolatile Backup: None
This register allows the ICs to track the age of the cell. An
LSb of 3.2 hours gives a full-scale range for the register of up
to 23.94 years. If enabled, this register is periodically backed
up to nonvolatile memory as part of the learning function.
The TTE register holds the estimated time to empty
for the application under present temperature and load
conditions. The TTE value is determined by dividing the
AvCap register by the AvgCurrent register. The corre-
sponding AvgCurrent filtering gives a delay in TTE empty,
but provides more stable results.
FullCap Register (010h)
Register Type: Capacity
TTF Register (020h)
Register Type: Time
Nonvolatile Restore: Derived from nFullCapNom (1A5h)
This register holds the calculated full capacity of the cell
based on all inputs from the ModelGauge m5 algorithm
including empty compensation. A new full-capacity value is
calculated continuously as application conditions change.
Nonvolatile Backup: None
The TTF register holds the estimated time to full for the
application under present conditions. The TTF value is
determined by learning the constant-current and con-
stant-voltage portions of the charge cycle based on expe-
rience of prior charge cycles. Time to full is then estimated
by comparing present charge current to the charge ter-
mination current. Operation of the TTF register assumes
all charge profiles are consistent in the application. See
Graph 26 in the Typical Operating Characteristics section
for sample performance.
nFullCapNom Register (1A5h)
Register Type: Capacity
Nonvolatile Backup and Restore: FullCapNom (023h)
This register holds the calculated full capacity of the cell,
not including temperature and empty compensation. A
new full-capacity nominal value is calculated each time a
cell relaxation event is detected. This register is used to
calculate other outputs of the ModelGauge m5 algorithm.
Age Register (007h)
RCell Register (014h)
Register Type: Resistance
Nonvolatile Backup: None
Initial Value: 0x0290
Register Type: Percentage
Nonvolatile Backup: None
The Age register contains a calculated percentage value
of the application’s present cell capacity compared to its
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The RCell register displays the calculated internal resis-
tance of the cell, or average internal resistance of each cell
in the cell stack. RCell is determined by comparing open-
circuit voltage (VFOCV) against measured voltage (VCell)
over a long time period while under load or charge current.
nVoltTemp Register (1AAh)
Register Type: Special
Nonvolatile Backup: AvgVCell and AvgTA registers if
nNVCfg2.enVT = 1
This register has dual functionality depending on con-
figuration settings. If nNVCfg2.enVT = 1, this register
provides nonvolatile back up of the AvgVCell and AvgTA
registers as shown in Figure 8.
VRipple Register (0BCh)
Register Type: Special
Nonvolatile Backup: None
Initial Value: 0x0000
Alternatively, if nNVCfg0.enAF = 1, this register stores an
accumulatedageslopevalueforusewiththeAgeForecasting
algorithm. Regardless of which option is enabled, this regis-
ter is periodically saved to nonvolatile memory as part of the
learning function. If neither option is enabled, this register
can be used as general purpose user memory.
The VRipple register holds the slow average RMS value of
VCell register reading variation compared to the AvgVCell
register. The default filter time is 22.5s. See the nRippleCfg
Register (1B1h) description. VRipple has an LSb weight of
1.25mV/128.
nSOC Register (1AEh)
ModelGauge m5 EZ Performance
Register Type: Special
ModelGauge m5 EZ performance provides plug-and-play
operation for the ICs. While the MAX1720x/MAX1721x
can be custom tuned to the applications battery through
a characterization process for ideal performance, the
ICs have the ability to provide reasonable performance
for most applications with no custom characterization
required. Figure 9 and Figure 10 show the performance of
the ModelGauge m5 algorithm in applications using only
the default cell model information.
Nonvolatile Backup: VFSOC and MixSOC registers if
nNVCfg2.enSOC = 1
This register has dual functionality depending on con-
figuration settings. If nNVCfg2.enSOC = 1, this register
provides nonvolatile backup of the MixSOC and VFSOC
registers as shown in Figure 7.
Alternatively, if nNVCfg0.enAF = 1, this register stores a
filtered version of the FullCapNom register value to be used
with the Age Forecasting algorithm. Regardless of which
option is enabled, this register is periodically saved to non-
volatile memory as part of the learning function. If neither
option is enabled, this register can be used as general-
purpose user memory.
While EZ performance provides good performance for
most cell types, some chemistries such as lithium-iron-
phosphate (LiFePO4) and Panasonic NCR/NCA series
cells require a custom model characterization for best
performance.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MixSOC Upper Byte
VFSOC Upper Byte
Figure 7. nSOC (1AEh) Format When nNVCfg2.enSOC = 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AvgVCell Upper 9 Bits
AvgTA Upper 7 Bits
Figure 8. nVoltTemp (1AAh) Format When nNVCfg2.enVT = 1
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ModelGauge m5 EZ CONFIGURATION PERFORMANCE
94% OF TESTS HAVE < 3% ERROR
60
50
40
30
20
10
0
TEST CONDITIONS:
• 300+ DIFFERENT BATTERIES
• 3000+ DISCHARGES
• +20°C AND +40°C
• RUN TIME OF > 3 HOURS
• AFTER FIRST CYCLE
1
2
3
4
5
6
7
8
9
10
WORST-CASE ERROR DURING DISCHARGE (%)
Figure 9. EZ Configuration Performance Histogram
DESCRIPTION
AFTER FIRST CYCLE* (%)
AFTER SECOND CYCLE* (%)
Tests with error less than 3%
Tests with error less than 5%
Tests with error less than 10%
94
97
95
98
99.5
99.7
*TEST CONDITIONS: +20ºC AND +40ºC, RUN TIME OF > 3 HOURS.
Figure 10. EZ Configuration Performance vs. Test Conditions
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mixing algorithm alters the weighting so that the coulomb-
counter result is dominant. From this point forward, the IC
switches to servo mixing. Servo mixing provides a fixed
magnitude continuous error correction to the coulomb
count, up or down, based on the direction of error from
the OCV estimation. This allows differences between
the coulomb count and OCV estimation to be corrected
quickly. See Figure 11.
OCV Estimation and Coulomb Count Mixing
The core of the ModelGauge m5 algorithm is a mixing
algorithm that combines the OCV state estimation with
the coulomb counter. After a power-on reset of the IC,
coulomb-count accuracy is unknown. The OCV state
estimation is weighted heavily compared to the coulomb
count output. As the cell progresses through cycles in the
application, coulomb-counter accuracy improves and the
100%
COULOMB COUNT INFLUENCE
SERVO MIXING
OCV INFLUENCE
0%
0.50
1.00
1.50
0
2.00
CELL CYCLES
Figure 11. Voltage and Coulomb Count Mixing
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The resulting output from the mixing algorithm does not
suffer accumulation drift from current measurement offset
error and is more stable than a stand-alone OCV estima-
tion algorithm. See Figure 12. Initial accuracy depends on
the relaxation state of the cell. The highest initial accuracy
is achieved with a fully relaxed cell.
MAXIMUM COULOMB COUNTER ERROR
(±0.1% PER HOUR IN THIS EXAMPLE)
TYPICAL OCV ESTIMATION ERROR
AS CELL IS CYCLED
(SHADED AREA)
MPDELGAUGE OCV + COULOMB COUNT MIXING
MAXIMUM ERROR RANGE
TIME
Figure 12. ModelGauge m5 Typical Accuracy Example
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requirements and internal losses of the cell. The ICs sub-
tracts the amount of charge not available to the applica-
tion from the MixCap register and reports the result in the
AvCap register.
Empty Compensation
As the temperature and discharge rate of an application
changes, the amount of charge available to the applica-
tion also changes. The ModelGauge m5 algorithm dis-
tinguishes between remaining capacity of the cell and
remaining capacity of the application and reports both
results to the user.
Since available remaining capacity is highly dependent on
discharge rate, the AvCap register can be subject to large
instantaneous changes as the application load current
changes. The result can increase, even while discharging,
if the load current suddenly drops. This result, although
correct, can be very counter-intuitive to the host software
or end user. The RepCap output register contains a filtered
version of AvCap that removes any abrupt changes in
remaining capacity. RepCap converges with AvCap over
time to correctly predict the application empty point while
discharging or the application full point while charging.
Figure 13 shows the relationship of these registers.
The MixCap output register tracks the charge state of
the cell. This is the theoretical mAh of charge that can be
removed from the cell under ideal conditions—extremely
low discharge current and no concern for cell voltage.
This result is not affected by application conditions such
as cell impedance or minimum operating voltage of
the application. ModelGauge m5 continually tracks the
expected empty point of the application in mAh. This
is the amount of charge that cannot be removed from
the cell by the application because of minimum voltage
LOAD INCREASES
MixCap REGISTER
ABSOLUTE mAh STATE OF BATTERY NOT CONSIDERING
TEMPERATURE AND DISCHARGE RATE
(i.e., CAPACITY AVAILABLE IF VERY LIGHT LOAD)
AvCap REGISTER
AVAILABLE CAPACITY OF THE CELL UNDER PRESENT
CONDITIONS
INCREASE IN AVAILABLE CAPACITY WHEN UNDER LOAD IS
COUNTERINTUITIVE TO USERS AND OPERATING SYSTEMS
RepCap REGISTER
REPORTED CAPACITY WITH NO SUDDEN JUMPS AND CORRECT
FORECAST OF EMPTY
EMPTY
TIME (h)
Figure 13. Handling Changes in Empty Calculation
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new FullCapRep register value based on the RepCap
register output. If the old FullCapRep value is too high, it
is adjusted on a downward slope near the end of charge
as defined by the MiscCfg.FUS setting until it reaches
RepCap. If the old FullCapRep is too low, it is adjusted
upward to match RepCap. This prevents the calculated
state of charge from ever reporting a value greater than
100%. See Figure 15.
End-of-Charge Detection
The ICs detect the end of a charge cycle when the appli-
cation current falls into the band set by the IChgTerm
register value while the VFSOC value is above the
FullSOCThr register value. By monitoring both the Current
and AvgCurrent registers, the device can reject false end-
of-charge events such as application load spikes or early
charge-source removal. See Figure 14. When a proper
end-of-charge event is detected, the device learns a
AVGCURRENT
C
URRENT
1.25 x ICHGTERM
0.125 x ICHGTERM
0mA
HIGH CURRENT LOAD SPIKES DO NOT GENERATE END OF CHARGE
DETECTION BECAUSE CURRENT AND AVERAGE CURRENT READINGS DO
NOT FALL INTO THE DETECTION AREA AT THE SAME TIME.
AVGCURRENT
C
URRENT
1.25 x ICHGTERM
0.125 x ICHGTERM
0mA
EARLY CHARGER REMOVAL DOES NOT GENERATE END OF CHARGE
DETECTION BECAUSE CURRENT AND AVERAGE CURRENT READINGS DO
NOT FALL INTO THE DETECTION AREA AT THE SAME TIME.
Figure 14. Blocking False End of Charge Events
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AVGCURRENT
C
URRENT
1.25 x ICHGTERM
0.125 x ICHGTERM
0mA
CORRECT
END OF CHARGE
DETECTION AREA
CASE 1: OLD FULL
C
AP
R
EP TOO HIGH
EP TOO LOW
New FULLCAPREP
CASE 2: OLD FULL
C
AP
R
REPCAP
Figure 15. FullCapRep Learning at End of Charge
Charge termination is detected by the IC when the follow-
ing conditions are met:
adjustments always occur as small corrections to prevent
instability of the system and prevent any noticeable jumps
in the fuel-gauge outputs. Learning occurs automatically
without any input from the host. In addition to estimating
the battery’s state of charge, the ICs observe the battery’s
relaxation response and adjusts the dynamics of the volt-
age fuel gauge. Registers used by the algorithm include:
• VFSOC register > FullSOCThr register
• AND IChgTerm x 0.125 < Current register < IChgTerm
x 1.25
•AND IChgTerm x 0.125 <AvgCurrent register < IChgTerm
x 1.25
• Application Capacity (FullCapRep register). This
is the total capacity available to the application at full,
set through the IChgTerm and FullSOCThr registers as
described in the End-of-Charge Detection section. See
the FullCap Register (010h) description.
Fuel Gauge Learning
The ICs periodically make internal adjustments to cell
characterization and application information to remove
initial error and maintain accuracy as the cell ages. These
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• Cell Capacity (FullCapNom register). This is the total
cell capacity at full, according to the voltage fuel gauge.
This includes some capacity that is not available to the
application at high loads and/or low temperature. The ICs
periodically compare percent change based on an open
circuit voltage measurement vs. coulomb-count change
as the cell charges and discharges, maintaining an accu-
rate estimation of the pack capacity in mAh as the pack
ages. See Figure 16.
RELAXATION EVENTS
100%
90%
Δ%4
80%
Δ%1
70%
Δ%5
60%
50%
Δ%2
40%
OBSERVED SIZE OF BATTERY:
ΔQACC
F
ULLCAPNOM =
x 100%
30%
20%
10%
ΔPACC
Δ%3
WHERE:
0%
ΔQACC = |ΔQ1| + |ΔQ2| + |ΔQ3| ...
ΔQACC = |Δ%1| + |Δ%2| + |Δ%3| ...
ΔQ4
1200mAh
1100mAh
1000mAh
ΔQ1
ΔQ5
900mAh
800mAh
700mAh
600mAh
500mAh
ΔQ2
400mAh
300mAh
200mAh
100mAh
ΔQ3
0mAh
Figure 16. FullCapNom Learning
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VEMPTY
R
EPSOC ESTIMATION
TOO HIGH
REPSOC RATE OF CHANGE
ADJUSTED SO THAT IT
REACHES 0% AS THE CELL’S
VOLTAGE REACHES VEMPTY
IDEAL
REPSOC
R
EPSOC ESTIMATION
TOO LOW
0%
Figure 17. Converge to Empty
• Voltage Fuel-Gauge Adaptation. The ICs observe the
battery’s relaxation response and adjust the dynamics
of the voltage fuel gauge. This adaptation adjusts the
RComp0 register during qualified cell relaxation events.
Converge-to-Empty
The MAX1720x/MAX1721x include a feature that guar-
antees the fuel gauge output converges to 0% as the cell
voltage approaches the empty voltage. As the cell's volt-
age approaches the expected empty voltage (AvgVCell
approaches VEmpty) the ICs smoothly adjust the rate
of change of RepSOC so that the fuel gauge reports
0% at the exact time that the cell's voltage reaches
empty. This prevents unexpected shutdown or an early
0% SOC reported by the fuel gauge. See Figure 17. In
addition, the fuel gauge limits RepSOC to not go below
1% until AvgVCell crosses VEmpty.
• Empty Compensation. The ICs update internal data
whenever an empty cell is detected (VCell < VEmpty) to
account for cell age or other cell deviations from the char-
acterization information.
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Determining Fuel Gauge Accuracy
nAgeFcCfg Register (1D2h)
To determine the true accuracy of a fuel gauge, as expe-
rienced by end users, the battery should be exercised
in a dynamic manner. The end-user accuracy cannot
be understood with only simple cycles. To challenge a
correction-based fuel gauge, such as a coulomb coun-
ter, test the battery with partial loading sessions. For
example, a typical user can operate the device for 10
minutes and then stop use for an hour or more. A robust
test method includes these kinds of sessions many times
at various loads, temperatures, and duration. Refer to the
Application Note 4799: Cell Characterization Procedure
for a ModelGauge m3/ModelGauge m5 Fuel Gauge.
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register. The recommended default value is
0xD5E3.
The nAgeFcCfg register is used to configure age fore-
casting functionality. Register data is nonvolatile and
is typically configured only once during pack assembly.
Figure 18 shows the register format.
DeadTargetRatio: Sets the remaining percentage of ini-
tial cell capacity where the cell is considered fully aged.
DeadTargetRatio can be adjusted between 75% and
86.72% with an LSb of 0.7813%. For example, if age fore-
casting was configured to estimate the number of cycles
until the cell’s capacity dropped to 85.1574% of when it was
new, DeadTargetRatio should be programmed to 1101b.
Initial Accuracy
The ICs use the first voltage reading after power-up or
after cell insertion to determine the starting output of the
fuel gauge. It is assumed that the cell is fully relaxed prior
to this reading; however, this is not always the case. If
there is a load or charge current at this time, the initial
reading is compensated using the characterized internal
impedance of the cell (RFast register) to estimate the
cell's relaxed voltage. If the cell was recently charged or
discharged, the voltage measured by the IC may not rep-
resent the true state of charge of the cell, resulting in initial
error in the fuel gauge outputs. In most cases, this error is
minor and is quickly removed by the fuel gauge algorithm
during the first hour of normal operation.
CycleStart: Sets the number of cell cycles before age
forecasting calculations begin. CycleStart has a range of
0.00 to 81.92 cycles with an LSb of 0.64 cycles. Since age
forecasting estimation becomes more accurate over time,
most applications use a default value of 30 cycles.
0: Always write this location 0.
1: Always write this location 1.
AgeForecast Register (0B9h)
Register Type: Special
Nonvolatile Backup: None
Cycle+ Age Forecasting
The AgeForecast register displays the estimated total
cycle life of the application cell. The AgeForecast value
should be compared against the Cycles (017h) register to
determine the estimated number of remaining cell cycles.
This is accomplished by accumulating the capacity loss
per cycle as the cell ages. The result will become more
accurate with each cycle measured. The AgeForecast
register has a full range of 0 cycles to 10485 cycles with a
0.16 cycle LSb. This register is recalculated from learned
information at power-up.
A special feature of the ModelGauge m5 algorithm is the
ability to forecast the number of cycles a user can get out
of the cell during its lifetime. This allows an application
to adjust a cell's charge profile over time to meeting the
cycle life requirements of the cell. See Figure 19. The
algorithm monitors the change in cell capacity over time
and calculates the number of cycles it takes for the cell’s
capacity to drop to a predefined threshold of 85% of origi-
nal. Remaining cycles below 85% of the original capacity
are unpredictable and not managed by age forecasting.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DeadTargetRatio
CycleStart
0
0
0
1
1
Figure 18. nAgeFcCfg Register (1D2h) Format
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INITIAL DATA
CHARGE PROFILE
CHANGED
100%
ADDITIONAL DATA
NEW AGE FORECAST SHOWS THAT
APPLICATION REQUIREMENTS
MIGHT BE MET
INITIAL AGE FORECAST SHOWS
THAT APPLICATION REQUIREMENTS
MIGHT NOT BE MET
MINIMUM CELL CAPACITY
REQUIRED BY THE APPLICATION
CYCLES
Figure 19. Benefits of Age Forecasting
Table 2. Minimum and Maximum Cell Sizes for Age Forecasting
SENSE RESISTOR (Ω)
(nCGain=0x4000)
MINIMUM CELL SIZE
FOR FORECASTING (mAh)
MAXIMUM CELL SIZE
FOR FORECASTING (mAh)
0.005
0.010
0.020
1600
800
5000
2500
1250
400
surement range for a given sense resistor. See the
Age Forecasting Requirements
Current Measurement section for details.
There are several requirements for proper operation of
the age forecasting feature as follows:
● Age forecasting requires a minimum of 100 cycles
before achieving reasonable predictions. Ignore the
age forecasting output until then.
● There is a minimum and maximum cell size that
the age forecasting algorithm can handle. Table 2
shows the allowable range of cell sizes that can be
accurately age forecasted depending on the size of
the sense resistor used in the application. Note this
range is different from the current and capacity mea-
● Age forecasting requires a custom characterized bat-
tery model to be used by the IC. Age forecasting is
not valid when using the ModelGauge m5 EZ model.
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The IC can store up to 203 snapshots of page 1Ah in non-
volatile memory. Individual registers from page 1Ah are
summarized in Table 3. Their nonvolatile backup must be
enabled in order for logging to occur. See each register's
detailed description in other sections of this data sheet.
The logging rate default is once every 10.5 equivalent
cell cycles but can be adjusted from 0.5 cycles up to 64.5
cycles using the nNVCfg2.CYCLESpSAVE setting.
Enabling Age Forecasting
The following steps are required to enable the age fore-
casting feature:
1) 1) Set nNVCfg2.enVT = 0 and nNVCfg2.enSOC =
0. These functions conflict with age forecasting and
must be disabled.
2) 2) Set nSOC to the value of nFullCapNom.
3) 3) Set nVoltTemp to 0x0001.
Life-Logging Data Example
4) 4) Set nNVCfg0.enAF = 1 to begin operation.
Figure 20 shows a graphical representation of sample
history data read from an IC. Analysis of this data can
provide information of cell performance over its lifetime as
well as detect any application anomalies that might have
affected performance.
Battery Life Logging
The MAX1720x/MAX1721x has the ability to log learned
battery information providing the host with a history of
conditions experienced by the cell pack over its life time.
Table 3. Life Logging Register Summary
REGISTER
REGISTER NAME
ADDRESS
FUNCTION
1A0h
1A1h
1A2h
1A3h
1A4h
1A5h
1A6h
1A7h
1A8h
1A9h
nQRTable00
nQRTable10
nQRTable20
nQRTable30
nCycles
Learned characterization information used to determine when the cell pack is empty under
application conditions.
Total number of equivalent full cycles seen by the cell since assembly.
Calculated capacity of the cell independent of application conditions.
nFullCapNom
nRComp0
Learned characterization information related to the voltage fuel gauge.
nTempCo
nIAvgEmpty
nFullCapRep
Typical current seen in by the application a the point where the cell reaches empty.
Calculated capacity of the cell under present application conditions.
The average voltage and temperature seen by the IC at the instance of learned data backup.
If age forecasting is enabled, this register contains different information.
1AAh
nVoltTemp
1ABh
1ACh
1ADh
nMaxMinCurr
nMaxMinVolt
nMaxMinTemp
Maximum and minimum current, voltage, and temperature seen by the IC during this logging
window.
Calculated present state of charge of the battery pack at the instance of learned data backup.
If age forecasting is enabled, this register contains different information.
1AEh
1AFh
nSOC
nTimerH
Total elapsed time since cell pack assembly not including time spent in shutdown mode.
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6 Months
TIME VS. CYCLES AND MAXIMUM/MINIMUM VOLTAGE
GIVES AN INDICATION OF THE USAGE PROFILE
0
4.2V
3.0V
+85°C
-40°C
2.0A
MAXIMUM/MINIMUM TEMPERATURE AND CURRENT
CAN INDICATE IF THE CELL HAS BEEN ABUSED
-5.0A
100%
F
ULLC
APN
OM
F
ULLC
APREP
QRESIDUAL
0%
CYCLES
Figure 20. Sample Life-Logging Data
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see the write flag information of history pages 1-8, send
the 0xE2FB command then read address 1E1h. To see
the valid flag information of pages 1–8, send the 0xE2FC
command and then read address 1EBh.
Determining Number of Valid Logging Entries
While logging data, the ICs begin on history page 1 and
continue until all history memory has been used at page
203. Prior to reading history information out of the ICs,
the host must determine which history pages has been
written and which, if any, had write errors and should be
ignored. Each page of history information has two associ-
ated write flags that indicate if the page has been written
and two associated valid flags that indicate if the write was
successful. The History Recall command [0xE2XX] is
used to load the history flags into page 1Eh of IC memory
where the host can then read their state. Table 6 shows
which command and which page the 1Eh address has the
flag information for a given history page. For example ,to
Once the write flag and valid flag information is read from
the IC, it must be decoded. Each register holds two flags
for a given history page. Figure 21 shows the register for-
mat. The flags for a given history page are always spaced
8 bits apart from one another. For example, history page
1 flags are always located at bit positions D0 and D8, his-
tory page 84 flags are at locations D3 and D11, etc. Note
that the last flag register contains information for only 3
pages, in this case the upper 5 bits of each byte should
be ignored.
HISTORY PAGE N WRITE
INDICATOR 2
HISTORY PAGE N WRITE
INDICATOR 1
HISTORY PAGE N+7 WRITE
INDICATOR 2
HISTORY PAGE N+1 WRITE
INDICATOR 2
HISTORY PAGE N+7 WRITE
INDICATOR 1
HISTORY PAGE N+1 WRITE
INDICATOR 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WRITE FLAG REGISTER FORMAT
HISTORY PAGE N VALID
INDICATOR 2
HISTORY PAGE N VALID
INDICATOR 1
HISTORY PAGE N+7 VALID
INDICATOR 2
HISTORY PAGE N+1 VALID
INDICATOR 2
HISTORY PAGE N+7 VALID
INDICATOR 1
HISTORY PAGE N+1 VALID
INDICATOR 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VALID FLAG REGISTER FORMAT
Figure 21. Write Flag Register and Valid Flag Register Formats
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Once all four flags for a given history page are known,
the host can determine if the history page contains valid
data. If either write flag is set then data has been written
to that page by the IC. If both write flags are clear, the
page has not yet been written. Due to application condi-
tions, the write may not have been successful. Next check
the valid flags. If either valid flag is set, the data should be
considered good. If both valid flags are clear then the data
should be considered bad and the host should ignore it.
Table 4 shows how to decode the flags.
then read the history data from the IC’s page 1Eh. Each
page of history data has the same format as page 1Ah. For
example, nCycles is found at address 1A4h and nCycles
history are at 1E4h, nTimerH is located at address 1AFh,
and nTimerH history is located at address 1EFh, etc.
History Data Reading Example
The host reads the life-logging data from a given IC. The
host must first determine how many history pages have
been written and if there are any errors. To start checking
history page 1, the host sends 0xE2FB to the command
Reading History Data
register, waits t
, then reads location 1E1h. If either
RECALL
Once all pages of valid history data have been identified,
they can be read from the ICs using the History Recall
command. Table 5 shows the command and history page
the D0 or the D8 bit in the read data word is a logic 1, the
host knows that history page 1 contains history data.
relationship. After sending the command, wait t
,
RECALL
Table 4. Decoding History Page Flags
WRITE INDICATOR 1
WRITE INDICATOR 2
VALID INDICATOR 1
VALID INDICATOR 2
PAGE STATUS
0
0
X
X
Page Empty.
Write Failure. Page has
Bad Data.
0
0
1
X
1
1
X
1
Write Success. Page
has Good Data.
X
Write Failure. Page has
Bad Data.
0
0
X
1
X
1
Write Success. Page
has Good Data.
X
Table 5. Reading History Data
COMMAND
0xE226
0xE227
...
HISTORY PAGE RECALLED TO PAGE 1EH
Page 1
Page 2
...
0xE2F0
Page 203
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The host can then check page 2 (bits D1 and D9) up to
page 7 (bits D7 and D15). The host continues on to pages
8 to 16 by reading location 1E2h, and then repeating
individual bit testing. This process is repeated for each
command and address listed in Table 6 until the host finds
a history page where both write flags read logic 0. This is
the first unwritten page. All previous pages contain data,
all following pages are empty.
commands 0xE226 to 0xE2F0 can be used to read the
history information from page 1Eh for processing.
Note: This example was simplified in order to describe
the procedure. A more efficient method would be for the
host to send a history command once and then read all
associated registers. For example, the host could send
the 0xE2FC command once and then read the entire
memory space of 1E0h to 1EFh that would contain all
write flags for pages 121 to 203 (1E0h to 1EAh) and all
valid flags for pages 1 to 40 (1EBh to 1EFh). This applies
for all 0xE2XX history commands.
The host must now determine which, if any, of the history
pages have bad data and must be ignored. The above
process is repeated for every location looking at the valid
flags instead of the write flags. Any history page where
both valid flags read logic 0 is considered bad due to a
write failure and that page should be ignored. Once the
host has a complete list of valid written history pages,
See Appendix A: Reading History Data
Psuedo-Code Example for a psuedo-code example of
reading history data.
Table 6. Reading History Page Flags
ASSOCIATED HIS-
TORY PAGES
COMMAND TO
RECALL WRITE FLAGS
WRITE FLAG
COMMAND TO RECALL
VALID FLAGS
VALID FLAG ADDRESS
ADDRESS
1E1h
1E2h
1E3h
1E4h
1E5h
1E6h
1E7h
1E8h
1E9h
1EAh
1EBh
1ECh
1EDh
1EEh
1EFh
1E0h
1E1h
1E2h
1E3h
1E4h
1E5h
1E6h
1E7h
1E8h
1E9h
1EAh
1–8
1EBh
1ECh
1EDh
1EEh
1EFh
1E0h
1E1h
1E2h
1E3h
1E4h
1E5h
1E6h
1E7h
1E8h
1E9h
1EAh
1EBh
1ECh
1EDh
1EEh
1EFh
1E0h
1E1h
1E2h
1E3h
1E4h
9–16
17–24
0xE2FC
0xE2FD
0xE2FE
25–32
33–40
41–48
49–56
57–64
0xE2FB
65–72
73–80
81–88
89–96
97–104
105–112
113–120
121–128
129–136
137–144
145–152
153–160
161–168
169–176
177–184
185–192
193–200
201–203
0xE2FC
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Alternate Initial Value: 95% (0x5F05)
ModelGauge m5 Algorithm Model Registers
The following registers are inputs to the ModelGauge algo-
rithm and store characterization information for the appli-
cation cells as well as important application specific speci-
fications. They are described only briefly here. Contact
Maxim for information regarding cell characterization.
The nFullSOCThr register gates detection of end-of-
charge. VFSOC must be larger than the nFullSOCThr
value before nIChgTerm is compared to the AvgCurrent
register value. The recommended nFullSOCThr register
setting for most custom characterized applications is
95%. For EZ Performance applications, the recommenda-
tion is 80% (0x5005). See the nIChgTerm Register (19Ch)
description and the End-of-Charge Detection section for
details. Figure 22 shows the register format.
nXTable0 (180h) to nXTable11 (18Bh) Registers
Register Type: Special
Nonvolatile Restore: There are no associated restore
locations for these registers.
nVEmpty Register (19Eh)
Cell characterization information used by the ModelGauge
algorithm to determine capacity versus operating condi-
tions. This table comes from battery characterization data.
These are nonvolatile memory locations. These registers
are free to user memory if using ModelGauge m5 EZ.
Register Type: Special
Nonvolatile Restore: VEmpty (03Ah) if nNVCfg0.enVE is set.
Alternate Initial Value: 0xA561 (VE=3.3V, VR=3.88V)
The nVempty register sets thresholds related to empty
detection during operation. Figure 23 shows the register
format.
nOCVTable0 (190h) to nOCVTable11 (19Bh) Registers
Register Type: Special
Nonvolatile Restore: There are no associated restore
locations for these registers.
VE: Empty Voltage. Sets the voltage level for detecting empty.
A10mV resolution gives a 0 to 5.11V range. This value is writ-
ten to 3.3V after reset if nonvolatile backup is disabled.
Cell characterization information used by the ModelGauge
algorithm to determine capacity versus operating condi-
tions. This table comes from battery characterization data.
These are nonvolatile memory locations. These registers
are free to user memory if using ModelGauge m5 EZ.
VR: Recovery Voltage. Sets the voltage level for clearing
empty detection. Once the cell voltage rises above this
point, empty voltage detection is reenabled. A 40mV reso-
lution gives a 0 to 5.08V range. This value is written to
3.88V after reset if nonvolatile backup is disabled.
nQRTable00 (1A0h) to nQRTable30 (1A3h) Registers
nDesignCap Register(1B3h)
Register Type: Special
Register Type: Capacity
Nonvolatile Backup and Restore: QRTable00 to
QRTable30 (012h, 022h, 032h, 042h)
Nonvolatile Restore: DesignCap (018h) if nNVCfg0.enDC
is set.
The nQRTable00 to nQRTable30 register locations con-
tain characterization information regarding cell capacity
that is not available under certain application conditions.
Alternate Initial Value: FullCapRep register value
The nDesignCap register holds the expected capacity of
the cell. This value is used to determine age and health
of the cell by comparing against the measured present
cell capacity.
nFullSOCThr Register (1C6h)
Register Type: Percentage
Nonvolatile Restore: FullSOCThr (013h) if nNVCfg0.enFT
is set
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nFullSOCThr
1
0
1
Figure 22. nFullSOCThr (1C6h)/FullSOCThr (013h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VE
VR
Figure 23. VEmpty (03Ah)/nVEmpty (19Eh) Format
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Alternate Initial Value: 1/3rd the hex value of the nFul-
lCapNom register (corresponds to C/9.6)
nRFastVShdn Register (1D5h)
Register Type: Special
The nIChgTerm register allows the device to detect when
a charge cycle of the cell has completed. nIChgTerm
should be programmed to the exact charge termination
current used in the application. The device detects end of
charge if all the following conditions are met:
Nonvolatile Restore: RFast (015h) and VShdnCfg (0B8h)
if nNVCfg1.enRFVSH is set
Alternate Initial Value: RFast defaults 0x0500 (312mΩ)
and VShdnCfg defaults to 0x007D (2.5V)
When enabled the nRFastVShdn register is used to
configure the initial values for the RFast and VShdnCfg
registers. If nNVCfg1.enRFVSH is clear, nRFastVShdn
can be used for general purpose data storage. Figure 24
shows the format.
• VFSOC Register > FullSOCThr Register
• AND IChgTerm x 0.125 < Current Register < IChgTerm
x 1.25
• AND IChgTerm x 0.125 < AvgCurrent Register <
IChgTerm x 1.25
nRFast: Restores to the RFast register using the follow-
ing equation:
See End-of-Charge Detection section for more details.
RFast = (nRFastVshdn AND 0xFF00) >> 4
nRComp0 Register (1A6h)
Register Type: Special
nVShdn: Restores to the VShdnCfg register using the
following equation:
Nonvolatile Restore: RComp0 (038h)
VShdnCfg = nRFastVShdn AND 0x00FF
The nRComp0 register holds characterization informa-
tion critical to computing the open-circuit voltage of a cell
under loaded conditions.
The RFast register value is used by the ModelGauge m5
algorithm to compensate an initial open-circuit voltage
starting point if the IC is powered up or reset while the cell
stack is under load and not relaxed. RFast is a unit-less
nTempCo Register (1A7h)
Register Type: Special
scalar with an LSb of (100 x R )/4096. The initial
SENSE
value of 0x0500 gives a default RFast value of 312.5 mΩ
with a 10mΩ sense resistor.
Nonvolatile Restore: TempCo (039h)
The nTempCo register holds temperature compensation
information for the nRComp0 register value.
The VShdnCfg register sets the voltage level at which
the IC will enter shutdown mode. If the AvgVCell register
voltage value that represents the lowest voltage of the cell
stack falls below the VShdnCfg register value the IC will
halt operation and enter shutdown mode. The VShdnCfg
register has an LSb weight of 20mV. The initial value of
0x007D gives a default VShdnCfg value of 2.5V. See the
Modes of Operation section.
nIAvgEmpty Register (1A8h)
Register Type: Current
Nonvolatile Backup and Restore: IAvgEmpty (036h) if
nNVCfg2.enIAvg is set.
Alternate Initial Value: 0x0100
This register stores the typical current experienced by
the fuelgauge when empty has occurred. If enabled, this
register is periodically backed up to nonvolatile memory
as part of the learning function.
nIChgTerm Register (19Ch)
Register Type: Current
Nonvolatile Restore: IChgTerm (01Eh) if nNVCfg0.enICT
is set.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nRFast
nVShdn
Figure 24. nRFastVshdn (1D5h) Format
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ModelGauge m5 Algorithm Configuration Registers
nRelaxCfg Register (1B6h)
The following registers allow operation of the ModelGauge
m5 algorithm to be adjusted for the application. It is recom-
mended that the default values for these registers be used.
Register Type: Special
Nonvolatile Restore: RelaxCfg (02Ah) if nNVCfg0.enRCfg
is set.
nFilterCfg Register (19Dh)
Alternate Initial Value: 0x2039
Register Type: Special
The nRelaxCfg register defines how the ICs detect if the
cell is in a relaxed state. See Figure 33. For a cell to be
considered relaxed, current flow through the cell must be
kept at a minimum while the change in the cell’s voltage
over time, dV/dt, shows little or no change. If AvgCurrent
remains below the LOAD threshold while VCell changes
less than the dV threshold over two consecutive periods
of dt, the cell is considered relaxed. Figure 26 shows the
nRelaxCfg register format:
Nonvolatile Restore: FilterCfg (029h) if nNVCfg0.enFCfg
is set.
Alternate Initial Value: 0x0EA4
The nFilterCfg register sets the averaging time period for
all ADC readings for mixing OCV results and coulomb
count results. It is recommended that these values are not
changed unless absolutely required by the application.
Figure 25 shows the nFilterCfg register format.
LOAD: Sets the threshold, which the AvgCurrent regis-
ter is compared against. The AvgCurrent register must
remain below this threshold value for the cell to be con-
sidered unloaded. Load is an unsigned 7-bit value where
1 LSb = 50μV. The default value is 800μV.
CURR: Sets the time constant for the AvgCurrent register.
The default POR value of 0100b gives a time constant of
5.625s. The equation setting the period is:
(CURR-7)
AvgCurrent time constant = 45s x 2
dV: Sets the threshold, which VCell is compared against.
If the cell’s voltage changes by less than dV over two con-
secutive periods set by dt, the cell is considered relaxed;
dV has a range of 0 to 40mV where 1 LSb = 1.25mV. The
default value is 3.75mV.
VOLT: Sets the time constant for the AvgVCell register.
The default POR value of 010b gives a time constant of
45.0s. The equation setting the period is:
(VOLT-2)
AvgVCell time constant = 45s x 2
MIX: Sets the time constant for the mixing algorithm. The
default POR value of 1101b gives a time constant of 12.8
hours. The equation setting the period is:
dt: Sets the time period over which change in VCell is
compared against dV. If the cell’s voltage changes by less
than dV over two consecutive periods set by dt, the cell is
considered relaxed. The default value is 1.5 minutes. The
comparison period is calculated as:
(MIX-3)
Mixing Period = 45s x 2
TEMP: Sets the time constant for the AvgTA register.
The default POR value of 0001b gives a time constant of
1.5min. The equation setting the period is:
(dt-8)
Relaxation Period = 2
x 45s
TEMP
AvgTA time constant = 45s x 2
1: Write these bits to 0.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
TEMP
MIX
VOLT
CURR
Figure 25. FilterCfg (029h)/nFilterCfg (19Dh) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOAD
dV
dt
Figure 26. RelaxCfg (02Ah)/nRelaxCfg (1B6h) Format
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Alternate Initial Value: 0x3870
nLearnCfg Register (19Fh)
Register Type: Special
The nMiscCfg control register enables various other func-
tions of the device. The nMiscCfg register default values
should not be changed unless specifically required by the
application. Figure 28 shows the register format:
Nonvolatile Restore: LearnCfg (028h) if nNVCfg0.enLCfg
is set.
Alternate Initial Value: 0x2603
0: Bit must be written 0. Do not write 1.
1: Bit must be written 1. Do not write 0.
The nLearnCfg register controls all functions relating to
adaptation during operation. The factory default value
for nLearnCfg is 0x2602. Figure 27 shows the register
format:
SACFG: SOC Alert Config. SOC Alerts can be gener-
ated by monitoring any of the SOC registers as follows.
SACFG defaults to 00 at power-up:
0: Bit must be written 0. Do not write 1.
1: Bit must be written 1. Do not write 0.
0 0 SOC alerts are generated based on the RepSOC
register.
Filt Empty: Empty Detect Filter. This bit selects whether
empty is detected by a filtered or unfiltered voltage read-
ing. Setting this bit to 1 causes the empty detection
algorithm to use the AvgVCell register. Setting this bit to
0 forces the empty detection algorithm to use the VCell
register. This default value is 0.
0 1 SOC alerts are generated based on the AvSOC register.
1 0 SOC alerts are generated based on the MixSOC
register.
1 1 SOC alerts are generated based on the VFSOC register.
MR: Mixing Rate. This value sets the strength of the servo
mixing rate after the final mixing state has been reached
(> 2.08 complete cycles). The units are MR0 = 6.25μV,
giving a range up to 19.375mA with a standard 0.010Ω
sense resistor. Setting this value to 00000b disables
servo mixing and the IC continues with time-constant mix-
ing indefinitely. The default setting is 18.75μV or 1.875mA
with a standard sense resistor.
LS: Learn Stage. See Figure 11. The learn stage value
controls the influence of the voltage fuel gauge on the
mixing algorithm. The learn stage defaults to 0h, making
the voltage fuel gauge dominate. The learn stage then
advances to 7h over the course of two full cell cycles to
make the coulomb counter dominate. Host software can
write the learn stage value to 7h to advance to the final
stage at any time. Writing any value between 1h and 6h
is ignored.
FUS: Full Update Slope. This field prevents jumps in the
RepSOC and FullCapRep registers by setting the rate of
adjustment of FullCapRep near the end of a charge cycle.
The update slope adjustment range is from 2% per 15
minutes (0000b) to a maximum of 32% per 15 minutes
(1111b).
nMiscCfg Register (1B2h)
Register Type: Special
Nonvolatile Restore: MiscCfg (02Bh) if nNVCfg0.enMC
is set
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Filt
Empty
0
0
1
0
0
1
1
0
0
LS
0
1
0
Figure 27. LearnCfg (028h)/nLearnCfg (19Fh) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FUS
1
0
MR
1
0
0
SACFG
Figure 28. MiscCfg (02Bh)/nMiscCfg (1B2h) Format
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higher levels for earlier learn states. RepL_per_stage has
an LSb of 1% giving a range of 0% to 7%.
nTTFCfg Register (1C7h)
Register Type: Special
RepLow Threshold = RepLow Field Setting +7% x RepL_
per_stage.
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
MinSlopeX: Sets the amount of slope-shallowing that
occurs when RepSOC falls below RepLow. MinSlopeX
LSb corresponds to a ratio of 1/16 giving a full range of
0 to 15/16.
Alternate Initial Value: CV_HalfTime = 0xA00 (30 minutes)
and CV_MixCap = 75% x FullCapNom
The nTTFCfg register configures parameters related to
the time to full (TTF) calculation. There is no associated
RAM register location that this register is recalled into
after device reset. These parameters can be tuned for
best TTF performance during characterization by Maxim.
Figure 29 shows the register format.
VoltLowOff: When the AvgVCell register value drops
below the VoltLow threshold, RepCap begins to bend
downwards by a ratio defined by the following equation.
VoltLowOff has an LSb of 20mV giving a range of 0 to
620mV.
nCV_HalfTime: Sets the HalfTime value with an LSb of
45s giving a full-scale range of 0 to 192 minutes.
(AvgVCell - VEmpty)/VoltLowOff
RepLow: Sets the threshold below which RepCap begins
to bend upwards. The RepLow field LSb is 2% giving a
full- scale range from 0% to 30%.
nCV_MixCapRatio: Sets the MixCapRatio with an LSb of
1/256 giving a full-scale range of 0 to 0.9961.
nConvgCfg Register (1B7h)
nRippleCfg Register (1B1h)
Register Type: Special
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
The nConvgCfg register configures operation of the
converge to empty feature. The recommended value for
nConvgCfg is 0x2241. Figure 30 shows the nConvgCfg
register format. The nNVCfg1.CTE bit must be set to
enable converge to empty functionality. If nNVCfg1.CTE
is clear this register can be used as general purpose data
storage.
The nRippleCfg register configures ripple measurement
and ripple compensation. The recommended value for this
register is 0x0204. Figure 31 shows the register format.
NR: Sets the filter magnitude for ripple observation as
defined by the following equation giving a range of 1.4
seconds to 180 seconds.
NR
RepL_per_stage: Adjusts the RepLow threshold setting
depending on the present learn stage using the follow-
ing equation. This allows the RepLow threshold to be at
Ripple Time Range = 1.4 seconds • 2
kDV: Sets the corresponding amount of capacity to com-
pensate proportional to the ripple.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nCV_HalfTime
nCV_MixCapRatio
Figure 29. nTTFCfg (1C7h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RepLow
VoltLowOff
MinSlopeX
RepL_per_stage
Figure 30. nConvgCfg (1B7h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
kDV
NR
Figure 31. nRippleCfg (1B1h) Format
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ModelGauge m5 Algorithm Additional Registers
VFOCV Register (0FBh)
Register Type: Voltage
The following registers contain intermediate ModelGauge
m5 data that can be useful for debugging or performance
analysis. The values in these registers become value
480ms after the IC is reset.
Nonvolatile Backup: None
The VFOCV register contains the calculated open-circuit
voltage of the cell as determined by the voltage fuel
gauge. This value is used in other internal calculations.
Timer Register (03Eh)
Register Type: Special
Nonvolatile Backup: None
Initial Value: 0x0000
QH Register (4Dh)
Register Type: Capacity
Nonvolatile Backup: None
Alternate Initial Value: 0x0000
This register holds timing information for the fuel gauge.
It is available to the user for debug purposes. The Timer
register LSb is equal to 175.8ms giving a full-scale range
of 0 to 3.2 hours.
The QH register displays the raw coulomb count gener-
ated by the device. This register is used internally as an
input to the mixing algorithm. Monitoring changes in QH
over time can be useful for debugging device operation.
dQAcc Register (045h)
Register Type: Capacity (16mAh/LSB)
Nonvolatile Backup: Translated from nFullCapNom
Alternate Initial Value: 0x0017 (368mAh)
AvCap Register (01Fh)
Register Type: Capacity
Nonvolatile Backup: None
This register tracks change in battery charge between
relaxation points. It is available to the user for debug
purposes.
TheAvCap register holds the calculated available capacity
of the cell pack based on all inputs from the ModelGauge
m5 algorithm including empty compensation. The register
value is an unfiltered calculation. Jumps in the reported
value can be caused by changes in the application such
as abrupt changes in load current or temperature. See the
Empty Compensation section for details.
dPAcc Register (046h)
Register Type: Percentage (1/16% per LSB)
Nonvolatile Backup: None
Initial Value: 0x0190 (25%)
AvSOC Register (00Eh)
Register Type: Percentage
Nonvolatile Backup: None
This register tracks change in battery state of charge
between relaxation points. It is available to the user for
debug purposes.
The AvSOC register holds the calculated available state
of charge of the cell based on all inputs from the
ModelGauge m5 algorithm including empty compensa-
tion. The AvSOC percentage corresponds with AvCap
and FullCapNom. The AvSOC register value is an unfil-
tered calculation. Jumps in the reported value can be
caused by changes in the application such as abrupt
changes in load current or temperature. See the Empty
Compensation section for details.
QResidual Register (00Ch)
Register Type: Capacity
Nonvolatile Backup: None
The QResidual register displays the calculated amount of
charge in mAH that is presently inside of, but cannot be
removed from the cell under present application condi-
tions. This value is subtracted from the MixCap value to
determine capacity available to the user under present
conditions (AvCap).
MixSOC Register (00Dh)
Register Type: Percentage
Nonvolatile Backup: None
VFSOC Register (0FFh)
Register Type: Percentage
Nonvolatile Backup: None
The MixSOC register holds the calculated present state of
charge of the cell before any empty compensation adjust-
ments are performed. MixSOC corresponds with MixCap
and FullCapNom. See the Empty Compensation section
for details.
The VFSOC register holds the calculated present state of
charge of the battery according to the voltage fuel gauge.
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DNR: Data Not Ready. This bit is set to 1 at cell inser-
tion and remains set until the output registers have been
updated. Afterwards, the ICs clear this bit indicating the
fuel gauge calculations are now up to date. This takes
between 445ms and 1.845s depending on whether the
ICs are in a powered state prior to the cell-insertion event.
MixCap Register (00Fh)
Register Type: Capacity
Nonvolatile Backup: None
The MixCap register holds the calculated remaining
capacity of the cell before any empty compensation
adjustments are performed. See the Empty Compensation
section for details.
RelDt2: Long Relaxation. This bit is set to a 1 whenever
the ModelGauge m5 algorithm detects that the cell has
been relaxed for a period of 48 to 96 minutes or longer.
This bit is cleared to 0 whenever the cell is no longer in a
relaxed state. See Figure 33.
VFRemCap Register (04Ah)
Register Type: Capacity
Nonvolatile Backup: None
FQ: Full Qualified. This bit is set when all charge termina-
tion conditions have been met. See the End-of-Charge
Detection section for details.
The VFRemCap register holds the remaining capacity of
the cell as determined by the voltage fuel gauge before
any empty compensation adjustments are performed.
See the Empty Compensation section for details.
EDet: Empty Detection. This bit is set to 1 when the IC
detects that the cell empty point has been reached. This
bit is reset to 0 when the cell voltage rises above the
recovery threshold. See the VEmpty register for details.
FStat Register (03Dh)
Register Type: Special
Nonvolatile Backup: None
RelDt: Relaxed Cell Detection. This bit is set to a 1 when-
ever the ModelGauge m5 algorithm detects that the cell is
in a fully relaxed state. This bit is cleared to 0 whenever a
current greater than the Load threshold is detected. See
Figure 33.
The FStat register is a read-only register that monitors the
status of the ModelGauge algorithm. Do not write to this
register location. Figure 32 is the FStat register format:
X: Don’t Care. This bit is undefined and can be logic 0 or 1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
RelDt EDet
FQ RelDt2
X
X
X
X
X
DNR
Figure 32. FStat (03Dh) Format
0
AVERAGE
CURRENT
RELAXATION LOAD THRESHOLD
DISCHARGING
dV 6
dV 5
dV 4
dV 3
CELL
VOLTAGE
dV 2
48–96
MINUTES
dt 1
dt 2
dt 3
dt 4
dt 5
dt 6
CELL IS RELAXED
FStat.RelDt BIT SET FStat.RelDt2 BIT SET
LONG RELAXATION
SECOND
READING
BELOW dV/dt
THRESHOLD
FIRST READING
BELOW dV/dt
THRESHOLD
CELL UNLOADED (RELAXATION BEGINS)
Figure 33. Cell Relaxation Detection
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function version of active mode with the balance between
power consumption and activity configurable by the appli-
cation. In shutdown mode, the internal LDO regulators are
disabled, all activity stops, all register and fuel-gauge
output values are lost, but nonvolatile configuration values
are preserved. Any learned information not yet stored to
nonvolatile memory is lost. Figure 34 shows the relation-
ship between the different operating modes.
Modes of Operation
The ICs operate in one of three power modes: shutdown,
hibernate, and active. While in active mode, the ICs operate
as a high-precision fuel gauge with temperature, voltage,
auxiliary inputs, current, and accumulated current mea-
surements acquired continuously, and the resulting values
updated in the measurement registers. Hibernate mode is
a reduced power consumption and reduced activity, but full
IC RESET
POWER CYCLE OR SOFTWARE POR
PACK IDLE
HibCfg.EnHib = 1 AND
CURRENT < HibCfg.HibThreshold FOR
LONGER THAN HibCfg.HibEnterTime
HIBERNATE MODE
FULL FUEL GAUGE FUNCTIONALITY
WITH REDUCED POWER
ACTIVE MODE
FULL FUEL GAUGE FUNCTIONALITY
WITH MAXIMUM MONITORING RATE
CONSUMPTION AND REDUCED
MONITORING RATE
PACK ACTIVE
HibCfg.EnHib = 1 AND
CURRENT > HibCfg.HibThreshold
FOR LONGER THAN HibCfg.HibExitTime
PACK CONNECT
RISING EDGE OF ANY
COMMUNICATION LINE
SOFTWARE SHUTDOWN
Config.SHDN = 1
PACK DISCONNECT
Config.COMMSH = 1 AND
COMMUNICATION LINES LOW
SHUTDOWN MODE
MINIMUM POWER CONSUMPTION
OPERATION PAUSED
REGISTER VALUES NOT
MAINTAINED
FIRMWARE UNDERVOLTAGE
SHUTDOWN
VCELL < nRFastVShdn.VShdn
Figure 34. Flowchart of Operating Modes
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Entering hibernate mode:
RESET command is sent, the ICs return to active
mode of operation.
● Pack Idle. Hibernate mode must be enabled by set-
ting HibCfg.EnHib = 1. The ICs then enter hibernate
mode if the absolute value of the Current register
falls below the HibThreshold setting for longer than
HibEnterTime. See the HibCfg register for details.
IC communication is always allowed in any mode of oper-
ation. See the detailed descriptions of the ShdnTimer,
HibCfg, and Config registers. If the IC was previously in
shutdown mode, starting communication wakes it up and
the data is invalid for 550ms.
Exiting hibernate mode:
● Pack Active. The ICs return to active mode if the
absolute value of the Current register rises above
the HibThreshold setting for longer than HibExitTime.
See the HibCfg register for details.
Status and Configuration Registers
The following registers control IC operation not related to
the fuel gauge such as power-saving modes, nonvolatile
backup, and ALRT1 pin functionality.
Entering shutdown mode (from active mode or hibernate
mode):
DevName Register (021h)
Register Type: Special
● Software Shutdown. Software shutdown can be
forced by setting Config.SHDN = 1 and waiting lon-
ger than the ShdnTimer register value (default 45s).
Nonvolatile Backup: None
The DevName register holds device type and firmware
revision information. This allows host software to easily
identify the type of IC being communicated to. Figure 35
shows the DevName register format.
● Firmware Undervoltage Shutdown. The ICs enter shut-
down mode if the VCell register value representing the
lowest voltage of the cell stack falls below the nRFast-
VShdn.VShdn threshold setting (2.5V by default).
Device: Indicates the device type as follows:
1h = MAX17201 or MAX17211
● Pack Disconnect. The IC enters shutdown if Config.
COMMSH = 1 and communication lines are open
(logic-low) for longer than the ShdnTimer period. This
option is not recommended.
5h = MAX17205 or MAX17215
Revision: Indicates the firmware revision inside the ICs.
nROMID0 (1BCh)/nROMID1 (1BDh)/nROMID2
(1BEh)/nROMID3 (1BFh) Registers
These shutdown entry modes are all programmable
according to the application. Shutdown events are gated
by the ShdnTimer register, which allows a long delay
between the shutdown event and entering the mode. By
behaving this way, the IC takes the best reading of the
relaxation voltage.
Register Type: Special
Nonvolatile Restore: There are no associated restore
locations for these registers
Each MAX1720x/1x IC contains a unique 64 bit identifi-
cation value that is contained in the nROMID registers.
Note this is the same ID that can be read using the
MAX17211/15 1-Wire ROM ID commands. The unique
ID can be reconstructed from the nROMID registers as
shown in Figure 36.
Exiting Shutdown Mode (ICs always exit into active mode):
● Pack Connect. The ICs return to active mode on the
rising edge of any communication line.
● IC Reset. If the ICs are power cycled or the software
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Revision
Device
Figure 35. DevName (021h) Format
NROMID3[15:0]
NROMID2[15:0]
NROMID1[15:0]
NROMID0[15:0]
ROM ID [63:48]
ROM ID [47:32]
ROM ID [31:16]
ROM ID [15:0]
Figure 36. nROMID (1BCh to 1BFh) Format
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BALCFG: Balancing Config. This field sets the cell balanc-
ing voltage threshold. When set to 0 cell balancing is dis-
abled. When set to any other value, cell balancing begins
when a voltage delta as determined by the following
equation is detected. Note there are other criteria for deter-
mining the start of cell balancing. See the Cell Balancing
(MAX17205/MAX17215 Only) section for details.
nRSense Register (1CFh)
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
The nRSense register is the designated location to store
the sense resistor value used by the application. This
value is not used by the IC as all current and capacity
information is reported in terms of μV and μVH. Host
software can use the nRSense register value to convert
current and capacity information into mA and mAH. It is
recommended that the sense resistor value be stored
with an LSb weight of 10μΩ giving a range of 10μΩ to
655.35mΩ. Table 7 shows recommended register settings
based on common-sense resistor values.
BALCFG
Balancing Threshold = 1.25mV • 2
CxEn: CELLx Channel Enable. Set to 1 to enable voltage
measurements of the CELLx pin. Voltage measured from
CELLx will be used as an input to the fuel gauge if CxEn
= 1 and ChEn = 0, regardless of BtEn state.
BtEn: BATT Channel Enable. Set to 1 to enable voltage
measurements of the V
pin. Voltage measured from
BATT
V
will be used as an input to the fuel gauge only if
BATT
nPackCfg Register (1B5h)
Register Type: Special
BtEn = 1, CxEn = 0, and ChEn = 0.
ChEn: CELL Channel Enable. Set to 1 to enable voltage
measurements of the CELL1, CELL2, and V
Nonvolatile Restore: PackCfg (0BDh)
pins.
BATT
The nPackCfg register configures the voltage and tem-
perature inputs to the ADC and also to the fuel gauge.
nPackCfg configuration must match the pack hardware
for proper operation of the IC. See the Typical Operating
Circuits section for recommended nPackCfg settings
based on operating circuit configuration. The default fac-
tory setting for nPackCfg is 0x0C01 for the MAX172x1
and 0x0A02 for the MAX172x5. Figure 37 shows the
register format.
Voltage measured from these pins is used as an input to the
fuel gauge if ChEn = 1 regardless of CxEn and BtEn states.
TdEn: Die Temperature Enable. Set to 1 to enable inter-
nal temperature measurements.
A1En: AIN1 Channel Enable. Set to 1 to enable tempera-
ture measurements on the AIN1 pin.
A2En: AIN2 Channel Enable. Set to 1 to enable tempera-
ture measurements on the AIN2 pin.
NCELLS: Number of Cells. This field configures the ICs
for the number of cells in series in the cell pack. This field
value must match the cell stack size for proper operation
of the fuel gauge and other IC functions.
FGT: Fuel Gauge Temperature Input Select. FGT in
combination with the TdEn, A1en, and A2en bits deter-
mines which temperature measurement is used by the
fuel gauge. This allows multiple temperature inputs to be
measured and still control which one is the input to the fuel
gauge. Table 8 shows how the fuel gauge input is selected.
0: Always write 0.
Table 7. Recommended nRSense Register Values for Common-Sense Resistors
SENSE RESISTOR
NRSENSE REGISTER
0.005Ω
0x01F4
0.010Ω
0x03E8
0.020Ω
0x07D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FGT
0
A2En A1En TdEn ChEn BtEn CxEn
BALCFG
0
NCELLS
Figure 37. PackCfg (0BDh)/nPackCfg (1B5h) Format
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Table 8. Fuel Gauge Temperature Input
FUEL GAUGE INPUT/TEMP
FGT
A2EN
A1EN
TDEN
REGISTER
0
1
0
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
Internal/DieTemp (135h)
AIN1/Temp1 (134h)
AIN2/Temp2 (13Bh)
AIN2/Temp2 (13Bh)
Internal/DieTemp (135h)
AIN1/Temp1 (134h)
AIN1/Temp1 (134h)
Temp1 (134h) and Temp2 (13Bh)
AIN1/Temp1 (134h)
Temp1 (134h) and Temp2 (13Bh)
Illegal Configuration
All Other Configurations
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
enOCV enX
0
0
enCfg enFCfg enRCfg enLCfg enICT enCG enVE enDC enMC enAF enHCfg enSBS
Figure 38. nNVCfg0 (1B8h) Format
enAF: Enable Age Forecasting. Set this bit to enable Age
Forecasting functionality. When this bit is clear nAgeFc-
Cfg can be used for general purpose data storage. When
set, nSOC and nVoltTemp become repurposed for age
forecasting data. When enAF is set to 1, nNVCfg2.enVT
and nNVCfg2.enSOC must be 0 for proper operation.
nNVCfg0 Register (1B8h)
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
The nNVCfg0 register manages nonvolatile memory
backup of device and fuel gauge register RAM locations.
Each bit of the nNVCfg0 register, when set, enables a
given register location to be restored from a correspond-
ing nonvolatile memory location after reset of the IC. If
nonvolatile restore of a given register is not enabled, that
location initializes to a default value after reset instead.
See the individual register descriptions for details. The
factory default value for nNVCfg0 register is 0x0100.
Figure 38 shows the nNVCfg0 register format.
enMC: Enable MiscCfg restore. Set this bit to enable
MiscCfg register to be restored after reset by the nMisc-
Cfg register. When this bit is cleared, MiscCfg restores
with its alternate initialization value and nMiscCfg can be
used for general- purpose data storage.
enDC: Enable DesignCap restore. Set this bit to enable
DesignCap register to be restored after reset by the
nDesignCap register. When this bit is cleared, DesignCap
restores with its alternate initialization value and nDesign-
Cap can be used for general-purpose data storage.
enSBS: Enable SBS. This bit enables SBS functions of
the IC. When set, all registers accessed with the SBS
2-Wire address will be regularly updated. When this bit
is clear all SBS related nonvolatile configuration register
locations can be used as general-purpose user memory.
enVE: Enable VEmpty restore. Set this bit to enable
VEmpty register to be restored after reset by the nVEmpty
register. When this bit is cleared, VEmpty restores with its
alternate initialization value and nVEmpty can be used for
general purpose data storage.
enHCfg: Enable HibCfg restore. Set this bit to enable
HibCfg register to be restored after reset by the nHibCfg
register. When this bit is cleared, HibCfg restores with its
alternate initialization value and nHibCfg can be used for
general-purpose data storage.
enCG: Enable CGain and COff restore. Set this bit to
enable CGain and COff registers to be restored after reset
by the nCGain register. When this bit is cleared, CGain
and COff restore with their alternate initialization values
and nCGain can be used for general-purpose data storage.
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enICT: Enable IChgTerm restore. Set this bit to enable
IChgTerm register to be restored after reset by the nIChg-
Term register. When this bit is cleared, IChgTerm restores
to a value of 1/3rd of the nFullCapNom register and nICh-
gTerm can be used for general-purpose data storage.
The nNVCfg1 register manages nonvolatile memory
restore of device and fuel gauge register RAM locations.
Each bit of the nNVCfg1 register, when set, enables a
given register location to be restored from a corresponding
nonvolatile memory location after reset of the ICs. If non-
volatile backup of a given register is not enabled, that loca-
tion initializes to a default value after reset instead. See the
individual register descriptions for details. Figure 39 shows
the nNVCfg1 register format.
enLCfg: Enable LearnCfg restore. Set this bit to enable
LearnCfg register to be restored after reset by the
nLearnCfg register. When this bit is cleared, LearnCfg
restores with its alternate initialization value and nLearnCfg
can be used for general-purpose data storage.
0: This location must remain 0. Do not write this location to 1.
enRCfg: Enable RelaxCfg restore. Set this bit to enable
RelaxCfg register to be restored after reset by the nRelax-
Cfg register. When this bit is cleared, RelaxCfg restores
with its alternate initialization value and nRelaxCfg can be
used for general-purpose data storage.
enCTE: Enable Converge-to-Empty. Set this bit to enable
the nConvgCfg register settings to affect the converge
to empty functionality of the IC. When this bit is clear,
converge-to-empty is disabled and nConvgCfg can be
used for general- purpose data storage.
enFCfg: Enable FilterCfg restore. Set this bit to enable
FilterCfg register to be restored after reset by the nFilter-
Cfg register. When this bit is cleared, FilterCfg restores
with its alternate initialization value and nFilterCfg can be
used for general-purpose data storage.
enCrv: Enable Curve Correction. Set this bit to enable
curvature correction on thermistor readings, improving
thermistor translation performance to -40°C to +80°C
(instead of -10°C to +50°C). Note that enCrv and enMtl
are mutually exclusive functions. Do not set both enCrv
and enMtl at the same time.
enCfg: Enable Config and Config2 restore. Set this bit to
enable Config and Config2 registers to be restored after
reset by the nConfig register. When this bit is cleared,
Config and Config2 restore with their alternate initializa-
tion values and nConfig can be used for general-purpose
data storage.
enAT: Enable Alert Thresholds. Set this bit to enable
IAlrtTh, VAlrtTh, TAlrtTh, and SAlrtTh registers to be
restored after reset by the nIAlrtTh, nVAlrtTh, nTAlrtTh,
and nSAlrtTh registers respectively. When this bit is
cleared, these registers restore with their alternate initial-
ization values and the nonvolatile locations can be used
for general-purpose data storage.
0: This location must remain 0. Do not write this location to 1.
enX: Enable XTable restore. Set this bit to enable nXTable
register locations to be used for cell characterization data.
When this bit is cleared, the ICs use the default cell model
and all nXTable register locations can be used as general-
purpose user memory.
enTTF: Enable time to full configuration. Set to 1 to enable
nTTFCfg (configures CVMixCap and CVHalftime) for tun-
ing of time-to-full performance. Otherwise, CVMixCap and
CVHalftime restore to their alternate initialization values and
nTTFCfg can be used for general-purpose data storage.
enOCV: Enable OCVTable restore. Set this bit to enable
nOCVTable register locations to be used for cell charac-
terization data. When this bit is cleared, the ICs use the
default cell model and all nOCVTable register locations
can be used as general-purpose user memory.
enODSC: Enable OD and SC overcurrent comparators.
Set this bit to enable ODSCTh and ODSCCfg registers
to be restored after reset by the nODSCTh and nODSC-
Cfg registers. When this bit is cleared, ODSCTh and
ODSCCfg restore with their alternate initialization values
(comparators disabled) and nODSCTh and nODSCCfg
can be used for general- purpose data storage.
nNVCfg1 Register (1B9h)
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
enTGO enMtl enFTh enRFVSH enODSC
0
0
0
0
0
0
enTTF enAT enCrv enCTE
0
Figure 39. nNVCfg1 (1B9h) Format
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enRFVSH: Enable RFast and VShdnCfg restore. Set this
bit to enable RFast and VShdnCfg registers to be restored
after reset by the nRFastVShdn register. When this bit is
cleared, RFast and VShdnCfg restore with their alternate
initialization values and nRFastVShdn can be used for
general-purpose data storage.
CYCLESpSAVE value. CYCLESpSAVE has an LSb
weight of 0.5 cycles giving a full range of 0.5 to 64.5
cycles (with an offset of +0.5 cycles). For example, set
CYCLESpSAVE to 19d to automatically save every 10
cycles. Since the MAX1720x/1x provides 202 history
writes, choose CYCLESpSAVE carefully according to the
maximum battery cycle lifespan. For example, if the bat-
tery supports 1000 cycles, set CYCLESpSAVE to at least
5 cycles (CYCLESpSAVE = 9).
enFTh: Enable FullSOCThr configuration restore. Set
this bit to enable FullSOCThr register to be restored
after reset by the nFullSOCThr register. When this bit is
cleared, FullSOCThr restore with its alternate initializa-
tion value and nFullSOCThr can be used for general-
purpose data storage.
enMet: Enable metal current sensing. Setting this bit to
1 enables temperature compensation of current read-
ings for allowing copper trace current sensing. This also
forces the PackCfg.TdEn bit to 1 after reset of the ICs
to guarantee internal temperature measurements occur.
See also nNVCfg1.enMtl, which enables nTCurve register
operation for adjustment of the current sensing tempera-
ture coefficient.
enMtl: Enable CGTempCo restore. Set this bit to enable
CGTempCo register to be restored after reset by the
nTCurve register. When this bit is cleared, CGTempCo
restores with its alternate initialization value. nTCurve can
be used for general-purpose data storage if both enCrv
and enMtl are clear. Do not set both enCrv and enMtl at
the same time.
enIAvg: Enable IAvgEmpty backup and restore. Set
this bit to enable IAvgEmpty register to be restored after
reset by the nIAvgEmpty register. When this bit is clear
IAvgEmpty will restore with its alternate initialization
value and nIAvgEmpty can be used as general-purpose
memory.
enTGO: Enable TGain and TOff restore. Set this bit to
enable TGain and TOff registers to be restored after
reset by the nTGain and nTOff registers. When this bit
is cleared, TGain and TOff restore with their alternate
initialization values. nTGain and nTOff can then be used
for general-purpose data storage.
enFC: Enable FullCap and FullCapRep backup and
restore. Set this bit to enable FullCap and FullCapRep
registers to be restored after reset by the nFullCapRep
register and FullCapRep to backup to nFullCapRep.
When this bit is clear FullCap and FullCapRep registers
restore from the nFullCapNom register. nFullCapRep can
then be used as general purpose user memory.
nNVCfg2 Register (1BAh)
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
enVT: Enable Voltage and Temperature backup. Set this
bit to enable storage of AvgVCell and AvgTA register
information into the nVoltTemp register during save opera-
tions. There is no corresponding restore option. When
nNVCfg2.enVT and nNVCfg0.enAF are clear nVoltTemp
can be used as general purpose memory. Note that enVT
should not be set simultaneously with nNVCfg0.enAF
(AgeForecasting).
The nNVCfg2 register manages nonvolatile memory back-
up and restore of device and fuel gauge register RAM loca-
tions. Each bit of the nNVCfg2 register, when set, enables
a given register location to be restored from or backed up
to a corresponding nonvolatile memory location after reset
of the ICs. If nonvolatile backup of a given register is not
enabled, that location initializes to a default value after
reset instead. See the individual register descriptions for
details. Figure 40 shows the nNVCfg2 register format.
enMMC: Enable MinMaxCurr Backup. Set this bit to
enable storage of MinMaxCurr register information into
the nMinMaxCurr register during save operations. There
is no corresponding restore option. When this bit is clear
nMinMaxCurr can be used as general-purpose memory.
CYCLESpSAVE: Cycles per Save. This field defines the
number of equivalent full cell cycles between backup
operations. A backup operation occurs each time the
Cycles register exceeds the nCycles register plus the
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
enT enSOC enMMT enMMV enMMC enVT enFC enIAvg enMet
CYCLESpSAVE
Figure 40. nNVCfg2 (1BAh) Format
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enMMV: Enable MinMaxVolt Backup. Set this bit to
enable storage of MinMaxVolt register information into
the nMinMaxVolt register during save operations. There
is no corresponding restore option. When this bit is clear
nMinMaxVolt can be used as general-purpose memory.
regulators and enters low-power mode. Figure 41 shows
the ShdnTimer register format.
CTR: Shutdown Counter. This register counts the total
amount of elapsed time since the shutdown trigger event.
This counter value stops and resets to 0 when the shut-
down timeout completes. The counter LSb is 1.4s
enMMT: Enable MinMaxTemp Backup. Set this bit to
enable storage of MinMaxTemp register information into
the nMinMaxTemp register during save operations. There
is no corresponding restore option. When this bit is clear
nMinMaxTemp can be used as general-purpose memory.
THR: Sets the shutdown timeout period from a minimum
of 45s to a maximum of 1.6h. The default POR value of 0h
gives a shutdown delay of 45s in active mode. In default
hibernate mode, the minimum shutdown time is 12 min-
utes. The equation setting the period is:
enSOC: Enable MixSOC and VFSOC Backup. Set this
bit to enable storage of MixSOC and VFSOC register
information into the nSOC register during save opera-
tions. There is no corresponding restore option. When this
bit and nNVCfg0.enAF are clear nSOC can be used as
general purpose memory. Note that enSOC should not be
set simultaneously with nNVCfg0.enAF (AgeForecasting).
(8+THR)
Shutdown Timeout Period = 175.8ms • 2
mode
in active
nConfig Register (1B0h)
Register Type: Special
Nonvolatile Restore: Config (01Dh) and Config2 (0BBh) if
nNVCfg0.enCfg is set.
enT: Enable TimerH backup and restore. Set this bit to
enable TimerH register to be backed up and restored by
the nTimerH register. When this bit is cleared, TimerH
restores with its alternate initialization value and nTimerH
can be used as general-purpose memory.
Alternate Initial Value: 0x2210 for Config, 0x0050 for
Config2
The nConfig register holds all shutdown enable, alert
enable, and temperature enable control bits. Writing a bit
location enables the corresponding function within one
task period. Figure 42, Figure 43, and Figure 44 show the
register formats.
ShdnTimer Register (03Fh)
Register Type: Special
Nonvolatile Backup: None
Initial Value: 0x0000
0: Bit must be written 0. Do not write 1.
1: Bit must be written 1. Do not write 0.
The ShdnTimer register sets the timeout period from when
a shutdown event is detected until the device disables the
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
THR
CTR
Figure 41. ShdnTimer (03Fh) Format
D15
D14
D13
D12
D11
D10
D9
D8
Tex
D7
D6
D5
D4
D3
D2
D1
D0
0
SS
TS
VS ALRTp AINSH Ten
SHDN COMMSH ALSH
1
FTHRM Aen dSOCen TAlrtEn
Figure 42. nConfig (1B0h) Format
D15
D14
D13
D12
D11
D10
D9
D8
Tex
D7
D6
D5
D4
D3
D2
D1
D0
0
SS
TS
VS ALRTp AINSH Ten
SHDN COMMSH
0
ETHRM FTHRM Aen Bei
Ber
Figure 43. Config (01Dh) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
POR_CMD
0
0
0
0
0
0
0
0
dSOCen TAlrtEn
0
1
0
0
0
Figure 44. Config2 (0BBh) Format
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Ber: Enable alert on battery removal when the ICs are
mounted host side. When Ber = 1, a battery-removal
condition, as detected by the AIN pin voltage, triggers an
alert. Note that if this bit is set to 1, the ALSH bit should
be set to 0 to prevent an alert condition from causing the
device to enter shutdown mode.
Tex: Temperature External. When set to 1, the fuel gauge
requires external temperature measurements to be writ-
ten from the host. When set to 0, the IC's own measure-
ments as configured by the PackCfg register are used
instead.
Ten: Enable Temperature Channel. Set to 1 and set
ETHRM or FTHRM to 1 to enable temperature measure-
ments as defined in the PackCfg register.
Bei: Enable alert on battery insertion when the ICs are
mounted host side. When Bei = 1, a battery-insertion
condition, as detected by the AIN pin voltage, triggers an
alert. Note that if this bit is set to 1, the ALSH bit should
be set to 0 to prevent an alert condition from causing the
device to enter shutdown mode.
AINSH: AIN1 Pin Shutdown. Set to 1 to enable device
shutdown when the IC is mounted host side and the bat-
tery is removed. The ICs enter shutdown if the AIN1 pin
remains high (AIN1 > V
- V
) for longer than the
THRM
DET
Aen: Enable alert on fuel-gauge outputs. When Aen = 1,
exceeding any of the alert threshold register values by
current, voltage, or SOC triggers an alert. This bit affects
the ALRT1 pin operation only. The Smx, Smn, Tmx, Tmn,
Vmx, Vmn, Imx, and Imn bits of the Status register (000h)
are not disabled. Note that if this bit is set to 1, the ALSH
bit should be set to 0 to prevent an alert condition from
causing the device to enter shutdown mode.
timeout of the ShdnTimer register. This also configures
the device to wake up when AIN1 is pulled low on cell
insertion. Note that if COMMSH and AINSH are both set
to 0, the device wakes up an edge of any of the DQ/SDA
or OD/SCL pins.
ALRTp: ALRT1 Pin Polarity. If ALRTp = 0 the ALRT1 pin is
active low and if ALRTp = 1 the ALRT1 pin is active high.
VS: Voltage ALRT1 Sticky. When VS = 1, voltage alerts
can only be cleared through software. When VS = 0, volt-
age alerts are cleared automatically when the threshold is
no longer exceeded.
FTHRM: Force Thermistor Bias Switch. This allows the
host to control the bias of the thermistor switch or enable
fast detection of battery removal. Set FTHRM = 1 to
always enable the thermistor bias switch. With a standard
10kΩ thermistor, this adds an additional ~200μA to the
current drain of the circuit.
TS: Temperature ALRT1 Sticky. When TS = 1, tempera-
ture alerts can only be cleared through software. When
TS = 0, temperature alerts are cleared automatically when
the threshold is no longer exceeded.
ETHRM: Enable Thermistor. Set to logic 1 to enable the
automatic THRM output bias and AIN1/AIN2 measurement.
SS: SOC ALRT1 Sticky. When SS = 1, SOC alerts can
only be cleared through software. When SS = 0, SOC
alerts are cleared automatically when the threshold is no
longer exceeded.
COMMSH: Communication Shutdown. Set to logic 1 to
force the device to enter shutdown mode if both SDA
and SCL are held low (MAX1720x) or DQ is held low
(MAX1721x) for more than timeout of the ShdnTimer
register. This also configures the device to wake up on a
rising edge of any communication. Note that if COMMSH
and AINSH are both set to 0, the device wakes up an
edge of any of the DQ/SDA or OD/SCL pins. See the
Modes of Operation section.
POR_CMD: Firmware Restart. Set this bit to 1 to restart
IC firmware operation without performing a recall of
nonvolatile memory into RAM. This allows different IC
configurations to be tested without changing nonvolatile
memory settings. This bit is set to 0 at power-up and auto-
matically clears itself after firmware restart. See Reset
Commands.
SHDN: Shutdown. Write this bit to logic 1 to force a shut-
down of the device after timeout of the ShdnTimer register
(default 45s delay). SHDN is reset to 0 at power-up and
upon exiting shutdown mode. In order to command shut-
down within 45s, first write HibCFG = 0x0000 to enter
active mode.
TAlrten: Temperature Alert Enable. Set this bit to 1 to
enable temperature based alerts. Write this bit to 0 to dis-
able temperature alerts. This bit is set to 1 at power-up.
dSOCen: 1% SOC Change Alert Enable. Set this bit to 1
to alert output on 1% SOC change. This bit is set to 0 at
power-up.
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D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Br
Smx
Tmx
Vmx
Bi
Smn
Tmn
Vmn
dSOCi
Imx
X
X
Bst
Imn
POR
X
Figure 45. Status (000h) Format
or may not need to be cleared by system software to
detect the next event. See Config.TS bit description. Tmn
is set to 0 at power-up.
Status Register (000h)
Register Type: Special
Nonvolatile Backup: None
Initial Value: 0x0002
Smn: Minimum SOC Alert Threshold Exceeded. This
bit is set to a 1 whenever SOC falls below the minimum
SAlrtTh value. This bit may or may not need to be cleared
by system software to detect the next event. See Config.
SS and MiscCFG.SACFG bit descriptions. Smn is set to
0 at power-up.
The Status register maintains all flags related to alert
thresholds and battery insertion or removal. Figure 45
shows the Status register format.
POR: Power-On Reset. This bit is set to a 1 when the
device detects that a software or hardware POR event
has occurred. This bit must be cleared by system soft-
ware to detect the next POR event. POR is set to 1 at
power-up.
Bi: Battery Insertion. Useful when the IC is used in a
host-side application. This bit is set to a 1 when the device
detects that a battery has been inserted into the system
by monitoring the AIN1 pin. This bit must be cleared by
system software to detect the next insertion event. Bi is
set to 0 at power-up.
Imn: Minimum Current Alert Threshold Exceeded. This bit
is set to a 1 whenever a Current register reading is below
the minimum IAlrtTh value. This bit is cleared automati-
cally when current rises above minimum IAlrtTh value.
Imn is set to 0 at power-up.
Vmx: Maximum Voltage Alert Threshold Exceeded. This
bit is set to a 1 whenever a VCell register reading is
above the maximum VAlrtTh value. This bit may or may
not need to be cleared by system software to detect the
next event. See Config.VS bit description. Vmx is set to
0 at power-up.
Bst: Battery Status. Useful when the IC is used in a host
side application. This bit is set to 0 when a battery is pres-
ent in the system and set to 1 when the battery is absent.
Bst is set to 0 at power-up.
Tmx: Maximum Temperature Alert Threshold Exceeded.
This bit is set to a 1 whenever a Temperature register
reading is above the maximum TAlrtTh value. This bit
may or may not need to be cleared by system software to
detect the next event. See Config.TS bit description. Tmx
is set to 0 at power-up.
Imx: Maximum Current Alert Threshold Exceeded. This
bit is set to a 1 whenever a Current register reading is
above the maximum IAlrtTh value. This bit is cleared
automatically when current falls below maximum IAlrtTh
value. Imx is set to 0 at power-up.
Smx: Maximum SOC Alert Threshold Exceeded. This bit
is set to a 1 whenever SOC rises above the maximum
SAlrtTh value. This bit may or may not need to be cleared
by system software to detect the next event. See Config.
SS and MiscCFG.SACFG bit descriptions. Smx is set to
0 at power-up.
dSOCi: State of Charge 1% Change Alert. This is set to
1 whenever the RepSOC register crosses an integer per-
centage boundary such as 50.0%, 51.0%, etc. Must be
cleared by host software. dSOCi is set to 0 at power-up.
Vmn: Minimum Voltage Alert Threshold Exceeded. This
bit is set to a 1 whenever a VCell register reading is
below the minimum VAlrtTh value. This bit may or may
not need to be cleared by system software to detect the
next event. See Config.VS bit description. Vmn is set to
0 at power-up.
Br: Battery Removal. Useful when the ICs are used in
a host-side application. This bit is set to a 1 when the
system detects that a battery has been removed from the
system. This bit must be cleared by system software to
detect the next removal event. Br is set to 0 at power-up.
Tmn: Minimum Temperature Alert Threshold Exceeded.
This bit is set to a 1 whenever a Temperature register
reading is below the minimum TAlrtTh value. This bit may
X: Don’t Care. This bit is undefined and can be logic 0 or 1.
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D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hib
PORSkip
Figure 46. Status2 (0B0h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
HibScalar
D0
EnHib
HibEnterTime
HibThreshold
0
0
0
HibExitTime
Figure 47. HibCfg (0BAh)/nHibCfg (1B4h) Format
HibScalar: Sets the task period while in hibernate mode
based on the following equation:
Status2 Register (0B0h)
Register Type: Special
Nonvolatile Backup: None
Initial Value: 0x0000
(HibScalar)
Hibernate Mode Task Period(s) = 702ms x 2
HibExitTime: Sets the required time period of con-
secutive current readings above the HibThreshold value
before the IC exits hibernate and returns to active mode
of operation.
The Status2 register maintains status of hibernate mode.
Figure 46 shows the Status register format.
PORSkip: This bit is set when initialization of the IC’s
RAM is skipped during reset. This occurs under conditions
where the RAM values are already valid prior to a reset
such as when the firmware restart command is sent to the
ICs by software.
Hibernate Mode Exit Time(s) = (HibExitTime + 1) x 702ms
(HibScalar)
x 2
HibThreshold: Sets the threshold level for entering or exit-
ing hibernate mode. The threshold is calculated as a fraction
of the full capacity of the cell using the following equation:
Hib: Hibernate Status. This bit is set to a 1 when the
device is in hibernate mode or 0 when the device is in
active mode. Hib is set to 0 at power-up.
Hibernate Mode Threshold(mA) = (FullCap(μVH)/(0.8
(HibThreshold)
)/2
hours x R
SENSE
HibEnterTime: Sets the time period that consecutive
current readings must remain below the HibThreshold
value before the ICs enter hibernate mode as defined by
the following equation. The default HibEnterTime value of
000b causes the ICs to enter hibernate mode if all cur-
rent readings are below the HibThreshold for a period of
5.625 seconds, but the ICs could enter hibernate mode as
quickly as 2.812s.
X: Don’t Care. This bit is undefined and can be logic 0 or 1.
nHibCfg Register (1B4h)
Register Type: Special
Nonvolatile Restore: HibCfg (0BAh) if nNVCfg0.enHCfg
is set.
Alternate Initial Value: 0x890B (5.625 second hibernate mode)
The nHibCfg register controls hibernate mode function-
ality. The ICs enters hibernate mode if the measured
system current falls below the HibThreshold setting for
longer than the HibEnterTime delay. While in hibernate
mode, the ICs reduce its operating current by slowing
down its task period as defined by the HibScalar setting.
The ICs automatically return to active mode of operation
if current readings go above the HibThreshold setting for
longer than the HibExitTime delay. Figure 47 shows the
register format.
(HibEnterTime)
(HibEnterTime + 1)
2.812s x 2
2.812s x 2
< Hibernate Mode Entry Time <
EnHib: Enable Hibernate Mode. When set to 1, the ICs
enter hibernate mode if conditions are met. When set to 0,
the ICs always remain in active mode of operation.
0: Bit must be written 0. Do not write 1.
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CommStat Register (061h)
Register Type: Special
Cell Balancing (MAX17205/MAX17215 Only)
To maintain equal charge on all cells inside a 2S or 3S
pack, the MAX17205/MAX17215 implements internal 10Ω
cell-balancing MOSFETs. While charging, if the ICs detect
that the voltage of a cell or cells is higher than the aver-
age voltage of the cell pack as determined by PackCfg.
BALCFG setting, the ICs enable an internal shunt FET to
discharge current from the corresponding cell. The small
difference in charging current will balance the charge level
of all cells in the pack over time.
Nonvolatile Backup: None
The CommStat register tracks the progress and error
state of any command sent to the Command register.
Figure 48 shows the register format.
X: Don’t Care. This bit is undefined and can be logic 0
or 1.
NVBusy: This read only bit tracks if nonvolatile memory
is busy or idle. NVBusy defaults to 0 after reset indicating
nonvolatile memory is idle. This bit is set after a nonvola-
tile related command is sent to the command register and
clears automatically after the operation completes.
Cell Balancing Window of Operation
When enabled, cell balancing occurs only during a
window near the end of a charge cycle when certain
conditions are met. First, the voltage fuelgauge state of
charge (VFSOC) register value must be larger than the
FullSOCThr register value indicating the pack is nearly
full. Second, the AvgCurrent register value must be above
0xFFF8 but less than 4 times the IChgTerm register value
indicating the charge cycle is nearing completion. Cell
balancing continues as long as VFSOC remains above
FullSOCThr. Figure 49 shows the window of when cell
balancing may occur.
NVError: This bit indicates the results of the previous
SHA-256 or nonvolatile memory-related command sent
to the command register. This bit is set if there was an
error executing the command. Once set, the bit must be
cleared by software to detect the next error.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
NVError NVBusy
X
Figure 48. CommStat (061h) Format
END OF
CHARGE
AVGCURRENT
READING
4 x ICHGTERM
CHARGING
0mA
0xFFF8
DISCHARGING
CELL BALANCING WINDOW
START OF
LOAD
PACK STATE OF
CHARGE
FULLSOCTHR
VFSOC
Figure 49. Cell Balancing Window of Operation
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Cell Balancing Order and Thresholds
Cell Balancing Circuits
The IC balances only one cell at a time, in order, starting
with the highest voltage cell in the pack. As soon as the
cell balancing window is entered the maximum and mini-
mum average cell voltages are calculated. If the difference
from max to min is more than the threshold defined by
the PackCfg.BALCFG setting, the corresponding internal
balancing switch is enabled to reduce charging current
flow through the highest cell. Table 9 shows all balancing
threshold levels determined by BALCFG. If enabled, the
recommended balancing threshold is 011b or 10.0mV.
Figure 50 shows the equivalent balancing circuits for 2S
and 3S cell packs. Internal cell-balancing MOSFETs allow
current to be drawn from an individual cell in the pack
during charge. To limit current during cell balancing, an
external resistor must be added in series with the CELL1
and CELL2 pins. If these resistors are not installed, power
in excess of the IC package maximum current rating could
be drawn leading to failure.
Table 9. Cell Balancing Thresholds
AVGCELL(1:4)–VCELL(1:4)
AVGCELL(1:4) - VCELL(1:4)
BALCFG VALUE
BALCFG VALUE
(mV)
(mV)
000
001
010
011
Balancing disabled
100
101
110
111
20.0
40.0
2.5
5.0
80.0
10.0
160.0
PACK+
PACK+
MAX17205/MAX17215
MAX17205/MAX17215
10Ω
10Ω
V
V
BATT
BATT
CELL3
CELL2
1nF
1nF
10Ω
10Ω
10Ω
R
BAL
CELL2
CELL1
CELL2
CELL1
R
BAL
UNUSED
CELL2
CELL1
1nF
1nF
R
BAL
CELL1
10Ω
10Ω
1nF
CSP
CSN
CSP
CSN
CSN (TDFN)
GND (WLP)
CSN (TDFN)
GND (WLP)
GND (WLP (ONLY)
GND (WLP (ONLY)
PACK-
PACK-
3S CONFIGURATION BALANCING CIRCUIT
2S CONFIGURATION BALANCING CIRCUIT
Figure 50. 2S and 3S Balancing Circuits
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measurement to allow for settling of the external filter on
the pin. This pause occurs once every task loop of the
processor and has minimal impact on the average balanc-
ing current as shown in Figure 51.
Cell Balancing Current
External series resistors on the CELL1 and CELL2 pins
are required to limit current flow when balancing. The
value of these resistors should be selected to prevent
exceeding the maximum rated current for these pins as
listed in the Electrical Characteristics table. The balancing
currents will not be the same for each cell. They can be
calculated as follows. Remember to size these resistors
to handle the power dissipated by balancing.
Analog Measurements
The MAX1720x/MAX1721x monitors cell pack voltage,
cell pack current, cell pack temperature, and the voltage
of each cell individually. This information is provided to
the fuel guage algorithm to predict cell capacity and also
made available to the user. Note that ADC related register
information is not maintained while the IC is in shutdown
mode. The following register information is invalid until
the first measurement cycle after the IC returns to active
mode of operation.
Bottom Cell: IBAL
Middle Cell: IBAL
= V
/(R
+R
)
MAX
CELL-MAX BAL Switch
= V
/(R
+R
)
MAX
CELL-MAX BAL Switch
Top Cell:
(R +R
IBAL
= V
/
MAX
CELL-MAX
+10Ω)
BAL SWITCH
where:
Voltage Measurement
R
is 10Ω (typ)
SWITCH
The MAX1720x/MAX1721x can monitor each cell in the
cell stack independently using the CELL1, CELL2, and
V
is the maximum cell voltage during charging
CELL-MAX
R
is the external series resistor to limit current
V
pins. The voltage of the entire stack in 2S to 4S
BAL
BATT
configurations is also monitored directly on the V
pin.
BATT
Note that a minimum resistance of R
should be kept
BAL
For larger cell stacks, the CELLx pin monitors an resistor
divider circuit. The cell balancing switches are managed
by firmware to ensure that balancing is disabled during
the sample window. Averages of individual cell voltages
are also tracked as well as the minimum and maximum
voltages seen by the fuel gauge. See the individual volt-
age register descriptions for details.
above75Ωtopreventthebalancingcurrentfromexceeding
the absolute maximum current ratings for the V
,
BATT
CELL1, CELL2, CSN (TDFN), and GND (WLP) pins.
Cell Balancing Duty Cycle
The ICs temporary interrupt cell balancing to prevent
interference with voltage and current measurements.
Balancing is disabled 45ms minimum prior to making a
55ms TYP
SETTLING TIME
BALANCING
AND ADC
BALANCING
ACTIVE
ACTIVE
MEASUREMENTS
351ms TYPICAL
Figure 51. Cell Balancing Duty Cycle
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Each update cycle, the lowest reading from all cell volt-
age measurements is placed in the VCell register. VCell
is used as the voltage input to the fuel gauge algorithm.
Voltage Measurement Timing
All analog measurements made by the IC are done so through
a single ADC with many input channels. ADC measurement
order and firmware post processing determine when a valid
reading becomes available to the user. In addition, not all
channels are measured each time through the firmware task
loop. Selection options for enabled channels creates a large
number of possible timing options. Table 10 shows the tim-
ing for all voltage measurements made by the IC for typical
pack configurations. Table values assume the corresponding
voltage measurement channel has been enabled through
configuration. All times in this table are considered typical.
AvgVCell Register (019h)
Register Type: Voltage
Nonvolatile Backup: None
The AvgVCell register reports an average of the VCell
register readings. The time period for averaging is con-
figurable from a 12-second to 24-minute time period. See
the FilterCfg register description for details on setting the
time filter. The first VCell register reading after power-up
or exiting shutdown mode sets the starting point of the
AvgVCell register. Note that when a cell relaxation event
is detected, the averaging period changes to the period
defined by the RelaxCfg.dt setting. The register reverts
back to its normal averaging period when a charge or
discharge current is detected.
VCell Register (009h)
Register Type: Voltage
Nonvolatile Backup: None
Table 10. Voltage Measurement Timing
FIRST UPDATE UPDATE RATE IN
UPDATE RATE IN
HIBERNATE MODE
(s)***
nPackCfg
SETTING
APPLICATION
VOLTAGES
REGISTER
AFTER RESET
ACTIVE MODE
(ms)*
(ms)**
Cell1, VCell
AvgCell1
150
700
450
150
450
150
450
200
750
450
250
1S Cell Pack
0x1C01
351
5.625
AvgVCell
Batt, VCell
2S–4S Cell Pack w/o
Channel Measurements
****
0x3A0N
351
351
5.625
5.625
AvgVCell
CellX, VCell
****
High-Cell Count Pack
0x390N
AvgVCell
Cell1, Cell2, VCell
AvgCell1, AvgCell2
AvgVCell
702
351
11.25
5.625
2S Cell Pack with
Channel Measurements
0x3C62
0x3C63
Cell1, Cell2, Cell3, VCell
1053
351
16.875
5.625
3S Cell Pack with
Channel Measurements
AvgCell1, AvgCell2,
AvgCell3
800
AvgVCell
450
*AvgCell1, AvgCell2, AvgCell3, and AvgVCell registers are initialized using a single reading instead of an average.
**Not all registers update at the same time. Updates are staggered to one channel per task period. Update order is CellX, Cell1,
Cell2, Cell3, then Batt.
***Hibernate mode update times assume the default HibCfg.HibScalar (0xB, 5.625s) setting of 16 task periods.
****N indicates number of cells in series.
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and Cell3 registers. The measurements for the lowest
cell in the stack, second cell, and third cell are placed in
Cell1, Cell2, and Cell3 registers respectively. If PackCfg.
ChEn = 0, PackCfg.CxEn = 0, and PackCfg.BtEn = 1 then
each register up to Cell4 is populated with Batt/PackCfg.
NCELLS. If PackCfg.ChEn = 0, PackCfg.BtEn = 0, and
PackCfg.CxEn = 1 then each register up to Cell4 is popu-
lated with the Cellx reading.
MaxMinVolt Register (01Bh)
Register Type: Special
Nonvolatile Backup: saves to nMaxMinVolt (1ACh) if
nNVCfg2.enMMV is set (does not restore from nonvolatile).
Initial Value: 0x00FF
The MaxMinVolt register maintains the maximum and
minimum of VCell register values since device reset. Each
time the voltage registers update, they are compared
against these values. If the new reading is larger than the
maximum or less than the minimum, the corresponding
value is replaced with the new reading. At power-up, the
maximum voltage value is set to 00h (the minimum) and
the minimum voltage value is set to FFh (the maximum).
Therefore, both values are changed to the voltage regis-
ter reading after the first update. Host software can reset
this register by writing it to its power-up value of 0x00FF.
The maximum and minimum voltages are each stored as
8-bit values with a 20mV resolution. Figure 52 shows the
register format.
AvgCell1 (0D4h)/AvgCell2 (0D3h)/AvgCell3 (0D2h)/
AvgCell4 (0D1h) Registers
Register Type: Voltage
Nonvolatile Backup: None
The AvgCell1, AvgCell2, AvgCell3, and AvgCell4 registers
report an 8-sample filtered average of the corresponding
Cell1, Cell2, Cell3, and Cell4 register readings, respectively.
CellX Register (0D9h)
Register Type: Voltage
Nonvolatile Backup: None
MaxVCell: Maximum VCell register reading (20mV
resolution)
The CellX register reports two times the voltage mea-
sured on the CELLx pin (V
- V
). The external
CELLx
CSP
MinVCell: Minimum VCell register reading (20mV
resolution)
resistor divider on the CELLx pin should always divide to
2/5 of the voltage of a single cell.
MaxMinVolt is not cumulative across the entire battery
lifetime. After each periodic nonvolatile-memory save,
MaxMinVolt resets to 0x00FF to find the next max/min
volt across the next segment of battery life. This behav-
ior helps provide a useful log across the battery lifetime
where each log segment shows the maximum and mini-
mum voltage experienced across only that segment.
Batt Register (0DAh)
Register Type: Special
Nonvolatile Backup: None
The Batt register reports the voltage of the entire cell
stack in 2S to 4S configuration. The register has a range
0 to 81.92V but is limited by the maximum voltage of the
VBATT pin. It has an LSb resolution of 1.25mV.
Cell1 (0D8h)/Cell2 (0D7h)/Cell3 (0D6)/Cell4 (0D5h)
Registers
If PackCfg.ChEn = 1, Batt is calculated by Cell1 + Cell2
+ Cell3.
Register Type: Voltage
Nonvolatile Backup: None
Otherwise, if PackCfg.CxEn = 1, Batt is calculated by
Cellx x PackCfg.NCELLS, giving a maximum output of
76.8V when using 15-cell configuration.
These registers maintain the measured or calculated volt-
age of each cell in the stack. If PackCfg.ChEn = 1 the ICs
monitor each cell (V
-V
, V
- V
, and
Otherwise, if PackCfg.BtEn = 1, Batt is a direct measure-
BATT CELL2 CELL2
CELL1
V
- V
) and reports results in the Cell1, Cell2,
ment of the V
pin with up to 20.48V range.
CELL1
CSP
BATT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MaxVCell
MinVCell
Figure 52. MaxMinVolt (01Bh)/nMaxMinVolt (1ACh) Format
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Current Measurement
Current Measurement Timing
The MAX1720x/MAX1721x monitors the current flow
through the cell pack by measuring the voltage between
the CSN and CSP pins over a ±51.2mV range. In active
mode, updates occur in intervals of 351.5ms. In hibernate
mode the update interval is set by the HibCfg register.
The cell balancing switches are managed by firmware to
ensure that balancing is disabled during the sample win-
dow. All ICs are calibrated for current-measurement accu-
racy at the factory. However, if the application requires,
Current register readings can be adjusted by changing
the COff and CGain registers using nCGain.
Current measurements are always enabled regardless of
nPackCfg settings. Table 11 shows the timing for current
measurements made by the ICs. All times in this table are
considered typical.
Current Register (00Ah)
Register Type: Current
Nonvolatile Backup: None
The IC measures the voltage between the CSP and CSN
pins and the result is stored as a two’s complement value
in the Current register. Voltages outside the minimum and
maximum register values are reported as the minimum or
maximum value. The register value should be divided by
the sense resistance to convert to amps. The value of the
sense resistor determines the resolution and the full-scale
range of the current readings. Table 12 shows range and
resolution values for typical sense resistances.
If the application uses a sense resistor with a large tem-
perature coefficient such as a copper metal board trace,
current readings can be adjusted based on the tempera-
ture measured by the ICs. The CGTempCo register stores
a percentage per °C value that is applied to current read-
ings if the nNVCfg2.enMet bit is set. If nNVCfg1.enMtl =
0, the default temperature coefficient of copper is used
for temperature adjustments. If enMtl = 1, the CGTempCo
register value is used for temperature adjustments.
AvgCurrent Register (00Bh)
Register Type: Current
Nonvolatile Backup: None
Additionally, the IC maintains a record of the minimum
and maximum current measured by the ICs and an
average current over a time period defined by the host.
Contents of the Current and AvgCurrent registers are
indeterminate for the first conversion cycle time period
after IC power-up.
The AvgCurrent register reports an average of Current
register readings over a configurable 0.7-second to 6.4-
hour time period. See the FilterCfg register description for
details on setting the time filter. The first Current register
reading after returning to active mode sets the starting
point of the AvgCurrent filter.
Table 11. Current Measurement Timing
FIRST UPDATE
AFTER RESET
(ms)*
UPDATE RATE
IN ACTIVE MODE HIBERNATE MODE
UPDATE RATE IN
nPackCfg
SETTING
APPLICATION
CURRENTS
Any
REGISTER
(ms)
(s)**
CurrentCurrent
AvgCurrent
150
150
351
351
5.625
5.625
Any
*AvgCurrent register is initialized using a single reading instead of an average.
**Hibernate mode update times assume the default HibCfg.HibScalar (0xB, 5.625s) setting of 16 task periods.
Table 12. Current Measurement Range and Resolution vs. Sense Resistor Value
SENSE RESISTOR (CGAIN=0X0400)
(Ω)
CURRENT REGISTER RESOLUTION
(μA)
CURRENT REGISTER RANGE
(A)
0.005
0.010
0.020
312.5
156.25
78.125
±10.24
±5.12
±2.56
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Alternate Initial Value: CGain = 0x0400 and COff = 0x0000
MaxMinCurr Register (01Ch)
Register Type: Special
The CGain and COff registers adjust the gain and offset
of the current measurement result. The current measure-
ment ADC is factory trimmed to data sheet accuracy
without the need for the user to make further adjustments.
The default power-up settings for CGain and COff apply
no adjustments to the Current register reading. For specif-
ic application requirements, the CGain and COff registers
can be used to adjust readings as follows:
Nonvolatile Backup: Periodically saves to nMaxMinCurr
(1ABh) if nNVCfg2.enMMC is set, but does not restore
from nonvolatile memory.
Alternate Initial Value: 0x807F
The MaxMinCurr register maintains the maximum and
minimum Current register values since the last IC reset or
until cleared by the host software. Each time the Current
register updates, it is compared against these values. If
the reading is larger than the maximum or less than the
minimum, the corresponding value is replaced with the
new reading. At power-up, the maximum current value is
set to 80h (the minimum) and the minimum current value
is set to 7Fh (the maximum). Therefore, both values are
changed to the Current register reading after the first
update. Host software can reset this register by writing it
to its power-up value of 0x807F. The maximum and mini-
mum voltages are each stored as two’s complement 8-bit
Current Register = Current ADC Reading × (CGain
Register/0400h) + COff Register
The nonvolatile backup of CGain and COff is combined
into a single register formatted as shown in Figure 54.
nCOff: Value to restore into the COff register giving a
range of -32 to +31 LSbs. COff signs extend if the value
is negative.
nCGain: Value to restore into bits D11 to D2 of the CGain
register as in the following equation. nCGAIN can be a
negative value. CGain signs extend to maintain polarity.
values with 0.4mV/R
the register format.
resolution. Figure 53 shows
SENSE
CGain = (nCGain AND 0xFFC0) >> 4
CGTempCo Register (16Dh)
Register Type: Special
MaxCurrent: Maximum Current register reading
(0.40mV/R resolution)
SENSE
MinCurrent: Minimum Current register reading
(0.40mV/R resolution)
Alternate Initial Value: 0x20C8
SENSE
If nNVCfg1.enCrv = 0 and nNVCfg2.enMet = 1 then use
CGTempCo to adjust current measurements for tempera-
ture. CGTempCo has a range of 0% to 3.1224% per °C
with a step size of 3.1224/0x10000 percent per °C. If
the nNVCfg1.enMtl bit is clear, CGTempCo defaults to a
value of 0x20C8 or 0.4% per °C, which is the approximate
temperature coefficient of a copper trace. If the nNVCfg1.
enMtl bit is set, CGTempCo restores from nTCurve (1C9h)
after the ICs reset to allow a custom-sense resistor tem-
perature coefficient to be used. Note that nNVCfg1.enCrv
and nNVCfg2.enMet cannot be enabled simultaneously.
MaxMinCurr is not cumulative across the entire battery
lifetime. After each periodic nonvolatile-memory save,
MaxMinCurr resets to 0x807F to find the next maximum
and minimum current across the next segment of battery
life. This behavior helps provide a useful log across the
battery lifetime in which each log segment shows the
maximum and minimum current experienced across only
that segment.
nCGain Register (1C8h)
Register Type: Special
Nonvolatile Restore: CGain (02Eh) and COff (02Fh) if
nNVCfg0.enCG is set.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MaxCurrent
MinCurrent
Figure 53. MaxMinCurr (01Ch)/nMaxMinCurr (1ABh) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nCGain
nCOff
Figure 54. nCGain Register (1C8h) Format
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Measurement results are compared to the voltage of the
THRM pin and converted to a ratiometric value from 0 to
100%. The active pullup is disabled when temperature
measurements are complete. This feature limits the time
the external resistor-divider network is active and lowers
the total amount of energy used by the system.
Copper Trace Current Sensing
The MAX1720x/1x has the ability to measure current
using a copper board trace instead of a traditional sense
resistor. The main difference being the ability to adjust
to the change in sense resistance over temperature.
To enable copper trace current sensing, set the follow-
ing configuration bits: nNVCfg1.enCrv=0 and nNVCfg2.
enMet=1. The IC's default temperature adjustment is
0.4% per °C, but can be adjusted using the nTCurve reg-
ister if nNVCfg1.enMtl=1. Note that copper trace current
sensing cannot be enabled at the same time as thermistor
curve adjustment. For 1-ounce copper, a length to width
ratio of 6:1 will create a 0.0035Ω sense resistor which is
suitable for most applications. Table 13 summarizes the
IC setting for copper trace sensing.
The ratiometric results are converted to temperature
using the temperature gain (TGain), temperature offset
(TOff), and temperature curve (nTCurve) register values
each time the AIN1 and AIN2 pins are measured. Internal
die temperature measurements are factory calibrated and
are not affected by TGain, TOff, nTCurve register settings.
Additionally the IC maintains a record of the minimum and
maximum temperature measured, and an average tem-
perature over a time period defined by the host.
Temperature Measurement
Temperature Measurement Timing
The IC can be configured to measure its own internal die
temperature and up to two external NTC thermistors. In
addition the IC can be configured to use any single input
or an average of both thermistors as the temperature
input to the fuel gauge calculations. See the nPackCfg
register for details.
Temperature measurement channels are individually
enabled using the nPackCfg register. ADC measurement
order and firmware post processing determine when a
valid reading will become available to the user. In addi-
tion, not all channels are measured each time through the
firmware task loop. Selection options for enabled chan-
nels creates a large number of possible timing options.
Table 14 shows the timing for all temperature measure-
ments made by the IC for some typical pack configura-
tions. All times in this table are considered typical.
Thermistor conversions are initiated by connecting the
THRM and REG3 pins internally. This enables the active
pullup to the external voltage-divider network. After the
pullup is enabled, the IC waits for a settling period of t
PRE
prior to making measurements on the AIN1 or AIN2 pins.
Table 13. Copper Trace Sensing
PARAMETER
SETTING
RESULT
nNVCfg1.enCRV
0
Thermistor curve compensation disabled
Sense resistor temperature compensation
enabled
nNVCfg1.enMet
1
Sense resistor temperature compensa-
tion set to default of 0.4% per °C (typical
copper).
nNVCfg2.enMlt
0
Sense resistor indicator to host software
set to 0.0035Ω as demonstrated on the
evaluation kit hardware.
nRense
0x012C
6:1
A 6:1 length to width ratio of 1oz copper
gives a resistance of 0.0035Ω.
R
Size
SENSE
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Table 14. Temperature Measurement Timing
FIRST UPDATE UPDATE RATE
UPDATE RATE
IN HIBERNATE
MODE*** (s)
APPLICATION
nPackCfg SETTING
REGISTER
AFTER RESET
(ms)*
IN ACTIVE
MODE** (ms)
TEMPERATURES
Temp, IntTemp,
AvgIntTemp
nPackCfg.TdEn = 1
nPackCfg.A1En = 0
nPackCfg.A2En = 0
nPackCfg.FGT = 0
703
Die Temperature
Only
550
550
550
550
5.625
5.625
AvgTA
351
703
Temp, Temp1, AvgTemp1
nPackCfg.TdEn = 0
nPackCfg.A1En = 1
nPackCfg.A2En = 0
nPackCfg.FGT = 0
Single
Thermistor Only
AvgTA
351
IntTemp, Temp1, Temp,
IntTemp, Temp1, Temp,
AvgIntTemp, AvgTemp1
Die Temperature
and Single
Thermistor,
Fuel Gauge
Thermistor 1
nPackCfg.TdEn = 1
nPackCfg.A1En = 1
nPackCfg.A2En = 0
nPackCfg.FGT = 0
1406
351
11.25
5.625
16.875
5.625
AvgTA
IntTemp, Temp1, Temp2,
Temp, AvgIntTemp,
AvgTemp1,AvgTemp2
nPackCfg.TdEn = 1
nPackCfg.A1En = 1
nPackCfg.A2En = 1
nPackCfg.FGT = 1
2109
All Channels
Active, Fuel Gauge
Thermistor 1
AvgTA
Temp
351
Twice in
2109****
Twice in
16.875****
All Channels
Active, Average of
Both Thermistors
for Fuel Gauging
nPackCfg.TdEn = 1
nPackCfg.A1En = 1
nPackCfg.A2En = 1
nPackCfg.FGT = 0
IntTemp, Temp1,
Temp2, AvgIntTemp,
AvgTemp1,AvgTemp2
550
2109
16.875
AvgTA
351
5.625
*All enabled registers are initialized using the first temperature reading the IC makes even if it is from a different temperature input.
**Not all registers update at the same time. Updates are staggered to one channel per task period. Update order is IntTemp, Temp1,
Temp2.
***Hibernate mode update times assume the default HibCfg.HibScalar setting of 16 task periods.
****Update interval in active mode alternates between 703ms and 1406ms. Update interval in hibernate mode alternates between
5.625s and 11.25s
Temp Register (008h)
Register Type: Temperature
Nonvolatile Backup: None
AvgTA Register (016h)
Register Type: Temperature
Nonvolatile Backup: None
The AvgTA register reports an average of the readings
from the Temp register. Averaging period is configurable
from 6 minutes up to 12 hours as set by the FilterCfg
register. The first Temp register reading after returning to
active mode sets the starting point of the averaging filters.
The Temp register value is selected from Temp1, Temp2,
IntTemp, or alternating between Temp1 and Temp2 regis-
ters as determined by the nPackCfg register setting. The
Temp register is the input to the fuel gauge algorithm.
Contents of Temp are indeterminate for the first conver-
sion cycle time period after IC power-up.
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the maximum and minimum temperature experienced
across only that segment.
MaxMinTemp Register (01Ah)
Register Type: Special
nTCurve Register (1C9h)
Nonvolatile Backup: periodically saves to nMaxMinTemp
(1ADh) if nNVCfg2.enMMT is set, but does not restore
from nonvolatile memory.
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register
Alternate Initial Value: 0x807F
The MaxMinTemp register maintains the maximum and
minimum Temp register (008h) values since the last fuel-
gauge reset or until cleared by host software. Each time
the Temp register updates, it is compared against these
values. If the reading is larger than the maximum or less
than the minimum, the corresponding values are replaced
with the new reading. At power-up, the maximum value is
set to 80h (minimum) and the minimum value is set to 7Fh
(maximum). Therefore, both values are changed to the
Temp register reading after the first update. Host software
can reset this register by writing it to its power-up value
of 0x807F. The maximum and minimum temperatures are
each stored as two’s complement 8-bit values with 1°C
resolution. Figure 55 shows the format of the register.
If nNVCfg1.enCrv = 1 and nNVCfg2.enMet = 0 then
nTCurve applies thermistor measurement curvature cor-
rection to allow thermistor measurements to be accurate
over a wider temperature range. A ±3°C accuracy can
be achieved over a -40°C to 85°C operating range. See
Table 15 for recommended nTCurve values. If nNVCfg1.
enCrv = 0 and nNVCfg2.enMet = 0 this location can be
used to general purpose data storage.
nTGain (1CAh) Register/nTOff (1CBh) Register
Register Type: Special
Nonvolatile Restore: TGain (02Ch) and TOff (02Dh) if
nNVCfg1.enTGO is set
Alternate Initial Value: TGain = 0xEE56 and TOff =
0x1DA4 (associated with nTCurve = 0x0025)
MaxTemperature: Maximum Temp register reading
(1ºC resolution)
External NTC Thermistors generate a temperature related
voltage to be measured by the AIN1 and AIN2 inputs. See
the typical operating circuits for examples of thermistor
circuits. The nTGain, nTOff, and nTCurve registers are
used to calculate temperature from the measurement of
the AIN1 and AIN2 pins with an accuracy of +/-3°C over a
range of -40°C to 85°C. Table 15 lists the recommended
nTGain, nTOff, and nTCurve register values for common
NTC thermistors.
MinTemperature: Minimum Temp register reading
(1ºC resolution)
MaxMinTemp is not cumulative across the entire battery
lifetime. After each periodic nonvolatile memory save,
MaxMinTemp resets to 0x807F to find the next maximum
and minimum temperatures across the next segment
of battery life. This behavior helps provide a useful log
across the battery lifetime where each log segment shows
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MaxTemperature
MinTemperature
Figure 55. MaxMinTemp (01Ah)/nMaxMinTemp (1ADh) Format
Table 15. Register Settings for Common Thermistor Types
R25C
(KΩ)
RECOMMENDED
NTGAIN
RECOMMENDED RECOMMENDED
THERMISTOR
BETA
NTOFF
0x1DA4
0x16A1
0x18E8
NTCURVE
Murata NCP15XH103F03RC
Fenwal 197-103LAG-A01
TDK Type F
10
10
10
3435
3974
4550
0xEE56
0xF49A
0xF284
0x0025
0x0064
0x0035
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state of charge, and available capacity respectively.
Host software should wait two full task periods (703ms
minimum in active mode) after writing the AtRate register
before reading any of the result registers.
Temp1 (134h)/Temp2 (13Bh)/IntTemp (135h) Registers
Register Type: Temperature
Nonvolatile Backup: None
If enabled in the nPackCfg register, the Temp1, Temp2,
and IntTemp registers contain the temperature readings
from the AIN1 thermistor, AIN2 thermistor, and internal
die temperature respectively. Contents of each register
are indeterminate for the first conversion cycle time period
after IC power-up. These registers display temperature in
degrees Celsius starting at absolute zero, -273ºC or 0ºK
with an LSb of 0.1ºC.
AtRate Register (004h)
Register Type: Current
Nonvolatile Backup: None
Host software should write the AtRate register with a neg-
ative two’s-complement 16-bit value of a theoretical load
current prior to reading any of the at-rate output registers.
AtQResidual Register (0DCh)
Register Type: Capacity
AvgTemp1 (137h)/AvgTemp2 (139h)/AvgIntTemp
(138h) Registers
Nonvolatile Backup: None
Register Type: Temperature
Nonvolatile Backup: None
The AtQResidual register displays the residual charge
held by the cell at the theoretical load current level
entered into the AtRate register.
The AvgTemp1, AvgTemp2, and AvgIntTemp registers
report a 4-sample filtered average of the corresponding
Temp1, Temp2, and IntTemp registers respectively. The
first of each temperature register reading after startup
sets the starting point of the averaging filters. These reg-
isters display temperature in degrees Celsius starting at
absolute zero, -273ºC or 0ºK with an LSb of 0.1ºC.
AtTTE Register (0DDh)
Register Type: Time
Nonvolatile Backup: None
The AtTTE register can be used to estimate time to empty
for any theoretical current load entered into the AtRate
register. The AtTTE register displays the estimated time
to empty for the application by dividing AtAvCap by the
AtRate register value.
AIN0 Register (027h)
Register Type: Special
Nonvolatile Backup: None
External temperature measurements on the AIN1 and
AIN2 pins are compared to the THRM pin voltage. The IC
stores the result as a ratio-metric value from 0% to 100%
in the AIN0 register with an LSB of 0.0122%. The nTGain,
nTOff, and nTCurve register values are then applied
to this ratio-metric reading to convert the result to tem-
perature. The value stored in the AIN0 register alternates
between measurements made on the AIN1 and AIN2 pins
during operation.
AtAvSOC Register (0CEh)
Register Type: Percentage
Nonvolatile Backup: None
The AtAvSOC register holds the theoretical state of
charge of the cell based on the theoretical current load
of the AtRate register. The register value is stored as a
percentage with a resolution of 0.0039% per LSB. If a 1%
resolution state-of-charge value is desired, the host can
read only the upper byte of the register instead.
At-Rate Functionality
AtAvCap Register (0DFh)
Register Type: Capacity
Nonvolatile Backup: None
The AtRate function allows host software to see theoreti-
cal remaining time or capacity for any given load current.
AtRate can be used for power management by limiting
system loads depending on present conditions of the cell
pack. Whenever the AtRate register is programmed to a
negative value indicating a hypothetical discharge current
the AtQResidual, AtTTE, AtAvSOC, and AtAvCap regis-
ters display theoretical residual capacity, time to empty,
The AtAvCap register holds the estimated remaining
capacity of the cell based on the theoretical load current
value of the AtRate register. The value is stored in terms of
µVh and must be divided by the application sense-resistor
value to determine the remaining capacity in mAh.
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comparator has been tripped. These register settings
are maintained in nonvolatile memory if the nNVCfg1.
enODSC bit is set.
Overcurrent Comparators
The MAX1720x/1x contains two programmable fast over-
current comparators called OD and SC that allow spikes
in system current to be detected. Both comparators have
programmable threshold levels and programmable de-
bounced delays. They can be enabled independently of
each other and can be enabled to give over-current indi-
cation on the ALRT1 pin. See Figure 56.
nODSCTh Register (18Eh)
Register Type: Special
Nonvolatile Restore: ODSCTh (0F2h) if nNVCfg1.enOD-
SC is set
Alternate Initial Value: 0x0000
The OD comparator threshold can be programmed from
0mV to -155mV with 5mV resolution (0 to -15.5A with
0.5A resolution using 10mΩ sense resistor), and has a
programmable delay from 0 to 14.6ms with 0.97ms reso-
lution. The SC comparator threshold can be programmed
from 0mV to -310mV with 10mV resolution (0 to -31A with
1A resolution using 10mΩ sense resistor), and has a pro-
grammable delay from 0 to 915µs with a 61µs resolution.
Either comparator can be configured for zero delay (2μs
typical propagation) that results in a nonlatching behavior
on the ALRT1 pin.
The nODSCTh register sets the current thresholds for
each alert. Bits D4 through D0 set the ODTH (over-
discharge threshold), and D12 to D8 set the SCTH (short-
circuit threshold). The format of the registers is shown in
Figure 57.
SCTH: Short-Circuit Threshold Setting. Sets the short cir-
cuit threshold to a value between 0mV and -155mV with a
step size of -5mV. The SCTH bits are stored as a 2’s-com-
plement value with 0x1F = 0mV and 0x00 = -155mV.
ODTH: Over-discharge Threshold Setting. Sets the over-
discharge threshold to a value between 0mV and -77.5mV
with a step size of -2.5mV. The ODTH bits are stored as
a 2’s-complement value with 0x1F = 0mV and 0x00 =
-77.5mV.
The ODSCTh register sets the threshold levels where
each comparator will trip. The ODSCCfg register enables
each comparator and sets their debounce delays. The
ODSCCfg register also maintains indicator flags of which
+
SCDLY
ODDLY
SCi
-
SCTH
ODTH
ODSCCFG
ODi
+
-
-
CSN
CSP
R
SENSE
Figure 56. Overcurrent Comparator Diagram
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
SCTH
X
X
X
ODTH
X: Don’t care.
Figure 57. ODSCTh Register (0F2h) and nODSCTh Register (18Eh) Formats
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nODSCCfg Register (18Fh)
Alert Function
Register Type: Special
The Alert Threshold registers allow interrupts to be gener-
ated by detecting a high or low voltage, current, tempera-
ture, or state of charge. Interrupts are generated on the
ALRT1 pin open-drain output driver. An external pullup is
required to generate a logic-high signal. Note that if the
pin is configured to be logic-low when inactive, the exter-
nal pullup increases current drain. The ALRTp bit in the
Config register sets the polarity of the ALRT1 pin output.
Alerts can be triggered by any of the following conditions:
Nonvolatile Restore: ODSCCfg (0F3h) if nNVCfg1.enOD-
SC is set.
Alternate Initial Value: 0x0000
The nODSCCfg register configures enabling of the Over
Discharge and Short Circuit alerts, as well as setting their
latching and delay behavior. The alert indicators are also
displayed and cleared in this register. The format of the
register is shown in Figure 58.
• Battery removal—(V
> V
- V
) and battery
AIN1
THRM
DET
SCDLY: Sets the latching and delay for the Short Circuit
detection from 2μs up to 917μs. If this field set to 0, the
alert will happen typically 2μs after the threshold is tripped
with no latching. Any non zero setting causes the indicator
to latch after a delay of 2μs + 61μs x SCDLY.
removal detection enabled (Ber = 1).
• Battery insertion—(V < V
- V ) and
DET-HYS
AIN1
THRM
battery insertion detection enabled (Bei = 1).
• Over/undervoltage—VAlrtTr register threshold violation
(upper or lower) and alerts enabled (Aen = 1).
SCen: Short Circuit Alert Enable. Set to 1 to enable alerts
when the SCTh value is exceeded.
• Over/undertemperature—TAlrtTr register threshold vio-
lation (upper or lower) and alerts enabled (Aen = 1).
SCi: Short Circuit Indicator. This bit is set to 1 to indicate
the short-circuit threshold was detected. Write to zero to
clear this bit if SCDLY is not 0. If SCDLY is 0, the alert
clears automatically when the alert condition is removed.
• Over/undercurrent—IAlrtTr register threshold violation
(upper or lower) and alerts enabled (Aen = 1).
• Over/under SOC—SAlrtTr register threshold violation
(upper or lower) and alerts enabled (Aen = 1).
ODDLY: Sets the latching and delay for the Over
Discharge detection from 2μs up to 14.657ms. If this field
is set to 0, the alert will happen typically 2μs after the
threshold is tripped with no latching. Any non zero setting
causes the indicator to latch after a delay of 2μs + 977μs
x ODDLY.
To prevent false interrupts, the threshold registers should
be initialized before setting the Aen bit. Alerts generated
by battery insertion or removal can only be reset by clear-
ing the corresponding bit in the Status (000h) register.
Alerts generated by a threshold-level violation can be
configured to be cleared only by software, or cleared
automatically when the threshold level is no longer violat-
ed. See the Config (01Dh) register description for details
of the alert function configuration.
ODen: Over Discharge Alert Enable. Set to 1 to enable
alerts when the ODTh value is exceeded.
ODi: Over Discharge Indicator. This bit is set to 1 to indicate
the over-discharge threshold was detected. Write to zero
to clear this bit if ODDLY is not 0. If ODDLY is 0, the alert
clears automatically when the alert condition is removed.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCi
SCen
X
X
SCDLY
ODi
ODen
X
X
ODDLY
X: Don’t care.
Figure 58. ODSCCfg Register (0F3h) and nODSCCfg Register (18Fh) Formats
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thresholds default to their maximum settings unless they
are configured to be restored from nonvolatile memory
instead by setting the nNVCfg1.enAT bit.
nVAlrtTh Register (1C0h)
Register Type: Special
Nonvolatile Restore: VAlrtTh (001h) if nNVCfg1.enAT is set.
Alternate Initial Value: 0xFF00 (disabled)
TMAX: Maximum temperature threshold. An alert is gen-
erated if the Temp register reading exceeds this value.
This field is signed 2's complement format with 1°C LSb
resolution.
The nVAlrtTh register shown in Figure 59 sets upper
and lower limits that generate an ALRT1 pin interrupt if
exceeded by the VCell register value. The upper 8 bits
set the maximum value and the lower 8 bits set the mini-
mum value. Interrupt threshold limits are selectable with
20mV resolution over the full operating range of the VCell
register. At power-up, the thresholds default to their maxi-
mum settings unless they are configured to be restored
from nonvolatile memory instead by setting the nNVCfg1.
enAT bit.
TMIN: Minimum temperature threshold. An alert is gener-
ated if the Temp register reading falls below this value.
This field is signed 2's complement format with 1°C LSb
resolution.
nSAlrtTh Register (1C2h)
Register Type: Special
Nonvolatile Restore: SAlrtTh (003h) if nNVCfg1.enAT is set.
Alternate Initial Value: 0xFF00 (disabled)
VMAX: Maximum voltage threshold. An alert is generated
if the VCell register reading exceeds this value. This field
has 20mV LSb resolution.
The nSAlrtTh register shown in Figure 61 sets upper
and lower limits that generate an ALRT1 pin interrupt if
exceeded by the selected RepSOC, AvSOC, MixSOC, or
VFSOC register values. See the MiscCFG.SACFG setting
for details.The upper 8 bits set the maximum value and
the lower 8 bits set the minimum value. Interrupt threshold
limits are selectable with 1% resolution over the full oper-
ating range of the selected SOC register. At power-up, the
thresholds default to their maximum settings unless they
are configured to be restored from nonvolatile memory
instead by setting the nNVCfg1.enAT bit.
VMIN: Minimum voltage threshold. An alert is generated if
the VCell register reading falls below this value. This field
has 20mV LSb resolution.
nTAlrtTh Register (1C1h)
Register Type: Special
Nonvolatile Restore: TAlrtTh (002h) if nNVCfg1.enAT is
set
Alternate Initial Value: 0x7F80 (Disabled)
The nTAlrtTh register shown in Figure 60 sets upper
and lower limits that generate an ALRT1 pin interrupt
if exceeded by the Temp register value. The upper 8
bits set the maximum value and the lower 8 bits set the
minimum value. Interrupt threshold limits are stored in
2’s-complement format with 1ºC resolution over the full
operating range of the Temp register. At power-up, the
SMAX: Maximum state of charge threshold. An alert is
generated if the selected SOC register reading exceeds
this value. This field has 1% LSb resolution.
SMIN: Minimum state of charge threshold. An alert is gen-
erated if the selected SOC register reading falls below this
value. This field has 1% LSb resolution.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VMAX
VMIN
Figure 59. VAlrtTh (001h)/nVAlrtTh (1C0h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TMAX
TMIN
Figure 60. TAlrtTh (002h)/nTAlrtTh (1C1h) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SMAX
SMIN
Figure 61. SAlrtTh (003h)/nSAlrtTh (1C2h) Format
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field is signed 2's complement with 400μV LSb resolution
nIAlrtTh Register (1C3h)
to match the upper byte of the Current register.
Register Type: Special
Nonvolatile Restore: IAlrtTh (0B4h) if nNVCfg1.enAT is set.
Alternate Initial Value: 0x7F80 (Disabled)
Memory
The memory space of the MAX1720x/1x is divided into 32
pages each containing 16 registers where each register
is 16 bits wide. Registers are addressed using an inter-
nal 9bit range of 000h to 1FFh. Externally registers are
accessed with an 8-bit address for 2-wire communication
(MAX1720x) or 16-bit address for 1-wire communica-
tion (MAX1721x). Registers are grouped by functional
block. See the functional descriptions for details of each
register's functionality. Certain memory blocks can be
permanently locked to prevent accidental overwrite. See
the Locking Memory Blocks section for details. Table 16
shows the full memory map of the ICs. Note that some
individual user registers are located on RESERVED mem-
ory pages in Table 17. These locations can be accessed
normally while the remainder of the page is considered
RESERVED. Memory locations listed as RESERVED
should never be written to. Data read from RESERVED
locations is not defined.
The nIAlrtTh register shown in Figure 62 sets upper
and lower limits that generate an ALRT1 pin interrupt
if exceeded by the Current register value. The upper 8
bits set the maximum value and the lower 8 bits set the
minimum vaue. Interrupt threshold limits are selectable
with 400μV resolution over the full operating range of the
Current register. At power-up, the thresholds default to
their maximum settings unless they are configured to be
restored from nonvolatile memory instead by setting the
nNVCfg1.enAT bit.
IMAX: Maximum current threshold. An alert is generated
if the current register reading exceeds this value. This
field is signed 2's complement with 400μV LSb resolution
to match the upper byte of the Current register.
IMIN: Maximum current threshold. An alert is generated
if the current register reading falls below this value. This
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IMAX
IMIN
Figure 62. IAlrtTh (0B4h)/nIAlrtTh (1C3h) Format
Table 16. Top-Level Memory Map
REGISTER
MAX1720X
MAX1721X
2-WIRE EXTERNAL 1-WIRE EXTERNAL
LOCK
DESCRIPTION
2-WIRE SLAVE
ADDRESS
2-WIRE
PAGE
PROTOCOL ADDRESS RANGE ADDRESS RANGE
00h
2
ModelGauge m5 DATA BLOCK
RESERVED
6Ch
I C
—
00h–4Fh
0000h–004Fh
01h–04h
05h–0Ah
LOCK2
—
—
—
ModelGauge m5 DATA BLOCK
(continued)
2
0Bh
0Ch
0Dh
LOCK2
SHA
6Ch
6Ch
6Ch
I C
B0h–BFh
C0h–CFh
D0h–DFh
00B0h–00BFh
00C0h–00CFh
00D0h–00DFh
2
SHA MEMORY
I C
ModelGauge m5 DATA BLOCK
(continued)
2
LOCK2
I C
0Eh–0Fh
10h–17h
18h–19h
RESERVED
—
—
—
—
—
SBS DATA BLOCK
16h
SBS
00h–7Fh
LOCK3
1Ah–1Bh LOCK1
2
NONVOLATILE MEMORY
16h
I C
80h–DFh
0180h-01DFh
1Ch
1Dh
1Eh
1Fh
LOCK4
LOCK5
2
NONVOLATILE HISTORY
RESERVED
16h
—
I C
E0h–EFh
—
01E0h-01EFh
—
—
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Table 17. Individual Registers
MAX1720X
MAX1721X
2-WIRE
EXTERNAL
ADDRESS
RANGE
1-WIRE EXTER-
NAL ADDRESS
RANGE
REGISTER PAGE
DESCRIPTION
2-WIRE SLAVE
ADDRESS
2-WIRE
PROTOCOL
2
060H
061h
07Fh
0F2h
0F3h
COMMAND REGISTER
CommStat REGISTER
Lock REGISTER
6CH
6Ch
6Ch
6Ch
6Ch
I C
60H
61h
7Fh
F2h
F3h
0060H
0061h
007Fh
00F2h
00F3h
2
I C
2
I C
2
ODSCTh REGISTER
ODSCCfg REGISTER
I C
2
I C
MODELGAUGE m5
REGISTER VFOCV
2
0FBh
0FFh
6Ch
6Ch
I C
FBh
FFh
00FBh
00FFh
MODELGAUGE m5
REGISTER VFSOC
2
I C
Table 18. ModelGauge m5 Register Memory Map
WORD
0h
00xh
Status
01xh
FullCap
02xh
TTF
03xh
04xh
0Bxh
0Dxh
Status2
1h
VAlrtTh
TAlrtTh
SAlrtTh
AtRate
RepCap
RepSOC
Age
TTE
DevName
QRTable10
FullCapNom
AvgCell4
AvgCell3
AvgCell2
AvgCell1
Cell4
2h
QRTable00
FullSocThr
RCellRCell
RFast
QRTable20
QRTable30
3h
4h
IAlrtTh
5h
FullCapRep
IAvgEmpty
dQAcc
dPAcc
6h
AvgTA
Cell3
7h
Cycles
AIN0
LearnCfg
FilterCfg
RelaxCfg
MiscCfg
TGain
Cell2
8h
Temp
DesignCap
AvgVCell
MaxMinTemp
MaxMinVolt
MaxMinCurr
Config
RComp0
TempCo
VEmpty
VShdnCfg
AgeForecast
HibCfg
Cell1
9h
VCell
CellX
Ah
Bh
Ch
Dh
Eh
Fh
Current
AvgCurrent
QResidual
MixSOC
AvSOC
MixCap
VFRemCap
QH
Batt
Config2
VRipple
AtQResidual
AtTTE
TOff
FStat
Timer
PackCfg
TimerH
IChgTerm
AvCap
CGain
AtAvSOC
AtAvCap
COff
ShdnTimer
m5 Algorithm section for details of specific register
operation. These locations (other than page 00h) can be
permanently locked by setting LOCK2. Unnamed register
locations are reserved locations and should not be written
to. See Table 18.
ModelGauge m5 Memory Space
Registers that relate to functionality of the ModelGauge
m5 fuel gauge are located on pages 00h-04h and are
continued on pages 0Bh and 0Dh. See the ModelGauge
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page 1Ah as the fuel gauge algorithm learns is limited
to 202 writes. Do not exceed these write limits. Table 19
shows the nonvolatile memory register map.
Nonvolatile Memory
Certain ModelGauge m5 and device configuration values
are stored in nonvolatile memory to prevent data loss if
the ICs lose power. The MAX1720x/MAX1721x internally
update page 1Ah values over time based on actual perfor-
mance of the ModelGauge m5 algorithm. The host system
doesnotneedtoaccessthismemoryspaceduringoperation.
Nonvolatile data from other accessible register locations
is internally mirrored into the nonvolatile memory block
automatically. Note that nonvolatile memory has a limited
number of writes. User accessible configuration memory
is limited to 7 writes. Internal and external updates to
Shadow RAM
Nonvolatile memory is never written to or read from direct-
ly by the communication interface. Instead, data is written
to or read from shadow RAM memory located at the same
address. Copy and recall commands are used to transfer
data between the nonvolatile memory and the shadow
RAM. Figure 63 describes this relationship. Nonvolatile
memory recall occurs automatically at IC power up and
software POR.
Table 19. Nonvolatile Register Memory Map
WORD
18xh
19xh
1Axh*
nQRTable00
nQRTable10
nQRTable20
nQRTable30
nCycles
1Bxh
nConfig
1Cxh
nVAlrtTh
nTAlrtTh
nSAlrtTh
nIAlrtTh
1Dxh
0h
nXTable0
nXTable1
nXTable2
nXTable3
nXTable4
nXTable5
nXTable6
nXTable7
nXTable8
nXTable9
nXTable10
nXTable11
nUser18C
nUser18D
nODSCTh
nODSCCfg
nOCVTable0
nOCVTable1
nOCVTable2
nOCVTable3
nOCVTable4
nOCVTable5
nOCVTable6
nOCVTable7
nOCVTable8
nOCVTable9
nOCVTable10
nOCVTable11
nIChgTerm
nFilterCfg
nUser1D0
1h
nRippleCfg
nMiscCfg
nDesignCap
nHibCfg
nUser1D1
2h
nAgeFcCfg
3h
nDesignVoltage
nUser1D4
4h
nUser1C4
nUser1C5
nFullSOCThr
nTTFCfg
nCGain
5h
nFullCapNom
nRComp0
nPackCfg
nRelaxCfg
nConvgCfg
nNVCfg0
nNVCfg1
nNVCfg2
nSBSCfg
nRFastVShdn
nManfctrDate
nFirstUsed
6h
7h
nTempCo
8h
nIAvgEmpty
nFullCapRep
nVoltTemp
nMaxMinCurr
nMaxMinVolt
nMaxMinTemp
nSOC
nSerialNumber0
nSerialNumber1
nSerialNumber2
nDeviceName0
9h
nTCurve
nTGain
Ah
Bh
Ch
Dh
Eh
Fh
nTOff
**
nROMID0
nManfctrName0 nDeviceName1
nManfctrName1 nDeviceName2
nManfctrName2 nDeviceName3
**
nROMID1
**
nVEmpty
nROMID2
nLearnCfg
nTimerH
nROMID3**
nRSense
nDeviceName4
*Locations 1A0h to 1AFh are updated automatically by the ICs each time it learns.
**The ROM ID is unique to each IC and cannot be changed by the user.
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SHADOW RAM
0180h
NONVOLATILE MEMORY
0180h
DATA WRITE
COPY NV BLOCK
NV RECALL
DATA READ
01DFh
01DFh
Figure 63. Shadow RAM and Nonvolatile Memory Relationship
Table 20. History Recall Command Functions
COMMAND
FUNCTION
Recall indicator flags to determine remaining SHA-256 secret
0xE2FE
0xE2FA
updates or clears
Recall indicator flags to determine remaining configuration
memory writes
Recall indicator flags to determine remaining battery life logging
0xE2FB, 0xE2FC
updates
Recall indicator flags to determine battery life logging update
0xE2FB–0xE2FE
0xE226–0xE2F0
errors
Recall battery life logging information
Nonvolatile Memory Commands
NV RECALL [E001h]
The following commands are used to copy or recall data
from the nonvolatile memory. All commands are written to
the Command register at memory address 060h to per-
form the desired operation. The CommStat register can
be used to track the status of the request.
This command recalls the entire block from nonvolatile
memory to shadow RAM addresses 180h to 1DFh. This
is an low power operation that will take up to t
to
RECALL
complete. Note that the supply voltage must be above
for the operation to complete successfully.
V
NVM
COPY NV BLOCK [E904h]
HISTORY RECALL [E2XXh]
This command copies the entire block from shadow RAM
to nonvolatile memory addresses 180h to 1DFh excluding
the unique ID locations of 1BCh to 1BFh. After issuing this
This command copies history data into page 1Eh of
memory. After issuing this command, the host must wait
t
for the operation to complete before reading
RECALL
command, the host must wait t
to complete. The configuration memory can be copied a
maximum of 7 times. Note that the supply voltage must be
for the operation
page 1Eh. Table 20 shows what history information can
be recalled. See the SHA-256 Authentication, Battery
Life Logging, and Memory sections for details on how to
decode this information.
BLOCK
above V
for the operation to complete successfully.
NVM
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Nonvolatile Block Programming
Determining the Number of Remaining Updates
The host must program all nonvolatile memory locations
at the same time by using the Copy NV Block command.
The host first writes all desired nonvolatile memory
shadow RAM locations to their desired values, then sends
The configuration memory can only be updated 7 times
by the user (First update occurs during manufacturing
test). The number of remaining updates can be calculated
using the following procedure:
the Copy NV Block command, and then waits t
for
BLOCK
1. Write 0xE2FA to the Command register (060h).
the copy to complete. The CommStat.NVError bit should
be read to determine if the copy command executed suc-
cessfully. Afterwards the host should send the power on
reset sequence to reset the IC and have the new nonvola-
tile settings take effect. Note that configuration memory is
2. Wait t
.
RECALL
3. Read memory address 1EDh.
4. Decode address 1EDh data as shown in Table 21.
Each block write has redundant indicator flags for reliabil-
ity. Logically OR the upper and lower bytes together then
count the number of 1s determine how many updates
have already been used. The first update occurs in manu-
facturing test prior to shipping to the user.
limited to n
total write attempts. The recommended
BLOCK
full sequence is:
1. Write desired memory locations to new values.
2. Clear CommStat.NVError bit.
General-Purpose Memory
3. Write 0xE904 to the Command register 0x060 to initiate
a block copy.
There are 7 nonvolatile memory words labelled nUser
that are dedicated to general purpose user data storage.
Most other nonvolatile memory locations could also be
used as general purpose storage if their normal func-
tion is disabled. The nNVCfg0, nNVCfg1, and nNVCfg2
registers control which nonvolatile memory functions are
enabled and disabled. Table 22 shows which nNVCfg bits
control different IC functions and the effects when the bit
is set or cleared. See the nNVCfg register descriptions for
complete details. Do not convert a nonvolatile register to
general purpose memory space if that register's function
is used by the application.
4. Wait t
for the copy to complete.
BLOCK
5. Check the CommStat.NVError bit. If set, repeat the
process. If clear, continue.
6. Write 0x000F to the Command register 0x060 to POR
the IC.
7. Wait t
for the IC to reset.
POR
8. Write 0x0001 to Counter Register 0x0BB to reset firmware.
9. Wait t for the firmware to restart.
POR
Table 21. Number of Remaining Config Memory Updates
LOGICAL OR OF UPPER
NUMBER OF UPDATES
REMAINING
ADDRESS 1EDh DATA
NUMBER OF UPDATES USED
AND LOWER BYTES
00000001b
00000011b
00000111b
00001111b
000000010000000xb
0000001x000000xxb
000001xx00000xxxb
00001xxx0000xxxxb
0001xxxx000xxxxxb
001xxxxx00xxxxxxb
01xxxxxx0xxxxxxxb
1xxxxxxxxxxxxxxxb
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
00011111b
00111111b
01111111b
11111111b
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Table 22. Nonvolatile Memory Configuration Options
REGISTER
NAME
FACTORY
DEFAULT
FUNCTION WHEN
CONTROL BIT IS SET
FUNCTION WHEN CONTROL
BIT(S) CLEARED
ADDRESS
CONTROL BIT(S)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
nXTable0
nXTable1
nXTable2
nXTable3
nXTable4
nXTable5
nXTable6
nXTable7
nXTable8
nXTable9
nXTableA
nXTableB
nUser18C
nUser18D
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
IC Uses Default Cell Model,
180h–18Bh Become
Free User Memory
180h–18Bh Hold Custom
Cell Model Information
nNVCfg0.enX
N/A
Always Free User Memory
18Eh
18Fh
nODSCTh
nODSCCfg
0x0000
0x0000
Overcurrent Comparators
Default Disabled, 18Eh-18Fh
Become Free User Memory
nNVCfg1
enODSC
nODSCCfg→ODSCCfg
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
nOCVTable0
nOCVTable1
nOCVTable2
nOCVTable3
nOCVTable4
nOCVTable5
nOCVTable6
nOCVTable7
nOCVTable8
nOCVTable9
nOCVTableA
nOCVTableB
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
IC Uses Default Cell Model,
190h–19Bh Become
Free User Memory
190h–19Bh Hold Custom
Cell Model Information
nNVCfg0.enOCV
IChgTerm = FullCapRep/3,
19Ch Becomes Free User
Memory
19Ch
nIChgTerm
0x0000
nNVCfg0.enICT
nIChgTerm→IChgTerm
FilterCfg = 0x0EA4, 19Dh
Becomes Free User Memory
19Dh
19Eh
19Fh
nFilterCfg
nVEmpty
nLearnCfg
0x0000
0x0000
0x2602
nNVCfg0.enFCfg
nNVCfg0.enVE
nNVCfg0.enLCfg
nFilterCfg→FilterCfg
nVEmpty→VEmpty
nLearnCfg→LearnCfg
VEmpty = 0xA561, 19Eh
Becomes Free User Memory
LearnCfg=0x2603, 19Fh
Becomes Free User Memory
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Table 22. Nonvolatile Memory Configuration Options (continued)
REGISTER
NAME
FACTORY
DEFAULT
FUNCTION WHEN
CONTROL BIT IS SET
FUNCTION WHEN CONTROL
BIT(S) CLEARED
ADDRESS
CONTROL BIT(S)
1A0h
1A1h
1A2h
1A3h
1A4h
1A5h
1A6h
1A7h
nQRTable00
nQRTable10
nQRTable20
nQRTable30
nCycles
0x3C00
0x1B80
0x0B04
0x0885
0x0000
0x0BB8
0x1070
0x263D
nQRTable30→QRTable30
N/A
Always nCycles→Cycles
Always nFullCapNom→FullCapNom
Always nRComp0→RComp0
Always nTempCo→TempCo
nFullCapNom
nRComp0
nTempCo
IAvgEmpty = -1 x nFullCap-
1A8h
1A9h
nIAvgEmpty
nFullCapRep
0x0000
0x0BB8
nNVCfg2.enIAvg
nNVCfg2.enFC
nIAvgEmpty→IAvgEmpty
nFullCapRep→FullCapRep
Nom, 1A8h Becomes Free
User Memory
nFullCapNom→FullCapRep,
1A9h Becomes Free User
Memory
AvgVCell→nVoltTemp and
AvgTA→nVoltTemp at each
backup event
Voltage and Temperature
Logging disabled, 1AAh
Becomes Free User Memory
(nNVCfg0.enAF = 0)
(nNVCfg2.enVT = 0)
1AAh
nVoltTemp
0x0000
Age Forecasting disabled,
1AAh Becomes
nVoltTemp stores Age Forecasting
learned information
Free User Memory
MaxMinCurr→nMaxMinCurr at each
1ABh Becomes
Free User Memory
1ABh
1ACh
1ADh
nMaxMinCurr
nMaxMinVolt
nMaxMinTemp
0x807F
0x00FF
0x807F
nNVCfg2.enMMC
nNVCfg2.enMMV
nNVCfg2.enMMT
backup event
MaxMinVolt→nMaxMinVolt at each
1ACh Becomes
Free User Memory
backup event
MaxMinTemp→nMaxMinTemp at each
1ADh Becomes
Free User Memory
backup event
nNVCfg2.enSOC
(nNVCfg0.enAF=0)
1AEh Becomes
Free User Memory
SOC→nSOC at each backup event
1AEh
1AFh
nSOC
0x0000
0x0000
Age Forecasting disabled,
1AEh Becomes
nSOC stores Age Forecasting backup
information
(nNVCfg2.enSOC = 0)
nNVCfg2.enT
Free User Memory
TimerH→nTimerH at each backup
1AFh Becomes Free User
Memory
nTimerH
event
Config = 0x2214, Config2 =
0x0050, 1B0h Becomes
Free User Memory
1B0h
1B1h
1B2h
nConfig
nRippleCfg
nMiscCfg
0x0000
0x0204
0x0000
nNVCfg0.enCfg
N/A
nConfig→Config2
Always nRippleCfg→RippleCfg
MiscCfg = 0x3870,
1B2h Becomes
nNVCfg0.enMC
nMiscCfg→MiscCfg
Free User Memory
FullCapRep→DesignCap,
1B3h Becomes
1B3h
nDesignCap
0x0000
nNVCfg0.enDC
nDesignCap→DesignCap
Free User Memory
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Table 22. Nonvolatile Memory Configuration Options (continued)
REGISTER
NAME
FACTORY
DEFAULT
FUNCTION WHEN
CONTROL BIT IS SET
FUNCTION WHEN CONTROL
BIT(S) CLEARED
ADDRESS
CONTROL BIT(S)
HibCfg = 0x890B, 1B4h
Becomes Free User Memory
1B4h
nHibCfg
0x0000
nNVCfg0.enHCfg
nHibCfg→HibCfg
0x0C01 for
MAX172x1
0x0A02 for
MAX172x5
1B5h
nPackCfg
N/A
Always nPackCfg→PackCfg
RelaxCfg=0x2039, 1B6h
Becomes Free User Memory
1B6h
1B7h
nRelaxCfg
nConvgCfg
0x0000
nNVCfg0.enRCfg
nNVCfg1.enCTE
nRelaxCfg→RelaxCfg
Converge-to-Empty Disabled,
1B7h Becomes
0x2241
Converge-to-Empty Enabled
Free User Memory
1B8h
1B9h
1BAh
nNVCfg0
nNVCfg1
nNVCfg2
0x0100
0x0006
0xFF0A
N/A
Always the Nonvolatile Memory Control Registers
SBS Functions Disabled, 1BBh
Becomes Free User Memory
1BBh
nSBSCfg
0x0002
nNVCfg0.enSBS
SBS Functions Enabled
1BCh
1BDh
1BEh
1BFh
nROMID0
nROMID1
nROMID2
nROMID3
Varies
Varies
Varies
Varies
N/A
Always the Unique 64-bit ID
VAlrtTh = 0xFF00, 1C0h
Becomes Free User Memory
1C0h
1C1h
1C2h
1C3h
nVAlrtTh
nTAlrtTh
nSAlrtTh
nIAlrtTh
0x0000
0x0000
0x0000
0x0000
nVAlrtTh→VAlrtTh
nTAlrtTh→TAlrtTh
nSAlrtTh→SAlrtTh
nIAlrtTh→IAlrtTh
TAlrtTh = 0x7F80, 1C1h
Becomes Free User Memory
nNVCfg1.enAT
SAlrtTh = 0xFF00, 1C2h
Becomes Free User Memory
IAlrtTh = 0x7F80, 1C3h
Becomes Free User Memory
1C4h
1C5h
nUser1C4
nUser1C5
0x0000
0x0000
N/A
Always Free User Memory
FullSOCThr = 0x5005, 1C6h
Becomes Free User Memory
1C6h
nFullSOCThr
0x0000
nNVCfg1.enFTh
nFullSOCThr→FullSOCThr
Time-to-Full Default
Configuration, 1C7h
Becomes Free User Memory
nTTFCfg configures time to full calcu-
1C7h
nTTFCfg
0x0000
nNVCfg1.enTTF
nNVCfg1.enCG
lation
CGain = 0x0400, COff =
0x0000, 1C8h Becomes Free
User Memory
nCGain.nCGain→CGainnCGain.
nCOff→COff
1C8h
1C9h
nCGain
0x0000
0x0025
CGTempCo = 0x20C8, 1C9h
Becomes Free User Memory
(nNVCfg1.enCrv = 0)
(nNVCfg2.enMet = 0)
nTCurve→CGTempCo
nTCurve
Thermistor Curvature Controlled by
nTCurve
1C9h Becomes Free User
Memory
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Table 22. Nonvolatile Memory Configuration Options (continued)
REGISTER
NAME
FACTORY
DEFAULT
FUNCTION WHEN
CONTROL BIT IS SET
FUNCTION WHEN CONTROL
BIT(S) CLEARED
ADDRESS
CONTROL BIT(S)
TGain = 0xEE56, 1CAh
Becomes Free User Memory
1CAh
nTGain
nTOff
0x0000
0x0000
nTGain→TGain
nTOff→TOff
nNVCfg1.enTGO
TOff = 0x1DA4, 1CBh
Becomes Free User Memory
1CBh
1CCh nManfctrName0 0x0000
1CDh nManfctrName1 0x0000
1CEh nManfctrName2 0x0000
1CCh-1CEFh Become Free
User Memory
nNVCfg0.enSBS
nManfctrName[2:0]→sManfctrName
1CFh
1D0h
1D1h
nRSense
nUser1D0
nUser1D1
0x03E8
0x0000
0x0000
N/A
N/A
Always Sense Resistor value
Always Free User Memory
1D2h Becomes Free User
1D2h
nAgeFcCfg
0xD5E3
nNVCfg0.enAF
Configures Age Forecast Feature
Memory
1D3h Becomes Free User
Memory
1D3h
1D4h
nDesignVoltage 0x0000
nNVCfg0.enSBS
N/A
nDesignVoltage→sDesignVolt
nUser1D4
0x0000
0x0000
Always Free User Memory
nRFastVShdn.
Rfast→RFastnRFastVshdn.
VShdn→VShdnCfg
VShdnCfg = 0x007D, RFast =
0x0500, 1D5h Becomes Free
User Memory
1D5h
nRFastVShdn
nNVCfg1.enRFVSH
1D6h Becomes Free User
Memory
1D6h
1D7h
nManfctrDate
nFirstUsed
0x0000
0x0000
nManfctrDate→sManfctrDate
nFirstUsed→sFirstUsed
1D7h Becomes Free User
Memory
1D8h nSerialNumber0 0x0000
1D9h nSerialNumber1 0x0000
1DAh nSerialNumber2 0x0000
1D8h-1DAFh Become Free
User Memory
nSerialNumber[2:0]→sSerialNumber
nDeviceName[4:0]→sDeviceName
nNVCfg0.enSBS
1DBh
1DCh
1DDh
1DEh
1DFh
nDeviceName0 0x0000
nDeviceName1 0x0000
nDeviceName2 0x0000
nDeviceName3 0x0000
nDeviceName4 0x0000
1DBh-1DFh Become Free
User Memory
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Stand-Alone ModelGauge m5 Fuel Gauge
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Memory Locks
Locking Memory Blocks
ModelGauge m5 RAM Registers and all nonvolatile
memory locations can be permanently locked to prevent
accidental data loss in the application. Locking a memory
block only prevents future writes to the locations. Reading
locked locations is still allowed. Note that locking a
memory location is permanent so carefully choose
all desired locks before sending the NV LOCK com-
mand. The SHA secret is stored in separate secure
non-readable memory. There is a different command for
locking the SHA secret and its state is not displayed in the
Lock register. See the SHA-256 Authentication section
for details. Once a lock bit is set, it can never be cleared.
Figure 64 shows which lock bits correspond to which
memory blocks of the IC.
Prior to sending the lock command the CommStat.
NVError bit should be cleared and after the command is
sent the CommStat.NVError bit should be read to deter-
mine if the lock command executed successfully. Note
that locking memory blocks is a permanent operation. The
recommended full sequence is:
5) 1) Clear CommStat.NVError bit.
6) 2) Write 0x6AXX to the Command register 0x060 to
lock desired blocks.
7) 3) Wait t
for the copy to complete.
UPDATE
8) 4) Check the CommStat.NVError bit. If set, repeat
the process.
Reading Lock State
NV LOCK [6AXXh]
The Lock register at address 07Fh reports the state of
each lock. See Figure 65 for the format of the Lock regis-
ter. If a LOCK bit is set the corresponding memory block
is locked. If the LOCK bit is cleared the corresponding
memory block is unlocked. Note that the SHA-256 Secret
lock state cannot be read through this register.
This command permanently locks a block or blocks of
memory. To set a lock, send 6AXXh to the Command
register where the lower 5 bits of the command determine
which locks will be set. Figure 64 shows a detailed format
of the NV LOCK command. Set each individual LOCK bit
to 1 to LOCK the corresponding register block. Set the
LOCK bit to 0 to do nothing at this time. For example writ-
ing 6A02h to the Command register sets LOCK2. Writing
6A1Fh sets all five locks. Writing 6A00h sets no locks.
X: Don't Care
1: LOCK is set
0: LOCK is clear
LOCK1: Locks register pages 1Ah, 1Bh
LOCK2: Locks register pages 01h, 02h, 03h, 04h, 0Bh, 0Dh
LOCK3: Locks register pages 18h, 19h
LOCK4: Locks register pages 1Ch
Smart Battery Compliant Operation
The MAX17201/MAX17205 is compliant to the Smart
Battery Specification v1.1 when nNVCfg0.enSBS =1.
Enabling SBS operation does not interfere with normal
operation of the IC. SBS formatted registers are accessed
at slave address 16h, memory addresses 100h to 17Fh
using SBS protocols. SBS functionality can be configured
using the nSBSCfg and nDesignVoltage registers.
LOCK5: Locks register pages 1Dh
D15
D14
D13
D12
D11
D10
D9
D8 D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
0
0
0
0
LOCK5 LOCK4 LOCK3 LOCK2 LOCK1
Figure 64. Format of LOCK Command
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
LOCK5 LOCK4 LOCK3 LOCK2 LOCK1
Figure 65. Format of Lock Register (07Fh)
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Stand-Alone ModelGauge m5 Fuel Gauge
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SBS Compliant Memory Space (MAX1720x Only)
sCell1 (13Fh)/sCell2 (13Eh)/sCell3 (13Dh)/sCell4
(13Ch) Registers
The MAX1720x contains an SBS v1.1 Compliant memory
space on pages 10h to 17h that can be accessed using the
Read Word, Write Word, and Read Block commands at
2-Wire slave address 16h. Table 23 lists the SBS compli-
ant registers. See the SBS 1.1 Specification for details of
registers at addresses 100h to 12Fh. Registers with colored
boxes in the table are shared between SBS and normal IC
functions and are always readable regardless of IC settings.
Their format is described in the Analog Measurements sec-
tion of the data sheet. All other registers on pages 13h to
17h are described in this section. Unnamed register loca-
tions are reserved and should not be written to.
These registers contain the same cell voltage information
displayed in Cell1 (0D8h) to Cell4 (0D5h) respectively
with SBS compliant formatting. In the sCell registers 1
LSb = 1mV giving a full scale range of 0.0V to 65.535V.
sAvgCell1 (14Fh)/sAvgCell2 (14Eh)/sAvgCell3
(14Dh)/sAvgCell4 (14Ch) Registers
These registers contain the same average cell voltage
information displayed in AvgCell1 (0D4h) to AvgCell4
(0D1h) respectively with SBS compliant formatting. In the
sCell registers 1 LSb = 1mV giving a full scale range of
0.0V to 65.535V.
sFirstUsed Register (136h)
This register contains a mirror of the value stored in non-
volatile memory address 1D7h.
Table 23. SBS Register Space Memory Map
WORD
10xh
11xh
12xh
13xh
14xh
15xh
16xh
17xh
sManfct
Access
sManfc-
trName*
0h
sFullCap
—
—
—
—
sManfctInfo**
sRemCa-
pAlarm
sDevice-
Name*
1h
2h
3h
4h
5h
6h
sRunTTE
sAvgTTE
sAvgTTF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
sRemTime-
Alarm
sDev
Chemistry*
sManfct-
Data**
sBatteryMode
sAtRate
—
—
sCharging-
Current
—
—
—
Temp1
IntTemp
sFirstUsed
sCharging-
Voltage
sBattery
Status
sAtTTE
7h
8h
sAtRateOK
sCycles
—
—
AvgTemp1
—
—
—
—
sAvCap
—
—
sTemperature sDesignCap
AvgIntTemp
sMixCap
sPack
9h
Ah
Bh
sDesignVolt
Voltage
—
—
—
AvgTemp2
—
—
—
—
—
—
—
—
—
—
—
—
—
sCurrent
sSpecInfo
sAvg
Current
sManfct-
Date
Temp2
sSerial-
Number**
Ch
sMaxError
—
sCell4
sAvgCell4
—
—
—
Dh
Eh
Fh
sRelSOC
sAbsSOC
sRemCap
—
—
—
—
—
—
sCell3
sCell2
sCell1
sAvgCell3
sAvgCell2
sAvgCell1
—
—
—
CGTempCo
—
—
—
—
—
*Location is read as ASCII data using the read block command.
**Location is read as hexadecimal data using the read block command.
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Stand-Alone ModelGauge m5 Fuel Gauge
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sAvCap Register (167h)
nSBSCfg Register (1BBh)
This register contains the same information as the AvCap
(01Fh) register. It is formatted for SBS compliance where
1 LSb = 1.0mAH giving a full-scale range of 0.0mAh to
65535mAh.
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register.
The nSBSCfg register manages settings for SBS mode
operation of the IC. If nNVCfg0.enSBS = 0 and SBS mode
is not used, this register can be used as general-purpose
data storage. Figure 66 shows the register format.
sMixCap Register (168h)
This register contains the same information as the
MixCap (00Fh) register. It is formatted for SBS compli-
ance where 1 LSb = 1.0mAH giving a full-scale range of
0.0mAh to 65535mAh.
MECfg: Configures sMaxError register output when oper-
ating in SBS mode.
sManfctInfo Register (170h)
00: Always report 0% error
01: Always report 1% error
10: Report actual experienced errror
11: Always report 3% error
The sManfctInfo register is accessed using the SBS pro-
tocol read block command. This register is intended to
provide custom information, and is outside the SBS 1.1
definition. This register function is not supported in the
MAX17201/MAX17205.
CapMd: Selects sBatteryMode.CapMd bit default setting
when operating in SBS mode. CapMd will reset to 0 every
time a pack removal occurs as detected by floating com-
munication lines.
Nonvolatile SBS Register Back-Up
When SBS mode operation is enabled by setting nNVCfg0.
enSBS = 1, data from several nonvolatile memory loca-
tions is translated into SBS memory space. Table 24 lists
these translations. Note that when performing an SBS
Read Block command, the IC automatically generates
the size data byte by counting the number of sequential
non-zero data bytes stored in the corresponding non-
volatile memory locations. The nonvolatile memory only
needs to store the actual data to be read by an SBS Read
Block command. If SBS mode of operation is disabled,
these locations become available for general purpose
nonvolatile data storage.
nDesignVoltage Register (1D3h)
Register Type: Special
Nonvolatile Restore: There is no associated restore loca-
tion for this register
The nDesignVoltage register holds a value representing
the expected average cell voltage of the design. This
value is used for SBS mWh calculations. The nDesign-
Voltage register has an LSb of 1mV giving a full-scale
range of 0mV to 65.535V.
Table 24. SBS to Nonvolatile Memory Mapping
NONVOLATILE MEMORY
ADDRESS
NONVOLATILE MEMORY
REGISTER NAME
SBS MEMORY ADDRESS
SBS REGISTER NAME
1D6h
nManfctrDate
nFirstUsed
1Bh
sManfctrDate
sFirstUsed
1D7h
36h
1CCh-1CEh
1D8h-1DAh
1DBh-1DFh
nManfctrName[2:0]
nSerialNumber[2:0]
nDeviceName[4:0]
(Read Block Command)
(Read Block Command)
(Read Block Command)
sManfctrName
sSerialNumber
sDeviceName
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CapMd
X
X
X
X
X
X
X
X
X
X
X
X
MECfg
X
X: Don’t care. This bit is undefined and can be logic 0 or 1.
Figure 66. nSBSCfg (1BBh) Format
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Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Note that the results of the authentication attempt are
determined by host verification. Operation of the ICs is not
affected by authentication success or failure.
nCGain and Sense Resistor Relationship
To meet SBS compliance, current and capacity registers
in the SBS memory space must have a an LSb bit weight
of 1.0mA or 1.0mAh. The current gain must be adjusted
based on the application sense resistor value to set the
proper bit weight. Table 25 shows the proper nCGain value
to use for the most common-sense resistor values. This is
the default register value only. It does not include any off-
set trim or custom gain adjustment. Note that changing the
nCGain register affects the gain reported by the standard
ModelGauge current and capacity registers.
Authentication Procedure
Figure 67 shows how a host system verifies the authen-
ticity of a connected battery. The host first generates a
random 160 bit challenge value and writes the challenge
to IC memory space 0C0h-0C9h. The host then sends
the Compute MAC with ROM ID (3500h) or Compute
MAC without ROM ID (3600h) to the Command register
060h and wait t
for computation to complete. Finally,
SHA
the host reads the MAC from memory space 0C0h-0CFh
to verify the result. This procedure requires the secret to
be maintained on the host side as well as in the battery.
The host must perform the same calculations in parallel to
verify the battery is authentic.
SHA-256 Authentication
Authentication is performed using a FIPS 180-4 compli-
ant SHA-256 one-way hash algorithm on a 512-bit mes-
sage block. The message block consists of a 160-bit
secret, a 160-bit challenge and 192 bits of constant data.
Optionally, the 64-bit ROM ID replaces 64 of the 192 bits
of constant data used in the hash operation. Contact
Maxim for details of the message block organization.
RANDOM CHALLENGE GENERATION
The host and the IC both calculate the result based on
the mutually known secret. The result of the hash opera-
tion is known as the message authentication code (MAC)
or message digest. The MAC is returned by the IC for
comparison to the host’s MAC. Note that the secret is
never transmitted on the bus and thus cannot be captured
by observing bus traffic. Each authentication attempt is
initiated by the host system by writing a 160-bit random
challenge into the SHA memory address space 0C0h to
0C9h. The host then issues the compute MAC or compute
MAC with ROM ID command. The MAC is computed per
FIPS 180-4, and stored in address space 0C0h to 0CFh
overwriting the challenge value.
SECRET
SECRET
PARALLEL COMPUTATION
MAC COMPUTATION
BATTERY
VERIFICATION
MACS DO NOT
MATCH
REJECT BATTERY
MACS MATCH
ACCEPT BATTERY
Table 25. nCGain Register Settings to
Meet SBS Compliance
HOST
SENSE
RESISTOR
VALUE
NCGAIN
REGISTER
VALUE
CORRESPONDING
CGAIN REGISTER
VALUE
Figure 67. Procedure to Verify a Battery
0.0025 Ω
0.005 Ω
0.010 Ω
0x4000
0x2000
0x1000
0x0400
0x0200
0x0100
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Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
The authentication process for this method is less com-
plex. The host simply writes the challenge to the IC mem-
ory space 0C0h-0C9h. The host then sends the Compute
MAC without ROM ID (3600h) to the Command register
060h. Note that Compute MAC with ROM ID Command
is not valid for this authentication method. The host then
Alternate Authentication Procedure
Figure 68 shows an alternative method of battery authen-
tication which does not require the host to know the
secret. In this method, each host device knows a chal-
lenge and MAC pair that match the secret stored in an
authentic battery, but each host device uses a different
pair. This eliminates the need for special hardware on the
host side to protect the secret from hardware intrusion. A
battery could be cloned for a single host device, but creat-
ing a clone battery that works with any host would not be
possible without knowing the secret.
waits t
for computation to complete and reads the
SHA
MAC from memory space 0C0h-0CFh to verify the result.
CHALLENGE 1
MAC 1
SECRET
MAC COMPUTATION
VERIFICATION
BATTERY
PASS
FAIL
HOST 1
CHALLENGE 2
MAC 2
SECRET
MAC COMPUTATION
VERIFICATION
BATTERY
PASS
FAIL
HOST 2
CHALLENGE N
MAC N
SECRET
MAC COMPUTATION
VERIFICATION
BATTERY
PASS
FAIL
HOST N
Figure 68. Battery Authentication Without a Host-Side Secret
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Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
program the ICs. Since the secret cannot be read from the
ICs, a parallel computation must be performed externally
in order the calculate the stored secret. Figure 69 shows
an example single step secret generation operation. Note
that new units have their secret value already cleared to
all 0s.
Secret Management
The secret value must be programmed to a known value
prior to performing authentication in the application. The
secret cannot be written directly. Instead, the user must
generate a new internal secret by performing a SHA com-
putation with the old internal secret and a seed value sent
as a challenge. To prevent any one entity from knowing
the complete secret value, the process can be repeated
multiple times by sending additional challenge seeds and
performing additional computations.
1. Clear the CommStat.NVError bit.
2. Write a challenge seed value to the SHA memory
space 0C0h–0C9h.
3. Write Compute Next Secret with ROM ID 3300h or
Compute Next Secret without ROM ID 3000h to the
Command register 060h.
Note that secret memory can only be changed a maximum
of n
times including erase operations and nonvola-
SECRET
tile memory updates are not guaranteed. See the n
SECRET
4. Wait t
+ t
for computation to complete
SHA
UPDATE
write limit in the Electrical Characteristics table. Any secret
update operation that fails does not change the secret value
stored in the ICs, but consumes one of the available limited
updates. Be careful not to use up all secret memory dur-
ing the generation process. Maxim strongly recommends
permanently locking the secret after it has been generated.
and new secret to be stored.
5. If CommStat.NVError is set, return to step 1.
Otherwise continue.
6. Verify the secret has been generated correctly with
a test challenge at this time. If verification fails return
to step 1. Also, see the Determining the Number of
Remaining Updates section to verify enough non-
volatile memory writes remain in order to repeat the
process.
Single Step Secret Generation
The single step secret generation procedure should be
used in production environments where the challenge
seed value can be kept confidential, for example when
there are no OEM manufacturing steps or situations
where an outside individual or organization would need to
know the challenge seed. Use the following sequence to
7. Write Lock Secret 6000h to the Command register
060h. Note this operation cannot be reversed.
8. Wait t
for secret to lock permanently.
UPDATE
SEED
STARTING SECRET
CLEARED TO ALL 0S
COMPUTE NEXT
PARALLEL COMPUTATION
FINAL SECRET
BATTERY
FINAL SECRET
Figure 69. Single Step Secret Generation Example
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Stand-Alone ModelGauge m5 Fuel Gauge
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SEED 1 GENERATION
STARTING SECRET
CLEARED TO ALL 0S
SEED 1
COMPUTE NEXT
COMPUTE NEXT
COMPUTE NEXT
CHALLENGE 1 AND MAC 1
FOR VERIFICATION
MIDDLE SECRET 1
COMPUTATION
MIDDLE SECRET 1
OEM 1
BATTERY
SEED 2 GENERATION
SEED 2
MIDDLE SECRET 1
CHALLENGE 2 AND MAC 2
FOR VERIFICATION
MIDDLE SECRET 2
COMPUTATION
MIDDLE SECRET 2
OEM 2
BATTERY
SEED 3 GENERATION
SEED 3
MIDDLE SECRET 2
CHALLENGE 3 AND MAC 3
FOR VERIFICATION
FINAL SECRET
FINAL SECRET
OEM 3
BATTERY
Figure 70. Multistep Secret Generation Example
Multistep Secret Generation Procedure
All OEMs
1. Clear the CommStat.NVError bit.
The multistep secret generation procedure should be
used in environments where an outside individual or
organization would need to know the challenge seed such
as OEM manufacturing. The multistep procedure is more
complicated, but allows a secret to be stored inside the ICs
without providing any information to an OEM manufacturer
that could jeopardize secret integrity. Figure 70 shows an
example where three OEM manufacturers are each pro-
vided with a seed value for a Compute Next operation.
The final secret value stored inside the ICs are known
only to the top-level manager who knows all seed values
and has performed the computation separately. Use the
following procedures when generating a multistep secret.
Note that the secret can only be updated or cleared
2. Write challenge seed value to the SHA memory
space 0C0h–0C9h.
3. Write Compute Next Secret with ROM ID 3300h or
Compute Next Secret without ROM ID 3000h to the
Command register 060h.
4. Wait t
+ t
for computation to complete
SHA
UPDATE
and new secret to be stored.
5. If CommStat.NVError is set, return to step 1.
Otherwise, continue.
6. Verify the secret has been generated correctly with
a test challenge at this time. If verification fails return
to step 1. Also see the Determining the Number of
Remaining Updates section to verify enough nonvolatile
memory writes remain in order to repeat the process.
n
times total. New units have their secret value
SECRET
already cleared to all 0s.
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Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Last OEM:
Compute MAC Without ROM ID [3600h]
The challenge value must be written to the SHA memory
space prior to performing a compute MAC. This command
initiates a SHA-256 computation without including the
ROM ID in the message block. Instead, the ROM ID por-
tion of the message block is replaced with a value of all
1s. Since the ROM ID is not used, this command allows
the use of a master secret and MAC response indepen-
1. Follow the procedure in the All OEMs section for the
final secret update.
2. Write Lock Secret 6000h to the Command register
060h. Note this operation cannot be reversed.
3. Wait t
for secret to lock permanently.
UPDATE
Top Level:
dent of the ROM ID. The ICs compute the MAC in t
SHA
1. Generate all seed values to provide to OEMs.
after receiving the last bit of this command. After the MAC
computation is complete, the host can read the MAC from
the SHA memory space.
2. Perform SHA calculations separately to determine
what the final secret is after all manufacturing steps.
3. Keep final secret value secure.
Compute MAC with ROM ID [3500h]
Determining the Number of Remaining Updates
The challenge value must be written to the SHA memory
space prior to performing a compute MAC. This command
is structured the same as the compute MAC without ROM
ID, except that the ROM ID is included in the message
block. With the unique ROM ID included in the MAC com-
putation, the MAC is unique to each unit. After the MAC
computation is complete, the host can read the MAC from
the SHA memory space.
The internal secret can only be updated or cleared n
SE-
times total. The number of remaining updates can
CRET
be calculated using the following procedure:
1. Write 0xE2FE to the Command register (060h).
2. Wait t
.
RECALL
3. Read memory address 1E6h.
4. Decode address 1E6h data as shown in Table 26. Each
secret update has redundant indicator flags for reliability.
Logically OR the upper and lower bytes together then
count the number of 1s to determine how many updates
have already been used. The first update occurs in manu-
facturing test to clear the secret memory prior to shipping
to the user.
Compute Next Secret Without ROM ID [3000h]
This command initiates a SHA-256 computation and uses
the resulting MAC as the next or new secret. The hash
operation is performed with the current 160-bit secret and
the new 160-bit challenge. Logical 1s are loaded in place
of the ROM ID. The last 160 bits of the MAC are used as
the new secret value. The host must allow t
after issu-
SHA
ing this command for the SHA calculation to complete,
then wait t for the new secret value to be stored
in nonvolatile memory. During this operation, the SHA
memory space is not updated. Note that the old secret
value must be known prior to executing this command in
order to calculate what the new secret value is.
Authentication Commands
UPDATE
All SHA authentication commands are written to memory
address 060h to perform the desired operation. Writing
the challenge or reading the MAC is handled by access-
ing the SHA memory space on page 0Ch through direct
write and read operations.
Table 26. Number of Remaining Secret Updates
LOGICAL OR OF UPPER AND
NUMBER OF UPDATES
ADDRESS 1E6H DATA
NUMBER OF UPDATES USED
LOWER BYTES
00000001b
00000011b
00000111b
00001111b
00011111b
00111111b
REMAINING
000000010000000xb
0000001x000000xxb
000001xx00000xxxb
00001xxx0000xxxxb
0001xxxx000xxxxxb
001xxxxx00xxxxxxb
1
2
3
4
5
6
5
4
3
2
1
0
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Full Reset
Compute Next SECRET WITH ROM ID [3300h]
This command initiates a SHA-256 computation and uses
the resulting MAC as the next or new secret. The hash
operation is performed with the current 160-bit secret, the
64-bit ROM ID, and the new 160-bit challenge. The last
160 bits of the output MAC are used as the new secret
1. Reset IC hardware by writing 000Fh to the Command
register at 060h.
2. Wait t
for reset to take affect.
POR
3. Reset IC fuel gauge operation by writing 0001h to the
Config2 register at 0BBh.
value. The host must allow t
after issuing this com-
SHA
mand for the SHA calculation to complete, then wait t
4. Wait t
for the fuel gauge to reset.
UP-
POR
for the new secret value to be stored in nonvolatile
DATE
Fuel Gauge Reset
memory. During this operation, the SHA memory space
is not updated. Note that the old secret value must be
known prior to executing this command in order to calcu-
late what the new secret value is.
1. Reset IC fuel gauge operation by writing 0001h to the
Config2 register at 0BBh.
2. Wait t
for the fuel gauge to reset.
POR
Reset Commands
CLEAR SECRET [5A00h]
There are two commands that can be used to reset either
the entire IC or just operation of the fuel gauge. Note
that the reset fuel gauge command is written to Config2
instead of to the Command register.
This command sets the 160-bit secret to all 0s. The host
must wait t
for the IC to write the new secret value
UPDATE
to nonvolatile memory. This command uses up one of the
secret write cycles.
Hardware Reset [000Fh to Address 060h]
LOCK SECRET [6000h]
Send the hardware reset command to the Command
register to recall all nonvolatile memory into shadow RAM
and reset all hardware based operations of the IC. This
command should always be followed by the reset fuel
gauge command to fully reset operation of the IC.
This command write protects the secret to prevent acci-
dental or malicious overwrite of the secret value. The
secret value stored in nonvolatile memory becomes per-
manent. The host must wait t
tion to complete.
for the lock opera-
UPDATE
SHA-256 Lock state is not shown in the Lock register.
Lock state can be verified by reading nonvolatile memory
history using the following sequence:
Fuel Gauge Reset [0001h to Address 0BBh]
The fuel gauge reset command resets operation of the
ICs without restoring nonvolatile memory values into
shadow RAM. This command allows different configura-
tions to be tested without using one of the limited number
of nonvolatile memory writes.
1. Send 0xE2FA to the Command register (060h)
2. Wait for t
.
RECALL
3. Read memory address 1ECh
Communication
If address 1ECh is 0x0000 then the secret is not locked.
If address 1ECh is anything other than 0x0000 then the
secret is permanently locked.
This section covers communication protocols and summa-
rizes all special commands used by the ICs. The MAX17201/
MAX17205 communicates over a 2-wire interface using
Device Reset
2
either I C or SBS protocols depending on memory address
There are two levels of reset for the IC. A full reset
restores the ICs to their power-up state the same as if
power had been cycled. A fuel gauge reset resets only
the fuel gauge operation without resetting IC hardware.
This is useful for testing different configurations without
writing nonvolatile memory. Use the following sequences
to reset the ICs.
selected by the host. The MAX17211/MAX17215 communi-
cates using the Maxim 1-Wire interface.
2-Wire Bus System (MAX17201/MAX17205 Only)
The MAX17201/MAX17205 uses a 2-Wire bus system to
2
communicate by both standard I C protocol or by SBS
smart battery protocol. The slave address used by the
host to access the ICs determines which protocol is used
and what memory locations are available to read or write.
The following description applies to both protocols. See
2
the I C and SBS Bus System descriptions for specific
protocol details.
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in SDA when SCL is high is interpreted as a START or
STOP control signal.
Hardware Configuration
The 2-wire bus system supports operation as a slave-only
device in a single or multi-slave, and single or multi-master
system. Up to 128 slave devices may share the bus using
7-bit slave addresses. The 2-wire interface consists of a
serial data line (SDA) and serial clock line (SCL). SDA and
SCL provide bidirectional communication between the ICs
and a master device at speeds up to 400kHz. The ICs’
SDA pin operates bi-directionally. When the ICs receive
data SDA operates as an input. When the IC returns data
SDA operates as an open-drain output with the host sys-
tem providing a resistive pull-up. See Figure 71. The IC
always operates as a slave device, receiving and trans-
mitting data under the control of a master device. The
master initiates all transactions on the bus and generates
the SCL signal, as well as the START and STOP bits that
begin and end each transaction.
Bus Idle
The bus is defined to be idle, or not busy, when no master
device has control. Both SDA and SCL remain high when
the bus is idle. The STOP condition is the proper method
to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition
by forcing a high-to-low transition on SDA while SCL is
high. The master terminates a transaction with a STOP
condition by a low-to-high transition on SDA while SCL
is high. A Repeated START condition can be used in
place of a STOP then START sequence to terminate one
transaction and begin another without returning the bus to
the idle state. In multimaster systems, a repeated START
allows the master to retain control of the bus. The START
and STOP conditions are the only bus activities in which
the SDA transitions when SCL is high.
I/O Signaling
The following individual signals are used to build byte
level 2-Wire communication sequences.
Acknowledge Bits
Bit Transfer
Each byte of a data transfer is acknowledged with an
acknowledge bit (ACK) or a no acknowledge bit (NACK).
Both the master and the IC slave generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
One data bit is transferred during each SCL clock cycle,
with the cycle defined by SCL transitioning low to high and
then high to low. The SDA logic level must remain stable
during the high period of the SCL clock pulse. Any change
V
PULLUP
R
PULLUP
BUS MASTER
DEVICE 2-WIRE PORT
DQ/SDA
Rx DATA
Tx DATA
Rx DATA
Tx DATA
WEAK
PULLDOWN
Rx = RECEIVE
Tx = TRANSMIT
OD/SCL
Tx CLOCK
Rx CLOCK
WEAK
PULLDOWN
Figure 71. 2-Wire Bus Interface Circuitry
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acknowledge-related clock pulse (ninth pulse) and keep it
low until SCL returns low. To generate a no acknowledge,
the receiver releases SDA before the rising edge of the
acknowledge-related clock pulse and leaves SDA high until
SCL returns low. Monitoring the acknowledge bits allows
for detection of unsuccessful data transfers. An unsuccess-
ful data transfer can occur if a receiving device is busy or
if a system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication. If a transaction is aborted mid-byte, the
master should send additional clock pulses to force the
slave IC to free the bus prior to restarting communication.
and the read/write (R/W) bit. When the bus is idle, the ICs
continuously monitor for a START condition followed by
its slave address. When the ICs receive a slave address
that matches its slave address, they respond with an
acknowledge bit during the clock period following the R/W
bit. The MAX1720x supports the slave addresses shown
in Table 27.
Read/Write Bit
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being
written by the master to the slave. R/W = 1 selects a read
transaction, with the following bytes being read from the
slave by the master.
Data Order
With 2-wire communication, a byte of data consists of
8 bits ordered most significant bit (MSb) first. The least
significant bit (LSb) of each byte is followed by the
Acknowledge bit. IC registers composed of multibyte val-
ues are ordered least significant byte (LSB) first.
Bus Timing
The IC is compatible with any bus timing up to 400kHz.
See the Electrical Characteristics table for timing details.
No special configuration is required to operate at any
speed. Figure 72 shows an example of standard 2-wire
bus timing.
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave address
Table 27. 2-Wire Slave Addresses
INTERNAL MEMORY RANGE
ADDRESS BYTE RANGE
SLAVE ADDRESS
PROTOCOL
ACCESSED
2
6Ch
I C
00h–FFh
00h–7Fh
80h–FFh
000h–0FFh
100h–17Fh
180h–1FFh
SMBUS
16h
2
I C
SDA
t
F
t
F
t
t
t
BUF
SP
R
t
SU;DAT
t
HD;STA
t
t
R
LOW
SCL
t
HD;STA
t
t
SU;STO
SU;STA
t
HD;DAT
S
Sr
P
S
Figure 72. 2-Wire Bus Timing Diagram
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2
not reserved addresses. Do not write to reserved address
locations. See Figure 73 for an example write data com-
munication sequence.
I C Protocols
The following 2-wire communication protocols must be
used by the bus master to access MAX17201/MAX17205
memory locations 000h to 1FFh. Addresses 000h to
0FFh and from 180h to 1FFh can be read continuously.
Addresses 100h to 17Fh must be read one word at a time.
2
I C Read Data Protocol
The read data protocol is used to transmit data from IC
memory locations 000h to 1FFh . Addresses 000h to 0FFh
and 180h to 1FFh can be read as a block. Addresses
100h to 17Fh must be read as individual words. The mem-
ory address is sent by the bus master as a single byte
value immediately after the slave address. Immediately
following the memory address, the bus master issues
a REPEATED START followed by the slave address.
The MAX17201/MAX17205 acknowlege the address and
begin transmitting data. A word of data is read as two
separate bytes that the master must ACK. Because the
address is automatically incremented after the least sig-
nificant bit (LSb) of each word received by the IC, the
MSB of the data at the next memory address can be read
immediately after the acknowledgment of the LSB of data
at the previous address. The master indicates the end
of a read transaction by sending a NACK followed by a
STOP. If the bus master continues an autoincremented read
transaction beyond memory address 0FFh or 1FFh, the IC
transmits all 1s until a NACK or STOP is received. Data from
reserved address locations is undefined. See Figure 74 for
an example read data communication sequence.
2
These protocols follow the standard I C specification for
communication.
2
I C Write Data Protocol
The write data protocol is used to transmit data to the
ICs at memory addresses from 000h to 1FFh. Addresses
000h to 0FFh and 180h and 1FFh can be written as a
block. Addesses 100h to 17Fh must be written one word
at a time. The memory address is sent by the bus master
as a single byte value immediately after the slave address.
The MSB of the data to be stored is written immediately
after the memory address byte is acknowledged. Because
the address is automatically incremented after the least
significant bit (LSb) of each word received by the IC, the
MSB of the data at the next memory address can be writ-
ten immediately after the acknowledgment of the LSB of
data at the previous address. The master indicates the
end of a write transaction by sending a STOP or Repeated
START after receiving the last acknowledge bit. If the bus
master continues an autoincremented write transaction
beyond address 0FFh or 1FFh, the ICs ignore the data.
Data is also ignored on writes to read-only addresses but
WRITE DATA COMMUNICATION PROTOCOL
DATA0
LSB
DATA0
MSB
DATA1
LSB
DATA N
MSB
SLAVE ADDRESS
MEMORY ADDRESS
EXAMPLE WORD WRITE TO I2C COMMAND REGISTER ADDRESS 060h
6Ch
60h
COMMAND
LSB
COMMAND
MSB
(SLAVE ADDRESS)
(MEMORY ADDRESS)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
2
Figure 73. Example I C Write Data Communication Sequence
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I2C READ DATA COMMUNICATION PROTOCOL
DATA0
LSB
DATA0
MSB
DATA1
LSB
DATA N
MSB
SLAVE ADDRESS
MEMORY ADDRESS
SLAVE ADDRESS
EXAMPLE READ DATA OF CURRENT AND AVGCURRENT REGISTERS ADDRESSES 00AH–00BH
6Ch
0Ah
6Dh
CURRENT
LSB
CURRENT
MSB
AVGCURRENT
LSB
AVGCURRENT
MSB
(SLAVE WRITE ADDRESS)
(MEMORY ADDRESS)
(SLAVE READ ADDRESS)
EXAMPLE READ DATA OF INTTEMP REGISTERS ADDRESS 135h
16h
35h
17h
INTTEMP
LSB
INTTEMP
MSB
(SLAVE WRITE ADDRESS)
(MEMORY ADDRESS)
(SLAVE READ ADDRESS)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
2
Figure 74. Example I C Read Data Communication Sequence
SBS WRITE WORD COMMUNICATION PROTOCOL
DATA
LSB
DATA
MSB
PEC
(OPTIONAL)
SLAVE ADDRESS
MEMORY ADDRESS
EXAMPLE WORD WRITE TO SBS ATRATE REGISTER ADDRESS 104h
16h
04h
DATA
LSB
DATA
MSB
PEC
(OPTIONAL)
(SLAVE ADDRESS)
(MEMORY ADDRESS)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
Figure 75. Example SBS Write Word Communication Sequence
immediately after the memory address byte is acknowl-
edged, followed by the MSB. A PEC byte can follow the
data word, but the data word is written without checking
the validity of the PEC. The master indicates the end
of a write transaction by sending a STOP or Repeated
START after receiving the last acknowledge bit. Data is
ignored on writes to read-only addresses but not reserved
addresses. Do not write to reserved address locations.
The write word protocol should not be used to write to
addresses supported by the write block protocol, use
write block at these locations instead. See Figure 75 for
an example Write Word communication sequence.
SBS Protocols
The following 2-wire communication protocols must be
used by the bus master to access MAX17201/MAX17205
memory locations 100h to 17Fh. These protocols follow
the smart battery specification for communication.
SBS Write Word Protocol
The Write Word protocol is used to transmit data to the IC
memory addresses between 100h and 17Fh that do not
require the write block protocol. The memory address is
sent by the bus master as a single-byte LSB value imme-
diately after the slave address, the MSb of the address
is omitted. The LSB of the data to be stored is written
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SBS Read Word Protocol
SBS Write Block Protocol
The Read Word protocol is used to read data from the
IC at memory addresses between 100h and 17Fh. The
memory address is sent by the bus master as a single
byte LSB value immediately after the slave address,
the MSb of the address is ignored. The LSB of the data
is read immediately after the memory address byte is
acknowledged, followed by the MSB. A PEC byte fol-
lows the data word. The master indicates the end of a
write transaction by sending a STOP or repeated START
after not acknowledging the last received byte. Data from
reserved address locations is undefined. The read word
protocol should not be used to read from addresses sup-
ported by the read block protocol, use read block at these
locations instead. See Figure 76 for an example read
word communication sequence.
The SBS Write Block protocol is not supported by the
MAX17201/MAX17205. Use the write data command
sequence to the corresponding nonvolatile memory locations
to update write/read block register locations. See Table 24.
SBS Read Block Protocol
The Read Block protocol is similar to the read word pro-
tocol except the master reads multiple words of data at
once. A data size byte is transmitted by the ICs immedi-
ately after the memory address byte and before the first
byte of data to be read. The read block protocol is only
supported at the register locations shown in Table 28.
PEC error checking is provided by the read block proto-
col if nNVCfg0.enSBS = 1. Figure 77 shows an example
Read Block communication sequence.
SBS READ WORD COMMUNICATION PROTOCOL
DATA
LSB
DATA
MSB
PEC
(OPTIONAL)
SLAVE ADDRESS
MEMORY ADDRESS
SLAVE ADDRESS
EXAMPLE WORD READ OF SBS STEMPERATURE REGISTER ADDRESS 108h
16h
08h
17h
STEMPERATURE
LSB
STEMPERATURE
MSB
PEC
(OPTIONAL)
(SLAVE WRITE ADDRESS)
(MEMORY ADDRESS)
(SLAVE READ ADDRESS)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
Figure 76. Example SBS Read Word Communication Sequence
Table 28. Valid SBS Read Block Registers
SIZE BYTE
MAX VALUE
ADDRESS
REGISTER
FORMAT
0120h
0121h
0122h
0123h
011Ch
0170h
sManfctName
sDeviceName
sDevChemistry
sManfctData
sSerialNumber
sManfctInfo
0Ah
0Ch
05h
1Ah
08h
18h
ASCII String
ASCII String
ASCII String
Hexadecimal
Hexadecimal
Hexadecimal
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SBS READ BLOCK COMMUNICATION PROTOCOL
PEC
(OPTIONAL)
SLAVE ADDRESS
MEMORY ADDRESS
SLAVE ADDRESS
SIZE
DATA0
DATA (size-2)
EXAMPLE BLOCK READ OF SBS DEVCHEMISTRY REGISTER ADDRESS 122h
16h
22h
17h
05h
(Size)
PEC
(OPTIONAL)
DATA0
DATA3
(SLAVE WRITE ADDRESS)
(MEMORY ADDRESS)
(SLAVE READ ADDRESS)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
Figure 77. Example SBS Read Block Communication Sequence
INPUT
XOR
MSb
XOR
XOR
LSb
Figure 78. PEC CRC Generation Block Diagram
Packet Error Checking
1-Wire Bus System (MAX17211/MAX17215 Only)
SBS read functions support packet error checking (PEC)
if nNVCfg0.enSBS is enabled. The host system is respon-
sible for verifying the CRC value it receives and taking
action as a result. SBS write functions accept a PEC byte
but complete the write function regardless of the value of
the PEC.
The MAX17211/MAX17215 communicate to a host
through a Maxim 1-Wire interface. The 1-Wire bus is a
system that has a single bus master and one or more
slaves. A multidrop bus is a 1-Wire bus with multiple
slaves, while a single-drop bus has only one slave device.
In all instances, these ICs are slave devices. The bus
master is typically a microprocessor in the host system.
The discussion of this bus system consists of five topics:
64-bit net address, CRC generation, hardware configura-
tion, transaction sequence, and 1-Wire signaling.
The CRC can be generated by the host using a circuit
consisting of a shift register and XOR gates as shown
in Figure 78, or it can be generated in software using
8
2
1
the polynomial X + X + X + 1. See the Smart Battery
Compliant Operation section for more information.
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Connect OD/SCL to the REG3 pin to enable communica-
tion at overdrive speed.
Hardware Configuration
Because the 1-Wire bus has only a single line, it is impor-
tant that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must connect to the bus with open-drain
or three-state output drivers. The MAX17211/MAX17215
use an open-drain output driver as part of the bidirectional
interface circuitry shown in Figure 79. If a bidirectional pin
is not available on the bus master, separate output and
input pins can be connected together. Communication
speed is controlled by the OD/SCL pin. Connect OD/SCL
to PACK- to enable communication at standard speed.
The 1-Wire bus must have a pull-up resistor on the host
side of the bus. A value of between 2kΩ and 5kΩ is rec-
ommended for most applications. The idle state for the
1-Wire bus is logic high. If, for any reason, a bus transac-
tion must be suspended, the bus must be left in the idle
state to properly resume the transaction later. Note that if
the bus is left low for more than t
, slave devices on
LOW0
the bus begin to interpret the low period as a reset pulse,
effectively terminating the transaction.
V
PULLUP
BUS MASTER
DEVICE 1-WIRE PORT
R
PULLUP
DQ/SDA
Rx
Tx
Rx
Tx
OD/SCL
WEAK
PULLDOWN
Rx = RECEIVE
Tx = TRANSMIT
STANDARD TIMING
V
PULLUP
Bus Master
DEVICE 1-WIRE PORT
R
PULLUP
DQ/SDA
Rx
Tx
Rx
Tx
OD/SCL
REG3
WEAK
PULLDOWN
0.47µF
Rx = RECEIVE
Tx = TRANSMIT
OVERDRIVE TIMING
Figure 79. 1-Wire Bus Interface Circuitry
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MAX17211/MAX17215 are as follows: the initialization
sequence (reset pulse followed by presence pulse), write
0, write 1, and read data. The bus master initiates all sig-
naling except for the presence pulse.
64-Bit Net Address (ROM ID)
The 1-Wire net address is 64 bits in length. The term net
address is synonymous with the ROM ID or ROM code
terms used in other 1-Wire documentation. The value of
the net address is stored in nonvolatile memory and can-
not be changed. In a 1-wire standard net address, the first
eight bits of the net address are the 1-Wire family code.
This value is the same for all ICs of the same type. The
next 48 bits are a unique serial number. The last eight bits
are a cyclic redundancy check (CRC) of the first 56 bits.
Table 29 details the net address data format. The 64-bit
net address and the 1-Wire I/O circuitry built into the
device enable the MAX17211/MAX17215 to communicate
through the 1-Wire protocol detailed in this data sheet.
Reset Time Slot
The initialization sequence required to begin any com-
munication with the MAX17211/MAX17215 is shown in
Figure 80. The bus master transmits (Tx) a reset pulse for
t . The bus master then releases the line and goes
RSTL
into receive mode (Rx). The 1-Wire bus line is then pulled
high by the pullup resistor. After detecting the rising edge
on the DQ pin, the MAX17211/MAX17215 waits for t
PDH
and then transmits the presence pulse for t . A presence
PDL
pulse following a reset pulse indicates that the MAX17211/
MAX17215 is ready to accept a net address command.
I/O Signaling
The 1-Wire bus requires strict signaling protocols to
ensure data integrity. The four protocols used by the
Write Time Slots
Table 29. 1-Wire Net Address Format
MSB: 8-BIT
LSB: 8-BIT FAMILY
CODE (26H)
48-BIT SERIAL NUMBER
CRC
t
t
RSTH
RSTL
V
t
PDH
PULLUP
t
PDL
GND
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
SLAVE IC ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND SLAVE IC
ACTIVE LOW
Figure 80. 1-Wire Initialization Sequence
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A write-time slot is initiated when the bus master pulls the
1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and
is low when sampled, a write 0 occurs. The sample win-
dow is illustrated in Figure 81. For the bus master to gen-
erate a write-1 time slot, the bus line must be pulled low
and then released, allowing the line to be pulled high less
write 0. All write-time slots must be t
in duration with
SLOT
a 1μs minimum recovery time, t , between cycles.
REC
than t
after the start of the write time slot. For the host
RDV
The MAX17211/MAX17215 samples the 1-Wire bus line
between t and t after the line falls. If
to generate a write 0 time slot, the bus line must be pulled
low and held low for the duration of the write-time slot.
LOW1_MAX
LOW0_MIN
the line is high when sampled, a write 1 occurs. If the line
WRITE 0 SLOT
WRITE 1 SLOT
t
t
SLOT
SLOT
t
LOW1
t
LOW0
V
t
REC
PULLUP
GND
> 1µs
DEVICE SAMPLE WINDOW
TYP
DEVICE SAMPLE WINDOW
TYP MAX
MIN
MAX
MIN
MODE
STANDARD
OVERDRIVE
15µs
2µs
15µs
30µs
3µs
15µs
2µs
15µs
30µs
3µs
1µs
1µs
READ DATA SLOT
DATA = 0
DATA = 1
t
t
SLOT
SLOT
t
REC
V
t
t
RDV
PULLUP
RDV
GND
> 1µs
MASTER SAMPLE WINDOW
MASTER SAMPLE WINDOW
MODE
15µs
2µs
15µs
2µs
STANDARD
OVERDRIVE
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
SLAVE IC ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND SLAVE IC
ACTIVE LOW
Figure 81. 1-Wire Write and Read Time Slots
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Read Time Slots
Match Net Address [55h]
A read-time slot is initiated when the bus master pulls
the 1-Wire bus line from a logic-high level to a logic-low
level. The bus master must keep the bus line low for at
least 1μs and then release it to allow the MAX17211/15 to
present valid data. The bus master can then sample the
This command allows the bus master to specifically
address one MAX17211/MAX17215 on the 1-Wire bus.
Only the addressed MAX17211/MAX17215 respond to
any subsequent function command. All other slave devices
ignore the function command and wait for a reset pulse.
This command can be used with one or more slave
devices on the bus.
data t
from the start of the read-time slot. By the end
RDV
of the read-time slot, the MAX17211/15 releases the bus
line and allows it to be pulled high by the external pullup
Skip Net Address [CCh]
resistor. All read-time slots must be t
in duration with
SLOT
This command saves time when there is only one
MAX17211/15 on the bus by allowing the bus master to
issue a function command without specifying the address
of the slave. If more than one slave device is present on
the bus, a subsequent function command can cause a data
collision when all slaves transmit data at the same time.
a 1μs minimum recovery time, t
, between cycles. See
REC
Figure 81 and the timing specifications in the Electrical
Characteristics table for more information.
Transaction Sequence
The protocol for accessing the MAX17211/MAX17215
through the 1-Wire port is as follows:
Search Net Address [F0h]
● Initialization
This command allows the bus master to use a process
of elimination to identify the 1-Wire net addresses of all
slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read
the complement of the bit, then write the desired value of
that bit. The bus master performs this simple three-step
routine on each bit location of the net address. After one
complete pass through all 64 bits, the bus master knows
the address of one device. The remaining devices can
then be identified on additional iterations of the process.
● Net address command
● Function command(s)
● Data transfer (not all commands have data transfer)
Net Address Commands
Once the bus master has detected the presence of one
or more slaves, it can issue one of the net address com-
mands described in the following paragraphs. The name of
each net address command (ROM command) is followed
by the 8-bit op code for that command in square brackets.
®
Refer to Chapter 5 of the Book of iButton Standards for
a comprehensive discussion of a net address search,
including an actual example.
Read Net Address [33h]
This command allows the bus master to read the
MAX17211/MAX17215’s 1-Wire net address. This com-
mand can only be used if there is a single slave on the
bus. If more than one slave is present, a data collision
occurs when all slaves try to transmit at the same time
(open-drain produces a wired-AND result).
1-Wire Functions
After successfully completing one of the net address com-
mands, the bus master can access the features of the
MAX17211/MAX17215 with either a read data or write data
function command described in the following paragraphs.
Any other IC operation such as a compute MAC operation
is accomplished by writing to the COMMAND register. See
the Summary of Commands section for details.
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Read Data [69h, LL, HH]
Write Data [6Ch, LL, HH]
This command reads data from the MAX17211/MAX17215
starting at memory address HHLL. Any memory address
from 0000h to 01FFh is a valid starting address. The LSb
of the data in address HHLL is available to be read imme-
diately after the MSb of the address has been entered.
Because the address is automatically incremented after
the MSb of each byte is received, the LSb of the data at
address HHLL+ 1 is available to be read immediately after
the MSb of the data at address HHLL. If the bus master
continues to read beyond address 01FFh, data is will be
undefined. Addresses labeled reserved in the memory
map contain undefined data values. The read data com-
mand can be terminated by the bus master with a reset
pulse at any bit boundary. Reads from nonvolatile memo-
ry addresses return the data in the shadow RAM. A recall
data command is required to transfer data from nonvola-
tile memory to the shadow RAM. See the Summary of
Commands section for more details. See Figure 82 for an
example read data communication sequence.
This command writes data to the MAX17211/15 starting at
memory address HHLL. Any memory address from 0000h
to 01FFh is a valid starting address. The LSb of the data
to be stored at address HHLL can be written immediately
after the MSb of address has been entered. Because the
address is automatically incremented after the MSb of
each byte is written, the LSb to be stored at address HHLL
+ 1 can be written immediately after the MSb to be stored
at address HHLL. If the bus master continues to write
beyond address 01FFh, the data is ignored by the IC.
Writes to read-only addresses and locked memory blocks
are ignored. Do not write to RESERVED address loca-
tions. Incomplete bytes are not written. Writes to unlocked
nonvolatile memory addresses modify the shadow RAM. A
Copy NV Block command is required to transfer data from
the shadow RAM to nonvolatile memory. See the Summary
of Commands section for more details. See Figure 82 for
an example Write Data communication sequence.
1-WIRE READ DATA PROTOCOL
CCh
(OR OTHER NET
ADDRESS COMMAND)
69h
RESET
MEMORY ADDRESS LSB
MEMORY ADDRESS MSB
DATA0 LSB
DATA0 MSB
DATA1 LSB
DATA N MSB
(READ DATA COMMAND)
1-WIRE WRITE DATA PROTOCOL
RESET
CCh
6Ch
(OR OTHER NET
ADDRESS COMMAND)
MEMORY ADDRESS LSB
MEMORY ADDRESS MSB
DATA0 LSB
DATA0 MSB
DATA1 LSB
DATA N MSB
(WRITE DATA COMMAND)
EXAMPLE READ OF NET ADDRESS
RESET
33h
NET ADDRESS LSB
(FAMILY CODE)
NET ADDRESS
1
NET ADDRESS
2
NET ADDRESS
3
NET ADDRESS
4
NET ADDRESS
5
NET ADDRESS
6
NET ADDRESS MSB
(CRC)
(READ NET ADDRESS)
EXAMPLE READ OF TEMP AND VCELL REGISTERS ADDRESS 0008h–0009h
CCh
69h
08h
00h
RESET
TEMP LSB
TEMP MSB
VCELL LSB
VCELL MSB
(SKIP NET ADDRESS)
(READ DATA COMMAND)
(ADDRESS LSB)
(ADDRESS MSB)
EXAMPLE WRITE OF ATRATE REGISTER ADDRESS 0004H
CCh
6Ch
04h
00H
RESET
ATRATE LSB
ATRATE MSB
(SKIP NET ADDRESS)
(WRITE DATA COMMAND)
(ADDRESS LSB)
(ADDRESS MSB)
= SLAVE TRANSMISSION
= HOST TRANSMISSION
Figure 82. Example 1-Wire Communication Sequences
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Stand-Alone ModelGauge m5 Fuel Gauge
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MAX1721x. For both 1-wire and 2-wire communication,
the function command must be written to the Command
(060h) or Config2 (0BBh) registers. Device commands
are described in detail in their respective sections of the
data sheet.
Summary of Commands
Any operation other than writing or reading a memory
location is executed by writing the appropriate command
to the Command or Config2 registers. Table 30 lists
all function commands understood by the MAX1720x/
Table 30. All Function Commands
COMMAND
TYPE
REGISTER
HEX
DESCRIPTION
Compute MAC Without
ROM ID
Computes hash operation of the message block with
logical 1s in place of the ROM ID.
SHA
060h
3600h
Compute MAC with
ROM ID
Computes hash operation of the message block including
the ROM ID.
SHA
SHA
060h
060h
3500h
3000h
Computes hash operation of the message block with
logical 1s in place of the ROM ID. The result is then
stored as the new secret.
Compute Next Secret
Without ROM ID
Computes hash operation of the message block includ-
ing the ROM ID. The result is then stored as the new
secret.
Compute Next Secret
with ROM ID
SHA
060h
3300h
Clear Secret
Lock Secret
SHA
SHA
060h
060h
5A00h
6000h
Resets the SHA-256 Secret to a value of all 0s
Permanently locks the SHA-256 Secret.
Copies all shadow RAM locations to nonvolatile
memory at the same time.
Copy NV Block
NV Recall
Memory
Memory
Memory
060h
060h
060h
E904h
E001h
E2XXh
Recalls all nonvolatile memory to RAM.
Recalls a page of nonvolatile memory history into RAM
page 1Eh.
History Recall
Permanently locks an area of memory. See the lock
section for details.
NV Lock
Memory
Reset
060h
060h
0BBh
6AXXh
000Fh
0001h
Recalls nonvolatile memory into RAM and resets the
IC hardware. Fuel gauge operation is not reset.
Hardware Reset
Fuel Gauge Reset
Restarts the fuel gauge operation without affecting
nonvolatile shadow RAM settings.
Reset
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MAX17211/MAX17215
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Appendix A: Reading History Data
Psuedo-Code Example
The following psuedo-code can be used as a reference for reading history data from the IC. The code first reads all
flag information, tests all flag information, then reads all valid history data into a two-dimensional array. Afterwards, the
HistoryLength variable will indicate the depth of the history array data.
Int WriteFlags[26];
Int ValidFlags[26];
Boolean PageGood[203];
Int HistoryData[203][16];
Int HistoryLength;
Int word, position, flag1, flag2, flag3, flag4;
//Read all flag information from the IC
WriteCommand(0xE2FB);
Wait(t
);
RECALL
WriteFlags[0] = ReadData(0x1E1);
WriteFlags[1] = ReadData(0x1E2);
WriteFlags[2] = ReadData(0x1E3);
WriteFlags[3] = ReadData(0x1E4);
WriteFlags[4] = ReadData(0x1E5);
WriteFlags[5] = ReadData(0x1E6);
WriteFlags[6] = ReadData(0x1E7);
WriteFlags[7] = ReadData(0x1E8);
WriteFlags[8] = ReadData(0x1E9);
WriteFlags[9] = ReadData(0x1EA);
WriteFlags[10] = ReadData(0x1EB);
WriteFlags[11] = ReadData(0x1EC);
WriteFlags[12] = ReadData(0x1ED);
WriteFlags[13] = ReadData(0x1EE);
WriteFlags[14] = ReadData(0x1EF);
WriteCommand(0xE2FC);
Wait(t
);
RECALL
WriteFlags[15] = ReadData(0x1E0);
WriteFlags[16] = ReadData(0x1E1);
WriteFlags[17] = ReadData(0x1E2);
WriteFlags[18] = ReadData(0x1E3);
WriteFlags[19] = ReadData(0x1E4);
WriteFlags[20] = ReadData(0x1E5);
WriteFlags[21] = ReadData(0x1E6);
WriteFlags[22] = ReadData(0x1E7);
WriteFlags[23] = ReadData(0x1E8);
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WriteFlags[24] = ReadData(0x1E9);
WriteFlags[25] = ReadData(0x1EA);
ValidFlags[0] = ReadData(0x1EB);
ValidFlags[1] = ReadData(0x1EC);
ValidFlags[2] = ReadData(0x1ED);
ValidFlags[3] = ReadData(0x1EE);
ValidFlags[4] = ReadData(0x1EF);
WriteCommand(0xE2FD);
Wait(t
);
RECALL
ValidFlags[5] = ReadData(0x1E0);
ValidFlags[6] = ReadData(0x1E1);
ValidFlags[7] = ReadData(0x1E2);
ValidFlags[8] = ReadData(0x1E3);
ValidFlags[9] = ReadData(0x1E4);
ValidFlags[10] = ReadData(0x1E5);
ValidFlags[11] = ReadData(0x1E6);
ValidFlags[12] = ReadData(0x1E7);
ValidFlags[13] = ReadData(0x1E8);
ValidFlags[14] = ReadData(0x1E9);
ValidFlags[15] = ReadData(0x1EA);
ValidFlags[16] = ReadData(0x1EB);
ValidFlags[17] = ReadData(0x1EC);
ValidFlags[18] = ReadData(0x1ED);
ValidFlags[19] = ReadData(0x1EE);
ValidFlags[20] = ReadData(0x1EF);
WriteCommand(0xE2FE);
Wait(t
);
RECALL
ValidFlags[21] = ReadData(0x1E0);
ValidFlags[22] = ReadData(0x1E1);
ValidFlags[23] = ReadData(0x1E2);
ValidFlags[24] = ReadData(0x1E3);
ValidFlags[25] = ReadData(0x1E4);
//Determine which history pages contain valid data
For loop = 0 to 202
{
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MAX17211/MAX17215
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with SHA-256 Authentication
word = (int)( loop/8 );
position = loop % 8 ; //remainder
flag1 = (WriteFlags[word] >> position) & 0x0001;
flag2 = (WriteFlags[word] >> (position+8)) & 0x0001;
flag3 = (ValidFlags[word] >> position) & 0x0001;
flag4 = (ValidFlags[word] >> (position+8)) & 0x0001;
if (flag1 || flag2) && (flag3 || flag4)
PageGood[loop] = True;
else
PageGood[loop] = False;
}
//Read all the history data from the IC
HistoryLength = 0;
For loop = 0 to 202
{
if(PageGood[loop]) == TRUE
{
SendCommand(0xE226 + loop);
Wait(t
);
RECALL
HistoryData[HistoryLength][0] = ReadData(0x1E0);
...
HistoryData[HistoryLength][15] = ReadData(0x1EF);
HistoryLength++;
}
}
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MAX17201/MAX17205/
MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Ordering Information
PART
CELL COUNT
INTERFACE
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
14 TDFN-EP*
15 WLP
2
MAX17201G+
1S
1S
I C
2
MAX17201G+T
I C
2
MAX17201G+00E**
MAX17201G+T0E**
MAX17205G+
1S
I C
2
1S
I C
2
> 1S
> 1S
> 1S
> 1S
1S
I C
2
MAX17205G+T
I C
2
MAX17205G+00E**
MAX17205G+T0E**
MAX17211G+
I C
2
I C
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
MAX17211G+T
1S
MAX17211G+00E**
MAX17211G+T0E**
MAX17215G+
1S
1S
> 1S
> 1S
> 1S
> 1S
1S
MAX17215G+T
MAX17215G+00E**
MAX17215G+T0E**
MAX17201X+
2
I C
2
MAX17201X+T
1S
I C
15 WLP
2
MAX17201X+00E**
MAX17201X+T0E**
MAX17205X+
1S
I C
15 WLP
2
1S
I C
15 WLP
2
> 1S
> 1S
> 1S
> 1S
1S
I C
15 WLP
2
MAX17205X+T
I C
15 WLP
2
MAX17205X+00E**
MAX17205X+T0E**
MAX17211X+
I C
15 WLP
2
I C
15 WLP
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
1-Wire
15 WLP
MAX17211X+T
1S
15 WLP
MAX17211X+00E**
MAX17211X+T0E**
MAX17215X+
1S
15 WLP
1S
15 WLP
> 1S
> 1S
> 1S
> 1S
15 WLP
MAX17215X+T
15 WLP
MAX17215X+00E**
MAX17215X+T0E**
15 WLP
15 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
**00E or T0E indicates IC supports EZ performance model only. No custom battery characterization.
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MAX17211/MAX17215
Stand-Alone ModelGauge m5 Fuel Gauge
with SHA-256 Authentication
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
2/16
Initial release
—
Updated General Description, Simplified Block Diagram, Absolute Maximum Ratings,
Package Information, Electrical Characteristics table, Pin Configuration, Pin Descrip-
tion, Functional Diagram, Single-Cell/Typical Operating Circuit (MAX17201/MAX17211
Only) section, Figure 1, Multicell Typical Operating Circuits (MAX17205/MAX17215
Only), Figure 2, Figure 3, Figure 6, Cell Balancing Current section, Current Measure-
ment section, Ordering Information, and removed Appendix B: Layout Guidelines,
corrected address locations where memory flags are read, corrected bump number,
and added future product references
1, 2, 13–16, 18,
23, 24, 26–28,
47–49, 68, 69,
72, 84, 85, 97,
98, 111–114
1
2
7/16
8/16
Updated Table 22, removed future product references
87, 115
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 115
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