MAX17511 [MAXIM]
Dual-Output, 3-/2-/1-Phase 2-/1-Phase Quick-PWM Controllers for VR12/IMVP7;
| 型号： | MAX17511 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Output, 3-/2-/1-Phase 2-/1-Phase Quick-PWM Controllers for VR12/IMVP7 |
| 文件： | 总72页 (文件大小：3512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5742; Rev 1; 7/11
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
General Description
Features
S Intel VR12/IMVP-7-Compliant Serial Interface
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T are dual-output, step-down, constant on-time
Quick-PWMK controllers for VR12/IMVP-7 CPU core sup-
plies. The controllers consist of two high-current switching
power supplies for CPU and GFX cores. The CPU regulator
(regulator A) is a three-phase constant on-time architecture.
The GFX regulator (regulator B) is also constant on-time
architecture. The MAX17411 supports 2-phase operation
and the MAX17511/MAX17511C/MAX17511N/MAX17511T
support 1-phase operation. The MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T include two internal
drivers on regulator A and one internal driver on regula-
tor B. External drivers such as the MAX17491 enable the
additional phases.
S 3-/2-/1-Phase Quick-PWM CPU Core Regulator
Two Internal Drivers and One External Driver
Transient-Phase Overlap Mode
Dynamic Phase Selection
S 2-/1-Phase Quick-PWM GFX Regulator
One Internal and One External Driver
S Active Overshoot Suppression
S 8-Bit VR12/IMVP-7 DAC
S ±±0.5 V
Accuracy Over Line, Load, and
Temperature
OUT
S Active Voltage Positioning with Programmable
Both regulator A and regulator B include output voltage
sensing and accurate load-line gain. Switching frequen-
cies are programmable from 200kHz to 600kHz per
phase. Output overvoltage protection (OVP, MAX17411/
MAX17511/MAX17511C/MAX17511N), undervoltage pro-
tection (UVP), and thermal protection ensure effective and
reliable operation. When any of these protection features
detect a fault, the controller shuts down both outputs.
Gain
S Accurate Lossless Current Balance
S Accurate Droop and Current Limit
S Remote Output and Ground Sense
S Power-Good Window Comparators (POKA and
POKB)
The multiphase regulators include transient-phase over-
lap and active overshoot suppression, which speed up
the response time and reduce the total output capaci-
tance. The CPU and GFX outputs are controlled inde-
pendently by writing the appropriate data into a function-
mapped register file. VID code transitions and soft-start
are enabled with a precision slew-rate control circuit. The
SVID interface also allows each regulator to be individu-
ally set into a low-power, single-phase, pulse-skipping
state to optimize efficiency. The MAX17411 is available in
a 48-pin, 6mm x 6mm, TQFN package. The MAX17511/
MAX17511C/MAX17511N/MAX17511T are available in a
40-pin, 5mm O5mm, TQFN lead-free package.
S 40.V to 24V Battery-Input Voltage Range
S Programmable 2±±kHz to 6±±kHz Switching
Frequency
S External Thermal-Fault Detection Output
(VR_HOT#)
S Overvoltage (MAX17411/MAX17.11/MAX17.11C/
MAX17.11N), Undervoltage, and Thermal-Fault
Protection
S Slew-Rate Controlled Soft-Start
S Passive Soft-Shutdown (2±I Discharge Switches)
S Integrated Boost Switches
S Low-Profile, 48-Lead/4±-Lead TQFN Packages
Applications
VR12/IMVP-7 CPU Core Power Supplies
Notebooks/Desktops/Servers
Quick PWM is a trademark of Maxim Integrated Products, Inc.
Ordering Information
PART
TEMP RANGE
-40NC to +105NC
-40NC to +105NC
PIN-PACKAGE
48 TQFN-EP*
40 TQFN-EP*
FEATURE
MAX17411GTM+
MAX17.11GTL+
3-/2-/1-Phase + 2-/1-Phase
3-/2-/1-Phase + 1-Phase
Ordering Information continued on last page.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
_______________________________________________________________ Maxim Integrated Products
1
For information on other Maxim products, visit Maxim’s website at www.maxim-ic.com.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ABSOLUTE MAXIMUM RATINGS
CC DDA DDB
V
, V
, V
to GND (AGND).........................-0.3V to +6V
BSTA_ to V
......................................................-0.3V to +26V
DDA
VDIO, CLK, ALERT# to GND (AGND).....................-0.3V to +6V
CSPAAVE, CSPBAVE, CSP_,
CSN_ to GND (AGND) ........................................-0.3V to +6V
BSTB to V
.......................................................-0.3V to +26V
DDB
LXA_ to BSTA_ ........................................................-6V to +0.3V
LXB to BSTB............................................................-6V to +0.3V
LX_ to GND (AGND) ................................................-6V to +26V
DHA_ to LXA_.......................................-0.3V to (V
DHB to LXB ........................................... -0.3V to (V
FBA, FBB to GND (AGND)....................... -0.3V to (V
SR, IMAX_ to GND (AGND) .................... -0.3V to (V
+ 0.3V)
+ 0.3V)
CC
CC
+ 0.3V)
+ 0.3V)
BSTA_
BSTB
POKA, POKB, EN to GND (AGND).........................-0.3V to +6V
VR_HOT# to GND (AGND)......................................-0.3V to +6V
Continuous Power Dissipation (T = +70NC)
A
THERMA, THERMB to GND (AGND) ....... -0.3V to (V
GNDSA, GNDSB to GND (AGND) .......................-0.3V to +0.3V
TON to GND..........................................................-0.3V to +26V
+ 0.3V)
40-Pin TQFN (derate 35.7mW/NC above +70NC) ...2857.1mW
48-Pin TQFN (derate 37mW/NC above +70NC) .........2963mW
Operating Temperature Range........................ -40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +165NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
CC
DRVPWMA to GND (AGND) .................. -0.3V to (V
DRVPWMB to GND (AGND) .................. -0.3V to (V
DLA_ to GND (PGND)............................ -0.3V to (V
DLB to GND (PGND).............................. -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
DDA
DDB
DDA
DDB
PACKAGE THERMAL CHARACTERISTICS (Note 1)
40 TQFN
Junction-to-Ambient Thermal Resistance (q ) ..........28°C/W
48 TQFN
Junction-to-Ambient Thermal Resistance (q ) ..........27°C/W
JA
JA
Junction-to-Case Thermal Resistance (q )..............1.6°C/W
Junction-to-Case Thermal Resistance (q )..............1.3°C/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www0maxim-ic0com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
PWM CONTROLLER
Input Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
, V
, V
4.5
5.5
V
CC DDA DDB
DAC codes from
1.000V to 1.520V
-0.5
+0.5
%
Measured at FB_ with
respect to GNDS_;
includes load regulation
error (Note 2)
DC Output Voltage
Accuracy
DAC codes from
0.800V to 0.995V
-5
-8
+5
+8
mV
DAC codes from
0.250V to 0.795V
Line Regulation Error
V
= 4.5V to 5.5V, V = 4.5V to 24V
0.1
-10
10
mV
mV
CC
IN
Upward transitions
-15
5
-5
15
V
Bit Accuracy
SETTLED
Downward transitions
GNDS_ Input Range
GNDS_ Gain
-200
0.97
-0.5
+200
1.03
+0.5
0.1
mV
V/V
FA
A
V
DV
/DV
GNDS_
1.00
0.01
GNDS
OUT
GNDS_ Input Bias Current
TON Shutdown Current
T = +25NC
A
EN = GND, V = 24V, V
= 0V, T = +25NC
FA
IN
CC
A
MAX17511N only, Reg A and Reg B
MAX17511C only, Reg B only
1.094 1.100
0.895 0.900
1.106
0.905
Boot Voltage
V
BOOT
2
______________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured at DHA_ (600kHz - 10%),
R
R
= 96.7kI(MAX17411 only),
= 48.35kI (MAX17511/MAX17511C/
TON
157
185
307
554
151
251
453
213
TON
MAX17511N/MAX17511T)
Measured at DHA_, V = 12V (300kHz - 10%),
R
(MAX17511/MAX17511C/MAX17511N/
MAX17511T)
IN
= 200kI(MAX17411 only), R
= 100kI
TON
TON
DHA_ On-Time (Note 3)
t
ns
ONA
276
470
128
226
338
638
174
277
Measured at DHA_ (200kHz - 10%),
R
R
= 303.3kI(MAX17411 only),
= 151.65kI (MAX17511/MAX17511C/
TON
TON
MAX17511N/MAX17511T)
Measured at DHB (600kHz + 10%),
R
R
= 96.7kI(MAX17411 only),
= 48.35kI (MAX17511/MAX17511C/
TON
TON
MAX17511N/MAX17511T)
Measured at DHB, V = 12V (300kHz + 10%),
R
(MAX17511/MAX17511C/MAX17511N/
MAX17511T)
IN
= 200kI(MAX17411 only), R
= 100kI
TON
TON
DHB On-Time (Note 3)
t
ns
ONB
Measured at DHB (200kHz + 10%),
R
TON
= 303.3kI(MAX17411 only), R
=
TON
385
150
521
250
151.65kI (MAX17511/MAX17511C/
MAX17511N/MAX17511T)
Minimum Off-Time (Note 3)
t
Measured at DH_
200
40
ns
ns
OFF(MIN)
Minimum DRVPWM_ Pulse
Width
BIAS CURRENTS
Quiescent Supply Current
Measured at V , SKIP mode, FB_ forced above
CC
the regulation point
I
5
10
1
mA
FA
FA
FA
BIAS
(V
CC
)
Quiescent Supply Current
(V
T
= +25NC, measured at V , FPWM mode,
DD_
A
I
0.02
16
DRV
)
FB_ forced above the regulation point
DD_
Shutdown Supply Current
(V
Measured at V , EN = GND
30
1
CC
)
CC
Shutdown Supply Current
(V
T
= +25NC, measured at V , EN = GND
0.01
A
DD
)
DD_
SLEW-RATE CONTROL
SetVID - fast slew rate =
10mV/Fs (min)
10
2.5
20
5
V
= 0V or V = 5V
SR
SR
SetVID - slow slew rate
= 2.5mV/Fs (min)
SetVID - fast slew rate =
20mV/Fs (min)
SetVID - slow slew rate
= 5mV/Fs (min)
Slew-Rate Accuracy
mV/Fs
V
V
= 3V or
= 1.5V
SR
SR
_______________________________________________________________________________________
3
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
= 1V;
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
CSN_
[SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices 100%
A
A
tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Soft-Start Slew Rate
Non-zero V
2.5
mV/Fs
BOOT
Discharge Switch
Resistance
CSNA, CSNB
20
I
Low
0.4
1.8
Mid-low
1.2
2.2
SR Four-Level Logic
Thresholds
V
CC
- 1.2V
Mid-high
High
V
V
CC
- 0.4V
FAULT PROTECTION
Upper POK_ (MAX17411/
MAX17511/MAX17511C/
MAX17511N/MAX17511T)
and Output Overvoltage
Protection Trip
Threshold(MAX17411/
MAX17511/MAX17511C/
MAX17511N)
SKIP mode after output reaches the regulation
voltage or PWM mode; measured at FB_ with
respect to the voltage target set by the VID code
(see Table 3)
200
250
300
mV
V
V
OVP
Soft-start, SKIP mode, and output has not reached
the regulation voltage; measured at FB_
1.72
1.77
0.8
1.82
Minimum OVP threshold, measured at FB_
Upper POK_ and Output
Overvoltage Propagation
Delay
FB_ forced 25mV above trip threshold
(MAX17411/MAX17511/MAX17511C/MAX17511N)
t
5
Fs
OVP
Lower POK_ and Output
Undervoltage Protection
Trip Threshold
Measured at FB_ with respect to unloaded output
voltage
V
-300
100
-250
-200
350
mV
UVP
Lower POK_ Propagation
Delay
FB_ forced 25mV below trip threshold
FB_ forced 25mV below trip threshold
5
Fs
Fs
Output Undervoltage
Propagation Delay
t
200
UVP
POK_ Output Low Voltage
POK_ Leakage Current
I
= 4mA
0.3
1
V
SINK
High state, POK_ forced to 5V, T = +25NC
FA
A
POK_ Startup Delay and
Transitions Blanking Time
Measured from the time when FB_ reaches the
target voltage
t
_
POK
20
Fs
V
Undervoltage-Lockout
Rising edge, 50mV typical hysteresis, controller
disabled below this level
CC
V
UVLO
4.05
4.25
4.45
V
Threshold
4
______________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
THERMAL PROTECTION
Measured at THERM_ with respect to V
falling
CC
VR_HOT# Trip Threshold
edge; specify as % error for all TEMP MAX DAC
code settings, typical hysteresis = 100mV
49.5
50.5
%
Thermal zone comparator trip points, measured
with respect to V ; voltage threshold
CC
corresponding to TMAX O(1 - N%),
N = 0, 3, 6, 9, 12, 15, 18, 25
49 +
24 O
N/31
50 +
24 O
N/31
51 +
24 O
N/31
Thermal Zone Registers Trip
Points
%
THERM_ Input Leakage
I
V
= 2.5V, T = +25NC
-100
+100
1
nA
THRM
THERM_
A
High-Z state (THERM_ > 0.505 x V ), VR_HOT#
forced to 5V, T = +25NC
CC
VR_HOT# Leakage Current
FA
A
Internal Thermal Fault
Shutdown Threshold
T
Typical hysteresis = 15NC
160
NC
TSHDN
VALLEY CURRENT LIMIT AND DROOP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
22.5
21.5
17.0
15.0
27.0
25.0
20.0
17.0
30.0
28.0
22.5
20.0
33.5
31.0
25.0
21.5
25.5
24.5
20.0
18.0
30.0
28.0
23.0
20.0
33.0
31.0
25.5
23.0
36.5
34.0
28.0
24.5
28.5
27.5
23.0
21.0
33.0
31.0
26.0
23.0
36.0
34.0
28.5
26.0
39.5
37.0
31.0
27.5
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
V
V
V
- V
= 0V,
= 1.5V,
,
CSP_
CSN_
SR
Valley Current-Limit
Threshold Voltage (Positive)
SR
V
ILIMA
mV
or one-phase
operation
_______________________________________________________________________________________
.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
= 0.65mI, I
MIN
29.0
28.0
22.0
19.5
35.0
32.5
26.0
22.0
39.0
36.5
29.0
26.0
43.5
40.0
32.5
28.0
22.5
21.5
13.0
11.0
27.0
25.0
15.0
13.0
30.0
28.0
17.0
15.0
33.5
31.0
20.0
17.0
TYP
33.0
32.0
26.0
23.5
39.0
36.5
29.9
26.0
43.0
40.5
33.0
30.0
47.5
44.0
36.5
32.0
25.5
24.5
16.0
14.0
30.0
28.0
18.0
16.0
33.0
31.0
20.0
18.0
36.5
34.0
23.0
20.0
MAX
37.0
36.0
30.0
27.5
43.0
40.5
33.8
30.0
47.0
44.5
37.0
34.0
51.5
48.0
40.5
36.0
28.5
27.5
19.0
17.0
33.0
31.0
21.0
19.0
36.0
34.0
23.0
21.0
39.5
37.0
26.0
23.0
UNITS
R
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
V
V
V
- V
= 3V or
= 5V,
,
CSP_
CSN_
SR
SR
Valley Current-Limit
Threshold Voltage (Positive)
V
exclude
one-phase
operaton
mV
ILIMA
V
V
V
- V
,
CSP_
CSN_
= 0V,
= 1.5V,
SR
SR
Valley Current-Limit
Threshold Voltage (Positive)
V
mV
ILIMB
or one-phase
operation
6
______________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
= 0.65mI, I
MIN
29.0
28.0
17.0
14.0
35.0
32.5
19.5
17.0
39.0
36.5
22.0
19.5
43.5
40.0
26.0
22.0
TYP
33.0
32.0
21.0
18.0
39.0
36.5
23.5
21.0
43.0
40.5
26.0
23.5
47.5
44.0
30.0
26.0
MAX
37.0
36.0
25.0
22.0
43.0
40.5
27.5
25.0
47.0
44.5
30.0
27.5
51.5
48.0
34.0
30.0
UNITS
R
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
V
V
V
- V
= 3V or
= 5V,
,
CSP_
CSN_
SR
Valley Current-Limit
Threshold Voltage (Positive)
SR
V
ILIMB
mV
exclude
one-phase
operaton
Current-Limit Threshold
Voltage (Zero Crossing)
V
ZERO
V
GND
- V
LX_
1
mV
mV
Current-Balance Offset
Voltage
-1.5
+1.5
CSPAAVE, CSPBAVE, CSP_,
Input Current
T
= +25NC
-0.12
+0.12
14
FA
FA
V
A
CSN_ Pulldown Current
7
3
V
-
CC
Phase Disable Threshold
CSPB2, CSPB1, CSPA3, CSPA2, CSPA1
V
CC
- 1
0.4
FB_ Droop Amplifier (GMD)
Offset
(V
- V
) at I = 0mA
FB_
-1.0
591
+1.0
609
mV
CSP_AVE
CSN_
FB_ Droop Amplifier (GMD)
Transconductance
DI
FB_
/D(V
- V ),
CSN_
CSP_AVE
600
FS
V
- V
= -15mV to +15mV
CSP_AVE
CSN_
_______________________________________________________________________________________
7
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
IMAX_ LOGIC
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
13.65 O
Threshold 0, fault
V /50
CC
Threshold 1, R
= 0.65mI,
14.20 O
14.65 O
/50
SENSE
I
= 39A
V /50
CC
V
CC
MAX
15.20 O
/50
15.65 O
/50
Threshold 2, R
Threshold 3, R
= 0.65mI, I
= 0.65mI,
= 36A
SENSE
MAX
V
V
CC
CC
16.20 O
/50
16.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 4, R
= 0.65mI,
17.20 O
/50
17.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
18.20 O
/50
18.65 O
/50
Threshold 5, R
Threshold 6, R
Threshold 7, R
Threshold 8, R
Threshold 9, R
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 39A
SENSE
SENSE
SENSE
SENSE
SENSE
MAX
MAX
MAX
MAX
MAX
V
CC
V
CC
19.20 O
/50
19.65 O
/50
= 36A
V
CC
V
CC
20.20 O
/50
20.65 O
/50
= 30A/23A
= 26A/20A
= 39A
V
CC
V
CC
21.20 O
/50
21.65 O
/50
V
CC
V
CC
V
IMAX_ Detection Thresholds
22.20 O
/50
22.65 O
/50
V
CC
V
CC
23.20 O
/50
23.65 O
/50
Threshold 10, R
Threshold 11, R
= 0.85mI, I
= 36A
MAX
SENSE
V
V
CC
CC
= 0.85mI,
24.20 O
/50
24.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 12, R
= 0.85mI,
= 0.95mI,
25.20 O
/50
25.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
Threshold 13, R
= 39A
26.20 O
/50
26.65 O
/50
SENSE
I
V
CC
V
CC
MAX
27.20 O
/50
27.65 O
/50
Threshold 14, R
Threshold 15, R
= 0.95mI, I
= 36A
MAX
SENSE
V
V
CC
CC
= 0.95mI,
28.20 O
/50
28.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 16, R
= 0.95mI,
29.20 O
/50
29.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
30.20 O
/50
Threshold 17, fault
V
CC
8
______________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
GATE DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High state (pullup)
Low state (pulldown)
0.9
0.7
2.5
2.0
2.0
0.7
DH_ Gate-Driver
On-Resistance
R
BST_ - LX_ forced to 5V
I
I
I
A
ON(DH)
High state (pullup)
0.7
DL_ Gate-Driver
On-Resistance
R
ON(DL)
Low state (pulldown)
0.25
Internal BST_ Switch On-
Resistance
BSTA1 to V
, BSTA2 to V
, BSTB to V
,
DDA
DDA
DDB
R
BST
10
2.2
2.7
2.7
8
20
V
DD_
= 5V
DH_ Gate-Driver Source
Current
I
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
DL_ forced to 2.5V
DH(SRC)
DH_ Gate-Driver Sink
Current
I
A
DH(SINK)
DL_ Gate-Driver Source
Current
I
A
DL(SRC)
DL(SINK)
DL_ Gate-Driver Sink
Current
I
DL_ forced to 2.5V
A
DH_ low to DL_ high
DL_ low to DH_ high
30
30
20
20
20
20
Driver Propagation Delay
DL_ Transition Time
DH_ Transition Time
ns
ns
ns
V
DL_ falling, C = 3nF
DL
DL_ rising, C = 3nF
DL
DH_ falling, C
= 3nF
= 3nF
DH
DH
DH_ rising, C
DRVPWMA, DRVPWMB
Logic-High Voltage
V
DD_
- 0.4
I
I
= 3mA
SOURCE
DRVPWMA, DRVPWMB
Logic-Low Voltage
= 3mA
0.4
V
SINK
LOGIC AND I/O
Enable Input High Voltage
Enable Input Low Voltage
Enable Input Current
V
0.67
-1
V
V
EN_IH
V
0.33
+1
EN_IL
T
= +25NC
FA
A
SERIALVID INTERFACE (per Intel SerialVID Specification—see the Detailed Description)
SerialVID Input Low Voltage
(CLK, VDIO)
V
-0.1
+0.45
V
V
V
V
IL
SerialVID Input High Voltage
(CLK, VDIO)
V
TT
+
V
IH
0.65
1V
SerialVID Output High
Voltage (VDIO, ALERT#)
V
OH
Open-drain pullup to V
V
TT
TT
SerialVID Output Low Level
(VDIO, ALERT#)
V
Open-drain pullup to V , R = 50I
0.36
OL
TT PU
_______________________________________________________________________________________
9
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
CSP_ CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
= 1V; [SerialVID = 1.00, FPWM MODE]; T = ±°C to +8.°C, unless otherwise noted. Typical values are at T = +25NC. All devices
A
A
100% tested at T = +25NC. Limits over temperature guaranteed by design.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SerialVID Open-Drain
Output On-Resistance
(VDIO, ALERT#, VRHOT#)
R
I
= 30mA
SINK
4
13
I
ON
SerialVID Logic-Input
Leakage Current
(CLK, VDIO)
T
T
= +25NC
-1
+1
FA
A
A
ALERT# Deasserted
Leakage Current
= +25NC, V
= 3.3V
1
FA
ALERT#
SerialVID Logic Slew Rate
(CLK, VDIO, ALERT#)
0.5
2.0
V/ns
SerialVID Input Capacitance
CLK Frequency
C
4
pF
PAD
f
13
-5
25
33.3
MHz
CLK
CLK Absolute Min/Max
Period
Specified as a percentage of f
+5
%
CLK
CLK High Time
CLK Low Time
Rise Time
t
Specified as a percentage of t
Specified as a percentage of t
period
period
45
45
%
%
HIGH
CLK
t
LOW
CLK
t
0.25
0.25
45
2.5
2.5
ns
ns
%
RISE
FALL
Fall Time
t
Duty Cycle
55
SerialVID Inactivity Timeout
t
0.14
0.40
Fs
RSTNA
ELECTRICAL CHARACTERISTICS
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
PWM CONTROLLER
Input Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
, V
, V
4.5
5.5
V
CC DDA DDB
DAC codes from 1.000V
to 1.520V
-0.8
+0.8
%
Measured at FB_
with respect to
GNDS_; includes load
regulation error
(Note 2)
DC Output Voltage
Accuracy
DAC codes from 0.800V
to 0.995V
-8
-8
+8
+8
mV
DAC codes from 0.250 to
0.795V
Upward transitions
-15
5
-5
V
BIT Accuracy
mV
SETTLED
Downward transitions
15
GNDS_ Input Range
GNDS_ Gain
-200
0.97
1.091
0.892
+200
1.03
1.109
0.908
mV
V/V
A
V
DV
/DV
OUT GNDS_
GNDS
MAX17511N only, Reg A and Reg B
MAX17511C only, Reg B only
Boot Voltage
V
BOOT
1± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Measured at DHA_ (600kHz - 10%),
R
TON
= 96.7kI (MAX17411 only), R
= 48.35K
157
213
TON
(MAX17511/MAX17511C/MAX17511N/MAX17511T)
Measured at DHA_, V = 12V (300kHz - 10%),
IN
R
= 200kI (MAX17411 only), R
= 100kI
276
470
338
638
TON
TON
DHA_ On-Time (Note 3)
t
ns
ONA
(MAX17511/MAX17511C/MAX17511N/MAX17511T)
Measured at DHA_ (200kHz - 10%),
R
= 303.3kI (MAX17411 only), R
=
TON
TON
151.65kI (MAX17511/MAX17511C/MAX17511N/
MAX17511T)
Measured at DHB (600kHz + 10%),
R
= 96.7kI (MAX17411 only), R
=
TON
TON
128
226
174
277
48.35kI (MAX17511/MAX17511C/MAX17511N/
MAX17511T)
Measured at DHB, V = 12V (300kHz + 10%),
R
(MAX17511/MAX17511C/MAX17511N/
MAX17511T)
IN
= 200kI (MAX17411 only), R
= 100kI
TON
TON
DHB On-Time (Note 3)
t
ns
ns
ONB
Measured at DHB (200kHz + 10%),
R
= 303.3kI (MAX17411 only), R
=
TON
TON
385
150
521
250
151.65kI (MAX17511/MAX17511C/MAX17511N/
MAX17511T)
Minimum Off-Time
(Note 3)
t
Measured at DH_
OFF(MIN)
BIAS CURRENTS
Quiescent Supply Current
Measured at V , SKIP mode, FB_ forced above
CC
the regulation point
I
10
30
mA
BIAS
(V
CC
)
Shutdown Supply Current
(V
Measured at V , EN = GND
FA
CC
)
CC
SLEW-RATE CONTROL
Slew-Rate Accuracy
Soft-Start Slew Rate
SetVID - fast slew rate =
10mV/Fs (min)
10
2.5
20
V
V
= 0V or V = 5V
SR
SR
SetVID - slow slew rate
= 2.5mV/Fs (min)
mV/Fs
SetVID - fast slew rate =
20mV/Fs (min)
= 3V or V = 1.5V
SR
SR
SetVID - slow slew rate
= 5mV/Fs (min)
5
Non-zero V
Low
2.5
mV/Fs
BOOT
0.4
Mid-low
Mid-high
High
1.2
2.2
1.8
SR Four-Level Logic
Thresholds
V
V
- 1.2V
CC
V
- 0.4V
CC
______________________________________________________________________________________ 11
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT PROTECTION
Upper POK_ (MAX17411/
MAX17511/MAX17511N/
MAX17511T) and Output
Overvoltage Protection Trip
Threshold (MAX17411/
MAX17511/MAX17511C/
MAX17511N)
SKIP mode after output reaches the regulation
voltage or PWM mode; measured at FB_ with
respect to the voltage target set by the VID code
(see Table 3)
200
300
mV
V
OVP
Soft-start, SKIP mode, and output has not reached
the regulation voltage, measured at FB_
1.72
-300
100
1.82
-200
V
Lower POK_ and Output
Undervoltage Protection
Trip Threshold
Measured at FB_ with respect to unloaded output
voltage
V
mV
UVP
UVP
Output Undervoltage
Propagation Delay
t
FB_ forced 25mV below trip threshold
350
0.3
Fs
V
POK_ Output Low Voltage
I
= 4mA
SINK
V
Undervoltage Lockout
Rising edge, 50mV typical hysteresis, controller
disabled below this level
CC
V
UVLO
4.05
49.5
4.45
V
Threshold
THERMAL PROTECTION
Measured at THERM_ with respect to V
falling
CC
VR_HOT# Trip Threshold
edge; specify as % error for all TEMP MAX DAC
code settings; typical hysteresis = 100mV
50.5
%
%
Thermal zone comparator trip points, measured
with respect to V , voltage threshold
CC
corresponding to TMAX O(1 - N%), N = 0, 3, 6, 9,
12, 15, 18, 25
49 +
24 O
N/31
51 +
24 O
N/31
Thermal Zone Registers
Trip Points
VALLEY CURRENT LIMIT AND DROOP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
22.5
21.5
17.0
15.0
27.0
25.0
20.0
17.0
30.0
28.0
22.5
20.0
33.5
31.0
25.0
21.5
28.5
27.5
23.0
21.0
33.0
31.0
26.0
23.0
36.0
34.0
28.5
26.0
39.5
37.0
31.0
27.5
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
V
V
V
- V
= 0V,
= 1.5V,
,
CSP_
CSN_
SR
Valley Current-Limit
Threshold Voltage (Positive)
SR
V
mV
ILIMA
or one-phase
operation
12 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
= 0.65mI, I
MIN
29.0
28.0
22.0
19.5
35.0
32.5
26.0
22.0
39.0
36.5
29.0
26.0
43.5
40.0
32.5
28.0
22.5
21.5
13.0
11.0
27.0
25.0
15.0
13.0
30.0
28.0
17.0
15.0
33.5
31.0
20.0
17.0
TYP
MAX
37.0
36.0
30.0
27.5
43.0
40.5
33.8
30.0
47.0
44.5
37.0
34.0
51.5
48.0
40.5
36.0
28.5
27.5
19.0
17.0
33.0
31.0
21.0
19.0
36.0
34.0
23.0
21.0
39.5
37.0
26.0
23.0
UNITS
R
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 30A
= 26A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXA
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
V
V
or V
5V, exclude
one-phase
operation
- V
= 3V
=
,
CSP_
CSN_
SR
Valley Current-Limit
Threshold Voltage (Positive)
SR
V
mV
ILIMA
V
V
V
- V
,
CSP_
CSN_
= 0V,
= 1.5V,
SR
Valley Current-Limit
Threshold Voltage (Positive)
SR
V
ILIMB
mV
or one-phase
operation
______________________________________________________________________________________ 13
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
= 0.65mI, I
MIN
29.0
28.0
17.0
14.0
35.0
32.5
19.5
17.0
39.0
36.5
22.0
19.5
43.5
40.0
26.0
22.0
TYP
MAX
37.0
36.0
25.0
22.0
43.0
40.5
27.5
25.0
47.0
44.5
30.0
27.5
51.5
48.0
34.0
30.0
UNITS
R
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
= 39A
= 36A
= 23A
= 20A
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
MAXB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= 0.65mI, I
= 0.65mI, I
= 0.65mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.85mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
= 0.95mI, I
V
V
or V
5V, exclude
one-phase
operation
- V
= 3V
=
,
CSP_
CSN_
SR
SR
Valley Current-Limit
Threshold Voltage (Positive)
V
mV
ILIMB
Current-Balance Offset
Voltage
-1.5
3
+1.5
mV
V
V
CC
-
Phase Disable Threshold
CSPB2, CSPB1, CSPA3, CSPA2, CSPA1
0.4
FB_ Droop Amplifier (G
Offset
)
)
MD
V
- V
at I
= 0mA
-1.0
588
+1.0
612
mV
FS
CSP_AVE
CSN_
FB_
FB_ Droop Amplifier (G
Transconductance
DI
/D(V
FB_
- V
),
MD
CSP_AVE
CSN_
V
- V
= -15mV to +15mV
CSP_AVE
CSN_
14 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
IMAX_ LOGIC
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
13.65 O
Threshold 0, fault
V /50
CC
14.20 O
14.65 O
/50
Threshold 1, R
= 0.65mI, I
= 39A
= 36A
SENSE
MAX
MAX
V /50
CC
V
CC
15.20 O
/50
15.65 O
/50
Threshold 2, R
Threshold 3, R
= 0.65mI, I
= 0.65mI,
SENSE
V
CC
V
CC
16.20 O
/50
16.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 4, R
= 0.65mI,
17.20 O
/50
17.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
18.20 O
/50
18.65 O
/50
Threshold 5, R
Threshold 6, R
Threshold 7, R
Threshold 8, R
Threshold 9, R
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.75mI, I
= 0.85mI, I
= 39A
SENSE
SENSE
SENSE
SENSE
SENSE
MAX
MAX
MAX
MAX
MAX
V
V
CC
CC
19.20 O
/50
19.65 O
/50
= 36A
V
CC
V
CC
20.20 O
/50
20.65 O
/50
= 30A/23A
= 26A/20A
= 39A
V
CC
V
CC
21.20 O
/50
21.65 O
/50
V
CC
V
CC
IMAX_ Detection
Thresholds
V
22.20 O
/50
22.65 O
/50
V
CC
V
CC
23.20 O
/50
23.65 O
/50
Threshold 10, R
Threshold 11, R
= 0.85mI, I
= 0.85mI,
= 36A
SENSE
MAX
V
V
CC
CC
24.20 O
/50
24.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 12, R
= 0.85mI,
25.20 O
/50
25.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
26.20 O
/50
26.65 O
/50
Threshold 13, R
= 0.95mI, I
= 39A
= 36A
SENSE
MAX
MAX
V
V
CC
CC
27.20 O
/50
27.65 O
/50
Threshold 14, R
Threshold 15, R
= 0.95mI, I
= 0.95mI,
SENSE
V
V
CC
CC
28.20 O
/50
28.65 O
/50
SENSE
I
= 30A/23A
V
CC
V
CC
MAXA/B
Threshold 16, R
= 0.95mI,
29.20 O
/50
29.65 O
/50
SENSE
I
= 26A/20A
V
V
CC
MAXA/B
CC
30.20 O
/50
Threshold 17, fault
V
CC
GATE DRIVERS
High state (pullup)
2.5
DH_ Gate-Driver On-
Resistance
BST_ - LX_ forced
to 5V
R
I
I
ON(DH)
Low state (pulldown)
2.0
2.0
0.7
High state (pullup)
DL_ Gate-Driver On-
Resistance
R
ON(DL)
Low state (pulldown)
______________________________________________________________________________________ 1.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ELECTRICAL CHARACTERISTICS (continued)
(Circuits of Figures 1 and 2. V = 10V, V
= V
= V
= 5V, EN = V , V
= 0V, V
= V
= V
= V
=
CSN_
IN
CC
DDA
DDB
CC GNDS_
FB_
CSP_AVE
CSP_
1V; [SerialVID = 1.00, FPWM MODE]; T = -4±°C to +1±.°C, unless otherwise noted. Specifications to -40NC and +105NC are guar-
A
anteed by design, not production tested.)
PARAMETER
SYMBOL
CONDITIONS
, BSTA2 to V , BSTB to V
DDB
MIN
TYP
MAX
UNITS
Internal BST_ Switch On-
Resistance
BSTA1 to V
DDA
DDA
R
20
I
BST
V
DD_
= 5V
DRVPWMA, DRVPWMB
Logic-High Voltage
V
DD_
- 0.4
I
= 3mA
V
V
SOURCE
DRVPWMA, DRVPWMB
Logic-Low Voltage
I
= 3mA
0.4
SINK
LOGIC AND I/O
Enable Input High Voltage
Enable Input Low Voltage
V
0.67
V
V
EN_IH
V
0.33
EN_IL
SERIALVID INTERFACE (per Intel SerialVID specification—see the Detailed Description)
SerialVID Input Low
Voltage (CLK, VDIO)
V
-0.1
+0.45
V
V
V
IL
SerialVID Input High
Voltage (CLK, VDIO)
V
TT
+
V
IH
0.65
1V
SerialVID Output Low Level
(VDIO, ALERT#)
V
OL
Open-drain pullup to V , R = 50I
0.36
13
TT PU
SerialVID Open-Drain
Output On-Resistance
(VDIO, ALERT#, VRHOT#)
R
I
= 30mA, T = 0°C to +105°C
4
I
ON
SINK
A
SerialVID Logic Slew Rate
(CLK, VDIO, ALERT#)
0.5
2.0
V/ns
SerialVID Input Capacitance
CLK Frequency
C
4
pF
PAD
f
13
-5
33.3
MHz
CLK
CLK Absolute Min/Max
Period
Specified as a percentage of f
+5
%
CLK
CLK High Time
CLK Low Time
Rise Time
t
Specified as a percentage of t
Specified as a percentage of t
period
period
45
45
%
%
HIGH
CLK
t
LOW
CLK
t
0.25
0.25
45
2.5
2.5
ns
ns
%
RISE
FALL
Fall Time
t
Duty Cycle
55
SerialVID Inactivity Timeout
t
0.14
0.40
Fs
RSTNA
Note 2: The equation for the target voltage V
is:
TARGET
V
= the slew-rate-controlled version of either V
DAC
TARGET
where V
= 0V for shutdown, V
= V
during startup, otherwise V = V (the V voltages for all possible
DAC ID ID
DAC
DAC
BOOT
VID codes are given in Table 3 and V
= the negative or positive offset to the output voltage based on the voltage
OFFSET
set from the offset register and the mode of operation (startup, shutdown, deeper sleep, or normal operation), as defined
elsewhere in this document.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit
times may be different due to MOSFET switching speeds.
16 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Typical Operating Characteristics
(T = +25NC, unless otherwise noted.)
A
REG A EFFICIENCY vs. LOAD CURRENT
IN PS0 STATE (SVID = 1V)
REG A EFFICIENCY vs. LOAD CURRENT
IN PS1 AND PS2 STATES (SVID = 0.65V)
REG A OUTPUT VOLTAGE vs. LOAD
CURRENT IN PS0 STATE (SVID = 1V)
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
1.050
1.000
0.950
0.900
0.850
0.800
7V
7V
7V
12V
12V
12V
20V
20V
PS2 STATE
PS1 STATE
20V
0.1
1
10
100
0.1
1
10
100
0
10 20 30 40 50 60 70 80 90 100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
REG A OUTPUT VOLTAGE
vs. LOAD CURRENT IN PS1 AND
PS2 STATES (SVID = 0.65V)
REG B EFFICIENCY vs. LOAD CURRENT
IN PS0 STATE (SVID = 1.25V)
(MAX17511/C/N/T ONLY)
REG B EFFICIENCY vs. LOAD CURRENT
IN PS1 AND PS2 STATES (SVID = 0.65V)
(MAX17511/C/N/T ONLY)
0.66
0.65
0.64
0.63
0.62
0.61
0.60
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
7V
7V
12V
12V
PS2 STATE
20V
PS1 STATE
20V
PS2 STATE
PS1 STATE
0
5
10
15
20
25
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
REG B OUTPUT VOLTAGE vs. LOAD
CURRENT IN PS0 STATE (SVID = 1.25V)
(MAX17511/C/N/T ONLY)
REG B OUTPUT VOLTAGE vs. LOAD CURRENT IN PS1
AND PS2 STATES (SVID = 0.65V)
(MAX17511/C/N/T ONLY)
0.66
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
PS2 STATE
PS1 STATE
0
5
10
LOAD CURRENT (A)
15
20
0
10
20
30
40
LOAD CURRENT (A)
______________________________________________________________________________________ 17
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Typical Operating Characteristics (continued)
(T = +25NC, unless otherwise noted.)
A
REG B SWITCHING FREQUENCY
vs. LOAD CURRENT (SVID = 0.65V)
(MAX17511/C/N/T ONLY)
REG A SWITCHING FREQUENCY
vs. LOAD CURRENT (SVID = 0.65V)
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
7V
7V
20V
12V
20V
12V
PS1 STATE
PS1 STATE
PS2 STATE
PS2 STATE
0
0
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
NON-ZERO V
STARTUP WAVEFORMS (V
, 1.05V)
BOOT
BOOT
(MAX17511/MAX17511T ONLY)
SHUTDOWN WAVEFORMS
MAX17411 toc11
MAX17411 toc12
V
V
, 5V/div
EN
V
, 5V/div
EN
0V
1V
, 500mV/div
OUTA
0V
V
, 1V/div
POKA
0V
0V
V
V
, 500mV/div
, 1V/div
OUTA
0V
0V
1V
POKA
V
V
, 500mV/div
, 1V/div
OUTB
V
OUTB
, 500mV/div
, 1V/div
0V
0V
POKB
0V
0V
V
V
POKB
V
, 1V/div
ALERT#
, 1V/div
ALERT#
0V
0V
200µs/div
THERMA = THERMB = GND
200µs/div
V
= 12V
V
= 12V
V
= 5A
V
= 5A
IN
IN
LOADA
LOADB
REG B LOAD-TRANSIENT RESPONSE
REG A LOAD-TRANSIENT RESPONSE
(MAX17511/C/N/T ONLY)
MAX17411 toc13
MAX17411 toc14
94A
28A
33A
10A
I
I
LOADA
LOADB
V
, 50mV/div
OUTB
V
OUTA
, 50mV/div
400µs/div
400µs/div
18 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Configurations
TOP VIEW
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
30 29 28 27 26 25 24 23 22 21
24
23
22
21
20
19
18
17
16
15
14
13
DRVPWMA 37
POKA
CLK
20
31
32
33
BSTA1
DRVPWMA
SR
38
39
40
41
42
43
44
45
46
47
48
SR
THERMA
THERMB
CSPAAVE
CSPA1
19 POKA
18 CLK
ALERT#
VDIO
THERMA
17 ALERT#
THERMB 34
AGND
16
15
14
VDIO
35
36
37
38
39
40
+
CSPAAVE
CSPA1
CSNA
MAX17511
MAX17511C
MAX17511N
MAX17511T
V
DDB
V
DDB
MAX17411
CSNA
DLB
DLB
CSPA2
PGNDB
DHB
13 DHB
12
CSPA2
CSPA3
EP = GND
CSPA3
LXB
11 BSTB
V
LXB
CC
V
CC
EP
EN
BSTB
+
1
2
3
4
5
6
7
8
9
10
TONA
DRVPWMB
2
3
4
5
6
7
8
9
10
1
11
12
TQFN
TQFN
Pin Description
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Switching Frequency Adjustment Input for Regulator B. An external resistor
between the input power source and TONB sets the switching period (per phase)
for regulator B according to the following equation:
1
—
TONB
t
= (R
+ 6.5kI) x 14.6pF
SWB
TONB
where f
= 1/t
is the nominal switching frequency.
SWB
SWB
TONB is high-impedance in shutdown. If REG B is disabled, connect TONB to GND or
V
.
CC
Switching Frequency Adjustment Input for Both Regulators. An external resistor
between the input power source and TON sets the switching period (per phase)
according to the following equations:
t
t
= (2 x R
= (2 x R
+ 6.5kI) x 17.9pF
+ 6.5kI) x 14.6pF
SWA
TON
—
2
TON
SWB
TON
where f
= 1/t
is the nominal switching frequency.
SW
SW
If REG B is disabled:
t
= (R
+ 6.5kI) x 17.9pF
SWA
TON
TON is high-impedance in shutdown.
______________________________________________________________________________________ 19
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Ground Remote-Sense Input for Regulator A. Connect GNDSA to the ground-sense
pin of the CPU located directly at the point of load. GNDSA internally connects to an
internal transconductance amplifier that adjusts the output voltage to compensate for
voltage drops between the controller analog ground and the load ground.
2
3
GNDSA
Feedback Remote-Sense Input and Voltage Positioning Transconductance (VPS)
Amplifier Output for Regulator A. Connect a resistor (R ) between FBA and the
FBA
positive side of the feedback remote sense (the CPU output remote sense (V
_
CC
)) to set the DC steady-state droop based on the voltage-positioning gain
SENSE
requirement.
R
FBA
= (N x R
)/(R
x G
)
PH
DROOP
SENSEA
MD
where R
is the desired voltage-positioning slope, G
= 600FS (typ), and
DROOP
MD
R
is the current-sense resistance with respect to the CSPAAVE to CSNA
SENSEA
3
4
FBA
current-sense inputs. See the CSP_AVE - CSN_ Inputs section. FBA is internally
connected to the input of an error comparator and an integrator that corrects for
output ripple, error comparator offsets, and the ground-sense offset of regulator A
as shown in Figure 5.
Shorting FBA directly to the output disables voltage positioning, but impacts the
stability requirements. Designs that disable voltage positioning require a higher
minimum output capacitance ESR to maintain stability (see the Output Capacitor
Selection section). FBA enters a high-impedance state in shutdown.
Open-Drain Output of the Thermal Comparators that monitor THERMA and
THERMB. These comparators are wire-ORed with output at VR_HOT#. This output
is required as backup to the temperature zone register in the event of an SVID bus
failure. The comparator responds to the temperature threshold voltage of 2.5V at
THERMA OR THERMB. This threshold is equivalent to the 100% threshold defined
in the Temperature-Zone register (12h).
4
5
VR_HOT#
AGND
5, 20
—
Analog Ground
2± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Feedback Remote-Sense Input and Voltage Positioning Transconductance (VPS)
Amplifier Output for Regulator B. Connect a resistor (R ) between FBB and the
FBB
positive side of the feedback remote sense to set the DC steady-state droop based
on the voltage-positioning gain requirement.
R
FBB
= (N x R
)/(R
x G
)
PH
DROOP
SENSEB
MD
where R
is the desired voltage-positioning slope, G
= 600FS (typ), and
DROOP
MD
R
is the current-sense resistance with respect to the CSPBAVE to CSNB
SENSEB
(MAX17411) or CSPB1 - CSNB (MAX17511/MAX17511C/MAX17511N/MAX17511T)
current-sense inputs. See the CSP_AVE – CSN_ Inputs section. FBB is internally
connected to the input of an error comparator and an integrator that corrects for
output ripple, error comparator offsets, and the ground-sense offset of regulator B
as shown in Figures 6 and 7.
6
6
FBB
Shorting FBB directly to the output disables voltage positioning, but impacts the
stability requirements. Designs that disable voltage positioning require a higher
minimum output capacitance ESR to maintain stability (see the Output Capacitor
Selection section).
FBB enters a high-impedance state in shutdown.
Ground Remote-Sense Input for Regulator B. Connect GNDSB to the ground-sense
pin of the GFX located directly at the point of load. GNDSB internally connects to an
internal transconductance amplifier that adjusts the output voltage to compensate
for voltage drops between the controller analog ground and the load ground.
7
8
7
GNDSB
Positive Current-Sense Average Input for Regulator B. Connect CSPBAVE to the
positive side of the differential output of external current-sense averaging network.
The averaging is achieved by using a resistive summation and current-sense
resistors, or by using a parallel DCR sense network with a single NTC thermistor for
thermal compensation (see Figure 9). The average current-sense input is used for
the load-line and current monitor.
—
CSPBAVE
Positive Current-Sense Input for Regulator B. Connect CSPB1 to the positive side of
the current-sense resistor or the DCR sense filter capacitor of regulator B as shown
in Figure 8.
9
8
9
CSPB1
CSNB
To completely disable Regulator B, Connect CSPB1 and CSPB2 to V
Also leave
CC.
BSTB, DHB, LXB, DLB, CSPBAVE, and CSNB unconnected. Address 1 is disabled
from the SVID bus.
Negative Current-Sense Input of Regulator B. Connect CSNB to the negative side
of the current-sense element as shown in Figure 8. An internal 20Idischarge
MOSFET between CSNB and ground is enabled under an input UVLO or shutdown
condition. A bypass capacitor between CSNB and GND in the range of 1nF to
0.1µF is recommended.
10
______________________________________________________________________________________ 21
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Positive Current-Sense Input for Second Phase of Regulator B. Connect CSPB2 to
the positive side of the current-sense element of the second phase of regulator B
11
—
CSPB2
as shown in Figure 8.Connect CSPB2 to V
disable the second phase of Regulator B.
and leave DRVPWMB unconnected to
CC
Open-Drain Power-Good Output for Regulator B. During soft-start and shutdown,
POKB stays low. At the end of soft-start, approximately 20Fs (typ) after FBB
reaches the output voltage set by the VID code, POKB becomes high-impedance
and remains high-impedance as long as FBB is in regulation.
POKB is blanked high-impedance when the slew-rate controller for regulator B is
active (VID transition occurs). In pulse-skipping mode, the upper POKB threshold is
blanked during downward transitions until the output voltage reaches its regulation
value.POKB is forced low in shutdown (EN = GND) and after any fault condition is
detected on either regulator.To obtain a logic signal, pull up POKB with an external
resistor connected to a positive logic supply of +5V and lower.
12
10
POKB
Direct-Drive PWM Output for Controlling the External Second Phase Driver for
13
14
15
—
11
12
DRVPWMB Regulator B. DRVPWMB is three-stated in shutdown when the controller detects an
output overvoltage fault condition on regulator B.
Boost Flying Capacitor Connection for High-Side Gate Voltage for the First Phase of
BSTB
LXB
Regulator B. Connect a ceramic capacitor between BSTB and LXB. See the Boost
Capacitors section.
Inductor Connection for the First Phase of Regulator B. LXB serves as the lower
supply rail for the DHB high-side gate driver. LXB is also used as an input to the
zero-crossing comparator for regulator B.
High-Side Gate-Driver Output for Regulator B. DHB output voltage swings from
16
17
13
—
DHB
V
to V . DHB is pulled low in shutdown.
LXB
BSTB
PGNDB
Power Ground of the Low-Side Driver of Regulator B
Low-Side Gate-Driver Output for the First Phase of Regulator B. DLB output voltage
swings from V
to GND. DLB is forced high when the controller detects an
DDB
18
14
DLB
output overvoltage fault condition on regulator B. DLB is forced low in shutdown
and in pulse-skipping mode when an inductor current zero crossing (LXB - GND) is
detected.
Driver-Supply Voltage Input for Regulator B. V
provides power for the low-side
DDB
driver of regulator B and is used to recharge the BSTB flying capacitor during the
on-time of DLB. Connect V to the 4.5V to 5.5V system supply voltage. Bypass
19
15
V
DDB
DDB
V
to power ground with a 1FF or greater ceramic capacitor.
DDB
21
22
23
16
17
18
VDIO
ALERT#
CLK
Serial VID Input/Output
Serial VID Alert Output. ALERT# is in the high state in shutdown.
Serial VID Clock Input
22 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Open-Drain Power-Good Output for Regulator A. During soft-start and shutdown,
POKA stays low. At the end of soft-start, approximately 20Fs (typ) after FBA
reaches the output voltage set by the VID code, POKA becomes high-impedance
and remains high-impedance as long as FBA is in regulation.
POKA is blanked high-impedance when the slew-rate controller for regulator A is
active (VID transition occurs). In pulse-skipping mode, the upper POKA threshold is
blanked during downward transitions until the output voltage reaches its regulation
value.
POKA is forced low in shutdown (EN = GND) and after any fault condition is
detected on either regulator.
To obtain a logic signal, pull up POKA with an external resistor connected to a
positive logic supply of +5V and lower.
24
25
19
POKA
Boost Flying Capacitor Connection for High-Side Gate Voltage for the First Phase
of Regulator A. Connect a ceramic capacitor between BSTA1 and LXA1. See the
Boost Capacitors section.
20
BSTA1
Inductor Connection for the First Phase of Regulator A. LXA1 serves as the lower
supply rail for the DHA1 high-side gate driver. LXA1 is also used as an input to the
zero-crossing comparator for regulator A.
26
27
21
22
LXA1
High-Side Gate-Driver Output for the First Phase of Regulator A. DHA1 output
DHA1
voltage swings from V
to V . DHA1 is pulled low in shutdown.
LXA1
BSTA1
Low-Side Gate-Driver Output for the First Phase of Regulator A. DLA1 output
voltage swings from V to V . DLA1 is forced high when the controller
DDA
GND
28
23
DLA1
detects an output overvoltage fault condition on regulator A. DLA1 is forced low
in shutdown and in pulse-skipping mode when an inductor current zero crossing
(LXA1 - GND) is detected.
Driver Supply Voltage Input for Regulator A. V
is the driver supply voltage
DDA
used for the DLA_ low-side drivers, and to recharge the BSTA_ flying capacitors
when the corresponding DLA_s are high. Connect V to the 4.5V to 5.5V system
29
30
24
—
V
DDA
DDA
supply voltage. Bypass V
capacitor.
to power ground with a 1FF or greater ceramic
DDA
PGNDA
DLA2
Power Ground of the Low-Side Drivers of Regulator A.
Low-Side Gate-Driver Output for the Second Phase of Regulator A. DLA2 Output
Voltage swings from V
to V . DLA2 is forced high when the controller
GND
DDA
31
25
detects an output overvoltage fault condition on regulator A. DLA2 is forced low
in shutdown and in pulse-skipping mode when an inductor current zero crossing
(LXA2 - GND) is detected.
High-Side Gate-Driver Output for the Second Phase of Regulator A. DHA2 Output
32
33
26
27
DHA2
LXA2
Voltage swings from V
to V . DHA2 is pulled low in shutdown.
LXA2
BSTA2
Inductor Connection for the Second Phase of Regulator A. LXA2 serves as the
lower supply rail for the DHA2 high-side gate driver. LXA2 is also used as an input
to the zero crossing comparator for Regulator A.
______________________________________________________________________________________ 23
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
FUNCTION
MAX17411
Boost Flying Capacitor Connection for High-Side Gate Voltage for the Second
Phase of Regulator A. Connect a ceramic capacitor between BSTA2 and LXA2. See
the Boost Capacitors section.
34
28
BSTA2
Maximum Current Threshold for Regulator A. This multivalued logic input sets
the valley current limit and compensates for inductor DCR. The maximum output
current value in register 21h is determined by the number of phases times the
maximum output current per phase set by IMAXA. If the voltage applied to IMAXA
is not within the defined threshold, the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T detect a fault and latch off. See Table 6 for more details.
35
29
IMAXA
IMAXB
Maximum Current Threshold for Regulator B. This multivalued logic input sets
the valley current limit and compensates for inductor DCR. The maximum output
current value in register 21h is determined by the number of phases times the
maximum output current per phase set by IMAXB. If the voltage applied to IMAXB
is not within the defined threshold, the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T detect a fault and latch off. See Table 6 for more details.
36
37
30
31
Direct-Drive PWM Output for Controlling the External Third Phase Driver for
DRVPWMA Regulator A. DRVPWMA is three-stated in shutdown when the controller detects an
output overvoltage fault condition on regulator A.
Fast Slew-Rate Adjustment for Both Regulators. The SR setting determines the
value stored in the Slew Rate Fast (24h) and Slew Rate Slow (25h) registers. The
input uses a four-level voltage sense to determine the slew rate setting upon power-
up and if NTC are used for the CSP_ signals. The SR values in the registers (24h
and 25h) change accordingly.
SR
38
32
SR THRESHOLD (V)
SR (min) (mV/Fs)
NTC
Yes
Yes
No
0
1.5
3
10
20
20
10
V
CC
No
Thermal-Sense Input for Regulator A. Connect THERMA to a resistor/thermistor-
divider network between V and THERMA to analog ground. The VR_HOT# is
CC
39
40
33
34
THERMA
THERMB
pulled low when the voltage at THERMA or THERMB drops below 0.5 x V
.
CC
If THERMA is held low at startup, REG A is forced in to non-zero V
an output voltage of 1.05V (MAX17411/MAX17511/MAX17511T).
mode with
BOOT
Thermal-Sense Input for Regulator B. Connect THERMB to a resistor/thermistor-
divider network between V and THERMB to analog ground. The VR_HOT# is
CC
pulled low when the voltage at THERMA or THERMB drops below 0.5 x V
.
CC
If THERMB is held low at startup, REG B is forced in to non-zero V
a output voltage of 1.05V (MAX17411/MAX17511/MAX17511T).
mode with
BOOT
Positive Current-Sense Average Input for Regulator A. Connect CSPAAVE to the
positive side of the differential output of external current-sense averaging network.
The averaging is achieved by using a resistive summation and current-sense
resistors, or by using a parallel DCR sense network with a single NTC thermistor for
thermal compensation (see Figures 1, 2, and 3). The average current-sense input is
used for the load-line and current monitor.
41
35
CSPAAVE
24 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Pin Description (continued)
PIN
MAX17.11/
MAX17.11C/
MAX17.11N/
MAX17.11T
NAME
CSPA1
CSNA
FUNCTION
MAX17411
Positive Current-Sense Input for the First Phase of Regulator A. Connect CSPA1 to
the positive side of the current-sense resistor or the DCR sense filter capacitor of
regulator A as shown in Figure 8.
To completely disable Regulator A, connect CSPA1, CSPA2, and CSPA3 to V
and leave BSTA1, DHA1, LXA1, DLA1, CSPAAVE, and CSNA unconnected.
Address 0 is also disabled from the SVID bus.
42
36
37
CC
Negative Current-Sense Input of Regulator A. Connect CSNA to the negative side
of the current-sense element as shown in Figure 8. An internal 20Idischarge
MOSFET between CSNA and ground is enabled under an input UVLO or shutdown
condition. A bypass capacitor between CSNA and GND in the range of 1nF to
0.1µF is recommended.
43
44
Positive Current-Sense Input for the Second Phase of Regulator A. Connect CSPA2
to the positive side of the current-sense resistor or the DCR sense filter capacitor of
regulator A as shown in Figure 8.
38
CSPA2
CSPA3
To completely disable Regulator A, connect CSPA1, CSPA2, and CSPA3 to V
CC.
Address 0 is also disabled from the SVID bus.
When Phase 2 is disabled, leave BSTA2, DHA2, LXA2, and DLA2 unconnected. If
phase 2 is disabled, phase 3 must be disabled as well.
Positive Current-Sense Input for Third Phase of Regulator A. Connect CSPA3 to
the positive side of the current-sense element of the third phase of regulator A as
shown in Figure 8.
45
46
39
40
Connect CSPA3 to V
and leave DRVPWMA unconnected to disable the third
CC
phase of Regulator A.
Analog Supply Voltage. Connect to a filtered 4.5V to 5.5V source. Bypass V
to
CC
V
CC
AGND with a 1FF or greater ceramic capacitor.
Controller Enable Input. Pull EN high or connect EN to V
for normal operation.
CC
Connect to ground to put the controller into its 30FA (max) shutdown state. During
soft-start, the controller slowly ramps the output voltage up to the boot voltage
with a 2.5mV/Fs (min) slew rate. During the transition from normal operation to
shutdown, the output is discharged through a 20Iinternal CSN_ FET.
47
48
1
EN
Toggling EN resets the fault latches. EN cannot withstand the battery voltage.
Switching Frequency Adjustment Input for Regulator A. An external resistor between
the input power source and TONA sets the switching period (per phase) for regulator
A according to the following equation:
—
TONA
t
= (R
+ 6.5kI) x 17.9pF
SWA
TONA
where f
= 1/t
is the nominal switching frequency.
SWA
SWA
TONA is high-impedance in shutdown. If REG A is disabled, connect TONA to GND.
PAD
(AGND)
EP
—
—
Exposed Pad. Connect EP to the ground plane with thermally enhanced vias.
PAD
(GND)
Exposed Pad. Connect EP to the ground plane with thermally enhanced vias. Power
ground pads and analog ground pads are all internally connected to the exposed pad.
EP
______________________________________________________________________________________ 2.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
10I
5V BIAS
2.2µF
29
V
46
DDA
V
CC
19
2.2µF
V
DDB
2.2µF
V
IN
R
TONA
48
27
25
26
28
30
7V TO 20V
INPUT
TONA
DHA
V
0.1µF
C
IN
IN
OPTIONAL
N
H1
0I
C
1µF
8
IN
BSTA1
0.22µF
LA1
5
LXA1
DLA1
VDD
LXA3
OUTPUTA
N
H3
DH
N
L1
D
L1
1
SENSE
BST
PGNDA
0.22µF
LA3
MAX17491
7
4
3
42
LX
DL
CSPA1
V
DD
6
2
LXA3
SENSE SENSE
LXA2
D
N
L3
L3
SKIP
37
45
GND
PWM
DRVPWMA
CSPA3
41
43
CSNA
CSPAAVE
CSNA
OUTPUTA
V
BIAS SUPPLY
TT
3.3V
V
IN
C
OUTA
MAX17411
44
10kI
10kI
75I
CSPA2
4
24
12
C
IN
32
34
VR_HOT#
VRA_READY
VRB_READY
VR_ENABLE
VR_HOT#
POKA
POKB
EN
DHA2
N
H2
0I
BSTA2
0.22µF
LA2
33
31
47
21
LXA2
DLA2
10I
10I
VDIO
N
L2
D
L2
SVID
INPUTS
1.05V LOGIC
LXA2
SENSE
23
22
CLK
ALERT#
CPU GND
SENSE
10I
R
R
THERMA
2
3
GNDSA
FBA
V
CC
R
NTCA
39
40
CPU V
CC
THERMA
THERMB
R
FBA
SENSE
10I
THERMB
R
NTCB
V
IN
R
TONB
1
7V TO 20V
INPUT
TONB
DHB
C13
0.1µF
C
IN
16
N
HB1
V
V
DD
IN
0I
OPTIONAL
14
15
18
17
BSTB
LXB
C
1µF
8
IN
LB1
0.22µF
OUTPUTB
5
C
OUTB
VDD
DLB
N
LB1
D
LB1
LXB2
SENSE
OUTPUTB
N
HB2
DH
1
BST
PGNDB
0.22µF
9
LB2
MAX17491
CSPB1
7
4
3
LX
V
DD
6
LXA2
SENSE
D
LB2
N
LB2
DL
SKIP
2
13
11
GND
PWM
DRVPWMB
CSPB2
10I
10I
8
CSPBAVE
CSNB
10
CSNB
38
35
SR
V
V
V
CC
AXG GND
SENSE
10I
7
6
GNDSB
FBB
IMAXA
CC
CC
AXG
SENSE
R
FBB
10I
36
17
IMAXB
PGNDB
POWER GROUND
ANALOG GROUND
5
AGND
AGND
20
EP
Figure 1. MAX17411 Typical CPU Core Application Circuit
26 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
5V BIAS
10I
2.2µF
24
V
DDA
40
15
V
V
CC
IN
V
DDB
7V TO 20V
INPUT
2.2µF
2.2µF
0.1µF
C
IN
22
20
DHA1
N
H1
0I
BSTA1
V
IN
LA1
OPTIONAL
0.22µF
21
23
LXA1
DLA1
C
1µF
8
IN
N
L1
D
L1
5
VDD
OUTPUTA
N
H3
DH
1
LXA3
SENSE
BST
36
CSPA1
0.22µF
LXA3
LXA2
SENSE SENSE
LA3
MAX17491
7
4
3
MAX17511
MAX17511C
MAX17511N
MAX17511T
LX
DL
V
6
DD
D
N
L3
L3
SKIP
2
31
39
GND
PWM
DRVPWMA
35
37
CSPAAVE
CSNA
CSPA3
OUTPUTA
CSNA
V
IN
V
IN
C
OUTA
R
TON
38
2
CSPA2
TON
C
IN
26
28
DHA2
N
H2
V
TT
BIAS SUPPLY
0I
3.3V
BSTA2
0.22µF
LA2
10kI
10kI
75I
27
25
LXA2
DLA2
5
19
10
10I
10I
LXA2
SENSE
VR_HOT#
VRA_READY
VRB_READY
VR_ENABLE
VR_HOT#
POKA
POKB
EN
N
L2
D
L2
CPU GND
SENSE
1
10I
10I
3
4
GNDSA
FBA
16
VDIO
SVID
INPUTS
1.05V LOGIC
CPU V
SENSE
CC
18
17
CLK
R
FBA
ALERT#
V
IN
V
CC
7V TO 20V
INPUT
R
R
THERMA
C13
0.1µF
R
NTCA
C
IN
13
11
DHB
N
HB1
33
THERMA
0I
BSTB
LB1
THERMB
0.22µF
OUTPUTB
12
14
LXB
DLB
R
NTCB
C
OUTB
N
LB1
D
LB1
34
32
THERMB
SR
V
CC
8
9
CSPB1
CSNB
10I
10I
29
30
IMAXA
IMAXB
V
V
CC
CC
AXG GND
SENSE
10I
10I
7
6
GNDSB
FBB
AXG
SENSE
R
FBB
POWER GROUND
EP
ANALOG GROUND
Figure 2. MAX17511 Typical Application Circuit (3-Phase + 1-Phase)
______________________________________________________________________________________ 27
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
R
VCC
10I
5V BIAS
C
C
24
VDDA
2.2µF
VDDB
2.2µF
V
DDA
V
CC
40
15
2
V
V
DDB
CC
V
C
VCC
1.0µF
IN
R
TON
7V TO 20V
INPUT
TON
DHA1
C
IN
31
39
C
0.1µF
INA1
22
20
DRVPWMA
CSPA3
N
HA1
CONNECT CSPA3 TO V
TO DISABLE REGA PHASE 3
CC
R
BSTA1
0I
V
CC
1
BSTA1
VR_ENABLE
EN
C
BSTA1
0.22µF
LA1
16
21
23
VDIO
LXA1
DLA1
OUTPUT A
OUTA
NTC
CSA
18
17
SVID INPUTS
(1.05V LOGIC)
C
CLK
N
LA1
R
LXA1
ALERT#
R
R
CSA2
CSA1
38
35
CSPA1
R20
10Ω
V
BIAS SUPPLY
3.3V
TT
CSPAAVE
R
CSA3
C
CSA
37
4
CSNA
FBA
R21
10Ω
R
R
R
C
POKA
10kI
POKB
RVHOT
75I
SNA
10nF
CPU V
SENSE
R10
10I
CC
10kI
R
FBA
5
19
10
VR_HOT#
VRA_READY
VRB_READY
VR_HOT#
POKA
C
FBA
4.7nF
R
GNDSA
10I
3
POKB
CPU GND
SENSE
GNDSA
C
GNDSA
4.7nF
V
IN
V
CC
7V TO 20V
INPUT
C
INB1
0.1µF
R
R
THERMB
THERMA
THERMA
C
INB
33
34
32
29
30
13
11
THERMA
THERMA
THERMB
SR
DHB
N
HB
R
BSTB
0I
THERMB
THERMB
SR
BSTB
C
BSTB
0.22µF
R
R
NTCB
NTCA
LB1
12
14
IMAXA
IMAXB
IMAXA
IMAXB
LXB
DLB
OUTPUT B
C
OUTB
N
LB
D
LB1
R
LXB
V
CC
R
CSB
R
R
R
SR1
IMAXA1
IMAXB1
C
CSB
MAX17511N
R23
10Ω
SR
IMAXA
IMAXB
8
9
CSPB1
CSNB
R24
10Ω
R
R
R
IMAXB2
C
SR2
IMAXA2
FFB
C
10nF
SNB
R11
10I
R
FBB
38
28
26
27
25
6
7
CONNECT CSPA2 TO V
TO DISABLE REGA PHASE 2
CC
FBB
V
CSPA2
BSTA2
DHA2
LXA2
CC
C
FBB
4.7nF
AXG V
CC
SENSE
AXG GND
SENSE
GNDSB
C
GNDSB
R
GNDSB
10I
POWER GROUND
ANALOG GROUND
4.7nF
DLA2
EP
Figure 3. MAX17511N Typical Application Circuit (1-Phase + 1-Phase)
28 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 10 Regulator A Typical Component Values (refer to the MAX17411/MAX17.11
Evaluation Kit)
VR12/IMVP-7
ATOM CPU, TDC = 303A/
VR12/IMVP-7 SV CPU
TDC = 36A/
VR12/IMVP-7 XE CPU
TDC = .2A/
COMPONENT
REF
QTY
I
= 6A
I
= .3A
I
= 94A
CCMAX
CCMAX
CCMAX
41±kHz OPERATION
(Figure 3)
32.kHz OPERATION
(Figures 1 and 2)
32.kHz OPERATION
(Figures 1 and 2)
V
IN
= 7V to 20V,
SVID = 1.1V
V
IN
= 7V to 20V,
SVID = 1.05V
V
IN
= 7V to 20V,
SVID = 0.9V
3
Conditions
Phases
—
—
—
—
1
2
Fairchild FDMS7680
Vishay (Siliconix)
SiR462DP
Fairchild FDMS7680
Vishay (Siliconix)
SiR462DP
High-Side FET
Low-Side FET
Schottky Diode
Sense Resistor
N
1 per phase
2 per phase
Fairchild FDMS7602S
H_
Fairchild FDMS7670AS
Vishay (Siliconix)
Sir158DP
Fairchild FDMS7670AS
Vishay (Siliconix)
Sir158DP
Fairchild FDMS76702S
1 per phase
N
D
L_
L_
None; most
applications do
not use Schottkys
None
None
None
None; most
applications use
DCR sensing
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
R
SENSE_
L_
0.36FH, 36A, 0.82mI
power inductor
Panasonic
0.36FH, 36A, 0.82mI
power inductor
Panasonic
1.5FH, 8A, 4.5mIpower
inductor
TOKO FDVE0630-1R5M
Inductor
1 per phase
ETQP4LR36AFC
ETQP4LR36AFC
4O470FF, 2V, 4.5mIlow- 4O470FF, 2V, 4.5mIlow-
ESR polymer capacitor
(D case)
ESR polymer capacitor
(D case)
1O470FF, 2V, 4.5mI
low-ESR
Output
Capacitors
Panasonic
Panasonic
C
OUT_
Total
Panasonic
EEFSX0D471E4
EEFSX0D471E4 or
Sanyo 2TPW470M4R
+18 x 22FF + 10 x 10FF
ceramic
EEFSX0D471E4 or
Sanyo 2TPW470M4R
+18 x 22FF + 10 x 10FF
ceramic
10FF, 25V, X5R ceramic
capacitors
10FF, 25V, X5R ceramic
capacitors
Input
Capacitors
10FF, 25V, X5R ceramic
C
Total
1
IN_
capacitor
3 per phase
3 per phase
180kI, 1% (300kHz) for
the MAX17411, 82.5kI,
1% (325kHz) for the
(MAX17511/MAX17511C/ (MAX17511/MAX17511C/
MAX17511N/MAX17511T) MAX17511N/MAX17511T)
180kI, 1% (300kHz) for
the MAX17411, 82.5kI,
1% (325kHz) for the
64.9kI, 1% (410kHz)
for the (MAX17511/
MAX17511C/
Switching
Frequency
R
TON
—
MAX17511N/MAX17511T)
V
SR
= 5V
V
= 5V
V
SR
= 5V
SR
Slew Rate
—
1
10mV/Fs
10mV/Fs
10mV/Fs
FB_ Droop
Setting
2.15kI, 1%
(droop = -5.9mV/A)
8.66kI, 1%
(droop = -1.9mV/A)
13kI, 1%
(droop = -1.9mV/A)
R
FBA
______________________________________________________________________________________ 29
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 10 Regulator A Typical Component Values (refer to the MAX17411/MAX17.11
Evaluation Kit) (continued)
VR12/IMVP-7
ATOM CPU, TDC = 303A/
VR12/IMVP-7 SV CPU
TDC = 36A/
VR12/IMVP-7 XE CPU
TDC = .2A/
COMPONENT
REF
QTY
I
= 6A
I
= .3A
I
= 94A
CCMAX
CCMAX
CCMAX
41±kHz OPERATION
(Figure 3)
32.kHz OPERATION
(Figures 1 and 2)
32.kHz OPERATION
(Figures 1 and 2)
5.62kI, 1% + 100kI,
5% NTC thermistor
B = 4250 (0603)
5.62kI, 1% +100kI,
5% NTC thermistor
B = 4250 (0603),
Murata
5.62kI, 1% + 100kI,
5% NTC thermistor
B = 4250 (0603)
THERMA
Setting
R
,
Murata
Murata
THERMA
—
R
NTC
NCP18WF104J03RB
TDK NTCG163JF104J
(0402) or
NCP18WF104J03RB,
TDK NTCG163JF104J
(0402) or Panasonic ERT-
J1VR104J
NCP18WF104J03RB
TDK NTCG163JF104J
(0402) or
Panasonic ERT-J1VR104J
Panasonic ERT-J1VR104J
Table 20 Regulator B Typical Component Values (refer to the MAX17411/MAX17.11
Evaluation Kit)
VR12/IMVP-7 GT; TDC
= 104A/ I = 20.A;
.±±kHz OPERATION
(MAX17.11/MAX17.11C/ (MAX17.11/MAX17.11C/
MAX17.11N/MAX17.11T) MAX17.11N/MAX17.11T)
(Figure 3)
VR12/IMVP-7 GT; TDC =
210.A/; I = 33A;
4±±kHz OPERATION
VR12/IMVP-7 GT;
TDC = 4±A/;
CCMAX
CCMAX
COMPONENT
REF
QTY
I
= 66A;
CCMAX
37±kHz OPERATION
(MAX17411) (Figure 1)
(Figure 2)
V
= 7V to 20V
V
= 7V to 20V
V
= 7V to 20V
IN
IN
IN
Conditions
Phases
—
—
—
—
SVID = 1.23V
SVID = 1.23V
SVID = 1.23V
1
1
2
Fairchild FDMS7680
Vishay (Siliconix)
SiR462DP
Fairchild FDMS7680
Vishay (Siliconix)
SiR462DP
High-Side FET
N
H_
1 per phase
Fairchild FDMC8200
Fairchild FDMS7670AS
Vishay (Siliconix)
Sir158DP
Fairchild FDMS7670AS
Vishay (Siliconix) Sir158DP
2 per phase
Fairchild FDMC8200
1 per phase
Low-Side FET
N
—
L_
L_
2 per phase
None; most
applications
do not use
Schottkys
Schottky
Diode
3A, 40V Schottky diode
Diodes Inc. B340LB-13-F
3A, 40V Schottky diode
Diodes Inc B340LB-13-F
3A, 40V Schottky diode
Diodes Inc B340LB-13-F
D
None; most
applications
use DCR
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
0.75mI, 1%, 1W
Cyntec Co. RL1632L4-
0R75m-FNH
Sense Resistor
Inductor
R
SENSE_
L_
sensing
0.36FH, 36A, 0.82mI
power inductor
Panasonic
0.36µH, 36A, 0.82mW
power inductor
Panasonic
3.3µH, 5.5A, 29.6mW
TOKO: FDV0530-3R3M
1 per phase
ETQP4LR36AFC
ETQP4LR36AFC
3± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 20 Regulator B Typical Component Values (refer to the MAX17411/MAX17.11
Evaluation Kit) (continued)
VR12/IMVP-7 GT; TDC =
104A/I = 20.A;
.±±kHz OPERATION
(MAX17.11/MAX17.11C/ (MAX17.11/MAX17.11C/
MAX17.11N/MAX17.11T) MAX17.11N/MAX17.11T)
(Figure 3)
VR12/IMVP-7 GT; TDC =
210.A; I = 33A;
4±±kHz OPERATION
VR12/IMVP-7 GT
TDC = 4±A/I
CCMAX
CCMAX
=
CCMAX
COMPONENT
REF
QTY
66A
37±kHz OPERATION
(MAX17411) (Figure 1)
(Figure 2)
3 × 470µF, 2V, 4.5mW
low-ESR polymer
capacitor (D case)
Panasonic
EEFSX0D471E4 or
NEC/TOKIN
2 O470µF, 2V, 4.5mW low-
ESR polymer capacitor
(D case) Panasonic
EEFSX0D471E4 or NEC/
TOKIN PSGV0E477M4.5
+14 x 22µF ceramic
Output
Capacitors
C
Total
Total
1 × 100µF + 47µF ceramic
OUT_
PSGV0E477M4.5
+14 x 22µF ceramic
3 × 10µF, 25V, X5R
ceramic capacitors per
phase
Input
Capacitors
4 O10FF, 25V, X5R
ceramic capacitors
C
10µF, 25V, X5R ceramic
IN_
Switching
Frequency
R
TON
1
64.9kI, 1% (500kHz)
82.5kI, 1% (400kHz)
180kI, 1% (370kHz)
Slew Rate
—
—
V
= 5V, 10mV/Fs
V
SR
= 5V, 10mV/Fs
V
SR
= 5V, 10mV/Fs
SR
100I, C
(no DC droop, AC couple
signal)
= 0.1µF
FFB
FB_ Droop
Setting
8.66kI,
1% (droop = -3.9mV/A)
17.4kI,
1% (droop = 3.9mV/A)
R
1
FBB
5.62kI, 1% + 100kW,
5% NTC thermistor B
= 4250 (0603) Murata
NCP18WF104J03RB
TDK NTCG163JF104J
(0402) or
5.62kI, 1% +100kI,
5% NTC thermistor B
= 4250 (0603) Murata
NCP18WF104J03RB
TDK NTCG163JF104J
(0402) or
5.62kI, 1% + 100kW,
5% NTC thermistor B
= 4250 (0603) Murata
NCP18WF104J03RB
TDK NTCG163JF104J
(0402) or
THERMB
Setting
R
,
THERMB
—
R
NTC
Panasonic ERT-
Panasonic ERT-J1VR104J
Panasonic ERT-J1VR104J
J1VR104J
______________________________________________________________________________________ 31
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ANALOG BLOCKS
DRVPWMA
EN
POKA
PHASE 2
DACS AND
SETVID
CIRCUITS A
REG A
3-PHASE
CONSTANT
ON-TIME
CONTROLLER
STATUS A
PHASE 1
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
FBA
CSPA_
CSNA
CURRENT
MONITOR A
CSPAAVE
DIGITAL BLOCKS
COMMON-
BIAS
CIRCUITRY
THERMA
REGISTER
FILE A
THERM
AMPA
ALERT#
CLK
MUX
SVID
INTERFACE
THERMB
THERM
AMPB
3-BIT ADC
VDIO
REGISTER
FILE B
CSPB2*
CSPB1
CURRENT
MONITOR B
CSNB
CSPBAVE*
VR_HOT#
STATUS B
FBB
DRVPWMB*
REG B
1-/2-PHASE
CONSTANT
ON-TIME
DACs AND
SETVID
CIRCUITS B
PHASE 1
CONTROLLER
POKB
*MAX17411 ONLY
Figure 4. MAX17411/MAX17511/MAX17511C/MAX17511N/MAX17511T High-Level Block Diagram
32 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
ILIMA
IMAXA
DRVPWMA
4-BIT DAC
PHASE-3 CONTROL
CSNA
Q
TRIG
CSPA3
CSNA
CSPA3
CSPA1
G
m(CCI2)
PHASE#3
ONE-SHOT
ON-TIME
ILIMA
ILIMA
CSNA
G
m(CCI)
BSTA2
DHA2
LXA2
CSPA2
CSNA
PHASE-2 DRIVERS
DLA2
PGND
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
TRIG2
CSPA1
CSNA
CSNA
Q
TRIG
PHASE#2
ONE-SHOT
ON-TIME
ILIMA
CSPA2
CSPA1
3-PHASE
G
m(CCI1)
MINIMUM
OFF-TIME
TRIG3
V
CC
CSNA
G
m(CCI)
Q
TRIG
REF (2.0V)
ONE-SHOT
AGND
SR
FBA
PHASE#1
ONE-SHOT
ON-TIME
DAC
TON (TONA)*
SVID
TARGET
DAC
I(SRA)
TRIG1
Q
TRIG
BSTA1
EN
R
S
MAIN PHASE DRIVERS
Q
DHA1
LXA1
FAULT
TARGET
3
2 1
S
R
PGND
LXA
PHASE
SELECT
TRIG
Q
REF
1mV
SKIP
CCVA
G
m(CCV)
V
DDA
FBA
DLA1
CSPAAVE
CSNA
PGND
POKA
SLOPE
Gm(FB)
FBA
FAULT
REGA FAULT BLOCK
GNDSA
TARGET
N
BLANK
PHASE CONTROL
SVID
PSI(3)
TO ADC
CSPAAVE - CSNA
CURRENT MONITOR
*() FOR THE MAX17411 ONLY.
Figure 5. Regulator A Block Diagram with SVID Functions
______________________________________________________________________________________ 33
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
CSPB2
CSNB
DRVPWMB
PHASE-2
CONTROL
ILIMB
MAX17411
2-PHASE
Q
TRIG
CSPB1
PHASE#2
CSNB
ONE-SHOT
CSPB1
ILIMB
ON-TIME
TONB TRIG2
TRIG2
MINIMUM
OFF-TIME
CSNB
G
m(CCI)
TRIG
CSPB2
Q
V
CC
ONE-SHOT
CSNB
FBB
REF (2.0V)
G
m(CCI)
PHASE#1
ONE-SHOT
TONB
SR
ON-TIME
DAC
Q
SVID
TARGET
TRIG1
TRIG
I(SRB)
DAC
BSTB
EN
MAIN PHASE
DRIVERS
R
S
Q
DHB
LXB
FAULT
TARGET
2
1
S
R
PHASE
SELECT
TRIG
Q
REF
PGND
LXB
CCVB
1mV
G
m(CCV)
SKIP
V
DDB
DLB
FBB
PGND
FBB
FAULT
CSPBAVE
CSNB
ILIMB
IMAXB
4-BIT
DAC
SLOPE
N
REGB FAULT
BLOCK
POKB
G
m(FB)
PHASE
CONTROL
TARGET
SKIP
GNDSB
BLANK
PHASE
CONTROL
CURRENT
MONITOR
TO ADC
CSPBAVE - CSNB
SVID
PSI (2)
Figure 6. MAX17411 Regulator B Block Diagram with SVID Function
34 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
CSPB1
CSNB
MINIMUM
OFF-TIME
ILIMB
Q
TRIG
ILIMB
IMAXB
4-BIT DAC
ONE-SHOT
V
CC
FBB
TON
REF (2.0V)
PHASE#1
ON-TIME
GND
SR
EN
ONE-SHOT
TRIG
DAC 2
SVID
TARGET
TRIG1
Q
BSTB
DAC
I(SRB)
R
S
MAIN PHASE DRIVERS
Q
DHB
LXB
S
R
FAULT
REF
PGND
LXB
Q
TARGET
1mV
SKIP
CCVB
V
SKIP
DDB
G
m(CCV)
DLB
FBB
CSPB1
CSNB
SLOPE
POKB
FBB
TARGET
FAULT
REGB FAULT BLOCK
G
m(FB)
GNDSB
MAX17511
MAX17511C
MAX17511N
MAX17511T
TO ADC
CSPB1-CSNB
CURRENT MONITOR
Figure 7. MAX17511/MAX17511C/MAX17511N/MAX17511T Regulator B Block Diagram with SVID Function
______________________________________________________________________________________ 3.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Free-Running Constant On-Time PWM
Detailed Description
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figures 5, 6, and 7). The con-
trol algorithm is simple: the high-side switch on-time is
determined solely by a one-shot whose period is inverse-
ly proportional to input voltage, and directly proportional
to output voltage or the difference between the main and
secondary inductor currents (see the On-Time One-Shot
section). Another one-shot sets a minimum off-time. The
on-time one-shot triggers when the error comparator
goes low, the inductor current of the selected phase is
below the valley current-limit threshold, and the minimum
off-time one-shot times out. Regulator A maintains 120N
out-of-phase operation by alternately triggering the three
phases after the error comparator drops below the out-
put voltage set point. Two-phase controller (regulator B,
MAX17411) maintains 180N out-of-phase operation by
alternately triggering the two phases after the error com-
parator drops below the output-voltage set point.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T are dual-output, step-down, constant on-
time controllers for VR12/IMVP-7 CPU core supplies.
The controllers consist of two high-current SMPSs for the
CPU and GFX cores. The CPU regulator (regulator A,
ADDR0) is a three-phase constant on-time architecture.
The optional third phase is configured with an external
MAX17491 driver. The second GFX regulator (regulator
B, ADDR1) is a single-phase (MAX17511/MAX17511C/
MAX17511N/MAX17511T) or two-phase (MAX17411)
constant on-time architecture. The three-phase CPU
core regulator runs 120° out-of-phase for true interleaved
operation, minimizing input capacitance. Figure 4 is the
high-level block diagram. Table 1 lists typical component
values for regulator A, and Table 2 lists typical compo-
nent values for regulator B.
CPU and GFX outputs are controlled independently by
writing the appropriate data into a function-mapped
register file. Output voltages are dynamically changed
through a 3-wire serial VID interface (3-wire SVID:
clock, data, ALERT#), allowing the switching regulators
to be individually programmed to different voltages.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T generate well-controlled technologies
between VID codes and automatically soft-start for non-
Triple 120° Out-Of-Phase Operation
The three phases in the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T operate 120°
out-of-phase to minimize input and output filtering
requirements, reduce electromagnetic interference
(EMI), and improve efficiency. This effectively low-
ers component count—reducing cost, board space,
and component power requirements—making these
devices ideal for high-power, cost-sensitive applications.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T share the current between three phases that
operate 120N out-of-phase, so the high-side MOSFETs
never turn on simultaneously during normal opera-
tion. The instantaneous input current of each phase is
effectively reduced, resulting in reduced input voltage
ripple, ESR power loss, and RMS ripple current (see the
Input Capacitor Selection section). Therefore, the same
performance can be achieved with fewer or less-
expensive input capacitors.
zero V
operation. The SVID interface also allows
BOOT
each regulator to be individually set into a low-power
pulse-skipping state. Individual phases can be shut
down based on the processors’ operating conditions (1-
or 3-phase operation is possible under software control).
Transient-phase overlap mode improves the current
delivery response time of regulator A, which reduces the
total output capacitance. Both regulators include active
overshoot suppression to reduce the required output
decoupling capacitance.
The devices include output overvoltage (MAX17411/
MAX17511/MAX17511C/MAX17511N), output under-
voltage, and thermal protections. When any of these
protection features detects a fault, the controller shuts
down both channels. True differential current sensing
improves load-line and current-limit accuracy. Both
regulators A and B feature programmable switching
frequency, allowing 200kHz to 600kHz per phase
operation. VR12/IMVP-7 requires temperature measure-
ments for the individual outputs. For this reason, an ADC
with MUX is included to digitize the analog variables of
interest. A thermistor-based temperature sensor pro-
vides a programmable thermal-fault output (VR_HOT#).
Dual 180° Out-Of-Phase Operation
(MAX17411 Only)
The two phases in the MAX17411 operate 180° out-of-
phase to minimize input and output filtering requirements,
reduce EMI, and improve efficiency. This effectively lowers
component count—reducing cost, board space, and com-
ponent power requirements—making this device ideal for
high-power, cost-sensitive applications. The MAX17411
shares the current between two phases that operate 180°
36 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
out-of-phase, so the high-side MOSFETs never turn on
TON Open-Circuit Protection
The TON inputs include open-circuit protection to avoid
long, uncontrolled on-times that could result in an overvolt-
age condition on the output. The MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T detect an open-
circuit fault if the TON current drops below 10FA for any
simultaneously during normal operation. The instanta-
neous input current of each phase is effectively reduced,
resulting in reduced input-voltage ripple, ESR power
loss, and RMS ripple current (see the Input Capacitor
Selection section). Therefore, the same performance can
be achieved with fewer or less-expensive input capacitors.
reason—the TON resistor (R ) is unpopulated, a high
TON
resistancevalueisused, theinputvoltageislow, etc. Under
these conditions, the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T stop switching (DH_ and DL_
pulledlow)andimmediatelysetthefaultlatchforbothregu-
+5V Bias Supply (V , V
, and V
)
CC
DDA
DDB
The Quick-PWM controllers require an external 5V bias
supply in addition to the battery. Typically, this +5V bias
supply is the notebook’s 95% efficient 5V system supply.
lator A and regulator B. Toggle EN or cycle the V
power
CC
The +5V bias supply must provide V
(PWM control-
CC
supply below 0.5V to clear the fault latch and reactivate
the controller.
ler) and V
and V
(gate-drive power). V
and
DDA
DDB
DDA
V
can be shorted together on the PCB. The maxi-
DDB
mum current drawn from the 5V bias supply is:
= I + f (Q + Q ) | +
G(HIGH) REGA
On-Time One-Shot
Regulator A and regulator B contain fast, low-jitter,
adjustable one-shots that set the respective high-side
MOSFETs on-time. The one-shot timing is shared among
the operating phases. The one-shot for the main phase
varies the on-time in response to the input and feedback
voltages. The main high-side switch on-time is inversely
I
BIAS
CC
SW G(LOW)
f
(Q
+ Q
) |
SW G(LOW)
G(HIGH) REGB
where I
is provided in the Electrical Characteristics
CC
table, f
and Q
is the switching frequency, and Q
SW
G(LOW)
are the MOSFET data sheet’s total
G(HIGH)
gate-charge specification limits at V = 5V. V , V
,
GS
CC DDA
proportional to the input voltage as measured by the V ,
IN
and V
can be connected together if the input power
DDB
and proportional to the feedback voltage (V
):
FB_
source is a fixed 4.5V to 5.5V supply. If the 5V bias sup-
ply is powered up prior to the battery supply, the enable
signal (EN going from low to high) must be delayed until
the battery voltage is present to ensure startup.
t
(V
+ 0.075V)
SW FB_
t
=
ON
V
IN
The one-shot for the second phase and third phase
varies the on-time in response to the input voltage
and the difference between the main and the other
inductor currents. Two identical transconductance
amplifiers integrate the difference between the master
and each slave’s current-sense signals. The respective
Switching Frequency (TON)
For the MAX17411, connect two resistors (R
and
TONA
R
) between TONA and V and TONB and V to
TONB
IN IN
set the switching period t
= 1/f , per phase:
SW
SW_
t
= C
x (R
+ 6.5kI)
SW_
TON_
TON_
error signals are used to correct the t
of the high-side
ON
where C
= 17.9pF for regulator A and C
=
TON_
TON_
MOSFETs for the 2nd and 3rd phase.
14.6pF for regulator B.
For the MAX17511/MAX17511C/MAX17511N/MAX17511T,
connect a resistor (R ) between TON and V to set the
During phase overlap, t is calculated based on the
ON
on-time requirements of the first phase, but reduced
by 33% when operating with three phases. For a three-
phase regulator, the third phase cannot be enabled
until the other two phases have completed their on-
time and the minimum off-times have expired. As
TON
IN
switching period t
= 1/f , per phase for both regulator
SW
SW
A and regulator B:
t
t
= (2 x R
= (2 x R
+ 6.5kI) x 17.9pF
+ 6.5kI) x 14.6pF
SWA
SWB
TON
such, the minimum period is limited by 3 x (t
+
ON
TON
t
). The maximum t
OFF(MIN)
is dependent on the
ON
If the MAX17511 regulator B is disabled, then
= (R + 6.5kI) x 17.9pF
minimum input and maximum output voltage:
= N × (t + t )
OFF(MIN)
t
SWA
TON
t
SW(MIN)
PH
ON(MAX)
High-frequency (600kHz) operation optimizes the
application for the smallest component size, trading off
efficiency due to higher switching losses. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
where:
V
FB_(MAX)
t
=
× t
SW(MIN)
ON(MAX)
V
IN(MIN)
and N = total number of active phases.
PH
______________________________________________________________________________________ 37
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
So:
where V
is the sum of the parasitic voltage drops
DIS
in the inductor discharge and charge paths, includ-
ing MOSFET, inductor, and PCB resistances; V is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
t
OFF(MIN)
CHG
t
=
SW(MIN)
1/ N − V
/V
PH
FB_(MAX) IN(MIN)
Hence, for a 7V input and 1.1V output, the maximum
switching frequency is 700kHz. Running at this limit
is not desirable since there is no room to allow the
regulator to make adjustments without triggering phase
overlap. For a three-phase, high-current application with
minimum 8V input, the practical switching frequency is
300kHz. On-times translate only roughly to switching
frequencies. The on-times guaranteed in the Electrical
Characteristics table are influenced by parasitics in the
conduction paths and propagation delays. For loads
above the critical conduction point, where the dead-time
effect (LX flying high and conducting through the high-
side FET body diode) is no longer a factor, the actual
switching frequency (per phase) is:
PCB resistances, and t
above.
is the on-time as determined
ON
Current Sense
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T sense the output current of each phase,
allowing the use of current-sense resistors or inductor
DCR as the current-sense element. Low-offset amplifiers
are used for current balance, voltage-positioning gain,
and current limit. Using the DC resistance (R
) of
DCR
the output inductor allows higher efficiency. The initial
tolerance and temperature coefficient of the inductor’s
DCR must be accounted for in the output-voltage droop-
error budget and current monitor. This current-sense
method uses an RC filter network to extract the current
information from the output inductor (see Figure 8).
(V
+ V
)
OUT
DIS
f
=
SW
t
(V + V
+ V
)
ON IN
DIS
CHG
INPUT (V
)
IN
N
C
IN
H
DH_
R2
INDUCTOR
R
R
=
R
CS
DCR
+
R1 + R2
R
DCR
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
L
L
1
1
LX_
DL_
=
DCR
C
R1
R2
EQ
N
L
C
OUT
D
L
FOR THERMAL COMPENSATION:
R1
R2
R SHOULD CONSIST OF AN NTC RESISTOR
IN SERIES WITH A STANDARD THIN-FILM RESISTOR
2
PGND
CSP_
CSN_
C
EQ
A) LOSSLESS INDUCTOR SENSING
INPUT (V
)
IN
N
C
IN
H
DH_
SENSE RESISTOR
MAX17411
R
L
L
SENSE
ESL
L
ESL
C
R
=
MAX17511
EQ EQ
LX_
R
SENSE
MAX17511C
N
L
C
OUT
MAX17511N
DL_
D
L
MAX17511T
C
EQ
R
EQ
PGND
CSP_
CSN_
B) OUTPUT SERIES RESISTOR SENSING
Figure 6. Current-Sense Methods
38 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
The RC network should match the time constant of the
where R
and V
is the equivalent DCR sense resistance
is the current-balance offset specification
SENSE
OS(IBAL)
inductor (L/R ):
DCR
in the Electrical Characteristics table. The worst-case cur-
rent mismatch occurs immediately after a load transient
due to inductor value mismatches, resulting in different di/
dt for the two phases. The time it takes for the current-bal-
ance loop to correct the transient imbalance depends on
the mismatch between the inductor values and switching
frequency.
R2
R1+ R2
R
=
R
CS
DCR
and:
L
1
1
R
=
+
DCR
C
R1 R2
EQ
where R
and R
is the required current-sense resistance,
is the inductor’s series DC resistance. Use
the typical inductance and R
the inductor manufacturer. To minimize the current-
sense error due to the bias current of the current-sense
), choose R1R2 to be less
than 2kI and use the above equation to determine the
sense capacitance (C ). Choose capacitors with 5%
tolerance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the Voltage Positioning sec-
tion for detailed information.
CS
DCR
Current Limit
The current-limit circuit employs a “valley” current-sens-
ing algorithm that senses the voltage across the current-
sense resistors or inductor DCR at the current-sense
inputs (CSP_ to CSN_). If the current-sense signal of
the selected phase is above the current-limit threshold,
the PWM controller does not initiate a new cycle until
the inductor current of the selected phase drops below
the valley current-limit threshold. When any one phase
exceeds the current limit, all phases are effectively
current limited since the interleaved controller does
not initiate a cycle with the next phase. Since only the
valley current is actively limited, the actual peak current
is greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are functions of the current-sense resistance, inductor
value, and battery voltage. The positive valley current-
limit threshold voltage at CSP_ to CSN_ is preset using
the IMAX_ and SR multivalue logic inputs.
values provided by
DCR
inputs (I
and I
CSP_
CSN_
EQ
When using a current-sense resistor for accurate output-
voltage positioning, the circuit requires a differential RC
filter to eliminate the AC voltage step caused by the
equivalent series inductance (L
resistor (see Figure 8). The ESL-induced voltage step
might affect the average current-sense voltage. The time
constant of the RC filter should match the L
time constant formed by the parasitic inductance of the
current-sense resistor:
) of the current-sense
ESL
/R
ESL SENSE
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-
sense signals seen by the current-sense inputs (CSP_,
CSN_).
L
ESL
= C
R
EQ EQ
R
SENSE
where L
is the equivalent series inductance of the
ESL
current-sense resistor, R
is the current-sense
SENSE
Feedback Adjustment Amplifier
resistance value, and C
and R
are the time-con-
EQ
EQ
Voltage-Positioning Amplifier (Steady-State Droop)
Regulators A and B include transconductance ampli-
fiers for adding gain to the voltage-positioning sense
path. The input of the amplifier is generated by summing
the current-sense voltage inputs, which differentially
sense the voltage across either current-sense resistors
or the inductor’s DCR. The output of the droop ampli-
stant matching components.
Current Balance
Regulator A integrates the difference between the current-
sense voltages and adjusts the on-time of the second and
third phases to maintain current balance. The current bal-
ance relies on the accuracy of the current-sense signals
across the current-sense resistor or inductor DCR. With
active current balancing, the current mismatch is deter-
mined by the current-sense resistor or inductor DCR values
and the offset voltage of the transconductance amplifiers:
fier, G
connects directly to the voltage-positioned
m(FB_)
feedback input (FB_) of the regulator, so the resistance
between FB_ and the output-voltage sense point deter-
mines the voltage-positioning gain:
V
= V
– (R
I
)
OUT
TARGET
FB O FB_
V
OS(IBAL)
I
= I
−I
=
where the target voltage (V
Nominal Output Voltage Selection section, and the
) is defined in the
OS(IBAL)
LMAIN LSEC
TARGET
R
SENSE
______________________________________________________________________________________ 39
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
G
output current I
. I is determined by the
FB_ FB_
The DCR circuit network is the divider of the actual induc-
tor DCR. Hence the effective resistance at CSPAAVE -
CSNA will be lower than the DCR resistance.
m(FB_)
sum of the current-sense voltages:
I
= G × V
FB_
m(FB)_
CSX
Since there are more unknowns than the equations in
the current-sense network, the component values must
be calculated by iteration. A spreadsheet helps as the
variation over temperature should also be checked. The
following steps provide some initial values to work with.
where V
= V
- V
or V
= V
-
CSX
CSP_AVE
CSN_
CSX
CSPB1
V
(for regulator B of the MAX17511/MAX17511C/
CSNB
MAX17511N/MAX17511T) is the differential current-
sense voltage, and G is 600Fs (typ) as defined
in the Electrical Characteristics table. The controller
uses the V or the V input to get the aver-
m(FB_)
1) Use typical L and DCR values in the calculations.
CSP_AVG
CSPB1
2) For inductors with low DCR less than 1mI, add
about 0.015mIto the DCR value to compensate for
parasitic resistances due to layout and assembly.
age inductor current from the positive current-sense
averaging network. Since the feedback voltage (FB_) is
regulated, the output voltage changes in response to the
feedback current I
defined by the characteristics of R
to create a load line with accuracy
FB_
3) Choose C
first since capacitor choices are
CSPAAVE
and G
.
FB_
m(FB_)
limited. A good value to start with is 0.22FF. It is
good to add a small capacitor position in parallel to
When the inductor’s DCR is used as the current-sense
element (R = R ), the current-sense inputs
C
to fine tune the total capacitance.
CSPAAVE
SENSE
DCR
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
4) Larger C
Smaller R
results in smaller R
values are required to reduce the error
values.
LX_
CSPAAVE
LX_
due to pin leakages. As a rule, the R
parallel should be about 2kI or less.
resistors in
LX_
CSP_AVE - CSN_ Inputs
The current-sense information across all phases are
averaged together at the CSP_AVE - CSN_ or the
CSPB1 - CSNB (MAX17511/MAX17511C/MAX17511N/
MAX17511T) inputs. This signal contains both the
DC average current information and the AC ripple
information. The MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T use the DC information to gen-
erate the load line, and the AC information for stability.
5) Select R
start with a value between 1kI
CSPAAVE2
and 4kI.
6) Select R . Large values like 20kIto 100kI
CSPAAVE1
are recommended. R
may even not be
CSPAAVE1
populated. Generally, R
helps to reduce
CSPAAVE1
the variation over temperature.
7) Use a 10kI NTC with a beta of 3435k. The beta
of 3435k is easier to keep effective DCR flat over
temperature.
CSPAAVE - CSNA Design Using
Inductor DCR Sensing
When the inductor DCR is used as the current-sense
element, a DCR circuit network shown in Figure 9 is used
to generate the average current signal for the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T.
8) Calculate R
assuming just one phase is used.
LXA_
After this value is determined, scale the actual R
by the number of active phases in the design.
LXA_
R
R
R
LXA1
Ln
LXA1
SENSE
1
3
2
4
CSPAAVE
LXAn
V
OUT
LXAn
SENSE
C
R
STEP
CSPAAVE
LXA2
LXA3
LXA2
SENSE
CSNA
R
CSNA1
R
R
CSPAAVE2
CSPAAVE1
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
LXA3
SENSE
CSNA
L
DCR
= R x C
EQ
CSPAAVE
WHERE R = R
//R
//R
// (R
+ R
// R
)
NTC
EQ
LXA1 LXA2 LXA3
CSPAAVE2
CSPAAVE1
R
NTC
Figure 9. CSPAAVE - CSNA DCR Network
4± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Differential Remote Sense
Both regulators A and B include differential, remote-
sense inputs to eliminate the effects of voltage drops
along the PCB traces and through the power pins of the
processor. The feedback-sense node connects to the
ler. To provide fast transient response, regulator A and
regulator B support phase-overlap mode, which allows
the dual and triple regulators to operate in-phase when
heavy load transients are detected, effectively reducing
the response time. After any high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the controller
simultaneously turns on all high-side MOSFETs with the
same on-time during the next on-time cycle. The phases
remain overlapped until the output voltage exceeds the
regulation voltage after the minimum off-time expires.
The on-time for each phase is based on the input volt-
age to FB_ ratio (i.e., follows the master on-time), but
reduced by 33% in a three-phase configuration, and not
reduced in a two-phase configuration. This maximizes
the total inductor current slew rate. After the phase-
overlap mode ends, the controller automatically begins
with the next phase. For example, if phase 2 provides
the last on-time pulse before overlap operation begins,
the controller starts switching with phase 3 when overlap
operation ends.
voltage-positioning resistor (R
). The ground-sense
FB_
(GNDS_) input connects to an amplifier that adds an
offset directly to the target voltage, effectively adjusting
the output voltage to counteract the voltage drop in the
ground path. Connect the voltage-positioning resistor
(R
FB_
) and ground-sense (GNDS_) input directly to
the remote-sense outputs of the processor as shown in
Figure 1. The correction range is bounded to less than
Q200mV. The remote-sense lines draw less than Q0.5FA
to minimize offset errors.
Integrator Amplifier
Regulators A and B utilize internal integrator amplifiers
that force the DC average of the FB_ voltage to equal the
target voltage, allowing accurate DC output voltage reg-
ulation regardless of the output voltage. The MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T dis-
able the integrators by connecting the amplifier inputs
together at the beginning of all VID transitions done in
pulse-skipping mode (PS2, PS3). The integrators remain
disabled until the transition is completed (the internal
target settles) and the output is in regulation (edge
detected on the error comparator).
Nominal Output Voltage Selection
The nominal no-load output voltage (V
) is defined
TARGET
by the selected voltage reference (SVID DAC), plus the
remote ground-sense adjustment (V
the following equation:
) as defined in
GNDS
V
= V
= V + V
DAC GNDS
TARGET
FB_
Transient-Phase Overlap Operation
When a transient occurs, the response time of the
controller depends on how quickly it can slew the induc-
tor current. Multiphase controllers that remain 180N or
120N out-of-phase when a transient occurs actually
respond slower than an equivalent single-phase control-
where V
is the selected SVID voltage. On startup,
DAC
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T slew the target voltage from ground to the
preset boot voltage. Table 3* lists the SVID code set for
VR12/IMVP7.
*Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±]
DAC SET POINT
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
VOLTAGE (V)
ACCURACY
—
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
0
0.2500
0.2550
0.2600
0.2650
0.2700
0.2750
0.2800
0.2850
0.2900
0.2950
8mV
2
8mV
3
8mV
4
8mV
5
8mV
6
8mV
7
8mV
8
8mV
9
8mV
10
8mV
______________________________________________________________________________________ 41
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
VOLTAGE (V)
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
ACCURACY
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
0.3000
0.3050
0.3100
0.3150
0.3200
0.3250
0.3300
0.3350
0.3400
0.3450
0.3500
0.3550
0.3600
0.3650
0.3700
0.3750
0.3800
0.3850
0.3900
0.3950
0.4000
0.4050
0.4100
0.4150
0.4200
0.4250
0.4300
0.4350
0.4400
0.4450
0.4500
0.4550
0.4600
0.4650
0.4700
0.4750
0.4800
0.4850
0.4900
0.4950
0.5000
42 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
VOLTAGE (V)
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
ACCURACY
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
0.5050
0.5100
0.5150
0.5200
0.5250
0.5300
0.5350
0.5400
0.5450
0.5500
0.5550
0.5600
0.5650
0.5700
0.5750
0.5800
0.5850
0.5900
0.5950
0.6000
0.6050
0.6100
0.6150
0.6200
0.6250
0.6300
0.6350
0.6400
0.6450
0.6500
0.6550
0.6600
0.6650
0.6700
0.6750
0.6800
0.6850
0.6900
0.6950
0.7000
0.7050
______________________________________________________________________________________ 43
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
VOLTAGE (V)
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
ACCURACY
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
8mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
93
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
0.7100
0.7150
0.7200
0.7250
0.7300
0.7350
0.7400
0.7450
0.7500
0.7550
0.7600
0.7650
0.7700
0.7750
0.7800
0.7850
0.7900
0.7950
0.8000
0.8050
0.8100
0.8150
0.8200
0.8250
0.8300
0.8350
0.8400
0.8450
0.8500
0.8550
0.8600
0.8650
0.8700
0.8750
0.8800
0.8850
0.8900
0.8950
0.9000
0.9050
0.9100
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
44 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
VOLTAGE (V)
ACCURACY
5mV
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
0.9150
0.9200
0.9250
0.9300
0.9350
0.9400
0.9450
0.9500
0.9550
0.9600
0.9650
0.9700
0.9750
0.9800
0.9850
0.9900
0.9950
1.0000
1.0050
1.0100
1.0150
1.0200
1.0250
1.0300
1.0350
1.0400
1.0450
1.0500
1.0550
1.0600
1.0650
1.0700
1.0750
1.0800
1.0850
1.0900
1.0950
1.1000
1.1050
1.1100
1.1150
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
5mV
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
______________________________________________________________________________________ 4.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
VOLTAGE (V)
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
ACCURACY
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
1.1200
1.1250
1.1300
1.1350
1.1400
1.1450
1.1500
1.1550
1.1600
1.1650
1.1700
1.1750
1.1800
1.1850
1.1900
1.1950
1.2000
1.2050
1.2100
1.2150
1.2200
1.2250
1.2300
1.2350
1.2400
1.2450
1.2500
1.2550
1.2600
1.2650
1.2700
1.2750
1.2800
1.2850
1.2900
1.2950
1.3000
1.3050
1.3100
1.3150
1.3200
46 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 30 VR12/IMVP-7 8-Bit DAC Code SVID[7:±] (continued)
DAC SET POINT
VOLTAGE (V)
LINE
VID7
VID6
VID.
VID4
VID3
VID2
VID1
VID±
HEX1
HEX±
ACCURACY
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1.3250
1.3300
1.3350
1.3400
1.3450
1.3500
1.3550
1.3600
1.3650
1.3700
1.3750
1.3800
1.3850
1.3900
1.3950
1.4000
1.4050
1.4100
1.4150
1.4200
1.4250
1.4300
1.4350
1.4400
1.4450
1.4500
1.4550
1.4600
1.4650
1.4700
1.4750
1.4800
1.4850
1.4900
1.4950
1.5000
1.5050
1.5100
1.5150
1.5200
*The output voltage accuracy in Table 3 is specified for T = 0°C to +85°C. See the Electrical Characteristics table for output volt-
A
age accuracy over T = -40°C to +105°C temperature range.
A
______________________________________________________________________________________ 47
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
waveforms to constantly be the complement of the
Output Voltage Transient Timing
At the beginning of an output voltage transition, the
MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T blank both power-good thresholds, prevent-
ing the POK_ open-drain outputs from changing states
during the transition. The controller enables the lower
power-good threshold approximately 20Fs after the
slew-rate controller reaches the target output voltage,
but the upper threshold is enabled only if the controller
remains in forced-PWM operation. If the controller enters
pulse-skipping operation, the upper threshold remains
blanked until an LX pulse is required.
high-side gate-drive waveforms. This keeps the switch-
ing frequency constant and allows the inductor current
to reverse under light loads, providing fast, accurate
negative output voltage transitions by quickly discharg-
ing the output capacitors. Forced-PWM operation comes
at a cost: the no-load +5V bias supply current remains
between 10mA to 50mA per phase, depending on the
external MOSFETs and switching frequency. To maintain
high efficiency under light-load conditions, the processor
can switch the controller to a low-power pulse-skipping
control scheme by entering PS2 or PS3.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T automatically control the current to the mini-
mum level required to complete the transition. The total
transition time depends on the SR input setting, the par-
ticular SETVID command (fast, slow) and the voltage dif-
ference, and the accuracy of the slew-rate controller (see
the Slew-Rate Accuracy in the Electrical Characteristics
table). The slew rate is not dependent on the total output
capacitance, as long as the surge current is less than the
current limit. For dynamic SVID transitions, the transition
Light-Load Pulse-Skipping
Operation (PS2, PS3)
When the SVID bus master issues a SetPS command
to PS2 or PS3, the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T immediately disable phases 2
and 3 (DH_2, DL_2 forced low, DRVPWM_ three-state),
and enters pulse-skipping operation. The pulse-skipping
mode enables the zero-crossing comparator of the
driver, so the controller pulls DL_ low when its current-
sense inputs detect “zero” inductor current. This keeps
the inductor from discharging the output capacitors
and forces the controller to skip pulses under light-load
conditions to avoid overcharging the output. If the VIDs
are set to a lower voltage setting, the output drops at a
rate determined by the load and the output capacitance.
The internal target still ramps as before, and POK_
remains blanked high impedance until 20Fs after the
output voltage reaches the internal target. Once this
time expires, POK_ monitors only the lower threshold.
Upon entering pulse-skipping operation, the MAX17411/
MAX17511/MAX17511C/MAX17511N temporarily set the
OVP threshold to 1.77V (typ), preventing false OVP faults
when the transition to pulse-skipping operation coincides
with an SVID code change. Once the VR_Settled com-
parator detects that the output voltage is in regulation,
the OVP threshold tracks the selected SVID DAC code.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T automatically use forced-PWM operation
during soft-start, regardless of the SetPS command.
time (t ) is given by:
TRAN
V
− V
NEW
OLD
/dt)
t
=
TRAN
(dV
TARGET
where dV
/dt is the slew rate set with the SR
TARGET
input and the SetVID command, V
is the original
OLD
output voltage, and V
is the new target voltage. The
NEW
maximum programmable slew rate is 20mV/Fs.
For non-zero V , the soft-start slew rate is fixed at
BOOT
2.5mV/Fs (minimum). The average inductor current per
phase required to make an output voltage transition is:
C
OUT
I
=
×(dV
/dt)
TARGET
L
N
TOTAL
where dV /dt is the required slew rate, C
TARGET
is
OUT
the total output capacitance, and N
of active phases.
is the number
TOTAL
Forced-PWM Operation (PS0, PS1)
During startup and normal operation, when the CPU is
actively running (PS0, PS1) the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T operate with
the low-noise, forced-PWM control scheme. Forced-
PWM operation disables the zero-crossing comparators
of all active phases, forcing the low-side gate-drive
Automatic Pulse-Skipping Switchover
In SKIP mode (PS2, PS3), an inherent automatic
switchover to PFM takes place at light loads (Figure 10).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor current’s
zero crossing. The zero-crossing comparator senses the
48 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
circuitry inhibits switching until V
rises above 4.25V.
CC
The controller powers up the reference once the system
enables the controller, V is above 4.25V, and EN is
CC
driven high. With the reference in regulation, the control-
ler ramps the output voltage to the programmed boot
∆I
∆t
V
IN - VOUT
L
=
voltage at the command slew rate for zero V
or the
BOOT
slow slew rate for non-zero V
.
BOOT
I
PEAK
V
BOOT
t
=
TRAN(START)
(dV
/dt)
I
= I
/2
TARGET
LOAD PEAK
where dV /dt is the slew rate.
TARGET
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
0
ON-TIME
TIME
Note the IMAX_ and SR multivalued logic inputs are
sampled after POR and the data latched into the
respective registers. These values cannot be changed
without driving the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T through another POR cycle.
Figure 10. Pulse Skipping/Discontinuous Crossover Point
inductor current across the low-side MOSFETs. Once V
LX_
drops below the zero-crossing comparator threshold (see
the Electrical Characteristics table), the comparator forces
DL_ low. This mechanism causes the threshold between
pulse-skipping PFM and non-skipping PWM operation
to coincide with the boundary between continuous and
discontinuous inductor-current operation. The PFM/PWM
crossover occurs when the load current of each phase is
equal to 1/2 the peak-to-peak ripple current, which is a
function of the inductor value. For a battery input range of
7V to 20V, this threshold is relatively constant, with only a
minor dependence on the input voltage due to the typi-
cally low duty cycles. The total load current at the PFM/
The startup sequence is as follows:
1) TheMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T have power and IC V
is > UVLO.
CC
2) EN goes high.
3) TheMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T’s SVID buses are active and idle.
4) If V
register = 00h, the MAX17411/MAX17511/
BOOT
MAX17511T wait at 0V, POK_ is deasserted and
ALERT# remains deasserted and hold until the SVID
command. If V
register is programmed to a
BOOT
PWM crossover threshold (I ) is approximately:
LOAD(SKIP)
VID setting other than zero (V
= 1.1V for the
BOOT
MAX17511N), the device ramps to the programmed
voltage, asserts POK_ and ALERT#, and hold until
the SVID command.
t
V
V
− V
OUT
SW OUT
IN
I
=
LOAD(SKIP)
2L
V
IN
Power-Up Sequence (POR, UVLO)
5) CPU initiates the SVID clock.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T are enabled when EN is driven high (Figures
11 and 12). The reference powers up first. Once the
internal reference exceeds its UVLO threshold, the inter-
nal analog blocks are turned on and masked by a 50Fs
one-shot delay. The startup ADC then begins to detect
the voltage applied to IMAX_ and SR inputs to set the
current limits and slew rate as well as the contents of the
ICC_MAX (21h), SR_Fast (24h), and SR_Slow (25h) reg-
isters. After this initialization, the PWM controller begins
6) CPU sends out the SetVID_Slow command to pro-
gram the initial output voltage.
7) TheMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T acknowledge and ramp to the voltage in
the SetVID_Slow command at the slow slew rate,
toggle status bit VR_Settled.
8) TheMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T assert POK_ for that rail.
9) Steps 4, 5, 6, 7, and 8 are repeated for regulator B.
switching. Power-on reset (POR) occurs when V
rises
CC
If V
drops below 4.25V after POR, the MAX17411/
CC
above approximately 2V, resetting the fault latch and
preparing the controller for operation. The V UVLO
MAX17511/MAX17511C/MAX17511N/MAX17511T
set the fault latch and turn off.
CC
______________________________________________________________________________________ 49
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
V
CC
SETVID COMMAND
EN
VID (D0–D7) = 0V
IGNORE SVID
IGNORE SVID
SET SLEW
RATE
PASSIVE
SHUTDOWN
V
CORE
INTERNAL
PWM CONTROL
POKA
t
BLANK
t
BLANK
20µs
Figure 11. Startup Sequence for Zero V
BOOT
V
CC
SETVID COMMAND
EN
VID (D0–D7) = BOOT VID
IGNORE SVID
IGNORE SVID
SOFT-START
(2.5mV/µs(min))
PASSIVE
SHUTDOWN
V
CORE
INTERNAL
PWM CONTROL
POKA
t
BLANK
t
BLANK
t
20µs
20µs
BLANK
Figure 12. Startup Sequence for Non-Zero V
BOOT
.± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Shutdown Control
Temperature Comparator (VR_HOT#)
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T feature two independent comparators with
inputs at THERMA and THERMB. These comparators
have accurate thresholds matching the appropriate ther-
mal levels required for the Temperature Zone register
(12h). Since these thresholds are nonlinear, it is essential
to use the correct resistor and thermistor values speci-
fied in Figures 1 and 2. When the maximum temperature
is exceeded at either THERMA or THERMB, VR_HOT#
is pulled low. For each regulator, place the thermistor
as close to the MOSFETs and inductors as possible.
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T EV kits provide good examples of thermistor
placement.
WhenENgoeslow,theMAX17411/MAX17511MAX17511C/
MAX17511N/MAX17511Tenterlow-powershutdownmode.
POK_ is pulled low immediately, and the output voltage
ramps down through an internal 20Idischarge resistor.
AfterENgoeslow,theMAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T shut down completely—the
drivers are disabled (DL_ and DH_ driven low, and DRVP-
WM_ is three-state), the reference turns off, and the sup-
ply current drops below 30FA. When an undervoltage fault
condition activates the shutdown sequence, the protec-
tion circuitry sets the fault latch to prevent the controller
from restarting. To clear the fault latch and reactivate the
controller, toggle EN or cycle V
power below 0.5V.
CC
The EN input controls both regulator A and regulator B
outputs. EN is active-high and is compatible with 1V log-
Fault Protection (Latched)
Output Overvoltage Protection (OVP) (MAX17411/
ic. When EN is asserted, with V
is active within 200Fs and enters an idle state, waiting for
= 0V, the SVID bus
BOOT
MAX17511/MAX17511C/MAX17511N Only)
The OVP circuit is designed to protect the load against
a shorted high-side MOSFET by drawing high cur-
rent and activating the adapter or battery protec-
tion circuits. The MAX17411/MAX17511/MAX17511C/
MAX17511N continuously monitor each output for an
overvoltage fault. An OVP fault is detected if the out-
put voltage exceeds the SVID DAC voltage by more
than 200mV (min), or the fixed 1.77V (typ) threshold
during a downward VID transition in SKIP mode. During
pulse-skipping operation (PS2, PS3), the OVP thresh-
old tracks the SVID DAC voltage as soon as the out-
put is in regulation; otherwise, the fixed 1.77V (typ)
threshold is used. When the OVP circuit detects an
overvoltage fault while in multiphase mode (PS0), the
MAX17411/MAX17511/MAX17511C/MAX17511N imme-
diately force DL_ high, three-state DRVPWM_, and pull
DH_ low. This action turns on the synchronous-rectifier
MOSFETs with 100% duty cycle and, in turn, rapidly
discharges the output filter capacitor and forces the
output low. If the condition that caused the overvoltage
(such as a shorted high-side MOSFET) persists, the
battery fuse blows or the high-current protection acti-
first commands and initial voltage target. For non-zero
V
, the SVID interface can accept commands after
BOOT
the output voltage reaches its target value.
Regulator A or regulator B can be independently placed
in non-zero V
mode by connecting THERMA or
BOOT
THERMB to ground at startup (MAX17411/MAX17511/
MAX17511T).
Power-Good (POKA, POKB)
Regulator
A
and regulator
B
have independent
power-good signals (POKA, POKB). These active-high
outputs indicate the startup sequence is complete
and the respective output voltage has moved to the
programmed SVID value. These signals are used for
system sequencing for other voltage regulators, the clock,
and microprocessor reset. POK_ remains asserted during
normal DC-DC operation and deasserts under any fault or
shutdown condition.
POKA and POKB continuously monitor the output voltage for
undervoltageandovervoltagefaultconditions. Iftheregulator
enters current limit, the respective POK_ signal will not go low
until the UVP threshold is reached. POK_ is actively held low
in shutdown (EN = GND) and during soft-start and shutdown.
Approximately 20Fs (typ) after the soft-start terminates, POK_
becomes high impedance as long as the feedback voltage
is above the UVP threshold (VID - 250mV) and below the
OVP threshold (VID + 250mV). POK_ goes low if the feed-
back voltage drops -200mV (max) below the target voltage
or rises 200mV (min) above the target voltage, or the SMPS
controller shuts down. POK_ must use an external pullup
vates. Toggle EN or cycle the V
power supply below
CC
0.5V to clear the fault latch and reactivate the control-
ler. When an overvoltage fault occurs, the MAX17411/
MAX17511/MAX17511C/MAX17511N immediately force
DL_high, pull DH_low and three-states DRVPWM_.
Output Undervoltage Protection (UVP)
If the output voltage on regulator A or B is 200mV (max)
below the target voltage and stays below this level
for 200Fs (typ), the controller activates the shutdown
sequence. The regulator turns on a 20Idischarge resis-
resistor between POK_ and V
level output.
to deliver a valid logic-
CC
______________________________________________________________________________________ .1
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
tor and sets the fault latch. DL_ and DH_ are forced low,
and DRVPWM goes to the three-state output defined in
the Electrical Characteristics table. Toggle EN or cycle
board parasitics should not exceed the following mini-
mum threshold to prevent shoot-through currents:
C
RSS
the V
power supply below 0.5V to clear the fault latch
CC
V
> V
IN(MAX)
GS(TH)
C
and reactivate the controller.
ISS
Adding a 4700pF between DL_ and power ground (C
NL
Thermal-Fault Protection
in Figure 13), close to the low-side MOSFET greatly
reduces coupling. Do not exceed 22nF of total gate
capacitance to prevent excessive turn-off delays. Shoot-
through currents can also be caused by a combination
of fast high-side MOSFET and slow low-side MOSFET.
If the turn-off delay time of the low-side MOSFET is
too long, the high-side MOSFET can turn on before the
low-side MOSFET has actually turned off. Adding a
resistor less than 5I in series with BST_ slows down the
high-side MOSFET turn-on time, eliminating the
shoot-through currents without degrading the turn-off
In addition to VR_HOT#, the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T feature internal
thermal-fault-protection circuits for regulator A and regu-
lator B. When the junction temperature rises above
+160NC, a thermal sensor sets the fault latch and forces
the DL_ and DH_ low, and three-states DRVPWM_.
Toggle EN or cycle the V
power supply below 0.5V to
CC
clear the fault latch and reactivate the controller after the
junction temperature cools by 15NC (typ).
MOSFET Gate Drivers
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty fac-
time (R
in Figure 13). Slowing down the high-side
BST
MOSFET also reduces the LX_ node rise time, thereby
reducing EMI and high-frequency coupling responsible
for switching noise.
tor seen in notebook applications, where a large V
IN
- V
differential exists. The high-side gate driv-
OUT
ers (DH_) source 2.2A and sink 2.7A, and the low-
side gate drivers (DL_) source 2.7A and sink 8A. This
ensures robust gate drive for high-current applications.
The DH_ high-side MOSFET drivers are powered by
internal boost switch charge pumps at BST_, while the
DL_ synchronous-rectifier drivers are powered directly
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
(R )*
BST
by the 5V bias supply (V
). Adaptive dead-time
DD_
BST
INPUT (V
)
IN
circuits monitor the DL_ and DH_ drivers and prevent
either MOSFET from turning on until the other is fully off.
The adaptive driver dead-time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. A low-resistance,
low-inductance path from the DL_ and DH_ drivers to the
MOSFET gates is required for the adaptive dead-time
circuits to work properly; otherwise, the sense circuitry
in the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T may interpret the MOSFET gates as “off”
while significant charge is still present.
C
BST
DH
LX
N
H
L
C
BYP
V
DD
DL
N
L
(C )**
Use very short, wide traces (50mils to 100mils wide if
the MOSFET is 1in from the driver). The DL_ low on-
resistance of 0.25I (typ) helps prevent DL_ from being
pulled up due to capacitive coupling from the drain to
the gate of the low-side MOSFET when the inductor
NL
PGND
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
switching node (LX_) transitions from ground to V . The
IN
THE SWITCHING NODE RISE TIME.
capacitive coupling between LX_ and DL_ created by
(C )** OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
NL
COUPLING THAT CAN CAUSE SHOOTTHROUGH CURRENTS.
the MOSFET’s gate-to-drain capacitance (C ), gate-
RSS
to-source capacitance (C
- C
), and additional
RSS
ISS
Figure 13. Gate-Drive Circuit
.2 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
REGISTERED FILE B
REGISTERED FILE A
MAX17411
MAX17511
MAX17511C
MAX17511N
MAX17511T
DATA
8
ADDR
2
LATCH
ENABLE
DATA-ACQUISITION SYSTEM
VR_HOT#
STATE
MACHINE
THERMA
THERMB
3
3-BIT DAC
2 TO 1
MUX
Figure 14. Data-Acquisition System Block Diagram
the system is alerted to an overtemperature fault in the event
of SVID bus failure.
External Drivers and Disabling Phases
The MMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T support an external driver, MAX17491, for
three-phase operation in regulator A. The MAX17411
also supports an external driver for two-phase operation
of regulator B. The DRVPWM_ output provides the signal
Serial VID Interface, Commands,
Registers, and Digital Control
A simplified block diagram of the SVID interface for
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T is shown in Figure 15. The interface consists
of a high-speed transceiver, control logic, and two inde-
pendent, identically configured register files for regula-
tors A and B. Refer to Intel’s VR12/IMVP-7 SVID protocol
documentation for complete details on the interface and
the required configuration of SVID data packets.
to trigger the driver. Connecting CSPA3/CSPB2 to V
CC
disables phase 3 of regulator A and phase 2 of regulator
B, respectively. Similarly, phase 2 can be disabled for
single-phase operation by connecting CSPA2 to V
.
CC
Data-Acquisition System
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T include current and thermal-monitoring func-
tions. A simplified data-acquisition system is employed
to convert the analog signals from the current-sense and
THERM_ inputs to 8-bit and 3-bit values in the ICC_MAX and
Temperature Zone registers, respectively (see Figure 14). An
independent VR_HOT# output is available to make certain
Regulator Addressing
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T do not feature programmable addressing.
Regulator A is hard coded to be SVID bus address 0, and
regulator B is hard coded to be SVID bus address 1.
______________________________________________________________________________________ .3
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
REGISTER FILE B
SAME CHARACTERISTICS
AS REGISTER FILE A
REGISTER FILE A
VENDOR
DATA
00h TO 06h
REGISTER
00h
REGISTER
06h
SVID INTERFACE
V
DD
LEVEL-SHIFT
STAGE
REGULATOR
STATUS AND
MONITORING
DATA
STATUS
REGISTER 10h
FROM REGULATOR
LOGIC
ALERT#
ALERT#
VDIN
10h TO 1Ch
TMONA
REGISTER
1Ch
VDIO
CLK
VDOUT
VCLK
DATA
SVID
LOGIC
VID MAX
REGISTER 30h
(2 x 34h)
ADDRESS
LATCH
#ACTIVE
PHASES AND
SKIP MODE
PWR STATE
REGISTER 32h
ENABLE
RSTNA
IMAXA, TMAX....
NO CLOCK
MONITOR
TRANSACTION
IN PROGRESS
V
BOOT
REGISTER 26h
FROM
REGULATOR LOGIC
OUPUT
VOLTAGE
AND PHASE
CONTROL
21h TO 34h
VID
RSTNA = RESET NO ACTIVITY
REGISTER 31h
V
OUT
SETPOINT
8-BIT
DAC
ADDER
OFFSET
REGISTER 33h
REGISTER
34h
Figure 15. SVID Interface Block Diagram
SetVID_Fast (01h)
Serial VID Commands
The MMAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T support the following commands
(Table 4) and registers according to Intel’s VR12/
IMVP-7 protocol specification. Note the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T sup-
port ALL CALL commands according to Intel specifica-
tion. For ALL CALL commands write 1111b or 1110b in
the address command bit.
The SetVID_Fast command contains the target SVID in the
payload byte. The output voltage range is defined in Table
3. The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T drive the respective output voltages to the new
VID setting with a fast slew rate as defined in the SR_Fast reg-
ister (24h). This register is programmed with the SR pin. The
default fast slew rate is 10mV/Fs.
.4 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
MAX17511T reset the ALERT# line after the ACK and start
moving the output voltage to the new target. For the case of
back-to-back SetVID commands to the same voltage, the VR
asserts ALERT# immediately since there is no settling time.
The SetVID_Fast command is preemptive. If the SVID bus
master interrupts current transition and attempts to move the
output to a new VID, the regulator responds immediately after
registering the new command. With back-to-back SetVID com-
mands, the MAX17411/MAX17511/MAX17511C/MAX17511N/
Table 40 Serial VID Commands
MASTER
PAYLOAD
SLAVE
PAYLOAD
COMMAND
DESCRIPTION
Extended
Command
Index
00h
01h
Extended
—
Not supported
Command sets the new SVID target (up or down) at the fast slew rate
programmed by the SR input. When the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T receive an SVID code for an
upward transition, they exit all low-power states to PS0 to ensure the
fastest slew to the new voltage. When the output reaches the new VID
target, the VR_Settled bit is set and ALERT# goes low.
SetVID-Fast
SetVID-Slow
VID Code
N/A
Command sets the new SVID target (up or down) at the slow slew rate
equal to 1/4 the fast slew rate programmed by the SR input. When the
MAX17411/MAX17511/MAX17511C/MAX17511N/MAX17511T receive an
SVID code for an upward transition, it exits all low-power states to PS0 to
ensure the fastest slew to the new voltage. When the output reaches the
new VID target, the VR_Settled bit is set and ALERT# goes low.
02h
03h
VID Code
VID Code
N/A
Command sets the new SVID target but does not control the slew
rate. The output is allowed to decay at a rate defined by the load. This
command is used for only high-to-low output transitions. When the
output reaches the new VID target, The VR_Settled bit is set but ALERT#
does not go low.
SetVID-
Decay
N/A
N/A
Command sets the power state PS_ of the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T so they can enable the correct
number of phases and control SKIP mode for optimized operation. See
the Power States (PS) section.
Byte Indicating
Power Status
of CPU
04h
05h
SetPS
Address of the
Index in the
Register File,
see Table 5
Command sets the address pointer in the data register table. Typically,
the next command, SetRegDAT, is the payload that gets loaded into
this address. However, for multiple writes to the same address, only one
SetRegADR is needed.
SetRegADR
N/A
N/A
New Data
Register
Contents
Command writes the contents to the data register that was previously
identified by the address pointer with SetRegADR.
06h
07h
SetRegDAT
GetReg
Specified Command returns the contents of the specified register as the payload.
Register See the Data and Configuration Registers section for a description of
Contents supported registers.
Define Which
Register
08h
TestMode
Reserved
—
—
—
—
—
09h–1Fh
N/A
______________________________________________________________________________________ ..
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
SetVID_Slow (02h)
The SetVID_Slow command contains the target SVID in
the payload byte. The output voltage range is defined
in Table 3. The MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T drive the respective output
voltage to the new VID setting with a slow slew rate
as defined in the SR_Slow register (25h). SetVID_Slow
transitions occur at 1/4 the fast slew rate. The
SetVID_Slow command is preemptive. If the SVID bus
master interrupts current transition and attempts to move
the output to a new VID, the regulator responds imme-
diately after registering the new command. With back-
to-back SetVID commands, the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T reset the ALERT#
line after the ACK and start moving the output voltage
to the new target. For the case of back-to-back SetVID
commands to the same voltage, the VR asserts ALERT#
immediately since there is no settling time.
If the SVID bus master attempts to program a power
state that is not supported, the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T acknowledge
with NAK (01b) and enter the lowest power state that
is supported. The MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T enter the new power state
after sending back the ACK of the SetPS command.
If the devices are in low-power states and receive a
SetVID_ command (either up or down), the target regu-
lators exit the low-power state to normal mode (PS0)
to move the voltage up at the requested slew rate and
reset the power-state register to 00h when they acknowl-
edge the SetVID (UP) command. The microprocessor
must reissue a low-power state command if it is in a low-
current condition at the new higher voltage.
The SetPS command is not preemptive; the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T wait
until it has completed the previous command or the out-
put has settled, then they change power state. If the VR
receives a SetPS command while it is still slewing from the
previous SetVID command, the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T reject (11b) the
SetPS command, indicating they cannot carry out the
command. These devices enter the new power state after
they send back the ACK of the SetPS command.
SetVID_Decay (03h)
The SetVID_Decay command contains the target SVID in
the payload byte. The range of voltage is defined in Table
3. It is used for VID down transitions. The MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T do
not control the slew rate, instead the output voltage
decays at a rate defined by the output load current.
If the VR receives a SetPS command while it is still slewing
down from a SetVID_Decay command, then the VR enters
the new power state, slewing down with the decay rate.
The SetVID_Decay command is preemptive for
positive-going SetVID_Fast or SetVID_Slow commands.
If the SVID bus master interrupts current transition
and attempts to move the output to a new VID, the
regulator responds immediately after registering the new
command. The ALERT# line remains high during
the SetVID_Decay transition. The SVID bus master
normally does not issue a SetVID_Decay with target
voltage higher than current setting. If this occurs, the
MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T reject the command (Acknowledge = 11b)
and remain at the same voltage setting.
SetRegADR (05h), SetRegDAT (06h),
and GetReg (07h)
Accessing the register files of the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T is accomplished
with three commands: SetRegADR, SetRegDAT, and
GetReg. SetRegADR sets the target register address,
SetRegDAT writes data to the specified register, and
GetReg retrieves data from the specified register. To
program a register, two commands must be executed in
order. SetRegADR chooses the address in Table 5 and
then the next command is a SetRegDAT to write or set
the data into the previously defined address. For multiple
writes to the same address, only one SetRegADR com-
mand is sent, followed by multiple SetRegDAT commands.
SetPS_ Set Power State (04h)
The SetPS command sends a byte that is encoded as to
the power state of the CPU. Based on the power-state
command, the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T can change their configura-
tion to meet the processor’s power needs with greater
efficiency. See the Power States (PS) section. The format
of the SetPS command payload is:
All the telemetry data from the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T is accessed
through the GetReg command. The payload byte in the
command contains an index into the data register file. A
slave device that receives the GetReg command must
insert the contents of the indexed data register into the
payload of the response.
B7
B6
B.
B4
B3
B2
B1
B±
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
.6 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
If SVID bus master issues a SetRegADR or GetReg
Access definitions for these registers are as follows:
command that contains a nonsupported address, the
MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T respond with the REJECT (11b) acknowl-
edge. If SVID bus master issues an ALL CALL
SetRegADR, SetRegDAT, or GetReg, the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T
respond with the not NAK (01b).
•ꢀ RO = Read only.
•ꢀ RW = Read write.
•ꢀ R-M = Read by SVID bus master (CPU).
•ꢀ W-PWM = Written by the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T only.
•ꢀ HC = Hard coded into the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T.
Data and Configuration Registers
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T support the data and configuration regis-
ters listed in Table 5. The registers retain data as long as
•ꢀ Platform = Programmed at PCB assembly using pin
strapping—cannot be overwritten by master.
•ꢀ Master = Programmed by the SVID bus master through
V
CC
is powered up and in regulation. During hard reset
the SVID bus with the SetRegADR, SetRegDAT.
(EN = low) or power cycle, all data is lost and registers
return to default contents. Regulator A and regulator B
include separate, independent register files.
•ꢀ PWM = Programmed by the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T during opera-
tion for reporting information to the master.
Table .0 Data and Configuration Register File Definition
INDEX
REGISTER NAME
DESCRIPTION
ACCESS
DEFAULT
The vendor ID is unique to Maxim and is assigned
by Intel
RO
HC
00h
Vendor ID
17h
RO
HC
01h
02h
Product ID
Uniquely identifies the MAX17411/MAX17511 products
01h
01h
Uniquely identifies the revision or stepping of the
MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T
RO
HC
Product Revision
Vendor Product Date
Code (Year/Month)
03h
04h
Not supported
Not supported
—
—
N/A
N/A
Lot Code
Identifies what version of SVID protocol is supported by
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T
RO
HC
05h
Protocol ID
01h
RO
HC
06h
07h–0Eh
0Fh
Capability
Not Used
SVID capability register
01h
—
—
—
Vendor Product Date
Code (Day/Time)
Not supported
—
N/A
Data register containing the Status1 data. This
register is read after the ALERT# signal is asserted. It
communicates the status of the MAX17411/MAX17511.
Status1 is cleared after a GetReg(10h) command.
R-M
W-PWM
10h
11h
Status1
Status2
00h
00h
Data register containing the Status2 data (SerialVID
Errors). Status2 is cleared after a GetReg(11h)
command.
R-M
W-PWM
______________________________________________________________________________________ .7
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table .0 Data and Configuration Register File Definition (continued)
INDEX
REGISTER NAME
DESCRIPTION
ACCESS
DEFAULT
Data register containing the measurement data from the
THERM_ input.
R-M
W-PWM
12h
Temperature Zone
00h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
Current Zone
Reserved
Not supported
—
—
—
—
—
—
—
—
—
—
N/A
—
Output Current
Output Voltage
Temperature
Output Power
Input Current
Input Voltage
Input Power
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
00h
N/A
N/A
N/A
N/A
N/A
N/A
This register contains a copy of the Status2 data that
was last read with the GetReg(Status2) command. In
the case of a communications error or parity error, when
the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T send the payload back to
the SVID bus master, the master can read the Status2_
LastRead register so the alert data is not lost.
R-M
W-PWM
1Ch
Status2_LastRead
Not Used
00h
—
1Dh–20h
21h
—
—
ICC_MAX (Maximum Data register containing the maximum output current
Based on the
IMAX_ logic voltage
level input
RO
Platform
Output Current
Capability)
limit that the regulator supports. The register uses a
binary format in amps, e.g., 64h = 100A.
Data register containing the temperature max the
platform supports and the level VR_HOT# asserts. This
register contains a fixed value of +100NC. Binary format
in NC, e.g., 64h = +100NC.
RO
HC
22h
23h
24h
Temp MAX
DC Load-Line
SR_Fast
64h
N/A
Not supported
—
Data register containing the fast slew-rate capability of
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T programmed at the SR input. Register
format is in mV/Fs, e.g., 0Ah = 10mV/Fs.
RO
Platform
0Ah = (10mV/Fs)
Data register containing the slow slew-rate capability of
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T. This value is 1/4 the rate programmed at
the SR input. Register format is in mV/Fs, e.g., 02h =
2.5mV/Fs.
RO
Platform
25h
26h
SR_Slow
02h = (2.5mV/Fs)
83h (0.9V) for Reg
B of MAX17511C.
ABh (1.1V) for
MAX17511N,
Data register containing the boot voltage. The register
uses SVID data format, e.g., 97h = 1.0V.
V
RO HC
BOOT
00h (0V) for other
devices
.8 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table .0 Data and Configuration Register File Definition (continued)
INDEX
27h
REGISTER NAME
VR tolerance
DESCRIPTION
ACCESS
DEFAULT
N/A
Not supported
Not supported
Not supported
—
—
—
—
—
28h
Current Offset
Temperature Offset
Not Used
N/A
29h
N/A
2Ah–2Fh
—
This register is programmable by the master and
sets the maximum VID the MAX17411/ MAX17511/
MAX17511C/ MAX17511N/MAX17511T support.
If a higher VID code is received, the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T
respond with “not supported” acknowledge. The
register uses SVID data format. This register must be
programmed by MASTER during boot-up sequence.
RW
Master
FBh
(1.5V)
30h
V
_MAX
OUT
Data register containing currently programmed VID
voltage. The register uses SVID data format.
RW
Master
31h
32h
VID Setting
Power State
00h
00h
RW
Master
W-PWM
Register containing the current programmed
power state.
This register contains an offset added to the
programmed SVID data. Data format is the number
of SVID steps. Negative offsets are in the two’s-
complement format. See the Offset Register (33h)
section.
VID Offset (Voltage
Margining)
RW
Master
33h
34h
00h
00h
Multi-VR
Configuration
This register contains the bit-mapped data for
configuring multiple regulators that utilize the SVID bus.
RW
Master
This register is a scratchpad register for temporarily
storing the SetRegADR payload. The data is
the address pointer for subsequent SetRegDAT
commands.
RW
Master
35h
SerRegADR
Not Used
00h
—
36h–6Fh
—
—
______________________________________________________________________________________ .9
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Status1 Register (10h)
The data in the Status1 register answers the following questions: Is the output voltage in regulation? Is the regulator
temperature approaching the thermal limit? Is the regulator’s output current approaching current limit? Also, should
the SVID bus master check the MAX17411/MAX17511/MAX17511C/MAX17511N/MAX17511T for SVID data errors in
the Status2 register? When there are any bit changes in Status1, the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T assert the ALERT# to notify the SVID bus master to start the polling process of reading the status from
each address on the bus.
Bit 0 in Status1 indicates that a SetVID command is completed and the output voltage has transitioned to within Q10mV
(max) of the final target voltage. During VR slewing/transitioning, the VR_Settled bit is “0”. Bit 1 indicates that the VR
temperature (in Temperature Zone register value (12h)) has reached 97% of the maximum temperature set in the Temp
MAX register (22h). Bit 2 indicates an overcurrent condition. The ICC MAX Alert bit (bit 2) is latched when it sets high.
A GetReg (Status1) command updates this latched bit. Bit 7 indicates that a Status2 register change was recorded.
When either bit 0, 1, 2, or 7 changes, the respective registers should be read to take further action. The format of the
Status1 register is:
B7
B6
B.
B4
B3
B2
B1
B±
ICC MAX
Alert
(Latched)
RSV
0b
RSV
0b
RSV
0b
RSV
0b
Read Status2
Therm Alert
VR_Settled
The bit values in the Status1 register reflect the most current status and a GetReg (Status1) command does not clear
them.
Status2 Register (11h)
Parity and data frame errors are recorded in the Status2 register. When the SVID bus master reads Status2, the
MAX17411/MAX17511/MAX17511C/MAX17511N/MAX17511T copy the contents into Status2_LastRead register (1Ch),
then clear the contents of the Status2 register. In the case of a parity error in the payload, the master can read the
Status2_LastRead register to get the status prior to reset.
The format of Status2 register is:
B7
B6
B.
B4
B3
B2
B1
B±
RSV
0b
RSV
0b
RSV
0b
RSV
0b
RSV
0b
RSV
0b
SVID Data
Frame Error
SVID Parity
Error
Temperature Zone Register (12h)
The digitized measurements from the thermistor bridges at THERMA and THERMB are recorded in the Temperature
Zone register. The required thresholds of the Temperature Zone register are nonlinear, but equate to increments listed
below. It is essential to use the correct resistor and thermistor values specified in Figures 1, 2, and 3. When 97%
TMAX (bit 6) for either is exceeded at either THERMA or THERMB, bit 1 of Status1 register (10h) is set and ALERT#
asserts low. When 100% TMAX bit (bit 7) for either regulator is set, VR_HOT# is pulled low. For each regulator, place
the thermistor as close to the MOSFETs and inductors as possible. The MAX17411/MAX17511 EV kits provide good
examples of thermistor placement.
The Temperature Zone register and VR_HOT# functions are independent. In the event of an SVID bus problem, the
VR_HOT# signal always responds correctly to force thermal throttling to prevent the CPU from catastrophically over-
heating. The format of the Temperature Zone Register is:
THERMISTOR
ALERT
COMPARATOR TRIP POINTS AND EXAMPLE TEMPERATURES
VR_HOT#
SCALED TO +1±±NC = 1±±%
B7
B6
B.
B4
B3
B2
B1
B±
100%
97%
94%
91%
88%
85%
82%
75%
EXAMPLE REGISTER CONTENTS FOR +9.NC
0
0
1
1
1
1
1
1
6± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Status2_LastRead (1Ch)
This register contains a copy of the Status2 data that
was last read with the GetReg (Status2) command. In
the case of a communications error or parity error, when
the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T send the payload back to the SVID bus
master, the master can read the Status2_LastRead reg-
ister so the alert data is not lost.
number of active phases in the regulator to determine
the data in the ICC_MAX register. If the voltage applied
to the IMAX_ input is not within the defined threshold
(e.g., IMAX shorted to ground or V ) the respective
CC
regulator is disabled. The data in this register is 8-bit
binary format in amps (1A/LSB), e.g., 4Bh = 75A. See
Table 6.
SR Fast (24h)
This register contains the guaranteed minimum fast
slew-rate data programmed at the SR multivalued logic
input. The default slew rate is 10mV/Fs (min). The data
is in 8-bit binary format in dV/dt, e.g., 10mV/Fs = 0Ah.
See Table 7.
Temp Max (22h)
This register contains the maximum temperature the VR
supports prior to issuing a thermal alert or VR_HOT#.
Temp MAX is set to +100NC.
The single-temperature threshold applies to both regulators
A and B. The data in this register is in 8-bit binary format in
degrees C, e.g., 64h = +100NC.
If NTC is used in the current-sensing network (CSP_,
CSN_), set V at 1.5V for 20mV/Fs and 0V for 10mV/Fs
SR
fastslewrate. Otherwise, V =3Vsetsthefastslewrateat
SR
Platform Performance Registers
These registers are programmed on the platform PCB
during manufacturing. The data tells the SVID bus master
the performance capability of the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T. Multivalued logic
inputs are used to set the data in these registers.
20mV/Fs and V = V
sets it at 10mV/Fs.
SR
CC
SR Slow (25h)
This register contains the guaranteed minimum slow
slew-rate data, which is 1/4 the value programmed at the
SR input. The data is in 8-bit binary format in dV/dt, e.g.,
2mV/Fs = 02h. See Table 7.
ICC_MAX (21h)
This register contains information on the maximum
current the motherboard VR supports. ICC_MAX is
programmed with the IMAX_ multivalue logic input. The
current limit computed from IMAX_ is multiplied by the
If NTC is used in the current-sensing network (CSP_,
CSN_), set V at 1.5V for 5mV/Fs and 0V for 2.5mV/Fs
SR
slow slew rate. Otherwise, V
= 3V sets the slow slew
SR
rate at 5mV/Fs and V = V
sets it at 2.5mV/Fs.
SR
CC
Table 60 Current-Limit Setting (V
= ±V or V
= 10.V)
SR
SR
REG A
MINMUM
REG A
REG A
PHASE
ICC_MAX
REPORT (A)
REG B
MiINIMUM PHASE OCP
REG B
REG B
PHASE
ICC_MAX
REPORT (A)
IMAX_
LEVEL
NO0
VOLTAGE
LEVEL (V)
R
(mI)
PHASE OCP
CURRENT
(A)
SENSE
V
V
CURRENT
(A)
SENSE
(mV)
SENSE
(mV)
< 13.65 O
0
—
—
Latched Off
—
—
Latched Off
—
V
/50
CC
1
2
14.5 OV /50
0.65
0.65
0.65
0.65
0.75
0.75
0.75
0.75
0.85
0.85
0.85
22.5
21.5
17.0
15.0
27.0
25.0
20.0
17.0
30.0
28.0
22.5
39
36
30
26
39
36
30
26
39
36
30
35
33
27
22
35
33
27
22
35
33
27
22.5
21.5
13.0
11.0
27.0
25.0
15.0
13.0
30.0
28.0
17.0
39
36
23
20
39
36
23
20
39
36
23
35
33
22
17
35
33
22
17
35
33
22
CC
15.5 OV /50
CC
3
16.5 OV /50
CC
4
17.5 OV /50
CC
5
18.5 OV /50
CC
6
19.5 OV /50
CC
7
20.5 OV /50
CC
8
21.5 OV /50
CC
9
22.5 OV /50
CC
10
11
23.5 OV /50
CC
24.5 OV /50
CC
______________________________________________________________________________________ 61
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Table 60 Current-Limit Setting (V
= ±V or V
= 10.V) (continued)
SR
SR
REG A
MINMUM
REG A
PHASE OCP
CURRENT
(A)
REG A
PHASE
ICC_MAX
REG B
MiINIMUM PHASE OCP
REG B
REG B
PHASE
ICC_MAX
REPORT (A)
IMAX_
LEVEL
NO0
VOLTAGE
LEVEL (V)
R
(mI)
SENSE
V
V
CURRENT
(A)
SENSE
(mV)
SENSE
(mV)
REPORT (A)
12
13
14
15
16
25.5 OV /50
0.85
0.95
0.95
0.95
0.95
20.0
33.5
31.0
25.0
21.5
26
39
36
30
26
22
35
33
27
22
15.0
33.5
31.0
20.0
17.0
20
39
36
23
20
17
35
33
22
17
CC
26.5 OV /50
CC
27.5 OV /50
CC
28.5 OV /50
CC
29.5 OV /50
CC
> 30.2 O
Latched
Off
17
—
—
—
—
Latched Off
—
V
/50
CC
See the Electrical Characteristics table for minimum V
for V = 3V or V = 5V.
SR SR
SENSE
Table 70 Programmed Slew-Rate Data
NTC for CSP_
SIGNALS
FAST SLEW RATE
(MIN) (mV/µs)
MINIMUM VALUE
REPORTED IN 24h
SLOW SLEW RATE
(MIN) (±mV/µs)
MINIMUM VALUE
REPORTED IN 2.h
V
SR
(V)
0
Yes
Yes
No
10
20
20
10
0Ah
14h
14h
0Ah
2.5
5
02h
04h
04h
02h
1.5
3
5
V
No
2.5
CC
V
BOOT
(26h)
This register is programmed by the platform designer and contains the boot voltage value. The VID Setting of 00h
sets the boot voltage as 0V. With this setting, the output voltage does not ramp up at power-up until the MAX17411/
MAX17511/MAX17511T receive a SetVID command. If V
is set to any other code, the output voltage ramps to
BOOT
the selected VID DAC setting on assertion of enable (EN = high). The output voltage maintains its value until a SetVID
command sets a new target. The default value for V register is 00h for the MAX17411/MAX17511/MAX17511T and
BOOT
Reg A of the MAX17511C. The default value for the V
register is ABh for the MAX17511N. It is programmed in an
BOOT
8-bit binary format. The default value for the V
register is 83h for Reg B of the MAX17511C
BOOT
.
V _MAX (30h)
OUT
This register is programmed by the CPU or SVID bus master to the maximum output voltage the CPU load can support.
Any attempts to set the SVID above V _MAX are blanked and ignored. The MAX17411/MAX17511/MAX17511C/
OUT
MAX17511N/MAX17511T respond with “not-supported” acknowledge. The default value is FBh (1.5V).
VID Setting (31h)
This register contains a copy of the currently programmed SVID data. The default value is 00h.
62 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Power State PS_ (32h)
The PS register contains information on the CPU’s power-consumption status. The MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T support states PS0 through PS3. See the Power States (PS) section for a complete descrip-
tion of these states and the resulting operating mode change in the MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T. If a power state is requested that is not supported by these devices, they acknowledge with command
rejected (11b) back to the SVID bus master. The PS_ register format is:
B7
B6
B.
B4
B3
B2
B1
B±
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Offset Register (33h)
This register contains an offset, which is added to the programmed SVID data. The format of this data is the number
of SVID steps/LSBs. For negative offsets, the value is the two’s complement of the number of SVID steps. The format
of the Offset register is:
OFFSET OR VOLTAGE MARGIN
B7
B6
B.
B4
B3
B2
B1
B±
Sign
0 = +
1 = -
SVID6
SVID5
SVID4
SVID3
SVID2
SVID1
SVID0
Default = 00h = no offset.
Bit 7 = Sign bit.
00000001 = 01h = +1 LSB Offset.
00000011 = 03h = +3 LSB Offset.
10000001 = 81h = -127 LSB Offset.
Multi-VR Configuration Register (34h)
This register contains the bit-mapped data for configuring multiple regulators that utilize the SVID bus.
Bit 0 (POK 0V) changes the response of the POK_ power-good output. Writing a 0 (default) to this bit enables the
standard definition for POK_ response. When a SetVID (0.0V) command is issued, the respective regulator turns off
and POK_ deasserts to 0V. Writing a 1 to bit 0 causes POK_ to remain high when SetVID (0.0V) is issued and POK_
only goes low under fault conditions or when the regulator is powered down using EN or the input supplies turn off.
Bit 1 (LOCK VID/PS) controls a lock function for the SVID code and power state PS. When bit 1 is a 0, the MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T are in normal mode and the SVID and PS are NOT locked. When
bit 1 is a 1, the MAX17411/MAX17511/MAX17511C/MAX17511N/MAX17511T lock the SVID and PS data and reject
all SetVID and SetPS commands. Bit 1 must be changed back to 0 before the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T accept new commands. The format of the Multi-VR register is:
MULTI-VR CONFIGURATION (34h)
B7
B6
B.
B4
B3
B2
B1
B±
RSV 0b
RSV 0b
RSV 0b
RSV 0b
RSV 0b
RSV 0b
LOCK VID/PS
POK 0V
______________________________________________________________________________________ 63
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
SetRegADR Register (35h)
This register is a scratchpad register for temporarily
storing the SetRegADR payload. The data is the address
pointer for subsequent SetRegDAT commands.
After exiting a low-power state, the CPU waits 3.3Fs
prior to entering the full-power mode. Regulators A and
B respond identically to the PS_ commands described
in Table 8. Regulator B controls phase 1 (MAX17411/
MAX17511/MAX17511C/MAX17511N/MAX17511T) and
phase 2 (MAX17411).
Critical VR12/IMVP-7 Functions
Voltage-Settled Function
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T include an auxiliary bank of comparators that
detect when the SVID transition is complete and the output
voltage is within Q10mV (2 LSB) of the new target VID set-
ting. After the output has settled, the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T set the VR_Settled
bit in the Status1 register and assert the ALERT# line.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the
following four factors dictate the rest of the design:
Power States (PS)
The SVID bus can be used to place the MAX17411/
MAX17511/M17511C/MAX17511N/MAX17511T into mul-
tiple operating states to optimize the efficiency and
power delivery capability. These states are entered by
issuing a SetPS command and the programmed state
is reflected in the power-state register (32h). The power
states are listed in order of power savings:
Input Voltage Range: The maximum value (V
)
IN(MAX)
must accommodate the worst-case high AC adapter
voltage. The minimum value (V ) must account for
IN(MIN)
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Maximum Load Current: There are two values to
PS0 = Represents full power or active mode.
consider. The peak load current (I
)
LOAD(MAX)
PS1 = Used in active mode or sleep mode and it
represents a low-current state.
determines the instantaneous component stresses and
filtering requirements, and thus drives output capaci-
tor selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load current
PS2 = Used in sleep mode and it represents a low-
voltage state and lower current state than PS1.
(I
) determines the thermal stresses and thus drives
LOAD
PS3 = Ultra-low-power sleep mode.
PS4–PS7 are not defined.
the selection of the input capacitors, MOSFETs, and other
critical heat-contributing components. Modern notebook
The SVID code and power states are independent
and can change at any time as determined by the
CPU operating state. When the MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T exit any low-
power state, they automatically enter PS0 for any SVID
command (SetVID_Fast/SetVID_Slow) that causes the
output to change from the previous value. Note the
SVID bus master must reissue a low-power state com-
mand to return the MAX17411/MAX17511/MAX17511C/
MAX17511N/MAX17511T to a low-current condition at
the new higher voltage.
CPUs generally exhibit I
= 0.8 x I
. For
LOAD
LOAD(MAX)
multiphase systems, each phase supports a fraction of
the load, depending on the current balancing. When
properly balanced, the load current is evenly distributed
among each phase:
I
LOAD
I
=
LOAD(PHASE)
N
TOTAL
where N
is the total number of active phases.
TOTAL
Table 80 Power State (PS) Control of Regulator Operation
PS_
0
PHASE 1
PHASE 2
PHASE 3
SKIP
COMMENTS
Full-power FPWM mode
1-phase FPWM
1-phase SKIP
1
1
1
0
1
0
0
0
1
2
1
0
0
1
3
1
0
0
1
1-phase SKIP
4–7
—
—
—
—
Not used
64 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Switching Frequency: This choice determines the
V
STEP
LOAD(MAX)
(R
+ R
) ≤
PCB
basic trade-off between size and efficiency. The optimal
frequency is largely a function of maximum input voltage
due to MOSFET switching losses that are proportional
ESR
∆I
The output-voltage ripple of a step-down controller
equals the total inductor ripple current multiplied by the
output-capacitor’s ESR. When operating multiphase out-
of-phase systems, the peak inductor currents of each
phase are staggered, resulting in lower output ripple
voltage by reducing the total inductor ripple current. For
multiphase operation, the maximum ESR to meet ripple
requirements is:
to frequency and V 2. The optimum frequency is also a
IN
moving target due to rapid improvements in MOSFET
technology that is making higher frequencies more
practical.
Inductor Operation Point: This choice provides trade-
offs between size vs. efficiency and transient responses
vs. output noise. Low inductor values provide better
transient response and smaller physical size, but also
result in lower efficiency and higher output noise due to
increased ripple current. The minimum practical induc-
tor value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor current
just touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit. The optimum operating point is usually
between 30% and 50% ripple current. For a multiphase
core regulator, select an LIR value of ~0.4.
V
× f
×L
IN SW
R
≤
V
RIPPLE
ESR
V
− N
(
× V
V
OUT
)
)
(
IN
TOTAL
OUT
where NTOTAL is the total number of active phases and
is the switching frequency per phase.
f
SW
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as
to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rat-
ing rather than by capacitance value (this is true for
polymer types). When using low-capacity ceramic filter
capacitors, capacitor size is usually determined by the
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
capacity needed to prevent V
and V
from caus-
SAG
SOAR
ing problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
V
− V
V
OUT
IN
OUT
L = N
TOTAL
f
×I
×LIR
V
SW LOAD(MAX)
IN
longer a problem (see the V
and V
equations in
SAG
SOAR
where N
is the total number of phases. Find a low-
TOTAL
the Transient Response section).
loss inductor having the lowest possible DC resistance
that fits in the allotted dimensions. The core must not
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the
value of the ESR zero relative to the switching frequency.
The boundary of instability is given by the following
equation:
saturate at the peak-inductor current (I
):
PEAK
I
LIR
2
LOAD(MAX)
I
=
1+
PEAK
N
TOTAL
Output Capacitor Selection
f
SW
π
f
≤
ESR
Output capacitor selection is determined by the control-
ler stability and the transient soar and sag requirements
of the application.
where:
and:
1
Output Capacitor ESR
The output-filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high-enough ESR
f
=
ESR
2π ×R
× C
EFF
OUT
to satisfy stability requirements. In CPU V
convert-
CORE
R
= R
+ R
+ R
PCB
ers and other applications where the output is subject to
large-load transients, the size of the output capacitor typ-
ically depends on how much ESR is needed to prevent
the output from dipping too low under a load transient.
Ignoring the sag due to finite capacitance:
EFF
ESR
DROOP
where C
is the total output capacitance, R
is
ESR
is the
OUT
the total equivalent series resistance, R
voltage-positioning gain, and R
DROOP
is the parasitic board
PCB
______________________________________________________________________________________ 6.
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
resistance between the output capacitors and sense
resistors.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of output
sag is also a function of the maximum duty factor, which
can be calculated from the on-time and minimum off-
time. For a multiphase controller, the worst-case output
sag voltage can be determined by:
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors are widely used and have typical ESR zero
frequencies below 50kHz. In the standard application
circuit, the ESR needed to support a 30mV
ripple is
P-P
2
L(∆I
)
t
LOAD(MAX)
30mV/(40A x 0.3) = 2.5mI. Four 470FF/2.5V Panasonic
SP (type SX) capacitors in parallel provide 1.5mI (max)
ESR. With a 2mI droop and 0.5mI PCB resistance,
the typical combined ESR results in a zero at 30kHz.
Ceramic capacitors have a high-ESR zero frequency, but
applications with significant voltage positioning can take
advantage of their size and low ESR. When using only
MIN
− t
V
≈
×
SAG
2N
× C
× V
Kt
[
]
TOTAL
OUT
OUT
SW
MIN
and:
t
= t
+ t
OFF(MIN)
MIN
ON
where t
is the minimum off-time (see the Electrical
OFF(MIN)
Characteristics table), Kt
ceramic output capacitors, output overshoot (V
)
SOAR
is the programmed switch-
SW
typically determines the minimum output capacitance
requirement. Their relatively low capacitance value
favors high-switching-frequency operation with small
inductor values to minimize the energy transferred
from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback
loop instability.
ing period, and N
phases. K = 66% when N
is the total number of active
TOTAL
= 3, and K = 100% when
PH
N
PH
= 2. V
must be less than the transient droop
SAG
DI
x R
. The capacitive soar voltage
DROOP
LOAD(MAX)
due to stored inductor energy can be calculated as:
2
(∆I
) L
LOAD(MAX)
V
≈
SOAR
2N
× C
× V
OUT OUT
TOTAL
Double-Pulsing and Feedback Loop Instability
Double pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough volt-
age ramp in the output-voltage signal. This “fools” the
error comparator into triggering a new cycle immediately
after the minimum off-time period has expired. Double
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability due to
insufficient ESR. Loop instability can result in oscillations
at the output after line or load steps. Such perturbations
are usually damped, but can cause the output voltage
to rise above or fall below the tolerance limits. The easi-
est method for checking stability is to apply a very fast
10% to 90% max load transient and carefully observe
the output-voltage ripple envelope for overshoot and
ringing. It can help to simultaneously monitor the induc-
tor current with an AC current probe. Do not allow more
than one cycle of ringing after the initial step-response
under/overshoot.
The actual peak of the soar voltage depends on the
time where the decaying ESR step and rising capaci-
tive soar are at their maximum. This is best simulated or
measured.
Input Capacitor Selection
The input capacitor must meet the ripple-current require-
ment (I
) imposed by the switching currents. The
RMS
multiphase Quick-PWM controllers operate out-of phase,
reducing the RMS input. The I requirements can be
RMS
determined by the following equation:
I
LOAD
I
=
×
RMS
N
× V
TOTAL
IN
N
× V
V
− N
(
× V
TOTAL OUT
)
)
(
TOTAL
OUT IN
where N
is the total number of out-of-phase switch-
TOTAL
ing regulators. The worst-case RMS current requirement
occurs when operating with V = 2(N O V ).
IN
TOTAL
OUT
Therefore, the above equation simplifies to I
= 0.5 x
RMS
Transient Response
(I
/N
). Choose an input capacitor that exhibits
LOAD TOTAL
The inductor ripple current impacts transient-response
less than +10NC temperature rise at the RMS input cur-
rent for optimal circuit longevity.
performance, especially at low V - V
differentials.
IN
OUT
66 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
and cause the fault latch to trip. To protect against this
possibility, the circuit can be overdesigned to tolerate:
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high-load-current capability when
using high-voltage AC adapters.
∆I
INDUCTOR
2
I
= N
I
+
LOAD
TOTAL VALLEY(MAX)
High-Side MOSFET Power Dissipation
The conduction loss in the high-side MOSFET (NH) is a
function of the duty factor, with the worst-case power dis-
sipation occurring at the minimum input voltage:
I
×LIR
LOAD(MAX)
2
= N
I
+
TOTAL VALLEY(MAX)
where I
is the maximum valley current
VALLEY(MAX)
2
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFET must
have a good-size heatsink to handle the overload power
dissipation. Choose a low-side MOSFET that has the
V
I
OUT
LOAD
P (NH Resistive) =
R
DS(ON)
D
V
N
IN TOTAL
where N
is the total number of phases. Calculating
TOTAL
lowest possible on-resistance (R
), comes in a
DS(ON)
the switching losses in the NH is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a ther-
mocouple mounted on NH:
moderate-sized package (i.e., one or two thermally
enhanced 8-pin SO packages), and is reasonably
priced. Make sure that the DL_ gate driver can supply
sufficient current to support the gate charge and the
current injected into the parasitic gate-to-drain capaci-
tor caused by the high-side MOSFET turning on; other-
wise, cross-conduction problems might occur (see the
MOSFET Gate Drivers section). The optional Schottky
diode (from DL to ground) should have a low forward
voltage and be able to handle the load current per phase
during the dead times.
V
xI
N
x f
Q
G(SW)
I
IN LOAD SW
P (NHSwitching) =
D
TOTAL
GATE
Boost Capacitor
2
C
x V
x f
SW
OSS
IN
+
The boost capacitors (C
) must be selected large
BST
2
enough to handle the gate-charging requirements of the
high-side MOSFET. Select the boost capacitors to avoid
discharging the capacitor more than 200mV while charg-
ing the gate of the high-side MOSFET:
where C
is the output capacitance of the high-side
OSS
MOSFET, Q
is the charge needed to turn on the
G(SW)
NH MOSFET, and I
is the peak gate-drive source/
GATE
sink current. The optimum high-side MOSFET trades
the switching losses with the conduction (R
N× Q
200mV
)
GATE
DS(ON)
C
=
BST
losses over the input voltage range. Ideally, the losses at
should be roughly equal to losses at V
V
,
IN(MAX)
IN(MIN)
where N is the number of high-side MOSFETs used for
one regulator, and Q is the gate charge specified in
the data sheet of the MOSFET. For example, assume one
FDS6298 n-channel MOSFET is used on the high side.
According to the manufacturer’s data sheet, a single
FDS6298 has a maximum gate charge of 10nC (V
= 5V). Using the above equation, the required boost
capacitance would be:
with lower losses in between. If V does not vary over
IN
GATE
a wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Low-Side MOSFET Power Dissipation
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
GS
2
V
I
OUT
LOAD
P (NLResistive) = 1−
R
DS(ON)
D
1×10nC
200mV
V
N
C
=
= 0.05µF
IN(MAX)
TOTAL
BST
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than I
but are not quite high enough to exceed the current limit
Selecting the closest standard value, this example
requires a 0.1FF ceramic capacitor.
LOAD(MAX)
______________________________________________________________________________________ 67
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
network (CSP_, CSN_), set V at 1.5V for 20mV/Fs and
Current Limit (IMAX)
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T have a current limit that is programmed in
discrete increments using multivalue logic inputs, IMAX_
and SR. The regulator’s maximum current limit, which is
the current limit per phase times the maximum number of
active phases, is reflected in the ICC_MAX register (21h)
for the respective regulator. The IMAX_ voltage deter-
mines the valley current-sense threshold. See Table 6.
SR
0V for 10mV/Fs fast slew rate. Otherwise, V = 3V sets
SR
the fast slew rate at 20mV/Fs and V
10mV/Fs.
= V
sets it at
SR
CC
Voltage Positioning
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the
output capacitance and processor’s power-dissipation
requirements. The MAX17411/MAX17511/MAX17511C/
The valley of the inductor current occurs at I
minus half the ripple current; therefore:
LOAD(MAX)
MAX17511N/MAX17511T use
a transconductance
amplifier to set the transient and DC output-voltage
droop (Figures 5, 6, and 7) as a function of the load.
This adjustability allows flexibility in the selected current-
sense resistor value or inductor DCR, and allows smaller
current-sense resistance to be used, reducing the over-
all power dissipated.
LIR
2
I
> I
1−
VALLEY
LOAD(MAX)
where:
V
Steady-State Voltage Positioning
SENSE
SENSE
I
=
VALLEY
Connect a resistor (R
) between FB_ and V
to
FB_
OUT
R
set the DC steady-state droop (load-line) based on the
required voltage-positioning slope (R
):
DROOP
×N
PH
where R
tor DCR.
is the sensing resistor or effective induc-
SENSE
R
DROOP
R
=
FB_
To set the current limit:
R
G
SENSE m(FB_)
1) Select the inductor (see the Inductor Selection section)
where the effective current-sense resistance (R
)
SENSE
2) Based on the current-sensing element (sense resis-
tor or DCR sensing), calculate CSP_ - CSN_ sensed
resistance value. See the Current Sense section.
Then, use a divider to normalize this value to one of
depends on the current-sense method (see the Current
Sense section), and the transconductance (G ) of
m(FB_)
the voltage-positioning amplifier is typically 600FS as
defined in the Electrical Characteristics table. When the
inductors’ DCR is used as the current-sense element,
each current-sense input should include an NTC therm-
istor to minimize the temperature dependence of the
voltage-positioning slope.
the four R
values in Table 6.
SENSE
3) Select ICC_MAX for the calculated R
value.
SENSE
Then, program the IMAX_ pin to its specified voltage
level in Table 6.
4) SR setting also scales the current limit. Set V
to
SR
one of the four voltages in Table 7 based on using
NTC or not using NTC in the current-sensing net-
work. See the Electrical Characteristics table.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount
all the power components on the top side of the board
with their ground terminals flush against one another.
The layouts of the MAX17411/MAX17511/MAX17511N/
MAX17511C/MAX17511T are intimately related to the
layout of the CPU. The high-current output paths from
the regulator must flow cleanly into the high-current
inputs on the processor. For VR12/IMVP-7 processors,
these inputs are orthogonal. This arrangement effectively
forces the regulator to be located diagonally with respect
to the processor. Refer to the MAX17411/MAX17511/
Slew-Rate Control
The MAX17411/MAX17511/MAX17511C/MAX17511N/
MAX17511T have a slew-rate control programmed in
discrete increments using a multivalue logic-input SR.
Connect SR to a voltage level as defined in Table 7
to set the fast slew rate. The MAX17411/MAX17511/
MAX17511C/MAX17511N/MAX17511T digitize the volt-
age at SR to set one of two discrete slew rates. The regu-
lator’s slow slew rate is set automatically relative to the
fast slew rate (SR_Slow = 1/4 SR_Fast). The selected fast
and slow slew rates are reflected in registers 24h and
25h, respectively. If NTC is used in a current-sensing
68 _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
MAX17511C/MAX17511N/MAX17511T Evaluation Kits'
specifications for layout examples and follow these
guidelines for good PCB layout:
•ꢀ Keep the high-current, gate-driver traces (DL_, DH_,
LX_, and BST_) short and wide to minimize trace
resistance and inductance. This is essential for high-
power MOSFETs that require low-impedance gate
drivers to avoid shoot-through currents. CSP_ and
CSN_ connections for current limiting and voltage
positioning must be made using Kelvin-sense con-
nections to guarantee the current-sense accuracy.
•ꢀ Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
•ꢀ Connect all analog grounds to a separate solid cop-
per plane, which connects to the ground pin of the
•ꢀ When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between
the input capacitors and the high-side MOSFET
than to allow distance between the inductor and the
low-side MOSFET or between the inductor and the
output filter capacitor.
Quick-PWM controller. This includes the V
capacitor, FB_, and GNDS bypass capacitors.
bypass
CC
•ꢀ Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCB (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached
in terms of fractions of centimeters, where a single
mIof excess trace resistance causes a measurable
efficiency penalty.
•ꢀ Route high-speed switching nodes away from sensi-
tive analog areas (FB_, CSP_, CSN_, etc.).
Layout Procedure
COMPONENT
DESCRIPTION
The general rule is that capacitors take priority over resistors since they provide a filtering function.
The list below is in order of priority.
1) V
, V
, and V
Capacitors
DDA DDB
CC
Place these near the IC pins with wide traces and good connection to PGND.
2) CSP_AVE - CSN_ Differential Filter
Place the capacitor and the step resistor near the IC pins. This input is most critical because it is
used for regulation and load line.
Capacitors
3) CSP_ - CSN_ Differential Filter Capacitors
Place these after placing the CSP_AVE - CSN_ capacitor and step resistor. This input is less critical
because it is only used for current limit and current balance.
4) Common-Mode Capacitors
The capacitors to AGND take the next priority.
.) FB_ and GNDS_ Capacitors
The FB_ capacitor will be slightly further from the IC since the FB_ resistor has priority to be closer to
the IC.
FB_
The FB_ resistor should be near the respective pin. Keep the trace short to reduce any inductance.
IMAX_ and SR resistors can be a little further from the IC. The voltages are sampled during the
IC initialization time.
IMAX_ and SR
DCR Network
The resistor network for CSP_AVE - CSN_ or CSP_ - CSN_ must be placed near the inductors.
Use Kelvin sense connection to the sense element (inductor or sense resistor).
Route CSP_AVE-_ as a differential pair as the first priority. Route CSP_ traces near CSN_ as a
second priority. Avoid any switching signals, especially DH and LX when routing these current-
sensing signals.
Current Sense
Thermistors
The NTC for CSP_AVE - CSN_ and CSPB1 - CSNB (MAX17511/MAX17511C/MAX17511N/
MAX17511T) sensing must be placed near the Phase 1 inductor to properly sense the temperature.
The NTC for THERM_ sensing should be placed near the power components of the first phase.
______________________________________________________________________________________ 69
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Layout Procedure (continued)
COMPONENT
Catch Resistors
DESCRIPTION
Catch resistors should be placed near the CPU so that the output voltage trace does not need to
route back to the IC. But the GND catch resistor is less critical as it only requires a via to connect to
the GND plane.
Remote Sense
Gate Drive
Route together in a quiet layer, avoiding any switching signals, especially DH and LX.
Keep the gate-drive traces short and wide. Use double vias especially for DL. Use 40mil to 50mil
traces for DL and 30mil to 40mil traces for DH and LX.
DH and LX are a pair, and should run side by side, or one above the other. DL and GND are the
other pair. Route DL next to the GND layer.
Keep DH and LX away from DL to avoid cross coupling. Also keep DH and LX away from any
sensitive signal traces.
The DL capacitor should be placed near the low-side MOSFET gate-source pins, and not near the
IC DL pins.
Snubbers should be placed at the LX node near the MOSFET or inductor, and not near the IC LX
pins.
Snubbers
BST
BST components should be placed near the IC, connecting to LX near the IC pin.
Pullups do not need to be near the IC and can be placed further to make space for other more
important components near the IC.
VRHOT#, POKA, POKB
Use 10kIpullup to +3.3V for POKA and POKB.
Use 75Ipullup to +1.05V for VRHOT#.
Refer to Intel specifications for final pullup resistor value and voltage.
Pullups for VDIO, VCLK, and ALERT# do not need to be too close to the IC and can be placed
further to make space for other more important components near the IC.
Refer to Intel specifications for final pullup resistor value and voltage.
SVID
Place a small 0.1FF decoupling capacitor for the +1.05V near the pullup resistors.
Keep the AGND polygon just large enough to cover AGND components. Do not make it any larger
than necessary. The AGND polygon should not run under any gate-drive traces since all AGND
connections should be on the other side of the IC, away from the driver pins.
AGND
AGND - PGND connection should be done away from the PGND pins so as not to be in the path of
AGND - PGND
the gate-drive currents. A good location is near to the V
pin.
CC
MAX17511/
MAX174511C/
MAX17511N/MAX17511T
Exposed Pad
Although the exposed pad is both AGND and PGND, it is better to define the exposed pad in the
schematics as PGND. This allows the exposed pad vias to connect to the PGND plane, providing a
low-impedance path for the gate-drive currents.
Place the power components close to keep the current loop small. Avoid large LX nodes. Use
multiple vias to keep the impedance low and to carry the high currents.
Power Components
7± _____________________________________________________________________________________
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
FEATURE
3-/2-/1-Phase + 1-Phase, 0V V
for Reg A,
3-/2-/1-Phase + 1-Phase, 1.1V V
BOOT
BOOT
MAX17.11CGTL+
-40NC to +105NC
40 TQFN-EP*
0.9V V
for Reg B
BOOT
MAX17.11NGTL+
MAX17.11TGTL+
-40NC to +105NC
-40NC to +105NC
40 TQFN-EP*
40 TQFN-EP*
3-/2-/1-Phase + 1-Phase, OVP Disabled
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www0maxim-ic0com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO0
LAND
PATTERN NO0
40 TQFN-EP
48 TQFN-EP
T4055+2
T4866+1
21-±14±
21-±141
9±-±±±2
9±-±±.7
______________________________________________________________________________________ 71
Dual-Output, 3-/2-/1-Phase + 2-/1-Phase
Quick-PWM Controllers for VR12/IMVP7
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1/11
Initial release
—
1, 2, 4, 5, 6,
7, 10, 12, 13,
14, 19, 20, 21,
Added the MAX17511C to the data sheet; updated the Absolute Maximum Ratings
1
7/11
to include Package Thermal Characteristics; changed the conditions in the Electrical 25,27, 28, 32,
Characteristics for the Valley Current-Limit Threshold Voltage sections.
33, 35, 38, 40,
49, 52, 53, 58,
62, 64
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
72
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
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