MAX17524ATJ+ [MAXIM]
4.5V to 60V, 3A, Dual-Output, High-Efficiency,Synchronous Step-Down DC-DC Converter;
| 型号： | MAX17524ATJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4.5V to 60V, 3A, Dual-Output, High-Efficiency,Synchronous Step-Down DC-DC Converter |
| 文件： | 总24页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
General Description
Benefits and Features
● Reduces External Components and Total Cost
• No Schottky - Synchronous Operation
• Internal Compensation Components
The MAX17524 dual-output, high-efficiency, high-voltage,
synchronous step-down DC-DC converter with integrated
high-side MOSFETs operates over an input-voltage range
of 4.5V to 60V. The device can deliver up to 3A on each
output and generates output voltages from 0.9V up to
• All-Ceramic Capacitors, Compact Layout
● Reduces Number of DC-DC Regulators to Stock
• Wide 4.5V to 60V Input
90% of V . This device features internal compensation.
IN
• Adjustable Output Range from 0.9V up to 90% of
The MAX17524 uses peak current-mode control, and can
be operated in pulse-width modulation (PWM), pulse-fre-
quency modulation (PFM), and discontinuous-conduction
mode (DCM) to enable high efficiency under light-load
conditions.
V
IN
• Delivers up to 3A on Each Output Over the Tem-
perature Range
• 100kHz to 1.1MHz Adjustable Frequency with
External Clock Synchronization
The feedback-voltage regulation accuracy is accurate to
within ±1.4% over -40°C to +125°C. The device is avail-
able in a 32-pin (5mm x 5mm) Thin QFN (TQFN) pack-
age. Simulation models are available.
• Available in a 32-Pin, 5mm x 5mm TQFN Package
● Independent Input-Voltage Pins for Each Output
● Reduces Power Dissipation
• Peak Efficiency of 90.3%
Applications
• PFM and DCM Modes Enable Enhanced Light-
Load Efficiency
• Auxiliary Bootstrap Supply (EXTVCC) for Improved
Efficiency
● Industrial Control Power Supplies
● General-Purpose Point-of-Load
● Distributed Supply Regulation
● Base Station Power Supplies
● Wall Transformer Regulation
● High-Voltage Single-Board Systems
• 5.2μA Shutdown Current
● Operates Reliably in Adverse Industrial Environments
• Hiccup-Mode Overload Protection
• Independent Adjustable Soft-Start Pin and Pro-
grammable EN/UVLO Pin for Each Output
• Monotonic Startup with Prebiased Output Voltage
• Built-in Independent Output-Voltage Monitoring
with RESET for Each Output
Ordering Information appears at end of data sheet.
• Overtemperature Protection
• High Industrial -40°C to +125°C Ambient Operating
Temperature Range / -40°C to +150°C Junction
Temperature Range
19-100201; Rev 0; 12/17
MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Absolute Maximum Ratings
IN_
V
to PGND_......................................................-0.3V to +65V
DL_ to PGND_ ...........................................-0.3V to V
+0.3V
CC_
PGND_ to SGND..................................................-0.3V to +0.3V
EXTVCC_ to SGND ..............................................-0.3V to +26V
EN/UVLO_ to SGND.............................................-0.3V to +65V
LX_ Total RMS Current ........................................................4.8A
Continuous Power Dissipation
(Multilayer Board) (T = +70°C,
A
FB_ , V
to SGND ..............................................-0.3V to +6V
derate 34.5mW/°C above +70°C.)..........................2758.6mW
Output Short-Circuit Duration....................................Continuous
Operating Temperature Range (Note 1)..............-40°C to 125°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
CC_
RESET_, SS_, MODE/SYNC_, CF_, RT to SGND ........-0.3V to
V
+0.3V
CC_
BST_ to PGND_....................................................-0.3V to +70V
BST_ to LX_............................................................-0.3V to +6V
BST_ to V
........................................................-0.3V to +65V
CC_
LX_ to PGND_............................................ -0.3V to V
+ 0.3V
IN_
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 32 TQFN
Package Code
T3255+4C
21-0140
90-0012
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD (Note 2)
Junction to Ambient (θ
)
23ºC/W
1.7ºC/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Note 1: Junction temperature greater than +125°C degrades operating lifetimes.
Note 2: Package thermal resistances were obtained using the MAX17524 Evaluation Kit (EV kit).
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics
(V = V
= 24V, R = Open (f
= 450 kHz), C
= 2.2μF, V
= V
= V
= V
= 0V, V = 1V,
EXTVCC FB
IN
EN/UVLO
RT
SW
VCC
MODE/SYNC
SGND
PGND
LX = SS = RESET = Open, V
to V = 5V, T = -40°C to 125°C, unless otherwise noted. Typical values are at T = +25°C. All volt-
BST
LX A A
ages are referenced to SGND and the data is intended for both the converters, unless otherwise noted.) (Note 3)
PARAMETER
INPUT SUPPLY (IN)
Input-Voltage Range
Input-Shutdown Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
4.5
60
V
IN
I
V
= 0V (shutdown mode)
5.2
1400
1400
1.36
5
9.5
μA
IN-SH
EN/UVLO
MODE/SYNC = Open
MODE/SYNC = Open, R = 22.1kΩ
I
μA
Q_PFM
RT
Input-Quiescent Current
I
DCM Mode, V = 0.1V
2
Q_DCM
LX
mA
I
V
= 0.8V, EXTVCC = DL = Open
Q_PWM
FB
ENABLE/UVLO (EN/UVLO)
V
V
V
rising
falling
1.19
1.216
1.089
1.245
1.116
ENR
EN/UVLO
EN/UVLO Threshold
V
V
V
1.065
ENF
EN/UVLO
V
(LDO)
CC
1mA ≤ I
≤ 20mA
4.75
4.75
50
5
5
5.25
5.25
140
0.4
VCC
V
Output-Voltage Range
V
CC
CC
6V ≤ V ≤ 60V, I
= 1mA
IN
VCC
V
V
Current Limit
Dropout
I
V
V
V
V
= 4.3V, V = 6V
90
mA
V
CC
VCC(MAX)
CC
IN
V
= 4.5V, I
= 25mA
CC
CC-DO
IN
VCC
V
rising
falling
4.09
3.69
4.2
3.8
4.29
3.89
CC_UVR
CC
CC
V
UVLO
V
CC
V
CC_UVF
EXTVCC
EXTVCC Switchover Threshold
V
rising
4.56
4.7
4.84
0.26
V
V
EXTVCC
EXTVCC Switchover Voltage
Hysteresis
0.205
0.232
HIGH-SIDE MOSFET AND LOW-SIDE DRIVER
High-Side nMOS On-
Resistance
R
I
= 0.3A, sourcing
85
1
180
+4
mΩ
μA
DS-ONH
LX
V
= (V
+1V) to (V - 1V),
LX
PGND IN
LX Leakage Current
I
-4
4.7
LX_LKG
T = +25°C
A
SOFT-START (SS)
Charging Current
FEEDBACK (FB)
I
V
= 0.5V
5
5.3
μA
SS
SS
MODE/SYNC = SGND or MODE/SYNC
= V
CC
0.888
0.9
0.912
FB Regulation Voltage
FB Input-Bias Current
V
V
FB-REG
MODE/SYNC = Open
0.9
0.915
0.943
+100
o
I
0 ≤ V ≤ 1V, T = 25 C
-100
nA
FB
FB
A
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics (continued)
(V = V
= 24V, R = Open (f
= 450 kHz), C
= 2.2μF, V
= V
= V
= V
= 0V, V = 1V,
EXTVCC FB
IN
EN/UVLO
RT
SW
VCC
MODE/SYNC
SGND
PGND
LX = SS = RESET = Open, V
to V = 5V, T = -40°C to 125°C, unless otherwise noted. Typical values are at T = +25°C. All volt-
BST
LX A A
ages are referenced to SGND and the data is intended for both the converters, unless otherwise noted.) (Note 3)
PARAMETER
MODE/SYNC
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
MODE/SYNC = V
(DCM mode)
V
- 0.6
M-DCM
CC
CC
MODE Threshold
V
MODE/SYNC = Open (PFM mode)
V
/2
V
M-PFM
CC
V
MODE/SYNC = SGND (PWM mode)
0.6
M-PWM
SYNC Frequency-Capture
Range
f
f
set by R
1.1 x f
1.4 x f
SW
SYNC
SW
RT
SW
SYNC Pulse Width
50
2
ns
V
V
IH
SYNC Threshold
V
0.8
IL
Number of Pulses Required to
Enter into SYNC Mode
8
CURRENT LIMIT
Peak Current-Limit Threshold
I
4.2
5.1
4.6
5.6
5.1
6.3
A
A
PEAK-LIMIT
Runaway Peak Current-Limit
Threshold
I
RUNAWAY-
LIMIT
PFM Peak Current-Limit
Threshold
I
MODE/SYNC = Open
1.15
A
PFM
MODE/SYNC = OPEN OR MODE/SYNC
= V
CC
-8
0
+8
60
Negative Current-Limit
Threshold
V
mV
NEG-LIM
MODE/SYNC = SGND
42
50
RT
R
R
R
R
= 100kΩ
= 22.1kΩ
= 8.25kΩ
= Open
97.5
430
950
420
105
454
112.5
478
RT
RT
RT
RT
Switching Frequency
f
kHz
V
SW
1100
450
1250
480
V
Undervoltage Trip Level to
FB
V
0.56
0.58
0.61
FB-HICF
Cause Hiccup
HICCUP Timeout
Minimum On-Time
Minimum Off-Time
LX Dead Time
(Note 4)
32768
90
Cycles
ns
t
140
165
ON-MIN
t
140
ns
OFF-MIN
LX
22
ns
DT
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics (continued)
(V = V
= 24V, R = Open (f
= 450 kHz), C
= 2.2μF, V
= V
= V
= V
= 0V, V = 1V,
EXTVCC FB
IN
EN/UVLO
RT
SW
VCC
MODE/SYNC
SGND
PGND
LX = SS = RESET = Open, V
to V = 5V, T = -40°C to 125°C, unless otherwise noted. Typical values are at T = +25°C. All volt-
BST
LX A A
ages are referenced to SGND and the data is intended for both the converters, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET
RESET Output-Level Low
V
110
200
100
mV
nA
I
= 10mA
RESETL
RESET
RESET Output-Leakage
Current
I
-100
90.4
93.4
T = T = 25ºC, V
= 5.5V
RESETLKG
A
J
RESET
FB Threshold for RESET
Assertion
V
V
falling
92.5
95.5
1024
94.6
97.7
%
%
FB-OKF
FB
FB
FB Threshold for RESET
Deassertion
V
V
rising
FB-OKR
RESET Delay after FB Reach-
es 95% Regulation
cycles
THERMAL SHUTDOWN (TEMP)
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
Temperature rising
165
10
°C
°C
Note 3: Electrical specifications are production tested at T = +25ºC. Specifications over the entire operating temperature range are
A
guaranteed by design and characterization.
Note 4: See the Overcurrent Protection (OCP)/Hiccup Mode section for more details
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics
(V
= V
= V
= V
= 24V, V
= V
= V
= 0V, C
= C
= 2.2μF, C
= C
= 0.1μF,
EN/UVLO1
IN1
EN/UVLO2
IN2
SGND
PGND1
PGND2
VCC1
VCC2
BST1
BST2
C
= C
= 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced
SS1
SS2
A
A
to SGND, unless otherwise noted.)
MAX17524, 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(PWM MODE, fSW = 450kHz)
MAX17524, 5V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(PWM MODE, fSW = 450kHz)
MAX17524, 5V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(PFM MODE, fSW = 450kHz)
toc02
toc03
toc01
100
90
80
70
60
50
40
30
20
10
0
100
90
100
90
80
70
60
50
40
30
20
10
0
80
VIN = 36V VIN = 48V
VIN = 24V
VIN = 12V
VIN = 6.5V
70
60
50
40
30
20
10
0
V
IN = 48V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 4.5V
VIN = 60V
V
IN = 48V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 6.5V
VIN = 60V
VIN = 60V
0.01
0.01
0
0.10
LOAD CURRENT (A)
1.00
0
1
2
3
0
1
2
3
LOAD CURRENT (A)
LOAD CURRENT (A)
MAX17524, 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(DCM MODE, fSW = 450kHz)
MAX17524, 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(PFM MODE, fSW = 450kHz)
MAX17524, 5V OUTPUT
EFFICIENCY vs. LOAD CURRENT
(DCM MODE, fSW = 450kHz)
toc06
toc04
toc05
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 60V
VIN = 48V
VIN = 36V
VIN = 60V
VIN = 48V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 4.5V
VIN = 60V
VIN = 48V
VIN = 36V
VIN = 24V
VIN = 12V
VIN = 4.5V
VIN = 24V
VIN = 12V
VIN = 6.5V
0.10
1.00
0.01
0.10
1.00
0.01
0.10
1.00
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
MAX17524, 5V OUTPUT
MAX17524, 5V OUTPUT
LOAD AND LINE REGULATION
(PWM MODE, fSW = 450kHz)
MAX17524, 3.3V OUTPUT
LOAD AND LINE REGULATION
(PWM MODE, fSW = 450kHz)
LOAD AND LINE REGULATION
(PFM MODE, fSW = 450kHz)
toc09
toc07
toc08
5.14
4.99
4.98
4.97
4.96
4.95
3.34
3.33
3.32
3.31
3.30
3.29
5.10
5.06
5.02
4.98
4.94
VIN = 6.5V
VIN = 12V
VIN = 36V
VIN = 12V
VIN = 60V
VIN = 36V
VIN = 12V
VIN = 60V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 4.5V
VIN = 24V
VIN = 48V
VIN = 6.5V
VIN = 24V
VIN = 48V
1
2
3
0
1
2
3
0
1
2
3
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 24V, V
= V
= V
= 0V, C
= C
= 2.2μF, C
= C
= 0.1μF,
EN/UVLO1
IN1
EN/UVLO2
IN2
SGND
PGND1
PGND2
VCC1
VCC2
BST1
BST2
C
= C
= 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced
SS1
SS2 A A
to SGND, unless otherwise noted.)
MAX17524, 5V OUTPUT
LOAD AND LINE REGULATION
(DCM MODE, fSW = 450kHz)
MAX17524, 3.3V OUTPUT
LOAD AND LINE REGULATION
(DCM MODE, fSW = 450kHz)
MAX17524, 3.3V OUTPUT
LOAD AND LINE REGULATION
(PFM MODE, fSW = 450kHz)
toc11
toc12
4.99
4.98
4.97
4.96
4.95
3.34
toc10
3.44
3.40
3.36
3.32
3.28
3.33
3.32
3.31
3.30
3.29
VIN = 4.5V
VIN = 12V
VIN = 36V
VIN = 60V
VIN = 12V
VIN = 60V
VIN = 36V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 48V
VIN = 24V
VIN = 6.5V
VIN = 6.5V
VIN = 24V
VIN = 48V
0
1
2
3
0.0
1.0
2.0
3.0
0
1
2
3
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
MAX17524, 5V OUTPUT
SOFT-START WITH PREBIAS VOLTAGE OF 2.5V
MAX17524, 5V OUTPUT
SOFT-START/SHUTDOWN FROM EN/UVLO
(fSW = 450kHz, PWM MODE, 3A LOAD)
MAX17524, 3.3V OUTPUT
SOFT-START/SHUTDOWN FROM EN/UVLO
(PWM MODE, 3A LOAD, fSW = 450kHz)
(PWM MODE, 5mA LOAD, fSW = 450kHz)
toc15
toc14
toc13
VEN/UVLO
5V/div
VEN/UVLO
VEN/UVLO
5V/div
2V/div
5V/div
2V/div
VOUT
VOUT
2V/div
5V/div
1A/div
VOUT
ILX
V
ILX
2A/div
5V/div
RESET
2A/div
5V/div
ILX
V
V
RESET
RESET
1ms/div
1ms/div
1ms/div
CONDITION: RESETIS PULLED UP TO VCC
CONDITION: RESETIS PULLED UP TO VCC
CONDITION: RESETIS PULLED UP TO VCC
MAX17524, 3.3V OUTPUT
SOFT-START WITH PREBIAS VOLTAGE OF 1.65V
MAX17524, 5V OUTPUT
STEADY STATE,
(PWM MODE, 3A LOAD, fSW = 450kHz)
MAX17524, 5V OUTPUT
STEADY STATE
(fSW = 450kHz, DCM MODE, 75mA LOAD)
(PWM MODE, 5mA LOAD, fSW = 450kHz)
toc17
toc18
toc16
VOUT(AC)
10mV/div
20mV/div
VOUT(AC)
VEN/UVLO
5V/div
VLX
VOUT
10V/div
2A/div
10V/div
VLX
1V/div
5V/div
1A/div
V
RESET
ILX
500mA/div
ILX
ILX
2µs/div
1ms/div
2µs/div
CONDITION: RESETIS PULLED UP TO VCC
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 24V, V
= V
= V
= 0V, C
= C
= 2.2μF, C
= C
= 0.1μF,
EN/UVLO1
IN1
EN/UVLO2
IN2
SGND
PGND1
PGND2
VCC1
VCC2
BST1
BST2
C
= C
= 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced
SS1
SS2
A
A
to SGND, unless otherwise noted.)
MAX17524, 3.3V OUTPUT
STEADY STATE
(fSW = 450kHz, DCM MODE, 75mA LOAD)
MAX17524, 3.3V OUTPUT
STEADY STATE
(fSW = 450kHz, PWM MODE, 3A LOAD)
MAX17524, 5V OUTPUT
STEADY STATE
(fSW = 450kHz, PFM MODE, 25mA LOAD)
toc21
toc20
toc19
VOUT(AC)
10mV/div
100mV/div
VOUT(AC)
VOUT(AC)
20mV/div
20V/div
VLX
VLX
VLX
10V/div
1A/div
10V/div
ILX
ILX
500mA/div
ILX
2A/div
40µs/div
2µs/div
2µs/div
MAX17524, 3.3V OUTPUT
STEADY STATE
(fSW = 450kHz, PFM MODE, 25mA LOAD)
MAX17524, 5V OUTPUT
LOAD TRANSIENT BETWEEN 0A AND 1.5A
MAX17524, 5V OUTPUT
LOAD TRANSIENT BETWEEN 1.5A AND 3A
(fSW = 450kHz, PWM MODE)
(fSW = 450kHz, PWM MODE)
toc22
toc23
toc24
VOUT(AC)
50mV/div
VOUT(AC)
VOUT(AC)
100mV/div
100mV/div
VLX
10V/div
1A/div
ILX
IOUT
IOUT
1A/div
2A/div
40µs/div
100µs/div
100µs/div
MAX17524, 3.3V OUTPUT
LOAD TRANSIENT BETWEEN 0A AND 1.5A
MAX17524, 5V OUTPUT
LOAD TRANSIENT BETWEEN 50mA AND 1.5A
MAX17524, 5V OUTPUT
LOAD TRANSIENT BETWEEN 50mA AND 1.5A
(fSW = 450kHz, PWM MODE)
(fSW = 450kHz, PFM MODE)
(fSW = 450kHz, DCM MODE)
toc27
toc25
toc26
VOUT(AC)
VOUT(AC)
VOUT(AC)
100mV/div
200mV/div
100mV/div
IOUT
IOUT
1A/div
1A/div
IOUT
1A/div
100µs/div
400µs/div
400µs/div
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 24V, V
= V
= V
= 0V, C
= C
= 2.2μF, C
= C
= 0.1μF,
EN/UVLO1
IN1
EN/UVLO2
IN2
SGND
PGND1
PGND2
VCC1
VCC2
BST1
BST2
C
= C
= 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced
SS1
SS2 A A
to SGND, unless otherwise noted.)
MAX17524, 3.3V OUTPUT
LOAD TRANSIENT BETWEEN 50mA AND 1.5A
MAX17524, 3.3V OUTPUT
LOAD TRANSIENT BETWEEN 50mA AND 1.5A
MAX17524, 3.3V OUTPUT
LOAD TRANSIENT BETWEEN 1.5A AND 3A
(fSW = 450kHz, DCM MODE)
(fSW = 450kHz, PFM MODE)
(fSW = 450kHz, PWM MODE)
toc30
toc29
toc28
VOUT(AC)
VOUT(AC)
100mV/div
100mV/div
VOUT(AC)
100mV/div
IOUT
1A/div
IOUT
1A/div
IOUT
1A/div
200µs/div
400µs/div
100µs/div
MAX17524, 5V OUTPUT
OVERLOAD PROTECTION
(PWM MODE, fSW = 450kHz)
MAX17524, 3.3V OUTPUT
OVERLOAD PROTECTION
(PWM MODE, fSW = 450kHz)
MAX17524, 5V OUTPUT
EXTERNAL CLOCK SYNCHRONIZATION WITH 495kHz
(PWM MODE, 3A LOAD)
toc31
toc32
toc33
VOUT
2V/div
2A/div
VOUT
2V/div
VLX
20V/div
VSYNC
5V/div
VOUT(AC)
20mV/div
ILX
ILX
2A/div
ILX
2A/div
4µs/div
20ms/div
20ms/div
MAX17524, 5V OUTPUT
EXTERNAL CLOCK SYNCHRONIZATION WITH 630kHz
(PWM MODE, 3A LOAD)
MAX17524, 3.3V OUTPUT
EXTERNAL CLOCK SYNCHRONIZATION WITH 495kHz
(PWM MODE, 3A LOAD)
toc34
toc35
VLX
VLX
20V/div
20V/div
VSYNC
VSYNC
5V/div
5V/div
VOUT(AC)
VOUT(AC)
20mV/div
20mV/div
ILX
ILX
2A/div
2A/div
4µs/div
4µs/div
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
(V
= V
= V
= V
= 24V, V
= V
= V
= 0V, C
= C
= 2.2μF, C
= C
= 0.1μF,
EN/UVLO1
IN1
EN/UVLO2
IN2
SGND
PGND1
PGND2
VCC1
VCC2
BST1
BST2
C
= C
= 5600pF, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced
SS1
SS2
A
A
to SGND, unless otherwise noted.)
MAX17524, 5V OUTPUT
CLOSED-LOOP BODE PLOT
(PWM MODE, fSW = 450kHz, 3A LOAD)
MAX17524, 3.3V OUTPUT
EXTERNAL CLOCK SYNCHRONIZATION WITH 630kHz
(PWM MODE, 3A LOAD)
toc37
50
25
120
60
toc36
PHASE
VLX
20V/div
0
0
VSYNC
5V/div
GAIN
VOUT(AC)
20mV/div
-25
-50
-60
-120
CROSSOVER
FREQUENCY = 44.5kHz
PHASE MARGIN = 69.91°
ILX
2A/div
1k
10k
100k
4µs/div
FREQUENCY (Hz)
MAX17524, FIGURE 4
STARTUP IN COINCIDENT TRACKING MODE
MAX17524, 3.3V OUTPUT
CLOSED-LOOP BODE PLOT
(PWM MODE, fSW = 450kHz, 3A LOAD)
(3A LOAD ON BOTH CONVERTERS)
toc39
toc38
50
25
120
60
PHASE
10V/div
1V/div
1V/div
VIN1
0
0
GAIN
-25
-50
-60
-120
CROSSOVER
VOUT1
VOUT2
FREQUENCY = 44.6kHz
PHASE MARGIN = 64.91°
400µs/div
1k
10k
100k
FREQUENCY (Hz)
MAX17524, FIGURE 5
MAX17524, FIGURE 6
STARTUP IN RATIOMETRIC TRACKING MODE
(3A LOAD ON BOTH CONVERTERS)
toc40
STARTUP IN SEQUENTIAL TRACKING MODE
(3A LOAD ON BOTH CONVERTERS)
toc41
10V/div
5V/div
VOUT1
1V/div
1V/div
VIN1
5V/div
2V/div
V
V
RESET1
VOUT2
VOUT1
VOUT2
5V/div
RESET2
400µs/div
400µs/div
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Pin Configuration
TOP VIEW
24
PGND1
PGND2
1
2
3
4
5
6
7
8
23
IN1
IN1
IN2
22
IN2
21
20
19
18
V
V
CC2
CC1
MAX17524
EN/UVLO2
EXTCVCC2
SS2
EN/UVLO1
EXTVCC1
SS1
EP
17 CF2
CF1
13 14 15 16
9
11 12
10
TQFN
5mm x 5mm
Pin Description
PIN
NAME
FUNCTION
Power Ground Pin of the Converter 1. Connect the PGND1 pin externally to the power-ground plane.
1
PGND1
Connect the SGND and PGND1 pins together at the ground return path of the V
Refer to the MAX17524 EV kit data sheet for a layout example.
bypass capacitor.
CC1
Power-Supply Input for Converter 1. 4.5V to 60V Input-Supply Range. Connect the IN1 pins together.
Decouple to PGND1 with a 2.2μF capacitor; place the capacitor close to the IN1 and PGND1 pins. Refer
to the MAX17524 EV kit data sheet for a layout example.
2, 3
4
IN1
5V LDO Output for Converter 1. Bypass V
with a 1μF ceramic capacitance to SGND. LDO does not
CC1
V
CC1
support the external loading on V
.
CC1
Enable/Undervoltage Lockout Pin for Converter 1. Drive EN/UVLO1 high to enable the output of con-
verter 1. Connect to the center of the resistor-divider between V and SGND to set the input voltage at
IN1
5
6
EN/UVLO1
which converter 1 turns on. Connect to the V
disabling the converter.
pins for always-on operation. Pull lower than V
for
ENF
IN1
External Power-Supply Input for the Internal LDO of Converter 1. Applying a voltage between 4.84V and
24V at the EXTVCC1 pin bypasses the internal LDO and improves the overall efficiency. Add a local by-
EXTVCC1 passing cap (0.1μF) on EXTVCC1 pin to SGND and also, add a 4.7Ω resistor from buck converter output
node to EXTVCC1 pin to limit V bypass-cap discharge current during an output short-circuit condi-
CC1
tion. When EXTVCC1 is not used, connect it to SGND.
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Pin Description (continued)
PIN
NAME
FUNCTION
7
SS1
Soft-Start Input for Converter 1. Connect a capacitor from SS1 to SGND to set the soft-start time.
Compensator Output for Converter 1. At switching frequencies, lower than 450kHz, connect a capacitor
from CF1 to FB1. Leave CF1 open if the switching frequency is equal to, or more than 450kHz. See the
Loop Compensation section for more details.
8
9
CF1
FB1
Feedback Input for Converter 1. Connect FB1 to the center tap of an external resistor-divider from the
output node of converter 1 to SGND to set the output voltage. See the Adjusting Output Voltage section
for more details.
Programmable Switching Frequency Input. Connect a resistor from RT to SGND to set the switching
frequency of both the converters. Leave RT open for the default 450kHz frequency. See the Setting the
Switching Frequency (RT) section for more details.
10
11
RT
Open-Drain RESET1 Output. The RESET1 output is driven low if FB1 drops below 92.5% of its set value.
RESET1 goes high 1024 cycles after FB1 rises above 95.5% of its set value.
RESET1
Mode Selection and External Clock Synchronization Input for Converter 1. The MODE/SYNC1 Pin
configures the converter 1 to operate either in PWM, PFM or DCM modes of operation. Leave MODE/
SYNC1 unconnected for PFM operation (pulse skipping at light loads). Connect MODE/SYNC1 to SGND
MODE/
SYNC1
12
13
14
for constant-frequency PWM operation at all loads. Connect MODE/SYNC1 to V
for DCM operation
CC1
at light loads. MODE/SYNC1 can also be used to synchronize the converter 1 to an external clock irre-
spective of the operating condition of converter 2. See the Mode Selection and External Synchronization
(MODE/SYNC) section for more details.
SGND
Analog Ground
Mode Selection and External Clock Synchronization Input for Converter 2. The MODE/SYNC2 Pin
configures the converter 2 to operate either in PWM, PFM or DCM modes of operation. Leave MODE/
SYNC2 unconnected for PFM operation (pulse skipping at light loads). Connect MODE/SYNC2 to SGND
MODE/
SYNC2
for constant-frequency PWM operation at all loads. Connect MODE/SYNC2 to V
for DCM operation
CC2
at light loads. MODE/SYNC2 can also be used to synchronize the converter 2 to an external clock irre-
spective of the operating condition of converter 1. See the Mode Selection and External Synchronization
(MODE/SYNC) section for more details.
Open-Drain RESET2 Output. The RESET2 output is driven low if FB2 drops below 92.5% of its set value.
RESET2 goes high 1024 cycles after FB2 rises above 95.5% of its set value.
15
16
RESET2
Feedback Input for Converter 2. Connect FB2 to the center tap of an external resistor-divider from the
output node of converter 2 to SGND to set the output voltage. See the Adjusting Output Voltage section
for more details.
FB2
Compensator Output for Converter 2. At switching frequencies, lower than 450kHz, connect a capacitor
from CF2 to FB2. Leave CF2 open if the switching frequency is equal to, or more than 450kHz. See the
Loop Compensation section for more details.
17
18
CF2
SS2
Soft-Start Input for Converter 2. Connect a capacitor from SS2 to SGND to set the soft-start time.
External Power-Supply Input for the Internal LDO of Converter 2. Applying a voltage between 4.84V and
24V at the EXTVCC2 pin bypasses the internal LDO and improves efficiency. Add a local bypassing cap
19
EXTVCC2 (0.1μF) on EXTVCC2 pin to SGND and also add a 4.7Ω resistor from the buck converter output node to
the EXTVCC2 pin to limit V bypass-cap discharge current during an output short-circuit condition.
CC2
When EXTVCC2 is not used, connect it to SGND.
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Pin Description (continued)
PIN
NAME
FUNCTION
Enable/Undervoltage Lockout Pin for Converter 2. Drive EN/UVLO2 high to enable the output of con-
verter 2. Connect to the center of the resistor-divider between V
and SGND to set the input voltage at
IN2
20
EN/UVLO2
which converter 2 turns on. Connect to the V
disabling the converter.
pins for always-on operation. Pull lower than V
for
ENF
IN2
5V LDO Output for Converter 2. Bypass V
with a 1μF ceramic capacitance to SGND. LDO does not
CC2
21
V
CC2
support the external loading on V
.
CC2
Power-Supply Input for Converter 2. 4.5V to 60V Input-Supply Range. Connect the IN2 pins together.
Decouple to PGND2 with a 2.2μF capacitor; place the capacitor close to the IN2 and PGND2 pins. Refer
to the MAX17524 EV kit data sheet for a layout example.
22, 23
IN2
Power Ground Pin of the Converter 2. Connect the PGND2 pin externally to the power-ground plane.
24
25
PGND2
DL2
Connect the SGND and PGND2 pins together at the ground return path of the V
Refer to the MAX17524 EV kit data sheet for a layout example.
bypass capacitor.
CC2
Low-Side Gate Driver Output for Converter 2. Use DL2 pin to drive the gate of the low-side external
nMOSFET.
26, 27
28
LX2
BST2
BST1
LX1
Switching Node of Converter 2. Connect LX2 pins to the switching side of the inductor.
Boost Flying Capacitor of Converter 2. Connect a 0.1μF ceramic capacitor between BST2 and LX2.
Boost Flying Capacitor of Converter 1. Connect a 0.1μF ceramic capacitor between BST1 and LX1.
Switching Node of Converter 1. Connect LX1 pins to the switching side of the inductor.
29
30, 31
Low-Side Gate Driver Output for Converter 1. Use DL1 pin to drive the gate of the low-side external
nMOSFET.
32
–
DL1
EP
Exposed Pad. Always connect EP to the SGND pin of the IC. Also, connect EP to a large SGND plane
with several thermal vias for best thermal performance. Refer to the MAX17524 EV kit data sheet for an
example of the correct method for EP connection and thermal vias.
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Functional Diagram
MAX17524
LDO
V
CC1
BST1
SELECT
IN1
INLDO
EXTVCC1
SGND1
LDO
ENOK1
1.216V
EN/UVLO1
CF1
LX1
HICCUP1
PWM/PFM/DCM
HICCUP LOGIC
V
CC1
FB1
ERROR AMPLIFIER
DL1
V
CC1
/LOOP
COMPEMSATION
SWITCHOVER
LOGIC
5µA
PGND1
SS1
ENOK1
FB1
MODE/
SYNC1
RESET
LOGIC
MODE
SELECTION
LOGIC
HICCUP1
RESET1
RT
CURRENT SENSE
OSCILLATOR
LDO
SLOPE
COMPENSATION
V
CC2
BST2
IN2
SELECT
INLDO
EXTVCC2
SGND2
LDO
ENOK2
1.216V
EN/UVLO2
CF2
LX2
HICCUP2
PWM/PFM/DCM
HICCUP LOGIC
V
CC2
FB2
ERROR AMPLIFIER
DL2
V
CC2
/LOOP
COMPENSATION
SWITCHOVER
LOGIC
5µA
PGND2
SS2
MODE/
SYNC2
ENOK2
FB2
MODE
SELECTION
LOGIC
RESET
LOGIC
HICCUP2
RESET2
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
switching frequency programmed by the resistor con-
nected at the RT pin. The external clock signals on the
Detailed Description
The MAX17524 dual-output, high-voltage, synchronous
step-down DC-DC converter with integrated high-side
MOSFETs operates over an input-voltage range of 4.5V
MODE/SYNC pins can have different frequency, but with
in 1.1 × f and 1.4 × f When an external clock is
SW
SW.
applied to MODE/SYNC pins, the internal oscillator fre-
quency changes to external clock frequency (from the
original frequency based on the RT setting) after detecting
8 external clock edges. When the external clock is applied
on-fly then the converter operates in PWM mode during
synchronization operation irrespective of the initial mode.
After the exit from external synchronization, the converter
enters into its original mode, which was set before syn-
chronization. Only if the initial mode is PFM, after the exit
from external synchronization, the part enters into DCM
mode initially and after 32 internal clock cycles, the part
enters PFM mode. MODE/SYNC pin of one converter can
be synchronized to the external clock irrespective of the
MODE/SYNC condition of the other converter. The mini-
mum external clock pulse-width high should be greater
than 50ns. See the MODE/SYNC section in the Electrical
Characteristics table for details.
to 60V. Output voltages from 0.9 up to 90% of V can be
IN
generated, and 3A load on each output can be delivered
by the device. Each converter features internal compen-
sation. The feedback-voltage regulation accuracy is accu-
rate to within ±1.4% over -40°C to +125°C.
The MAX17524 features a peak-current-mode control
architecture. Internal transconductance error amplifiers
produce integrated-error voltages at two internal nodes,
which set the duty cycle using PWM comparators, high-
side current-sense amplifiers, and slope-compensation
generators. At each rising edge of the clock, the high-side
MOSFETs turn on and remain on until either the appropri-
ate or maximum duty cycle is reached, or the peak current
limit is detected. During the high-side MOSFETs' on-time,
the inductor currents ramp up. During the second half of
the switching cycle, high-side MOSFETs turn off and the
low-side MOSFETs turn on. The inductors release the
stored energy as their currents ramp down and provide
current to the outputs.
PWM Mode Operation
In PWM mode, the inductor current is allowed to go nega-
tive. PWM operation provides constant frequency opera-
tion at all loads, and is useful in applications sensitive to
switching frequency. However, the PWM mode of opera-
tion gives lower efficiency at light loads compared to PFM
and DCM modes of operation.
The MAX17524 features a RT pin to program the switch-
ing frequency and two MODE/SYNC pins to program
the mode of operation and to synchronize to an external
clock. The device also features independent adjustable-
input undervoltage lockout, adjustable soft-start, open-
drain RESET, and auxiliary bootstrap LDO for improved
efficiency.
PFM Mode Operation
PFM mode of operation disables negative inductor cur-
rent and additionally skips pulses at light loads for high
efficiency. In PFM mode, the inductor current is forced to
Mode Selection and External Synchronization
(MODE/SYNC)
The MAX17524 features two independent mode selec-
tion pins for the two converters. The logic state of the
a fixed peak of I
(1.15A (typ)) every clock cycle until
PFM
the output rises to 103.5% of the set nominal output volt-
age. Once the output reaches 103.5% of the set nominal
output voltage, both the high-side and low-side FETs are
turned off and the converter enters hibernate operation
until the load discharges the output to 101% of the set
nominal output voltage. Most of the internal blocks are
turned off in hibernate operation to save quiescent cur-
rent. After the output falls below 101% of the set nominal
output voltage, the converters come out of hibernate
operation, turn on all internal blocks, and again com-
mence the process of delivering pulses of energy to the
output until it reaches 103.5% of the set nominal output
voltage. The advantage of the PFM mode is higher effi-
ciency at light loads because of lower quiescent current
drawn from supply. The disadvantage is that the output-
voltage ripple is higher compared to PWM or DCM modes
of operation and switching frequency is not constant at
light loads.
MODE/SYNC pin is latched when V
and EN/UVLO
CC
voltages exceed the respective UVLO rising thresholds
and all internal voltages are ready to allow LX switching.
If the state of the MODE/SYNC pin is open at power-up,
the converter operates in PFM mode at light loads. If the
voltage at the MODE/SYNC pin is lower than V
at
M-PWM
power-up, the converter operates in constant-frequency
PWM mode at all loads. If the voltage at the MODE/SYNC
pin is higher than V
at power-up, the converter
M-DCM
operates in constant-frequency DCM mode at light loads.
State changes on the MODE/SYNC pin are ignored dur-
ing normal operation.
The internal clocks of the MAX17524 can be synchro-
nized to external clock signals on the MODE/SYNC
pins. The external synchronization clock frequency must
be between 1.1 × f
and 1.4 × f , where f
is the
SW
SW
SW
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
DCM Mode Operation
Setting the Switching Frequency (RT)
DCM mode of operation features constant frequency
operation down to lighter loads than PFM mode, not
by skipping pulses, but by disabling negative inductor
current at light loads. DCM operation offers efficiency
performance that lies between PWM and PFM modes.
The output-voltage ripple in DCM mode is comparable to
PWM mode and relatively lower compared to PFM mode.
The switching frequency of both the converters can be
programmed from 100kHz to 1.1MHz by using a resis-
tor connected from the RT pin to SGND. The switching
frequency (f ) is related to the resistor connected at the
SW
RT pin (R ) by the following equation:
RT
10500
R
≅
−1.23
RT
f
SW
Linear Regulator (V
and EXTVCC)
CC
The MAX17524 has two internal LDO (Low-dropout)
regulators for each converter that power V . One LDO
Where R is in kΩ and f
is in kHz. Leaving the RT pin
RT
SW
open makes the converters operate at the default switch-
ing frequency of 450kHz. See Table 1 for RT resistor
values for a few common switching frequencies.
CC
is powered from V and the other LDO is powered
IN
from EXTVCC. Only one of the two LDOs is in opera-
tion at a time depending on the voltage levels present
Operating Input-Voltage Range
at the EXTVCC pin. When V
is above its UVLO and
CC
The minimum and maximum operating input voltages for
a given output-voltage setting should be calculated as
follows:
if EXTVCC is greater than 4.7V (typ), internal V
is
CC
powered by EXTVCC and LDO from V is disabled.
IN
If EXTVCC is less than 4.7V, V
is powered up from
CC
V . Powering V
IN
from EXTVCC increases efficiency
CC
V
+ I
× R
+ R
DCR(MAX) DS-ONL(MAX)
at higher input voltages. EXTVCC voltage should not
exceed 24V.
(
)
)
OUT
(
OUT MAX
(
)
V
=
IN MIN
(
)
1− f
× t
(
)
SW MAX
OFF-MIN MAX
(
)
(
)
Typical V
output voltage is 5V. Bypass V
to SGND
powers
CC
CC
CC
+ I
× R
-R
with a 2.2μF low-ESR ceramic capacitor. V
(
)
(
DS-ONH(MAX) DS-ONL(MAX)
)
OUT MAX
(
)
the internal blocks and the low-side MOSFET driver and
recharges the external bootstrap capacitor. Both LDOs
can source up to 90mA (typ). The MAX17524 employs
an undervoltage-lockout circuit that forces both the con-
V
OUT
V
=
IN MAX
(
)
f
× t
SW MAX
ON-MIN MAX
(
)
(
)
verters off when V
converter can be immediately re-enabled when V
falls below V
. The buck
CC
CC_UVF
where:
>
CC
V
I
= Steady-state output voltage
= Maximum load current
OUT
V
. The 400mV UVLO hysteresis prevents chat-
CC_UVR
tering on power-up and power-down.
OUT(MAX)
R
= Worst-case DC resistance of the inductor
Add a local bypassing cap of 0.1μF on the EXTVCC pin
to SGND. Also, add a 4.7Ω resistor from buck converter
DCR(MAX)
f
t
= Maximum switching frequency
SW(MAX)
output node to the EXTVCC pin to limit V
bypass cap
CC
= Worst-case minimum switch off-time
OFF-MIN(MAX)
discharge current and to protect the EXTVCC pin from
reaching its absolute maximum rating (-0.3V) during
output short-circuit condition. In applications where the
buck-converter output is connected to the EXTVCC pin,
if the output is shorted to ground, then the transfer from
EXTVCC to internal LDO happens seamlessly without
any impact to the normal functionality. Connect EXTVCC
pin to SGND when the pin is not being used.
(165 ns)
t
= Worst-case minimum switch on-time
ON-MIN(MAX)
(140 ns)
R
and R
= Worst-case on-
DS-ONH(MAX)
DS-ONL(MAX)
state resistances of the external low-side and internal
high-side MOSFETs, respectively.
Table 1. Switching Frequency vs. RT Resistor
SWITCHING FREQUENCY (kHz)
RT RESISTOR (kΩ)
100
200
105
51.1
450
Open or 22.1
8.25
1100
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Overcurrent Protection (OCP)/Hiccup Mode
Thermal-Shutdown Protection
MAX17524 has a robust overcurrent-protection (OCP)
scheme that protects the device under overload and out-
put short-circuit conditions. A cycle-by-cycle peak current
limit turns off the high-side MOSFET whenever the high-
The MAX17524 features independent thermal-shutdown
protection for both the converters to limit the junction tem-
perature. When the junction temperature of the converter
exceeds +165ºC, an on-chip thermal sensor shuts down
the converter, allowing the converter to cool. The thermal
sensor turns the converter on again after the junction
temperature cools by 10ºC. Soft-start gets deasserted
during thermal shutdown and it initiates the startup opera-
tion when the converter recovers from thermal shutdown.
Carefully evaluate the total power dissipation (see the
Power Dissipation section) to avoid unwanted triggering
of the thermal shutdown during normal operation.
side switch current exceeds an internal limit of I
PEAK-
(4.6A (typ)). A runaway peak current limit on the
LIMIT
high-side switch current at I
(5.6A (typ))
RUNAWAY-LIMIT
protects the device under high input voltage, short-circuit
conditions when there is insufficient output voltage avail-
able to restore the inductor current that built up during the
on period of the step-down converter. One occurrence of
the runaway current limit triggers a hiccup mode. In addi-
tion, if, due to a fault condition, feedback voltage drops
Applications Information
to V
any time after soft-start is complete and hic-
FB-HICF
cup mode is triggered. In hiccup mode, the converter is
protected by suspending switching for a hiccup timeout
period of 32,768 clock cycles of half the programmed
switching frequency. Once the hiccup timeout period
expires, soft-start is attempted again. Note that when soft-
start is attempted under overload conditions, if feedback
Input-Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor RMS current requirement (I
defined by the following equation:
) is
RMS
voltage does not exceed V
, the device continues
FB-HICF
to switch at half the programmed switching frequency for
the time duration of the programmed soft-start time and
1024 clock cycles. Hiccup mode of operation ensures low
power dissipation under output short-circuit conditions.
V
× ( V − V
OUT
)
OUT
IN
I
= I
×
OUT(MAX)
RMS
V
IN
where, I
is the maximum load current. I
RMS
has
OUT(MAX)
a maximum value when the input voltage equals twice the
RESET Output
output voltage (V = 2 x V
), so
IN
OUT
The MAX17524 includes two independent RESET com-
parators to monitor the status of the output voltages of the
two converters. The open-drain RESET output requires
an external pullup resistor. RESET goes high (high
impedance) 1024 switching cycles after the regulator
output increases above 95% of the designed set nominal
output voltage. RESET goes low when the regulator out-
put voltage drops to below 92% of the nominal regulated
voltage. RESET also goes low during thermal shutdown
I
OUT MAX
(
)
I
=
.
RMS MAX
(
)
2
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
long-term reliability. Use low-ESR ceramic capacitors with
high-ripple-current capability at the input. X7R capacitors
are recommended in industrial applications for their tem-
perature stability. Calculate the input capacitance using
the following equation:
or when the EN/UVLO pin goes below V
.
ENF
Prebiased Output
I
When the converter starts into a prebiased output, both
the high-side and the low-side switches are turned off so
that the converter does not sink current from the output.
High-side and low-side switches do not start switching
until the PWM comparator commands the first PWM
pulse, at which point switching commences. The output
voltage is then smoothly ramped up to the target value in
alignment with the internal reference.
OUT(MAX)× D× 1−D
(
)
C
=
IN
η× f
× ∆V
SW
IN
where:
D = V
/V is the duty ratio of the converter
OUT IN
f
= Switching frequency
SW
ΔV = Allowable input-voltage ripple
IN
η = Efficiency
Maxim Integrated
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Select a low-loss inductor closest to the calculated value
with acceptable dimensions and having the lowest pos-
In applications where the source is located distant from
the device input, an appropriate electrolytic capacitor
should be added in parallel to the ceramic capacitor
to provide necessary damping for potential oscillations
caused by the inductance of the longer input power path
and input ceramic capacitor.
sible DC resistance. The saturation current rating (I
)
SAT
of the inductor must be high enough to ensure that
saturation can occur only above the peak current-limit
(I
).
PEAK-LIMIT
Output-Capacitor Selection
Low-Side MOSFET Selection
X7R ceramic output capacitors are preferred due to their
stability over temperature in industrial applications. The
output capacitors are usually sized to support a step load
of 50% of the maximum output current in the application,
so the output-voltage deviation is contained to 3% of the
output-voltage change. The minimum required output
capacitance can be calculated as follows:
The MAX17524 requires an external nMOSFET for each
converter to operate and the low-side gate drive output DL
pin drives the nMOSFET. The key selection parameters to
select the nMOSFET include:
● Maximum Drain-Source Voltage (V
)
DS-MAX
● Miller Plateau Voltage during all operating conditions
< 3.5V
I
× t
RESPONSE
1
2
STEP
● Low Drain-Source On-State Resistance (R
)
C
=
×
DS(ON)
OUT
∆V
OUT
● Total Gate Charge (Q )
g
0.33
● Output Capacitance (C
)
t
≅
oss
RESPONSE
f
C
● Power-Dissipation Rating and Package Thermal
Resistance
where:
The nMOSFET must be of logic-level type with guaran-
teed on-state resistance specification at V ≈ 4.5V. It
is also important that the chosen nMOSFET has suitable
dynamic parameters so that the MAX17524 is able to turn
I
t
= Load current step
STEP
GS
= Response time of the controller
= Allowable output-voltage deviation
RESPONSE
ΔV
OUT
f
= Target closed-loop crossover frequency
it on and off within the specified dead time (LX ). Ensure
C
DT
that the losses in the selected MOSFET do not exceed its
power rating. Using a low body diode reverse recovery
Select f to be 1/10th of f
less than or equal to 500kHz. If the switching frequency is
if the switching frequency is
C
SW
charge (Q ) MOSFET reduces the converter loss.
rr
more than 500kHz, select f to be 50kHz. Actual derating of
C
ceramic capacitors with DC bias voltage must be considered
while selecting the output capacitor. Derating curves are
available from all major ceramic capacitor manufacturers.
The negative current capability of the low-side MOSFET
is limited by V
. V
translates to negative
NEG-LIM NEG-LIM
current limit (I ) by the following relation:
NEG-LIM
V
= I
× R
NEG-LIM
NEG-LIM DS(ON)LS
Adjusting Output Voltage
where R
side MOSFET.
is the on-state resistance of the low-
Set the output voltage of each converter with a resistive
voltage-divider connected from the output-voltage node
DS(ON)LS
(V
) to SGND (see Figure 1). Connect the center node
OUT
Inductor Selection
Three key inductor parameters must be specified for
operation with the device: inductance value (L), inductor
of the divider to the FB pin. Use the following procedure
to choose the resistive voltage-divider values:
Calculate resistor R
follows:
from the output to the FB pin as
TOP
saturation current (I
) and DC resistance (R
). The
SAT
DCR
switching frequency and output voltage determine the
inductor value (L) in Henry as follows:
3
301×10
R
=
TOP
f
x C
OUT_SEL
0.9× V
OUT
(
)
C
L =
f
SW
where:
is in kΩ
R
where V
is the output voltage in V and f
is the
SW
TOP
OUT
switching frequency in Hz.
f
= Crossover frequency is in kHz
C
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
The soft-start time (t ) is related to the capacitor con-
SS
V
OUT
nected at SS (C ) by the following equation:
SS
C
SS
R
TOP
t
=
SS
−6
5.55×10
FB
For example, to program a 1ms soft-start time, a 5.6nF
capacitor should be connected from the SS pin to SGND.
Note that during start-up, the device operates at half the
programmed switching frequency until the output voltage
reaches 67% of set output nominal voltage.
R
BOT
SGND
Figure 1. Setting the Output Voltage
Setting the Input Undervoltage-Lockout Level
The MAX17524 features two independent EN/UVLO pins
for the two converters. Each EN/UVLO pin has an adjust-
able input undervoltage-lockout level. Set the voltage at
which the converter turns on with a resistive voltage-divid-
C
= Actual capacitance of the selected output
OUT_SEL
capacitor at DC-bias voltage in μF.
Calculate resistor R
follows:
from the FB pin to SGND as
BOT
er connected from V to SGND as shown in Figure 2.
IN
R
V
× 0.9
− 0.9
Connect the center node of the divider to EN/UVLO.
Choose R1 to be 3.3MΩ and then calculate R2 as follows:
TOP
OUT
R
=
BOT
(
)
R
is in kΩ.
R1×1.216
R2 =
BOT
V
−1.216
(
)
INU
Loop Compensation
The MAX17524 is internally loop compensated. However,
if the switching frequency is less than 450kHz, connect a
where V
is the input-voltage level at which the con-
INU
verter is required to turn on. Ensure that V
than 0.8 x V
is higher
INU
0402 capacitor (C ) between the CF pin and the FB pin.
F
to avoid hiccup during slow power up
OUT
Use Table 2 to select the value of C .
F
(slower than soft-start)/power down. If the EN/UVLO pin is
driven from an external signal source, a series resistance
of minimum 1kΩ is recommended to be placed between
the output pin of signal source and the EN/UVLO pin, to
reduce voltage ringing on the line.
Soft-Start Capacitor Selection
The MAX17524 implements independent adjustable soft-
start operation to reduce inrush currents for both the con-
verters. A capacitor connected from the SS pin to SGND
programs the soft-start time. The selected output capaci-
tance (C ) and the output voltage (V ) deter-
OUT_SEL OUT
mine the minimum required soft-start capacitor as follows:
V
IN
−6
C
≥ 28×10 × C
× V
OUT_SEL OUT
R1
R2
SS
EN/UVLO
Table 2. Selection of Capacitor C
F
SWITCHING FREQUENCY
C (pF)
F
RANGE (kHz)
SGND
Figure 2. Setting the Input Undervoltage Lockout
200 to 300
2.2
1.2
300 to 450
Maxim Integrated
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
If the application has a thermal-management system that
ensures that the exposed pad of the device is maintained
Power Dissipation
At a particular operating condition, the power losses that
lead to temperature rise of the part are estimated as
follows:
at a given temperature (T ) by using proper heat
EP(MAX)
sinks, then the junction temperature of the device can be
estimated at any given maximum ambient temperature as:
P
= P
IC_LOSS1
+ P
IC_LOSS2
IC_LOSS
T
= T
+ θ ×P
J(MAX)
EP(MAX)
JC
IC_LOSS
1
Note: Junction temperatures greater than +125°C
degrades operating lifetimes.
P
= P
×
−1
IC_LOSS1
OUT1
ç1
2
− I
× R
− P
PCB Layout Guidelines
)
(
OUT1
DCR1
ACLOSS_L1
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due to
the high di/dt of the currents. Since inductance of a cur-
rent-carrying loop is proportional to the area enclosed by
the loop, if the loop area is made very small, inductance
is reduced. Additionally, small-current loop areas reduce
radiated EMI.
2
− I
× R
× 1− D
1
(
)
)
(
OUT1
DS_ON1(LS)
1
− V
×
Q
+ Q
× f
SW
IN1
oss1
rr1
2
P
= V
×I
OUT1 OUT1
OUT1
The expressions for P
and P
, where:
are same as
OUT2
IC_LOSS2
A ceramic input filter capacitor should be placed close
to the IN pins of the IC. This eliminates as much trace
inductance effects as possible and gives the IC a cleaner
of P
and P
IC_LOSS1
OUT1
P
OUT_
= Output power of the converter.
voltage supply. A bypass capacitor at the V
pin also
CC
η_ = Efficiency of the converter.
should be placed close to the pin to reduce effects of trace
impedance.
R
= DC resistance of the inductor (see the Typical
DCR_
Operating Characteristics for more information on effi-
When routing the circuitry around the IC, the analog small
signal ground and the power ground for switching cur-
rents must be kept separate. They should be connected
together at a point where switching activity is minimum.
This helps keep the analog ground quiet. The ground
plane should be kept continuous (unbroken) as far as
possible. No trace carrying high switching current should
be placed directly over any ground plane discontinuity.
ciency at typical operating conditions).
P
= AC loss of the inductor.
ACLOSS_L_
R
= On-state resistance of the low side
DS_ON_(LS)
MOSFET.
Q
rr_
= Body-diode reverse-recovery charge of the low-
side MOSFET.
D = Duty cycle of the converter.
_
PCB layout also affects the thermal performance of the
design. A number of thermal throughputs that connect to a
large ground plane should be provided under the exposed
pad of the part, for efficient heat dissipation.
Q
oss_
= Output charge of the low side MOSFET.
For a typical multilayer board, the thermal performance
metrics for the package are given below:
θ
= 23ºC/W
= 1.7ºC/W
For a sample layout that ensures first pass success, refer
to the MAX17524 EV kit layout available at www.maximin-
tegrated.com.
JA
θ
JC
The junction temperature of the device can be estimated
at any given maximum ambient temperature (T
from the following equation:
)
A(MAX)
T
= T
+ θ ×P
J(MAX)
A(MAX)
JA
IC_LOSS
Maxim Integrated
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
converter output. Figure 4 shows the coincident tracking
of the converter outputs. Figure 5 shows the ratiometric
tracking of the converter outputs. Figure 6 shows the out-
put voltage sequencing where converter 1 is the master.
Coincident/ Ratiometric Tracking and Output
Voltage Sequencing
The soft-start pins (SS1 and SS2) can be used to track
the output voltages to that of another power supply at
startup. Figure 3 shows the independent soft-start of each
V
V
OUT1
OUT2
SS1
MAX17524
SS2
TIME
Figure 3. Independent Soft-Start of Each Converter Output
L1
V
OUT1
R1
LX1
SS1
FB1
C3
V
OUT1
R2
MAX17524
V
OUT2
V
OUT1
L2
R5
LX2
V
OUT2
TIME
SS2
R3
R6
FB2
C4
R4
R5 = R3/10
R6 = R4/10
Figure 4. Coincident Tracking of the Converter Outputs
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
L1
V
OUT1
R1
LX1
SS1
SS2
FB1
C3
V
OUT1
R2
MAX17524
V
OUT2
L2
LX2
V
OUT2
TIME
R3
FB2
C4
R4
Figure 5. Ratiometric Tracking of the Converter Outputs
EN/UVLO1
L1
V
OUT1
R1
LX1
EN/UVLO1
RESET1
FB1
C3
V
OUT1
R2
MAX17524
RESET1 = EN/UVLO2
EN/UVLO2
L2
LX2
V
OUT2
RESET2
R3
FB2
V
OUT2
C4
R4
RESET2
Figure 6. Output-Voltage Sequencing
Maxim Integrated
│ 22
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Application Circuit
RESET2
RESET1
V
IN2
V
IN1
IN1
IN2
24V
24V
C1
C2
2.2µF
2.2µF
V
BST1
BST2
OUT1
V
OUT2
C12
C11
5V, 3A
3.3V, 3A
L2
L1
10µH
0.1µF
0.1µF
LX2
DL2
CF2
LX1
DL1
CF1
C4
2x47µF
C3
2x22µF
6.8µH
R1
140kΩ
R3
100kΩ
Q1
Q2
MAX17524
R4
37.5kΩ
R2
30.9kΩ
FB2
EN/UVLO2
EXTVCC2
FB1
V
OUT1
EN/UVLO1
EXTVCC1
V
IN2
V
IN1
R5
4.7Ω
C9
0.1µF
PGND1
PGND2
f
= 450kHz
SW
MODE/SYNC1
V
MODE/SYNC2
V
SS2
L1 = XAL6060-103ME
L2 = XAL6060-682ME
CC1
SS1
SGND
CC2
RT
C1 = C2 = 2.2µF/X7R/100V/1210
(GRM32ER72A225K)
C3 = 2 x 22µF/X7R/10V/1210
(GRM32ER71A226K)
PGND1
PGND2
SGND
C5
2.2µF
C7
5.6nF
C8
5.6nF
C6
2.2µF
C4 = 2 x 47µF/X7R/10V/1210
(GRM32ER71A476KE15)
Q1 = Q2 = SIS468DN
MODE/SYNC2:
CONNECT TO SGND FOR PWM MODE
CONNECT TO V FOR DCM MODE
MODE/SYNC1:
CONNECT TO SGND FOR PWM MODE
CONNECT TO V FOR DCM MODE
CC2
CC1
OPEN FOR PFM MODE
OPEN FOR PFM MODE
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
32 TQFN
(5mm x 5mm)
MAX17524ATJ+
-40°C to +125°C
+Denotes a lead(Pb)-free/RoHS compliant package.
Maxim Integrated
│ 23
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MAX17524
4.5V to 60V, 3A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
12/17
Initial release
Corrected Document Control Identifcation number
—
0.5
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 24
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