MAX17843 [MAXIM]
12-Channel, High-Voltage Smart Sensor Data-Acquisition Interface;
| 型号： | MAX17843 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Channel, High-Voltage Smart Sensor Data-Acquisition Interface |
| 文件： | 总131页 (文件大小：2069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
General Description
Benefits and Features
● 12-Cell Battery-Voltage Measurement for Lithium-Ion,
The MAX17843 is a programmable, highly integrated,
high-voltage, 12-channel battery-monitoring smart data-
acquisition interface with extensive features for safety. It
is optimized for use with batteries used in automotive sys-
tems, hybrid electric battery packs, electric cars, and any
system that stacks long series strings of secondary metal
batteries. This highly integrated battery sensor incorpo-
rates a high-speed differential UART bus for robust daisy-
chained serial communication.
NiMH, or Super-Cap Cells
● Two Auxiliary Analog Inputs for NTC Thermistor or
Absolute Voltage Measurement
● Die Temperature Measurement and alert
● High-Accuracy Differential Measurement I/Os
• ±2mV Accuracy at +25°C and 3.6V
● Integrated 12-Channel Data-Acquisition System
• Differential High-Voltage Mux to ADC
• 14-Bit ADC Resolution with Oversampling
• 12 Cell Voltages Measured within 142μs
• Module Voltage Measurement
The analog front-end combines a 12-channel voltage-
measurement data-acquisition system with a high-voltage
switch-bank input. All measurements are done differen-
tially across each cell. The full-scale measurement range
is from 0 to 5.0V with a usable range of 0.2V to 4.8V. A
high-speed successive approximation (SAR) A/D con-
verter is used to digitize the cell voltages at 14-bit resolu-
tion with oversampling. All 12 cells can be measured in
under 142μs. The MAX17843 uses a 2-scan approach
for collecting cell measurements and correcting them for
errors. This 2-phase approach yields excellent accuracy
over temperature and in the face of extreme noise in the
system.
• Redundant ADC
● Battery Fault Detection
• Overvoltage and Undervoltage Digital Threshold
Detection
• Enhanced Diagnostic Features for Fault Detection
to Support ASIL and FMEA
● 12 Internal Cell-Balancing Switches
• Support Up to 150mA per Switch
• Emergency Cell-Discharge Mode
The MAX17843 has two auxiliary analog inputs that can
be used to measure external thermistor components. A
negative temperature coefficient (NTC) thermistor can be
configured with the AUXIN analog inputs to accurately
monitor module or battery-cell temperature. A thermal-
overload detector disables the MAX17843’s linear regula-
tor to protect the IC, and a die-temperature measurement
is also available.
● Integrated 9V to 65V Input Linear Regulator
● Integrated Temperature-Compensated, Voltage
Reference
● Robust Differential Daisy-Chain UART Interface
• Up to 32 Connected ICs in a Single Daisy-Chain
• Compatible with Direct MCU Connection
• Standard UART bytes at 2Mb/s (max) Rate
● Four General-Purpose Digital I/O Lines
Applications
● Built-In Diagnostics to Support ASIL D and FMEA
● 48V Vehicle Battery Modules or Systems
● High-Voltage Electric Vehicle (EVs)
● Hybrid Electric Vehicles (HEVs)
● Battery Packs
Requirements
● Ultra-Low-Power Dissipation
• 2.0mA (typ) Standby-Mode Supply Current
• 3μA Shutdown Mode Leakage Current
● Electric Bikes
● High-Power Battery-Backup Systems
● Super-Cap Backup Systems
● Power Tools
● -40°C to +125°C Operating Temperature Range
(AEC-Q100 Grade 1)
● 64-Pin, Lead-Free/RoHS-Compliant, 10mm x 10mm
LQFP Package
Ordering Information appears at end of data sheet.
19-100084; Rev 2; 4/18
MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Precision Internal Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Measurement Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Cell Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Block Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Auxiliary Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
THRM Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Computing Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Temperature Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Die Temperature Alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Acquisition Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Oversampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Infinite Impulse Response Filtering (IIR Filter): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
RDFILT Bit in SCANCTRL Register (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AUTOBALSWDIS Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Acquisition Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Scan Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Measurement Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Voltage Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Cell Mismatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Cell Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Temperature Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Maxim Integrated
│ 2
www.maximintegrated.com
MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
(
)
TABLE OF CONTENTS CONTINUED
Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Cell-Balancing Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum Cell-Balancing Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Cell-Balancing Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Emergency-Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Device ID Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Power-On And Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power-On Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Shutdown Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
UART Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART RX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
UART Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
External Loopback Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Internal Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
TX Adaptive Mode for Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Battery-Management UART Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Command Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Preamble Character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Data Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Stop Character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
UART Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
UART Communication Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Command Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Command-Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Data-Check Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Maxim Integrated
│ 3
www.maximintegrated.com
MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
(
)
TABLE OF CONTENTS CONTINUED
PEC Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Alive-Counter Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Fill Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Battery-Management
UART Protocol Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
HELLOALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
WRITEALL Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
WRITEDEVICE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
READALL Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
READDEVICE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
READBLOCK Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
ALTREF Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
V
AA
Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSAMP Offset Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Zero-Scale ADC Diagnostic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Full-Scale ADC Diagnostic Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
BALSW Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
BALSW Short Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
BALSW Open Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Even/Odd Sense Wire Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Diagnostic Test Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Shutdown Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
HVMUX Switch Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
HVMUX Switch Shorted Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
HVMUX Test Source Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Cn Open Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Cn Shorted to SWn Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Cn Leakage Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Cell Overvoltage Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Cell Undervoltage Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
ALRTHVUV Comparator Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
HVMUX Sequencer Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ALU Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Calibration ROM Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Vehicle Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Battery-Management Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Distributed-Module Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
External Cell Balancing Using BJT Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
External Cell-Balancing Short-Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
High-Z Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
UART Supplemental ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
UART Supplemental ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Single-Ended RX Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
UART Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Device Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Error Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
PEC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
VERSION Register (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
ADDRESS Register (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
STATUS Register (address 0x02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
FMEA1 Register (address 0x03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ALRTCELL Register (address 0x04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ALRTOVCELL Register (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ALRTUVCELL Register (address 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ALRTBALSW Register (address 0x08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MINMAXCELL Register (address 0x0A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
FMEA2 Register (address 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
AUTOBALSWDIS Delay Register (address 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ID1 Register (address 0x0D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
ID2 Register (address 0x0E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DEVCFG1 Register (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
GPIO Register (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MEASUREEN Register (address 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SCANCTRL Register (address 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ALRTOVEN Register (address 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ALRTUVEN Register (address 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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WATCHDOG Register (address 0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ACQCFG Register (address 0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
BALSWEN Register (address 0x1A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DEVCFG2 Register (address 0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
BALDIAGCFG1 Register (address 0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
BALSWDCHG Register (address 0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
TOPCELL Register (address 0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
CELLn Register (addresses 0x20 to 0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
VBLOCK Register (address 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
AIN1 Register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
AIN2 Register (address 0x2E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TOTAL Register (address 0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
OVTHCLR Register (address 0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
OVTHSET Register (address 0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UVTHCLR Register (address 0x44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UVTHSET Register (address 0x46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MSMTCH Register (address 0x48). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
AINOT Register (address 0x49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
AINUT Register (address 0x4A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
BALSHRTTHR Register (address 0x4B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
BALLOWTHR Register (address 0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
BALHIGHTHR Register (address 0x4D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DIAG Register (address 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DIAGCFG Register (address 0x51). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CTSTEN Register (address 0x52). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ADCTEST1A Register (address 0x57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ADCTEST1B Register (address 0x58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
ADCTEST2A Register (address 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
ADCTEST2B Register (address 0x5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
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LIST OF FIGURES
Figure 1. Simplified Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 2. Cell and switch input Filter Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. MAX17843 Functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. MAX17843 64-Pin LQFP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. ESD Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Analog Front-End (AFE Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. VBLKP Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. Auxiliary Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Auxiliary Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Die Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. IIR Flowchart with Respect to the AMENDFILT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. IIR Filter Diagram with Respect to RDFILT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Logic Diagram when Balancing Switches Are Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Acquisition Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. Acquisition, OVSAMP[2:0]=0h and SCANMODE=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17. Acquisition, OVSAMP[2:0] > 0 and SCANMODE=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Cell Voltage-Alert Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 19. Internal Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 20. Cell-Balancing Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. HV Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. SHDNL Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. Power-On Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25. Shutdown Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 26. Power-On and Shutdown Timing (UART Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 27. Shutdown Timing (Software Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 28. System Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 29. UART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 30. UART Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 31. Command Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 32. Preamble Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 33. Data Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 34. Stop Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 35. Communication Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 36. ALTREF Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 37. VAA Diagnostic ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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)
LIST OF FIGURES CONTINUED
Figure 38. VAA Diagnostic ADC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 39. LSAMP Offset Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 40. ADC Zero-Scale Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 41. ADC Full-Scale Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 42. Balancing Switch Short. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 43. BALSW Short Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 44. BALSW Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 45. Cell Sense-Wire Open Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 46. Sense-Wire Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 47. Test Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 48. Shutdown Diagnostic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 49. HVMUX Switch Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 50. SWn to Cn Short. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 51. SWn-1 to Cn Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 52. Redundant HVMUX Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 53. HVMUX Sequencer Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 54. HVMUX Sequencer Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 55. ALU Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 56. AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 57. AUXINn Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 58. Electric Vehicle System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 59. Daisy-Chain System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 60. Distributed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 61. External Cell Balancing (BJT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 62. UART Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 63. High-Z Idle Mode Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 64. External ESD Protection for UART TX Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 65. External ESD Protection for UART RX Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 66. Application Circuit for Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 67. UART Transformer Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 68. UART Optical Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 69. Device Initialization Sequence in Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 70. CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 71. PEC Calculation Pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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12-Channel, High-Voltage Smart Sensor
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LIST OF TABLES
Table 1. System Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2. Numeric Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3. Data-Acquisition Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4. Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5. THRM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. AINTIME. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. AMENDFILT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. RDFILT Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Acquisition Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Acquisition Time Examples (with AINCFG[5:0] = 00h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 12. Measurement Alerts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Maximum Allowed Balancing Current per Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. Cell-Balancing Watchdog Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15. Emergency Discharge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 16. Low-Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 17. Low-Voltage Regulator Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. HV Charge-Pump Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Oscillator Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. Shutdown Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 21. UART RX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22. Data Character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23. Battery-Management UART Protocol (Data Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. Battery-Management UART Protocol (Command Packet Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 25. Command-Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 26. Data-Check Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 27. HELLOALL Sequencing (z = Total Number of Devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 28. WRITEALL Sequencing (Unchanged by Daisy-Chain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 29. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 30. READALL Command Sequencing (z = Number of Devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. READDEVICE Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 32. READBLOCK Sequencing for Block Size = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 33. READBLOCK Sequencing for Block Size = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 34. Summary of Built-In Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35. BALSW Short Diagnostic Autoconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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LIST OF TABLES CONTINUED
Table 36. BALSW Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 37. BALSW Open-Diagnostic Autoconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 38. Odd Sense-Wire Open Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 39. Sense-Wire Open-Diagnostic Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 40. HVMUX Output Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 41. Shutdown Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 42. HVMUX Switch Open Diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 43. HVMUX Test-Source Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 44. Cn Pin Open Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 45. Expected ALU Diagnostic and Block Register Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 46. CRC Bit Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 47. BJT Balancing Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Simplified Operating Circuit
MODULE N+1
CELL STACK
C81
3.3µF
25V
R80
40Ω
MODULE-
(N+1)
D81
SW12
DCIN
DCIN INPUT
CIRCUIT
HV
DCIN
MODULE+
(N)
D91
UART DAISY-CHAIN FROM
UPPER MODULE OR
SYSTEM CONTROLLER
VBLKP
CPP
C82
0.1µF
100V
MAX178xx
MODULE n+1
CPN
C12
SW12
C11
SW11
C10
SW10
C9
RXUP
RXUN
TXLP
TXLN
CELL #12
CELL #11
CELL #10
CELL #9
CELL #8
CELL #7
CELL #6
CELL #5
CELL #4
CELL #3
CELL #2
CELL #1
UPPER PORT
COMMUNICATION
RXLP
RXLN
TXUP
TXUN
INTERFACE CIRCUIT
MAX17843
GPIO0
GPIO1
GPIO2
GPIO3
SW9
C8
GPIO INTERFACE
CIRCUIT
SW8
C7
VAA
C83
1.0µF
SW7
C6
CELL INPUT
FILTER
INTERFACE
CIRCUIT
AGND
VDDL1
SW6
C5
C84
0.47µF
GNDL1
VDDL2
UART DAISY-CHAIN FROM
LOWER MODULE OR
C85
SW5
C4
0.47µF
GNDL2
VDDL3
SYSTEM CONTROLLER
MAX178xx
C86
MODULE n-1,
ISOLATOR, OR
INTERFACE IC
SW4
C3
0.47µF
GNDL3
TXLP
TXLN
RXUP
RXUN
SW3
C2
LOWER PORT
COMMUNICATION
RXLP
RXLN
TXUP
TXUN
INTERFACE CIRCUIT
SW2
C1
SHDNL/
C87
1.0nF
25V
SW1
C0
MODULE-
(N)
D90
SW0
ANALOG AUX
INPUT INTERFACE
CIRCUIT
THRM
AUXIN2
AUXIN1
AGND
AGND
MODULE
N-1 CELL
STACK
CAPACITOR RATINGS SHOWN IN THIS DATASHEET ARE BASED ON EXPECTED
REFERENCE CIRCUIT CONDITIONS AND MAY BE MODIFIED BASED ON FINAL
APPLICATION REQUIREMENTS.
Figure 1. Simplified Operating Circuit
Maxim Integrated
│ 11
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Simplified Operating Circuit (continued)
R13
1kΩ
C13
330nF
VBLKP
C12
R12
C12
1kΩ
R32
100nF
22Ω
Cell 12
Cell 11
Cell 10
Cell 9
Cell 8
Cell 7
Cell 6
Cell 5
Cell 4
Cell 3
Cell 2
Cell 1
SW12
C11
C26
100nF
R11
1kΩ
C11
100nF
MAX17843
R31
22Ω
SW11
C10
C25
100nF
R10
1kΩ
C10
100nF
R30
22Ω
SW10
C9
C24
100nF
R9
1kΩ
C9
100nF
R29
22Ω
SW9
C8
C23
100nF
R8
1kΩ
C8
100nF
R28
22Ω
SW8
C7
C22
100nF
R7
1kΩ
C7
100nF
R27
22Ω
SW7
C6
C21
100nF
R6
1kΩ
C6
100nF
R26
22Ω
SW6
C5
C20
100nF
R5
1kΩ
C5
100nF
R25
22Ω
SW5
C4
C19
100nF
R4
1kΩ
C4
100nF
R24
22Ω
SW4
C3
C18
100nF
R3
1kΩ
C3
100nF
R23
22Ω
SW3
C2
C17
100nF
R2
1kΩ
C2
100nF
R22
22Ω
SW2
C1
C16
100nF
R1
1kΩ
C1
100nF
R21
22Ω
SW1
C0
C15
100nF
R0
1kΩ
C0
100nF
R20
22Ω
SW0
C14
1µF
AGND
Figure 2. Cell and switch input Filter Operating Circuit
Maxim Integrated
│ 12
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Functional Block Diagram
+9V TO
65V
THRM
HV
VAA
2.307V
REFERENCE
ALTERNATE 1.23V
REFERENCE
VBLKP
LINEAR REGULATOR
C12
C11
C10
+3.3V
HV
HV CHARGE
PUMP
POR
DIE TEMPERATURE
CPP
CPN
C9
C8
16MHZ
OSC
32KHZ
OSC
V’BLKP
C7
C6
C5
+
-
C4
CONTROL
AND
STATUS
ADC1
LS AMP
C3
C2
C1
C0
MAX17843
AGND
AUXIN2
AUXIN1
TXUP
TXUN
RXUP
RXUN
ADC2
UPPER PORT
V’BLKP
(5/8) x VAA
DIE
TEMPERATURE
RXLP
AGND
FAULT DETECTION
SUPPORT CIRCUITRY
RXLN
TXLP
TXLN
ALTMUX SWITCH BANK
CELL BALANCING
HV
LOWER PORT
SHDNL/
Figure 3. MAX17843 Functional block diagram
Maxim Integrated
│ 13
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Absolute Maximum Ratings
HV to AGND............................................................ -0.3 to +80V
TXLP, TXLN to GNDL2............................................-0.3V to +6V
TXUP, TXUN to GNDL3 ..........................................-0.3V to +6V
DCIN, SWn, VBLK, and Cn to AGND .........-0.3V to V
+ 0.3V
HV
-0.3V to +72V
Cn to Cn-1..............................................................-72V to +72V
SWn to SWn-1.......................................................-0.3V to +16V
CPP to AGND....................................... V
CPN to AGND.......................................... -0.3V to V
GPIO0, GPIO1, GPIO2, GPIO3 to GNDL1..-0.3V to V
- 1V to V
+ 1V
+ 0.3V
+ 0.3V
DCIN
HV
DCIN
DDL1
V
V
V
V
V
to AGND........................................................... -0.3v to +4V
Max Continuous Current into Any Pin (Note 1)................±20mA
Max Continuous Current into SWn Pin (Note 2)............±400mA
Max Average Power for ESD Diodes (Note 3)............. 14.4/√τW
Package Continuous Power (Note 4)............................2000mW
Package Junction-to-Ambient
AA
to GNDL1.....................................................-0.3V to +4V
to GNDL2.....................................................-0.3V to +6V
to GNDL3.....................................................-0.3V to +6V
DDL1
DDL2
DDL3
to V
, V
, and V
.......................-0.3V to +0.3V
AA
DDL1 DDL2
DDL3
AGND to GNDL1, GNDL2, GNDL3......................-0.3V to +0.3V
Thermal Resistance (θ ).............................................40°C/W
JA
AUXIN1, AUXIN2, THRM to AGND.............-0.3V to V + 0.3V
Operating Temperature Range......................... -40°C to +125°C
Storage Temperature Range............................ -55°C to +150°C
Junction Temperature (continuous)...................................150°C
Soldering Lead Temperature (10s max)............................300°C
AA
SHDNL to AGND........................................-0.3 to V
+ 0.3V
DCIN
CTG to AGND..........................................................-0.3V to +6V
RXLP, RXLN, RXUP, RXUN to GNDL1..................-30V to +30V
Note 1: Balancing switches disabled.
Note 2: One balancing switch enabled, 60s (max).
Note 3: Average power for time period τ where τ is the time constant (in μs) of the transient diode current during a hot-plug event.
For, example, if τ is 330μs, the maximum average power is 0.793W. Peak current must never exceed 2A. Actual average
power during hot-plug must be calculated from the diode current waveform for the application circuit and compared to the
maximum rating.
Note 4: Multilayer board. For T > +70°C derate 25mW/°C.
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maxim Integrated
│ 14
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
POWER REQUIREMENTS
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
9
65
3
V
DCIN
I
V
V
= 0V
0.1
2.0
µA
DCSHDN
SHDNL
SHDNL
> 1.8V, baud rate = 0
(100% idle), SCAN = 0, BALSWEN,
CTSTEN = 0000h
I
1.5
2.0
2.7
mA
mA
DCSTBY
Supply Current
(Note 6)
Baud rate = 2Mb/s (0% idle time
preambles mode), 200pF load on TXUP,
200pF on TXUN, TXL not active, SCAN
= 0, BALSWEN, CTSTEN = 0000h
I
5
DCCOMM
MEASUREEN = 0FFFh,
acquisition mode
I
3.5
0.9
5.4
1.1
8
mA
mA
DCMEAS
MEASUREEN = 0FFFh, acquisition
HV Measurement Current
I
1.3
HVMEAS
mode, V
= V
+ 5.5V
HV
DCIN
Incremental HV Current
for n Balancing Switches
Enabled
V
= V
+ 5.5V,
(n+1) x
5
(n+1) x
13.5
(n+1) x
26
HV
DCIN
I
µA
HVBAL
cell-balancing mode
VOLTAGE INPUTS (Cn, for n = 1 to 12 and V
)
BLKP
Unipolar mode
Bipolar mode
0.2
4.8
V
V
Differential Input Range,
V
= V - V
V
CELLn
CELLn
Cn
Cn-1
(Note 7)
-2.3
+2.3
Common-Mode Input Range
Input Leakage Current
V
SWn inputs not connected
= 71V, Cn = 0V
0
65
V
CnCM
I
V
-200
-10
+200
nA
LKGCn_L
HV
C0 = 5V, C1 to C5 = 28V,
C6 to C12 = 65V; V = 71V
Input Leakage Current
I
-200
±10
+200
nA
LKGCn_H
HV
V
Input Resistance
BLKP
R
V
= V = 57.6V
DCIN
4.5
1.7
10
20
6
MΩ
kΩ
VBLKP
BLKP
(to AGND)
HVMUX Switch Resistance
R
CTSTDAC[3:0] = Fh
2.5
MUX
CELL-BALANCING INPUTS (SWn for n = 1 to 12)
V
= 60V, V
= 5 x N,
DCIN
SWn
Leakage Current
I
-1
+1
5
µA
LKG_SW
all SWn pins biased
Resistance, SWn to SWn-1
R
BALSWENn = 1, I
= 100mA
SWn
0.5
2
Ω
SWn
AUXILIARY INPUTS (AUXIN1, AUXIN2)
Input Voltage Range
Input Leakage Current
THRM OUTPUT
V
0
V
V
AUXINn
THRM
I
ADC off; V
= 1.65V
AUXINn
-400
10
25
+400
nA
LKG_AUX
Switch Resistance, THRM
R
100
+1
Ω
THRM
to V
AA
THRM Leakage
I
V
= 1.65V
-1
µA
THRM
THRM
Maxim Integrated
│ 15
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics (continued)
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MEASUREMENT ACCURACY
Unipolar mode, V
= 3.6V,
CELLn
Initial Total-Acquisition Error
(HVMUX Inputs, ADC1 or
ADC2)
DCIN = 43.2V, T = +25°C,
V
A
CELLn
-2
-3.5
-6
+2
+3.5
+6
mV
VSAMPL[2:0] = 011b,
ERRINIT
filter coefficient, FC [2:0] = 010b
Unipolar mode, 0.2V ≤ V
≤ 4.8V,
CELLn
5C < T < 40°C OVSAMPL[2:0] = 011b,
A
filter coefficient, FC [2:0] = 010b
Initial-Acquisition Error
(HVMUX Inputs, ADC1 or
ADC2) (Note 8)
Unipolar mode, 0.2V ≤ V
OVSAMPL[2:0] = 011b, filter coefficient,
FC[2:0]= 010b
≤ 4.8V,
CELLn
V
±0.75
mV
CELLnERR
Bipolar mode, -2.3V ≤ V
OVSAMPL[2:0] = 011b, filter coefficient,
≤ 2.3V,
CELLn
-6
+6
FC[2:0] = 010b
Initial-Acquisition Error
(HVMUX Inputs, ADC1 or
ADC2) (Note 9)
Unipolar mode, 0.2V ≤ V
≤ 4.8V,
CELLn
0C < T < 40°C, OVSAMPL[2:0] = 011b,
-3.5
-3.5
-6
+3.5
+3.5
+6
mV
mV
A
filter coefficient, FC[2:0]= 010b
Unipolar mode, 0.2V ≤ V
≤ 4.8V
CELLn
5C < T < 40°C OVSAMPL[2:0] = 011b,
A
filter coefficient, FC [2:0] = 010b
Initial-Acquisition Error
(ALTMUX Inputs, ADC1
or ADC2) (Note 8)
Unipolar mode, 0.2V ≤ V
OVSAMPL[2:0] = 011b, filter coefficient,
FC[2:0] = 010b
≤ 4.8V,
CELLn
V
SWnERR
mV
Bipolar mode, -2.3V ≤ V
OVSAMPL[2:0] = 011b, filter coefficient,
≤ 2.3V,
CELLn
-6
+6
FC[2:0] = 010b
Total-Acquisition Noise
(Note 9)
V
No oversampling
1.1
mVRMS
mV
CELLNOISE
9V ≤ V
≤ 57.6V V
= 57.6V,
BLKP
DCIN
Total-Acquisition Error
V
V
OVSAMPL[2:0 ]= 011b, filter coefficient,
-110
+110
BLKERR
OS_AUX
(V
Input)
BLKP
FC[2:0] = 010b
Offset Error for AUXIN
Measurement
-3
+3
mV
%
Gain Error for AUXIN
Measurement
A
-0.3
+0.3
V_AUX
Total Error for Die-
Temperature Measurement
(Note 9)
T
T = -40°C to +105°C, no averaging
-5
±3
+5
ºC
DIE_ERR
J
Differential Nonlinearity
(Any Conversion)
DNL
±1.0
LSbs
bits
ADC Resolution
12
Maxim Integrated
│ 16
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics (continued)
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
DIAGSEL[2:0] = 011b,
MIN
TYP
MAX
UNITS
Level-Shifting Amplifier
Offset (Note 10)
V
-200
+200
mV
OS_LSAMP
OVSAMPL[2:0] = 011b
V
Diagnostic ADC1
DIAGSEL[2:0] = 010b, OVSAMPL[2:0]
= 011b, ADCSELECT = 0
V
AA
DIAG_
-20
-30
+20
+30
mV
mV
Measurement Accuracy
VAAERR1
V
Diagnostic ADC2
DIAGSEL[2:0] = 010b, OVSAMPL[2:0]
= 011b, ADCSELECT = 1
V
AA
DIAG_
Measurement Accuracy
VAAERR2
SHDNL INPUT AND CHARGE PUMP
Input Low Voltage
Input High Voltage
V
0.55
12
V
V
IL_SHDNL
V
1.8
8
IH_SHDNL
V
V
≥ 12V
9.5
6.7
4.7
V
DCIN
DCIN
Regulated Voltage
V
SHDNLIMIT
FORCEPOR
= 9V
V
Pulldown Resistance
R
FORCEPOR = 1
2.5
4.5
8
kΩ
SHDNL Input Leakage
Resistance
R
20.5
MΩ
SHDNL
Charge-Pump Current
(Note 11)
V
< V
,
SHDNL
SHDNLIMIT
I
15
117
350
0.8
µA
SHDNL
baud rate = 2Mbps
GENERAL-PURPOSE I/O (GPIO0–GPIO3)
Input Low Voltage
Input High Voltage
Pulldown Resistance
Output Low Voltage
Output High Voltage
REGULATOR
V
V
V
IL_GPIO
V
2.4
0.5
IH_GPIO
R
GPIO[15:12] = 0h (input)
2
7.5
0.4
MΩ
V
GPIO
V
I
I
= 3mA
OL_GPIO
OH_GPIO
SINK
V
= 3mA
V
- 0.4
V
SOURCE
DDL1
Output Voltage
V
0 ≤ I
< 10mA
3.2
10
3.3
20
3.4
70
V
mA
V
AA
VAA
Short-Circuit Current
I
V
V
V
shorted to AGND
falling
AASC
AA
AA
AA
V
V
2.85
2.95
3.0
40
3.02
3.1
PORFALL
POR Threshold
POR Hysteresis
rising
V
PORRISE
V
mV
PORHYS
Thermal-Shutdown
Temperature (Note 9)
T
Temperature rising
165
10
°C
°C
SHDN
Thermal-Shutdown
Hysteresis (Note 9)
T
HYS
HV CHARGE PUMP
9V ≤ V
≤ 12V, I
= 1.5mA
5
5
5.5
5.5
6
6
DCIN
LOAD
Output Voltage (V -V
)
V
V
HV DCIN
HV-DCIN
12V ≤ V
≤ 65V, I
= 3mA
DCIN
LOAD
Charge Pump Efficiency
(Note 12)
38
%
Maxim Integrated
│ 17
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics (continued)
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
HV Headroom
SYMBOL
CONDITIONS
ALRTHVHDRM = 0
MIN
TYP
MAX
UNITS
V
4.7
V
HVHDRM
OSCILLATORS
32kHz Oscillator Frequency
16MHz Oscillator Frequency
DIAGNOSTIC TEST SOURCES
f
32.11
15.68
32.768
16
33.42
16.32
kHz
OSC_32K
f
MHz
OSC_16M
CTSTDAC[3:0] = 9h,
< V - 1.4V, V = 3.3V
50
36
62.5
45
75
54
V
Cn
AA
AA
CTSTDAC[3:0] = 6h,
< V - 1.4V, V = 3.3V
V
Cn
AA
AA
Cell-Test Source Current
I
µA
µA
µA
TSTCn
CTSTDAC[3:0] = 6h,
> V + 1.4V
-54
-75
25
-45
-36
-50
37.5
27
V
Cn
AGND
CTSTDAC[3:0] = 9h,
> V + 1.4V
-62.5
31.25
22.5
62.5
45
V
Cn
AGND
CTSTDAC[3:0] = 9h,
< V - 1.4V, V
HV
V
= 53.5V
= 53.5V
Cn
HV
HVMUX Test-Source
Current
I
TSTMUX
CTSTDAC[3:0] = 6h,
< V - 1.4V, V
HV
18
V
Cn
HV
CTSTDAC[3:0] = 9h,
< V - 1.4V, V = 3.3V
50
75
V
AUXINn
AA
AA
CTSTDAC[3:0] = 6h,
< V - 1.4V, V = 3.3V
36
54
V
AUXINn
AA
AA
AUXIN Test-Source Current
I
TSTAUXIN
CTSTDAC[3:0] = 6h,
> V + 1.4V
-54
-75
-45
-36
-50
V
AUXINn
AGND
CTSTDAC[3:0] = 9h,
> V + 1.4V
-62.5
V
AUXINn
AGND
DIAGNOSTIC REFERENCES
ALTREF Voltage (Note 10)
V
A
DIAGSEL[2:0] = 001b
1.23
1.242
±25
1.254
V
ALTREF
ALTREF Temperature
Coefficient (ΔV
/ΔT)
ppm/°C
ALTREF
ALTREF
(Note 9)
PTAT Output Voltage
(Note 9)
V
T = +120°C
1.2
3.07
0
V
mV/°C
°C
PTAT
J
PTAT Temperature
Coefficient (ΔV
/ΔT)
A
V_PTAT
PTAT
(Note 9)
PTAT Temperature Offset
(Note 9)
T
OS_PTAT
ALERTS
ALRTVDDLn Threshold
ALRTGNDLn Threshold
V
V
= 3.3V
AA
3
3.15
0.15
3.25
0.3
V
V
VDDL_OC
V
AGND = 0V
0.05
GNDL_OC
Maxim Integrated
│ 18
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics (continued)
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
ALRTHVUV Threshold
ALRTHVOV Threshold
SYMBOL
CONDITIONS
falling
MIN
3.8
7
TYP
4.1
MAX
4.25
10
UNITS
V
V
V
- V
- V
V
V
HVUV
HVOV
HV
DCIN
V
rising
8.5
HV
DCIN
ALRTTEMP Threshold
(Note 9)
T
T
115
120
2
125
°C
°C
ALRTTEMP
ALRTTEMP Hysteresis
(Note 9)
ALRTTEMP
HYS
UART OUTPUTS (TXLP, TXLN, TXUP, TXUN)
Output Low Voltage
V
I
= 20mA
0.4
V
V
OL
SINK
Output High Voltage
(TXLP, TXLN)
V
V
I
= 20mA
= 20mA
V
V
- 0.4
- 0.4
OH
SOURCE
SOURCE
DDL2
Output High Voltage
(TXUP, TXUN)
I
V
OH
DDL3
-1
Leakage Current
I
V
= 1.5V
TX
+1
µA
LKG_TX
UART INPUTS (RXLP, RXLN, RXUP, RXUN)
Input Voltage Range
V
-25
+25
V
V
RX
CH
Receiver High Comparator
Threshold (Notes 13, 17)
V
/
V
/
DDL
DDL
V
V
/2
DDL
2 - 0.4
2 + 0.4
Receiver Zero-Crossing
Comparator Threshold
(Note 13)
V
-0.4
0
+0.4
V
ZC
-V
2 - 0.4
/
-V
2 + 0.4
/
DDL
Receiver Low Comparator
Threshold (Notes 13, 17)
DDL
V
-V
/2
V
CL
DDL
75
Receiver Comparator
Hysteresis (Note 13)
V
mV
HYS_RX
Receiver Common-Mode
Voltage Bias (Notes 13, 17)
V
V
/3
V
CM
DDL
Leakage Current
I
V
= 1.5V
±1.0
4
µA
pF
LKG_RX
RX
Input Capacitance
(RXLP, RXLN)
C
RXL
Input Capacitance
(RXUP, RXUN)
C
2
pF
RXU
UART TIMING
Baud rate = 2Mb/s
Baud rate = 1Mb/s
Baud rate = 0.5Mb/s
8
1/f
OSC
_16M
Bit Period (Note 14)
t
16
32
BIT
Rx Idle to START Setup
Time (Notes 9, 15)
t
0
1
4
t
BIT
RXSTSU
STOP Hold Time to Idle
(Notes 9, 15)
1/f
OSC
_16M
t
SPHD
Maxim Integrated
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Electrical Characteristics (continued)
(V
= +48V, T = T
to T
, unless otherwise noted, where T
= -40°C and T
=+125°C. Typical values are at T = +25°C.
DCIN
A
MIN
MAX
MIN
MAX A
Operation is with the recommended application circuit.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RX Minimum Idle Time
(STOP bit to START bit)
(Notes 9, 15)
t
1
t
RXIDLESPST
BIT
RX Fall Time (Notes 9, 16)
RX Rise Time (Notes 9, 16)
t
0.5
0.5
t
t
FALL
BIT
BIT
t
RISE
Propagation Delay (RX Port
to TX port) (Note 9)
t
2.5
1
3
t
PROP
BIT
Startup Time from SHNDL
High and V = 0V to
t
ms
AA
STARTUP
RXUP/RXUN Valid
Note 5: Unless otherwise noted, limits are 100% production tested at T = +25°C. Limits over the operating temperature range and
A
relevant supply voltage range are guaranteed by design and characterization.
Note 6: Acquisition mode (ADC conversions) is entered when the SCAN bit is set and ends when SCANDONE is set. With the
typical acquisition duty-cycle very low, the average current (I
) is much less than I
. Total supply current during
DCIN
DCMEAS
communication: I
= I
+ I
.
DCIN
DCCOMM
DCSTBY
Note 7: Range over which measurement settling time and accuracy is guaranteed.
Note 8: = V - V , V = V , and V = 12 x │V │ (9V min).
Note 9: Guaranteed by design and not production tested.
V
CELLn
Cn
Cn-1 CELLn
CELLn-1
DCIN
CELLn
Note 10: As measured during specified diagnostic mode; 5V full-scale for unipolar mode measurements and 2.5V full-scale for bipolar
measurements.
Note 11: I
measured with V
= 0.3V, STOP characters, zero idle time, V
= 3.3V.
SHDNL
SHDNL
RX_PEAK
Note 12: Charge pump efficiency = δI
/δI
, where I
is applied from HV to AGND, δI
= 5mA, and δI
= I
SUPPLY DCIN
LOAD SUPPLY
LOAD
LOAD
(for I
= 5mA) - I
(for I
= 0).
) where V
LOAD
DCIN
RXP
LOAD
Note 13: Differential signal (V
- V
and V
do not exceed a common-mode voltage range of ±25V.
RXN
RXP
RXN
Note 14: In daisy-chain applications, the bit time of the second STOP bit may be less than specified to account for clock-rate variation
and sampling error between devices.
Note 15: Maximum limited by application circuit.
Note 16: Fall time measured 90% to 10%; rise time measured 10% to 90%.
Note 17: V
= V
for lower port; V
= V
for upper port.
DDL
DDL2
DDL
DDL3
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Pin Configuration
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SW8
C8
THRM
AGND
AUXIN1
AUXIN2
CTG
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SW9
C9
SW10
C10
NC
MAX17843
SW11
C11
NC
RXLN
RXLP
GNDL2
VDDL2
TXLN
TXLP
NC
SW12
C12
VBLKP
NC
HV
DCIN
CPP
CPN
NC
GPIO0
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
LQFP
Figure 4. MAX17843 64-Pin LQFP Pin Configuration
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Pin Description
PIN
NAME
TYPE
―
FUNCTION
1, 18, 19,
26, 27, 60
N.C.
Not Connected. Connect to ground or leave unconnected.
2, 4, 31
AGND
Ground
Analog Ground. Connect to negative terminal of cell 1 and ground plane.
Active-Low Shutdown Input. Drive > 1.8V to enable operation and drive < 0.6V to reset
device and place in shutdown mode. +72V tolerant. If not driven externally, this input can
be controlled solely through UART communication and software control. Bypass with a
1nF capacitor to AGND. For single-ended UART, SHDNL must be driven externally.
3
SHDNL
Input
3.3V Regulator Output Used to Supply V
capacitor to ground.
, V
, andV
. Bypass with a 1µF
DDL3
DDL1 DDL2
5
V
Power
AA
6
7
8
TXUN
TXUP
Output
Output
Ground
Negative Output for Upper-Port Transmitter. Driven between V
and GNDL3.
DDL3
Positive Output for Upper-Port Transmitter. Driven between V
and GNDL3.
DDL3
GNDL1
Digital Ground. Connect to ground plane.
3.3V Digital Supply. Connect externally to V and bypass with 0.47µF capacitor to
AA
GNDL1.
9
V
Power
DDL1
10
GNDL3
Ground
Ground for Upper-Port Transmitter. Connect to ground plane.
3.3V Supply for Upper-Port Transmitter. Connect externally to VAA and bypass with
0.47µF capacitor to GNDL3.
11
12
13
V
Power
Input
Input
DDL3
RXUN
RXUP
Negative Input for Upper-Port Receiver. Tolerates ±30V.
Positive Input for Upper-Port Receiver. Tolerates ±30V. Connect to ground for single-
ended operation.
14
15
16
17
20
21
GPIO3
GPIO2
GPIO1
GPIO0
TXLP
I/O
I/O
General-Purpose I/O 3. Driven between V
General-Purpose I/O 2. Driven between V
General-Purpose I/O 1. Driven between V
General-Purpose I/O 0. Driven between V
and GNDL1. 2MΩ internal pulldown.
and GNDL1. 2MΩ internal pulldown.
and GNDL1. 2MΩ internal pulldown.
and GNDL1. 2MΩ internal pulldown.
DDL1
DDL1
DDL1
DDL1
I/O
I/O
Output
Output
Positive Output for Lower-Port Transmitter. Driven between V
and GNDL2.
DDL2
TXLN
Negative Output for Lower-Port Transmitter. Driven between V
and GNDL2.
DDL2
3.3V Supply for Lower-Port Transmitter. Connect externally to VAA and bypass with
0.47µF capacitor to GNDL2.
22
23
24
V
Power
Ground
Input
DDL2
GNDL2
RXLP
Ground for Lower-Port Transmitter. Connect to ground plane.
Positive Input for Lower-Port Receiver. Tolerates ±30V. Connect to ground for single-
ended operation.
25
28
RXLN
CTG
Input
Input
Negative Input for Lower-Port Receiver. Tolerates ±30V.
Reserved for Factory use. Connect to ground.
Auxiliary Voltage Input 2 to Measure External Temperature. Connect to a voltage-divider
consisting of a 10kΩ pullup to THRM and 10kΩ NTC thermistor to ground. If not used,
connect to the pullup only.
29
30
AUXIN2
AUXIN1
Input
Input
Auxiliary Voltage Input 1 to Measure External Temperature. Connect to a voltage-divider
consisting of a 10kΩ pullup to THRM and a 10kΩ NTC thermistor to ground. If not used,
connect to the pullup only.
3.3V Switched Output. Used to supply the voltage-dividers for the auxiliary inputs. The
output is enabled only during measurements, or as configured by THRMMODE[1:0].
This output can source up to 2mA.
32
THRM
Power
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Pin Description (continued)
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
NAME
SW0
C0
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
FUNCTION
Balance Input for Cell 1 Negative.
Voltage Input for Cell 1 Negative. Connect to AGND.
Balance Input for Cell 1 Positive (Cell 2 Negative)
Voltage Input for Cell 1 Positive (Cell 2 Negative)
Balance Input for Cell 2 Positive (Cell 3 Negative)
Voltage Input for Cell 2 Positive (Cell 3 Negative)
Balance Input for Cell 3 Positive (Cell 4 Negative)
Voltage Input for Cell 3 Positive (Cell 4 Negative)
Balance Input for Cell 4 Positive (Cell 5 Negative)
Voltage Input for Cell 4 Positive (Cell 5 Negative)
Balance Input for Cell 5 Positive (Cell 6 Negative)
Voltage Input for Cell 5 Positive (Cell 6 Negative)
Balance Input for Cell 6 Positive (Cell 7 Negative)
Voltage Input for Cell 6 Positive (Cell 7 Negative)
Balance Input for Cell 7 Positive (Cell 8 Negative)
Voltage Input for Cell 7 Positive (Cell 8 Negative)
Balance Input for Cell 8 Positive (Cell 9 Negative)
Voltage Input for Cell 8 Positive (Cell 9 Negative)
Balance Input for Cell 9 Positive (Cell 10 Negative)
Voltage Input for Cell 9 Positive (Cell 10 Negative)
Balance Input for Cell 10 Positive (Cell 11 Negative)
Voltage Input for Cell 10 Positive (Cell 11 Negative)
Balance Input for Cell 11 Positive (Cell 12 Negative)
Voltage Input for Cell 11 Positive (Cell 12 Negative)
Balance Input for Cell 12 Positive
SW1
C1
SW2
C2
SW3
C3
SW4
C4
SW5
C5
SW6
C6
SW7
C7
SW8
C8
SW9
C9
SW10
C10
SW11
C11
SW12
C12
Voltage Input for Cell 12 Positive
V
Block Voltage Positive Input. Internal 10MΩ pulldown during measurement.
BLKP
HV
Decoupling Capacitor Connection for the HV Charge Pump. V
(typical). Bypass with a 50V, 4.7µF capacitor to DCIN.
= V
+ 5.5V
HV
DCIN
61
Power
DC Supply for the Low-Voltage Regulator, HV Charge Pump, and SHDNL Charge
Pump. Connect to a voltage source between 9V and 65V through a 100Ω series resistor.
Bypass with a 100V, 2.2μF capacitor to ground.
62
DCIN
Power
Positive Capacitor Connection for the HV Charge Pump. Connect a 100V, 0.1µF
capacitor from CPP to CPN.
63
64
CPP
CPN
Power
Power
Negative Capacitor Connection for the HV Charge Pump
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Detailed Description
The data-acquisition system consists of the major blocks as described in Table 1.
Table 1. System Blocks
BLOCK
DESCRIPTION
Primary analog-to-digital converter. Uses a 12-bit successive-approximation register (SAR), with a
ADC1
ADC2
reference voltage of 2.307V and is supplied by V . V diagnostic result yields V . This is the default
ADC selected by the ADCSELECT bit in the SCANCTRL register.
AA AA AA
Secondary analog-to-digital converter. Uses a 12-bit successive-approximation register (SAR) with a
reference voltage of 2.307V and is supplied by V . This is the secondary ADC. V diagnostic result
AA
AA
yields V /2. Writing the ADCSELECT bit to 1 selects this ADC for measurements.
AA
HVMUX
12-channel, high-voltage (65V) differential multiplexer for Cn inputs.
High-voltage charge-pump supply (V
that must switch high-voltage signals. Supplied by DCIN.
+ 5.5V) for the HVMUX, ALTMUX, BALSW, and LSAMP circuits
DCIN
HV CHARGE PUMP
Level-shifting amplifier with a gain of 6/13. The result is that a 5V differential signal is attenuated to
2.307V, which is the reference voltage for the ADC.
LSAMP
LVMUX
Multiplexes various low-voltage signals including the level-shifted signals and temperature signals to the
ADC for subsequent A-to-D conversion.
ALTMUX
BALSW
12-channel, high-voltage differential multiplexer for SWn inputs.
Cell-balancing switches.
LINREG
REF
3.3V (V ) linear regulator used to power the ADC and digital logic. Supplied by DCIN (9V to 65V).
AA
2.307V precision reference voltage for ADC and LINREG. Temperature-compensated.
1.242V precision reference voltage used for diagnostics.
ALTREF
16MHZ OSC
32kHz OSC
16MHz oscillator with 2% accuracy for clocking state-machines and UART timing.
32,768Hz oscillator for driving charge pumps and timers.
Differential UART for communication with host or downstack devices. Autodetects baud rates of 0.5, 1, or
2Mbps.
LOWER PORT
UPPER PORT
Differential UART for communication with upstack devices.
CONTROL AND
STATUS
ALUs, control logic, and data registers.
DIE TEMP
A proportional-to-absolute-temperature (PTAT) voltage source used to measure the die temperature.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
RXUP, RXUN,
RXLP, RXLN
HV
CTG
MAX17843
CPP
VAA
THRM, AUXINn
DCIN
SHDNL, CPN
VDDL3
SW12
SW11
TXUP, TXUN
GNDL3
VDDL2
SWn
SW1
SW0
TXLP, TXLN
GNDL2
VDDL1
Cn, VBLKP
AGND
HV
VAA
GPIOn
GNDL1
NOTES:
1. ALL DIODES ARE RATED FOR ESD CLAMPING CONDITIONS. THEY ARE NOT INTENDED TO ACCURATELY
CLAMP DC VOLTAGE.
2. ALL DIODES HAVE A PARASITIC DIODE FROM AGND TO THEIR CATHODE THAT IS OMITTED FOR CLARITY.
THESE PARASITIC DIODES HAVE THEIR ANODE AT AGND.
Figure 5. ESD Diode Diagram
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
CELL TEST
SOURCES
HIGH-VOLTAGE MUX
VBLKP
VAA
SOURCE
VAA
AGND
C12
C11
C10
SOURCE
12
SOURCE
11
REF
THRM
SOURCE
10
VBLKP
HVMUX INTEGRITY
DETECTION
C9
C8
C7
SOURCE
9
SOURCE
8
+
SOURCE
7
LS AMP
ADC IN +
C6
C5
SOURCE
6
-
ADC1
ADC IN -
SOURCE
5
C4
C3
C2
REF DIAGNOSTIC
SOURCE
4
ALTREF
REF
SOURCE
3
LV
MUX1
SOURCE
2
C1
C0
SOURCE
1
DIE TEMPERATURE
SOURCE
0
AGND
SOURCE
AUXIN2
AUXIN2
AUXIN1
SOURCE
AUXIN1
REF
THRM
AUXIN2
ADC IN +
ADC IN -
AUXIN1
LV
MUX2
ADC2
V’BLKP
(5/8) x VAA
DIE TEMPERATURE
AGND
Figure 6. Analog Front-End (AFE Inputs)
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Measurement Calibration
Data Conventions
The acquisition system is calibrated at the factory and
cannot be changed afterwards. The calibration param-
eters are stored in a ROM consisting of 12 read-only
registers, CAL0–CAL10 and CAL15. ROMCRC[8:0] is
an 8-bit CRC value based on the calibration ROM and is
stored in ID2[15:8] at the factory. ROMCRC[8:0] can be
used to check the integrity of the calibration, as described
in the Diagnostics section.
Representation of data follows the conventions shown in
Table 2. All registers are 16-bit words.
Data Acquisition
Data acquisition is composed of the distinct processes
defined in Table 3, and is controlled by various configu-
ration registers described in this section. Configuration
changes should be made prior to the acquisition in which
the changes are to be effected.
Cell Inputs
Precision Internal Voltage References
Up to 12 voltage measurements can be sampled
differentially from the 13 cell inputs. The differential signal
The measurement system uses two precision, temper-
ature-compensated voltage references. The references
are completely internal to the device and do not require
any external components. The primary voltage reference
(REF) is used to derive the linear regulator output voltage
and to supply the ADC reference. An alternate, indepen-
dent reference(ALTREF) can be used to verify the primary
reference voltage, as described in the Diagnostics section.
(V
) is defined as V - V
for n = 1–12.
CELLn
Cn
Cn-1
Cells to be measured are selected by MEASUREEN[11:0].
During the scan, each selected signal is multiplexed into
the level-shifting amplifier (LSAMP) as shown in Figure 6.
Since the common-mode range of the input signals is 0 to
65V, the signal must be level-shifted to the common-mode
range of the amplifier. The amplifier has a gain of 6/13, so
a 5V differential signal is attenuated to 2.307V, which is
the ADC reference voltage.
Table 2. Numeric Conventions
DESCRIPTION
Binary number
CONVENTION
0b prefix
EXAMPLE
0b01100001 = 61h
0x61
Hexadecimal address
Hexadecimal data
Register bit
0x prefix
h suffix
61h
Register name [x]
Field name [x:y]
{xxxx, yyyy}
STATUS[15] = 1
DA[4:0] = 0b01100 = 0Ch
{DA[4:0], 0b001} = 61h
Register field
Concatenated numbers
Table 3. Data-Acquisition Processes
PROCESS
DESCRIPTION
The ADC samples a single input channel, converts it to a 12-bit binary value, and stores it in an
ALU register.
Conversion
Scan
The ADC sequentially performs conversions on all enabled cell input channels.
The ADC performs two scans for the purpose of minimizing errors. The conversions (two
for each input channel) are averaged together to form a single 14-bit binary value called
a measurement. Note: The auxiliary inputs are only scanned once to create the auxiliary
measurements.
Measurement cycle or Sample
Acquisition or Acquisition mode
If oversampling is enabled, the ADC takes sequential measurements and averages them
together to form one 14-bit binary value for each input channel sampled. If there is no
oversampling, the acquisition is essentially a single-measurement cycle. Note: The auxiliary
inputs are never oversampled and are stored as 12-bit values.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Once the signal is properly conditioned, the ADC can start
the conversion. The 12-bit conversion is stored in an ALU
register where it can be averaged with subsequent con-
versions. The ALU output is a 14-bit value and is ultimately
stored in a 16-bit register with the two least-significant bits
zero. Disabled channels result in a measurement value of
0000h. Unless stated otherwise, measurement values are
assumed to be 14-bit values. The 16-bit register values
can be converted to 14-bit values by dividing by 4 (and
vice versa). To convert the measurement value in register
CELLn to a voltage, convert the 14-bit hexadecimal value
to a decimal value and then convert to voltage as follows:
The input range can effectively be extended from -2.5V to
+5V by taking one bipolar measurement and one unipo-
lar measurement. Any bipolar measurements over 2.3V
should be replaced with the unipolar measurement.
Note: Conversions for some diagnostic modes automati-
cally use either bipolar or unipolar mode, regardless of the
POLARITY bit value.
Block Voltage Input
The V
input (total module voltage) is selected for
BLKP
measurement by MEASUREEN14. The measurement
is stored in the VBLOCK register with a full-scale value
of 60V (3.662mV/bit). It can be compared to the sum
of the cell voltages as a diagnostic. To precondition
V
= CELLn[15:2] x 5V/16384 = CELLn[15:2] x
CELLn
305.176μV.
V
BLKP
for conversion, it is voltage-divided by a factor of
Input Range
26. The divider is disconnected by default to minimize
power consumption. The divider is connected by setting
MEASUREEN15 (BLKCONNECT = 1) with sufficient set-
tling time prior to the acquisition. For high acquisition rates,
BLKCONNECT can remain enabled to reduce cycle time.
The input range in unipolar mode is nominally 0 to 5V;
however, the ADC has reduced linearity at its range
extents and so accuracy is specified for the input range
0.2V to 4.8V. Some applications may require specified
accuracy below 0.2V, or even below 0V. To this end, the
bipolar mode (POLARITY = 1) has a nominal input range
of -2.5V to +2.5V, as shown in Table 4, with accuracy
specified from -2.3V to +2.3V.
Table 4. Input Range
CELL INPUT VOLTAGE
CELLN[15:2] (14 BITS)
CELLN[15:0]
(16 BITS)
BIPOLAR MODE (V)
UNIPOLAR MODE (V)
HEXADECIMAL
DECIMAL
0d
-2.5
0
0
2.5
5
0000h
2000h
3FFFh
0000h
8000h
FFFCh
8192d
16383d
+2.5
V
REF
R1 = 10MΩ – R2
V
THRM
VBLKP
V
/26
+
-
BLKP
LV
MUX
ADC
R2 = 384.5kΩ
AGND
Figure 7. V
Measurement
BLKP
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
if oversampling is enabled; they are measured only once
and stored as 12-bit values in the AIN1 and AIN2 registers.
Auxiliary Inputs
The AUXIN1 and AUXIN2 inputs can be used to measure
external temperatures by enabling MEASUREEN[13:12].
These inputs have a common-mode input range of 0 to
To measure external temperature, the auxiliary input is
connected to a voltage-divider consisting of a 10kΩ pullup
to THRM and a 10kΩ NTC thermistor to ground, as shown
in Figure 9.
V
. For these measurements, the ADC reference volt-
AA
age is V
, which is switched from V , as shown in
AA
THRM
Figure 8. The auxiliary inputs are not oversampled even
V
AA
CONVERSIONS IN
PROGRESS
THRM
V
REF
AUXIN1
AUXIN2
AGND
+
-
LV
MUX
ADC
Figure 8. Auxiliary Measurement
THRM
R60
10kΩ
R61
10kΩ
MAX17843
AUXIN1
AUXIN2
AGND
C62
100pF
C60
100pF
C61
100pF
RTH2
10kΩ
R
TH1
10kΩ
t
t
THERMISTOR
WIRE HARNESS
Figure 9. Auxiliary Application Circuit
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The resistance of an NTC thermistor increases as the
temperature decreases and is typically specified by its
THRM Output
The THRM output has two modes of operation, automatic
and manual, as shown in Table 5.
resistance R at T = 25°C = 298.15K and a material
0
0
constant β (3400K typ). To the first order, the resistance
The automatic mode minimizes power consumption, but
after the THRM output is enabled, the AUXIN voltages
must be allowed to settle before the conversion. Since the
auxiliary inputs are the last inputs measured, the duration
of the measurement cycle itself can provide sufficient set-
tling time, depending on what measurements are enabled
and the time constants for the auxiliary input circuit. Up
to 384μs of additional settling time, if required, can be
configured by ACQCFG[5:0] (see Table 6), or by utilizing
the manual mode. The ability to configure the settling time
allows for a range of time constants to be considered in
designing the auxiliary application circuit.
R
is at a temperature T in Kelvin can be computed as
TH
follows:
(β(1/T-1/T ))
R = R e
0
0
The temperature T of the thermistor (in °C) can then be
calculated as follows:
T (in °C) = (β/ln((R /10kΩ) +
TH
(β/298.15K)) - 273.15K
Temperature Alerts
Auxiliary voltage measurements can be directly compared
to precalculated voltages in the AINUT and AINOT reg-
isters that correspond to specific over/undertemperature
thresholds. When a measurement exceeds the AINUT
or AINOT threshold level, the ALRTCOLD or ALRTHOT
bits, respectively, are set in the STATUS register. An
alert is cleared only by a new measurement that is within
threshold.
Computing Temperature
In Figure 9, V
= V
x R /(10KΩ + R
)
TH
AUXINn
THRM
TH
and this measurement is stored in the AINn register. The
thermistor resistance can then be solved for as follows:
R
= (V
x 10kΩ)/(V
- V
),
TH
AUX
THRM
AUXINn
where V
= 3.3V nominally.
THRM
Table 5. THRM Output
MODE
ACQCFG[9:8]
DESCRIPTION
00b
01b
10b
11b
THRM output enabled at the beginning of the acquisition and disabled at the end
of the acquisition.
Automatic
THRM output is enabled
THRM output is disabled
Manual
Table 6. AINTIME
ADDITIONAL SETTLING TIME PER ENABLED AUXILIARY
CHANNEL = 6µs + (AINTIME x 6µs)
ACQCFG[5:0] (AINTIME)
00h
01h
02h
…
6μs
12μs
18μs
…
1Fh
384 μs
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
where V
= 2.307V. The measured voltage can be
Die Temperature Measurement
REF
converted into °C as follows:
The die temperature measurement allows the host to
compute the device temperature (T ) as it relates to
the acquisition accuracy, and allows the device to auto-
T
(in °C) = (V /A
) + T
- 273°C
OS_PTAT
DIE
DIE
PTAT V_PTAT
See the Electrical Characteristics table for A
and
V_PTAT
matically shut itself down when T
> 145°C. The mea-
DIE
T
values.
OS_PTAT
surement employs a source whose voltage (V
) is
PTAT
Die Temperature Alert
proportional to absolute temperature (PTAT), as shown in
Figure 10. The V measurement is enabled by setting
The ALRTTEMP bit is updated at the end of each mea-
surement cycle for which DIAGSEL[2:0] = 0b110. If
ALRTTEMP is set, it signifies that T
that the diagnostic measurement did not have sufficient
settling time (< 50μs) and therefore can not be accurate. If
ALRTTEMP is set, the host should consider the possibility
that the acquisition does not meet the expected accuracy
specification, or that the die temperature measurement
itself may be inaccurate due to insufficient settling time
(< 2 cell measurements enabled).
PTAT
DIAGSEL[2:0] to 0b110 and the 14-bit measurement is
stored in DIAG[15:2]. The die temperature measurement
requires a settling time of 50µs from the start of the mea-
surement cycle until the diagnostic conversion. As long as
two or more cell measurements are enabled, there will be
sufficient settling time for this measurement. See Figure 17
and Table 10 for a detailed view of this timing.
> T
, or
ALRTTEMP
DIE
The PTAT voltage is computed as follows:
V
PTAT
= (DIAG[15:2]/16384d) x V
REF
V
REF
ALRTEMP
V
THRM
+
-
1.230V
+
-
+
-
LV
MUX
ADC
+
-
V
PTAT
AGND
Figure 10. Die Temperature Measurement
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
10) All enabled auxiliary conversions, in ascending order
(AUXIN1, AUXIN2).
Acquisition Mode
The host enters the acquisition mode by writing a logic-one
to the SCAN bit in the SCANCTRL register. This write is
actually an automatic strobe of the bit since SCAN always
reads logic-zero. In daisy-chained devices, acquisitions
in upstack devices are delayed by the propagation delay
11) Set SCANDONE bit.
Oversampling
Oversampling mode performs multiple measurement
cycles in a single acquisition, and averages the samples
in the ALU to reduce the measurement noise and effec-
tively increase the resolution of each measurement result.
In oversampling mode, acquisition times are proportional
to the number of oversamples, as shown in Table 8. The
number of oversamples can be configured from 4 to 128
by OVSAMPL[2:0], as shown in Table 7. The AUXIN mea-
surements are never oversampled, even in oversampling
mode.
(t ) of the command packet through each device.
PROP
The acquisition is complete when the device sets the
SCANDONE bit. The basic acquisition process is outlined
below with a detailed flowchart in Figure 8:
1) Disable HV charge pump.
2)
V
BLKP
conversion, if enabled.
3) All enabled cell conversions (first):
a. Ascending order (1:12) if pyramid mode, or
b. Descending order (12:1) if top-down mode.
To add n bits of measurement resolution requires at least
2n
2
oversamples. Since the ADC resolution is 12 bits,
4) All enabled cell conversions (second):
a. Descending order (12:1).
13-bit resolution requires at least 4 oversamples and to
achieve the maximum 14-bit resolution requires at least
16 oversamples; therefore, with no oversampling, only
the higher 12 bits of the measurement are statistically
significant and with 4 or 8 oversamples, only the higher
13 bits are statistically significant. Taking more than 16
oversamples further reduces the measurement variation.
5)
V
BLKP
conversion (second), if enabled.
6) Diagnostic conversion (first), if enabled.
7) Diagnostic conversion (second), if enabled.
8) Enable HV charge pump for recovery period unless:
a. OVSAMP[2:0] = 0 (no oversampling), or
Of course with no oversampling, measurements can be
averaged externally to achieve increased resolution, but
at a higher computational cost for the host.
b. All oversample measurements are complete.
9) Repeat steps 1–8 until all oversamples are done.
Table 7. Oversampling
OVSAMPL[2:0]
000b (default)
001b
OVERSAMPLES
THEORETICAL RESOLUTION
ACQUISITION WATCHDOG TIMEOUT
0
4
12 bits
13 bits
13 bits
14 bits
14 bits
14 bits
14 bits
14 bits
1.10ms
2.08ms
3.36ms
5.92ms
10.99ms
21.18ms
41.56ms
41.56ms
010b
8
011b
16
32
64
128
128
100b
101b
110b
111b
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
the equation, so it’s a tradeoff between response times to
change in input value versus the noise attenuation. Refer
to the application note in detail for how the filter affects the
accuracy performance of MAX17843.
Infinite Impulse Response Filtering (IIR Filter):
To augment the accuracy performance, an IIR filtering
scheme is implemented where the results of the cell volt-
ages are filtered after the oversampling. The IIR filter is
implemented by the simple equation below:
Two new bits are added for the control of the data flow
through the filter:
Y(n) = FC x X(n) + (1 - FC) x Y(n-1)
where FC = filter coefficient, user-selectable 3 bits.
The default value is b’010, which has a weight of 3/8:
● X (n) = 3/8
1) AMEND Filter (AMENDFILT) bit
2) Read Filter (RDFILT) bit
AMENDFILT is in SCANCTRL register 0x13.
This bit when set to ‘1’ enables the automatic transfer
of the new ADC conversion from the ALUn to CELLn
registers through the IIR filter at the end of the scan. The
default value is ‘0’, which keeps the scan conversion data
in the ALUn register as an unfiltered result.
● Y (n-1) = 5/8
The detailed filter coefficient settings are mentioned in the
DEVCFG1 register. The filter can be turned off by setting
the coefficient bits to b’111. The smaller that coefficient
is, the more the history, represented by Y (n-1) outputs in
Y(n-1)
X(n)
Y(n)
INTERNAL
REGISTER
COMBINATIONAL
LOGIC
USER
REGISTER
IIR FILTER LOGIC
DIAGRAM
Figure 11. IIR Filter Block Diagram
Table 8. AMENDFILT Bit
AMENDFILT BIT
FUNCTIONALITY AND RECOMMENDED USAGE
No transfer of the ADC conversion result from ALUn to CELLn registers. Unfiltered data is stored in ALUn
registers at the end of the scan. This bit should be set to ‘0’ during any diagnostic conversion such as open-
sense wire, or using balancing switches.
0
1
Automatic transfer of the ADC conversion result from ALUn to CELLn registers at the end of the scan
through the IIR filter. Instantaneous unfiltered data is available in ALUn registers while the filtered data is
stored in the CELLn registers. This bit should be set to ‘1’ during normal cell-voltage measurements.
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Data-Acquisition Interface
RDFILT Bit in SCANCTRL Register (0x13)
This bit chooses where the ADC scan data is read from. Writing this bit to ‘1’ enables the read to occur from filtered CELLn
registers. The default value is ‘0’, wherein the read of the scanned data occurs from unfiltered ALUn registers.
START OF ADC SCAN
NO
ADC SCAN
COMPLETE?
YES
INSTANTANEOUS RESULT IN ALUn REGISTERS
UNFILTERED RESULT
NO
STORED IN ALUn
REGISTERS
AMENDFILT = 1?
YES
IIR FILTER
{CELLn = FC x ALU REGISTER +
(1-FC) x CELLn REGISTER}
INSTANTANEOUS RESULT IN ALUn REGISTERS
FILTERED RESULT STORED IN CELLn REGISTERS
Figure 12. IIR Flowchart with Respect to the AMENDFILT Bit
Table 9. RDFILT Bit
RDFILT BIT
FUNCTIONALITY AND RECOMMENDED USAGE
Reads UNFILTERED result from the ALUn registers.
To read back the result of diagnostic conversion such as open sense wire stored in ALUn registers.
0
1
Reads FILTERED result from the CELLn registers.
To read back the cell-voltage measurement data.
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
IIR filtering will be applicable for CELLn and V
results of both the ADCs.
BLKP
ALU REGISTERS
CELL REGISTERS
14
14
14
14
CELL1
ALU1
REGISTER
14
CELL2
REGISTER
ALU2
14
CELLn
REGISTER
DEMUX
IIR FILTER
MUX
ALUN
14
14
14
14
CELL12
ALU12
REGISTER
VBLOCK
REGISTER
BLOCK ALU
CONTROL
CIRCUITRY
RDFILT
14
UART DATA BUS
Figure 13. IIR Filter Diagram with Respect to RDFILT
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Data-Acquisition Interface
It is divided into two 8-bit time-delay settings, with lower-
byte register-delay setting for cell-recovery time, while
upper byte of the register used for the delay setting of
certain diagnostics such as sense-wire open. This delay
should be set as appropriate by the customer according
to their cell characteristics and properties and to enhance
the maximum SoC of the battery available. Once the
measurement is executed and the Scan done bit is set,
the AUTOBALSWDIS bit should be cleared by the host.
AUTOBALSWDIS Feature
This feature enables the automatic disabling of the balanc-
ing switches during measurements. The main purpose
of this feature is to phase out the additional voltage drop
due to cell balancing in accuracy measurements. This
ultimately allows the system to get more precise cell-
voltage readings, which helps to calculate higher accu-
racy of state-of-charge (SoC). The AUTOBALSWDIS bit
is the D11 bit in the DEVCFG1 register. This bit when
set to '1' turns off the balancing switches. A delay in
the AUTOBALSWDIS delay register (0x0C) is selected
based on the DELAYSEL bit in the SCANTCTRL register
(0x13), and the set wait time is added after the scan is
enabled before the start of actual measurements. The
AUTOBALSWDIS delay register has a minimum delay
setting of 96μs, with maximum being up to 24.57ms.
Enabling the AUTOBALSWDIS bit adds a delay before
the start of measurements, but after the scan is enabled;
therefore, this feature can be used during normal cell
measurements as well as during diagnostic measure-
ments with two separate delay timers that can be
independently set.
AUTOBALSWDIS/
BALSWDISABLE/
DISABLING OF
BALANCING SWITCHES
EMGCYDCHG/
THRMSHDN/
BALANCING SWITCH
ENABLE
(BALSWEN)n
RST/
POR
PRIORITY OF OPERATION
THRMSHDN > EMGCYDCHG > AUTOBALSWDIS/BALSWDISABLE > BALSWENn
Figure 14. Logic Diagram when Balancing Switches Are Disabled
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Data-Acquisition Interface
measurement data registers are also cleared. The acquisi-
tion watchdog-timeout interval depends on the oversam-
pling configuration, as shown in Table 7.
Acquisition Watchdog Timeout
If the acquisition does not finish within a predetermined
time interval, the SCANTIMEOUT bit is set, the ADC
logic is reset, the ALU registers are cleared, and the
STANDBY MODE
NO
COMPARE
SCAN BIT SET?
MEASUREMENTS TO
THRESHOLDS AND
UPDATE ALERTS
YES
LATCH ACQUISITION
CONFIGURATION;
DISABLE HV CHARGE
PUMP
CONVERT AUXINn
INPUTS IF ENABLED;
USE AINCFG SETTLING
TIME
SET ADC STATE
MACHINE TIMEOUT
PERIOD
COMPARE AUXINn
MEASUREMENT TO
THRESHOLDS, UPDATE
ALERTS
CLEAR ALL ALU
REGISTERS
NO
AMENDFILT
SET?
YES
SET CELL = FILTOUT
SET SCANDONE
PERFORM
MEASUREMENT
SCANS FOR VBLKP,
Enable HV charge pump
for 100.3µs
CELLn, DIAG PER
MEASUREEN
ENABLE HV CHARGE
PUMP
NO
ALL SAMPLES
DONE?
YES
STANDBY MODE
Figure 15. Acquisition Mode Flowchart
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
offset and reference-induced errors. The two conversions
are then offset corrected and averaged in the ALU.
Scan Modes
The cell, block, and diagnostic-measurement cycle con-
sists of two conversion phases. In each phase, the ADC
scans through the enabled input channels. There are
two scan modes configured by the SCANMODE bit. If
SCANMODE = 0, the mode is pyramid mode, as shown
in Figure 16. If SCANMODE = 1, the mode is top-down
mode. In pyramid mode, the ADC scans first ascending
and then descending. In top-down mode, the ADC scans
descending in both phases. In the second scan, the
amplifier inputs are inverted to effectively chop out any
After the cell and block scans are complete, the diag-
nostic conversions are made, if enabled, and finally, the
auxiliary inputs, if enabled, are converted. The auxiliary
inputs are measured using a single conversion and stored
in the AIN1 and AIN2 registers. Any extra settling time, if
configured by AINCFG[5:0], is implemented just before
the conversion for each AUXIN channel, so if both inputs
are enabled, the extra settling time occurs twice.
Figure 16. Acquisition, OVSAMP[2:0]=0h and SCANMODE=0
Figure 17. Acquisition, OVSAMP[2:0] > 0 and SCANMODE=0
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Data-Acquisition Interface
Acquisition Time
The total acquisition time can be calculated by summing all the required processes, as shown in Table 10 and Table 11.
There is one measurement cycle per oversample.
Table 10. Acquisition Time
PROCESS
Initialization
measurement
TIME (µs)
CONDITION
FREQUENCY
13
Always
If V is enabled
BLKP
Once per acquisition
V
27
BLKP
12.5
If cell input(s) enabled and V
If cell input(s) enabled and V
enabled
disabled
BLKP
BLKP
Cell scan setup
Cell scans
20
9 x n
For n = Number of enabled cell inputs
If zero-scale ADC output diagnostic enabled
If full-scale ADC output diagnostic enabled
11.4
Every measurement cycle
11.4
Diagnostic
measurement
(if enabled)
86.2
If V
diagnostic enabled
ALTREF
86.2
If die temperature diagnostic enabled
If any other diagnostic mode enabled
22.9
10
If AUXIN1 is enabled
6µs x AINCFG[5:0]
10
AUXIN measurement
(if enabled)
Once per acquisition
If AUXIN2 is enabled
6µs x AINCFG[5:0]
HV recovery (if
oversampling enabled)
After every measurement
cycle except the last
100.3 x m
For m = Number of oversamples
Table 11. Acquisition Time Examples (with AINCFG[5:0] = 00h)
ENABLED MEASUREMENTS
12 cells
12 cells, V
NO OVERSAMPLING
141.0µs
FOUR OVERSAMPLES
825.9µs
EIGHT OVERSAMPLES
1739.1µs
160.5µs
903.9µs
1895.1µs
BLKP
12 cells, AUXIN1 and AUXIN2
161.0µs
845.9µs
1759.1µs
12 cells, V
12 cells, V
and AUXIN2
, AUXIN1 and AUXIN2
180.5µs
923.9µs
1915.1µs
BLKP
BLKP
, die temperature, AUXIN1
266.7µs
1268.7µs
2604.7µs
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
set threshold to full scale, or setting the undervoltage set
threshold to zero scale, effectively disables voltage alerts.
Measurement Alerts
After the measurement cycle, the ALU compares the
enabled measurements to the various configured thresh-
olds, as shown in Table 12, and sets the alert bits before
the ALU data is transferred to the data registers. In over-
sampling mode, the alert status is updated after the last
oversample. The alerts are updated whether or not the
data is moved from the ALU registers to the data registers
and are only updated for those measurements enabled in
the MEASUREEN register.
The ALRTOV and ALRTUV bits in the STATUS register
are set when any alert flag is set in the ALRTOVCELL or
ALRTUVCELL registers, respectively. ALRTCELL[n] is the
logical OR of ALROVCELL[n] and ALRTUVCELL[n].
Cell Mismatch
Enable the mismatch alert to signal when the minimum
and maximum cell voltages differ by more than a specified
voltage. The MSMTCH register sets the 14-bit threshold
Voltage Alerts
(V
) for the mismatch alert (ALRTMSMTCH).
MSMTCH
Use the ALRTOVEN and ALRTUVEN registers to enable
voltage alerts for the cell and auxiliary inputs. If a cell-
voltage alert is enabled, the cell input voltage is compared
against the programmable overvoltage and undervoltage
thresholds after every acquisition as shown in Figure 14.
Separate thresholds for both setting and clearing the alert
provide hysteresis. Configure the set thresholds for cell
Whenever V
- V
> V
, thenALRTMSMTCH
MAX
MIN
MSMTCH
= 1. The alert bit is cleared when a new acquisition does
not exceed the threshold condition. To disable the alert,
write FFCH to the MSMTCH register (default value).
Cell Statistics
The cell numbers with the lowest and highest voltages
are stored in the MINMAXCELL register. When multiple
cells have the same minimum or same maximum volt-
age, only the highest cell position having that voltage is
reported. The sum of all enabled cell voltages is stored
in the TOTAL register as a 16-bit value. For acquisitions
with no enabled cell inputs, the MINMAXCELL and TOTAL
registers are not updated.
undervoltage (V
) and overvoltage (V
)
UVTHSET
OVTHSET
using the UVTHSET and OVTHSET registers. Configure
the clear thresholds for cell undervoltage (V
)
UVTHCLR
and cell overvoltage (V
) using the UVTHCLR
OVTHCLR
and OVTHCLR registers.
Alert flags in theALRTOVCELL register are set, if enabled,
when the acquired cell voltage is over V . Alerts
OVTHSET
in the ALRTUVCELL register are set, if enabled, when the
acquired cell voltage is under V . The alerts are
cleared when the cell voltage moves in the opposite direc-
tion and crosses the clear threshold. The voltage must
cross the threshold; if it is equal to a threshold, the alert
flag does not change. Therefore, setting the overvoltage
Temperature Alerts
UVTHSET
Temperature alerts, if enabled, occur when the acquired
AUXINx input voltages fall outside the thresholds config-
ured by the AINOT and AINUT registers. Unlike the cell-
voltage alerts, the temperature thresholds do not have the
hysteresis afforded by separate set and clear thresholds.
Table 12. Measurement Alerts
DESCRIPTION
Cell overvoltage (OV)
Cell undervoltage (UV)
Cell mismatch
CONDITION OR RESULT
- V > V
VOVTHSET
ALERT BIT
ALRTOV, ALRTOVn
ALRTUV, ALRTUVn
ALRTMSMTCH
None
LOCATION
STATUS, ALRTOVCELL
STATUS, ALRTUVCELL
STATUS
V
Cn
Cn-1
V
- V
< V
Cn
Cn-1 UVTHSET
V
- V
> V
MSMTCH
MAX
MIN
Cell with minimum voltage
Cell with maximum voltage
Total of all cell voltages
n where V
= V
MINMAXCELL
MINMAXCELL
TOTAL
CELLn
CELLn
MIN
n where V
Σ V
= V
None
MAX
where n = 1–12
None
CELLn
AUXINx overvoltage
(undertemperature)
V
> V
ALTRTCOLD, ALRTOVAINx
ALRTHOT, ALRTUVAINx
STATUS, ALRTOVCELL
STATUS, ALRTUVCELL
AUXINx
AUXINx
AINUT
AINOT
AUXINx undervoltage
(overtemperature)
V
< V
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Enabling adjacent balancing switches simultaneously
may increase the balancing current significantly, so care
must be taken to not exceed the device’s maximum
operating conditions. Fault detection is described in the
Diagnostics section.
Cell Balancing
Cell-Balancing Switches
Cell balancing can be performed using any of the 12 inter-
nal cell-balancing switches to discharge cells. The cell-
balancing current is limited by the external balancing resis-
tors and the internal balancing switch resistance (R ).
SW
V
OVER-VOLTAGE
ALERT SET
OVER-VOLTAGE SET AND CLEAR
THRESHOLDS POR DEFAULT VALUE (+5.0V)
OVER-VOLTAGE CLEAR
THRESHOLD (OVTHRCLR)
OVER-VOLTAGE
ALERT CLEARED
UNDER-VOLTAGE
ALERT CLEARED
CELL VOLTAGE
N
UNDER-VOLTAGE CLEAR
THRESHOLD (UVTHCLR)
UNDER-VOLTAGE SET
THRESHOLD (UVTHRSET)
UNDER-VOLTAGE
ALERT SET
UNDER-VOLTAGE SET
AND CLEAR THRESHOLDS
POR DEFAULT VALUE (+0.0V)
T
Figure 18. Cell Voltage-Alert Thresholds
TO CELL n+1
SENSE
RFILTER
Cn
WIRE
TO HVMUX
CFILTER
RBALANCE
SWn
TO ALTMUX
BALSWEN
HV
RBAL
FILTER
BALANCING
SWITCH (n)
CELL n
RBALANCE
RFILTER
SWn-1
TO ALTMUX
TO HVMUX
SENSE
WIRE
Cn-1
CFILTER
AGND
TO CELL n-1
Figure 19. Internal Cell Balancing
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Data-Acquisition Interface
Maximum Cell-Balancing Current
Cell-Balancing Watchdog
The maximum balancing current is limited by package
power dissipation, average die temperature, average duty
cycle of the switch, and the number of switches conduct-
ing current at any one time.
Even if the host fails to disable the cell-balancing mode, the
cell-balancing watchdog can automatically disable the cell-
balancing switches regardless of the BALSWEN configu-
ration. The cell-balancing watchdog does not modify the
contents of the BALSWEN register. Use the WATCHDOG
register to configure the timeout value from 1s to 3840s
(64min), as shown in Table 14. The pre-divider configu-
ration CBPDIV[2:0] effectively sets the rate at which the
CBTIMER[3:0] counts down (see Figure 20).
The power dissipation must not exceed the absolute
maximum rating of the package, nor should the die tem-
perature go outside the range specified for the desired
level of measurement accuracy. Higher die temperatures
and higher average duty cycles increase the probability
of internal electromigration, so the maximum balancing
current is lowered accordingly, as shown in Table 13 for
an assumed 10-year device lifetime.
Table 13. Maximum Allowed Balancing Current per Switch
AVERAGE LIFETIME DUTY CYCLE
T
= 85°C
T
= 105°C
T
= 125°C
DIE
DIE
DIE
(10 YEARS)
15%
> 320mA
> 320mA
> 320mA
> 320mA
215mA
20%
320mA
256mA
161mA
129mA
25%
Table 14. Cell-Balancing Watchdog Configuration
RANGE OF CBTIMER[3:0]
CBPDIV[2:0]
TIMER LSb PERIOD
MINIMUM
MAXIMUM
000b
001b
010b
011b
100b
101b
110b
Timer Disabled
Timer Disabled
1s
4s
1s
4s
15s
60s
16s
64s
128s
256s
16s
64s
128s
256s
240s
960s
1920s
3840s
CBPDIV2
CBPDIV1
CBPDIV0
BIT 3 BIT 2 BIT 1 BIT 0
TIMER ZERO
FLAG
32.768KHz
CBPDIV
CBTIMER
CELL BALANCING
SWITCH ENABLE
BALSWEN
CBTIMER ENABLE
Figure 20. Cell-Balancing Watchdog
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Data-Acquisition Interface
The host should periodically update CBTIMER to ensure
that it does not count down to zero. If the countdown
timer is allowed to reach zero, the cell-balancing switches
are disabled until the timer is either disabled or refreshed
by writing a nonzero value.
4) Read-only counter DCHGCNTR[3:0] increments at
a 2Hz rate with periodic rollover at Fh. The host can
read this counter periodically to confirm the mode is
active.
5) The GPIO3 pin is driven high while the countdown is
active.
To allow timed balancing with no host interaction, the
GPIO3 pin is configured to output a logic-high level while
the timer is counting using the GPIO3TMR configuration
bit of the GPIO register. An external diode is connected
from GPIO3 to SHDNL to prevent shutdown while the
timer is counting. Once the timer expires, the device shuts
down. The host may intervene prior to the timer expiring
to keep the device active and to reconfigure the device.
The emergency-discharge mode alternates between a
1-minute discharge cycle for odd cells and a 1-minute
discharge cycle for even cells. There is a 62.5ms minimum
off-time at the end of each discharge cycle to ensure no
overlap between even and odd discharge cycles. The
duty cycle of each discharge cycle can be configured by
DCHGWIN[2:0], as shown in Table 15.
Emergency-Discharge Mode
By clearing EMGCYDCHG, the emergency-discharge
mode terminates and the following occurs:
The emergency-discharge mode performs cell-balancing
in a controlled manner so the cells can be discharged
to a safe level in the event of an emergency. The
BALSWDCHG and DEVCFG1 registers provide control
for this mode. A timeout value for the mode is configured
by DISCHGTIME[7:0], as shown in Table 15.
1) The discharge timer is reset.
2) Control of the cell-balancing switches reverts to the
BALSWEN register.
3) Control of GPIO3 reverts to the GPIO register.
The emergency-discharge mode also terminates if
DCHGTIME[7:0] = 0h or the discharge time has reached
the configured timeout.
The emergency-discharge mode is activated by setting
the EMGCYDCHG bit with DCHGTIME[7:0] ≠ 00h. In
emergency-discharge mode, the following occurs:
To prevent the emergency-discharge mode from terminat-
ing prematurely due to a device shutdown (which could
occur due to an extended lapse in host communications),
connect an external diode from GPIO3 to SHDNL to keep
SHDNL high while the timer is counting.
1) The CBTIMER[3:0] is cleared to prevent the cell-
balancing watchdog from disabling the cell balancing.
2) Cell-balancing switches are controlled by
BALSWDCHG, not BALSWEN.
3) The discharge timer starts to count down.
Table 15. Emergency Discharge Mode
FUNCTION
REGISTER FIELD
CONFIGURATION
BEHAVIOR
Switches on for 7.5s, off for 52.5s
Switches on for 15s, off for 45s
…
0h
1h
…
7h
DCHGWIN[2:0]
7.5s/bit
Duty cycle
Switches on for 59.94s, off for 62.5ms
00h
01h
02h
…
Discharge mode disabled
Discharge mode disabled after 4 hours
Discharge mode disabled after 6 hours
…
DCHGTIME[7:0]
2 hours/bit
Timeout
FFh
Discharge mode disabled after 512 hours
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ated (see Figure 21). This event can be detected with
the ALRTRST bit, as shown in Table 16. After a thermal
Low-Voltage Regulator
An internal linear regulator supplies low-voltage power
shutdown, the regulator is not enabled until T
due to hysteresis.
< 130°C
DIE
(V ) for the ADC and digital logic. The regulator is
AA
disabled when SHDNL is active-low or when the die tem-
perature (T ) exceeds 145°C. Once V
2.95V (typ), an internal power-on reset (POR) is gener-
decays below
The low-voltage regulator is continuously monitored for
undervoltage, as described in Table 17.
DIE
AA
Table 16. Low-Voltage Regulator
INPUT: DCIN
INPUT VOLTAGE: 9V to 65V
OUTPUT:
OUTPUT VOLTAGE: 3.3V
V
AA
DISABLE:
V
< 0.6V or T
> 145°C
SHNDL
DIE
Table 17. Low-Voltage Regulator Diagnostic
FAULT
CONDITION
< 2.95V
ALERT
LOCATION
V
undervoltage
V
ALRTRST
STATUS[15]
AA
AA
R
DCIN
DCIN
VAA
LINEAR
REGULATOR
REGULATOR
ENABLE
THERMAL
SHUTDOWN
+
SHDNL
TO SHDNL
CHARGE PUMP
C
DCIN
20MV
HYST.
C
VAA
+
-
INTERNAL
POR/
C
SHDNL
3.0V
+
-
AGND
Figure 21. Low-Voltage Regulator
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
the C12 input, there is insufficient headroom to guarantee
that HVMUX switch resistance is sufficiently low for an
accurate acquisition of the channel. To properly identify
HV Charge Pump
The high-voltage multiplexers must be powered by a sup-
ply higher than any monitored voltage. To this end, an
internal charge pump draws power from the DCIN input
this fault condition, if V –V
is too low during the
HV C12
acquisition, the HV headroom-alert flag (ALRTHVHDRM)
is set in the FMEA2 register. The HV undervoltage and
HV headroom-alert functions can be verified by disabling
to provide a high-voltage supply (V ) that is regulated to
HV
V
DCIN
+ 5.5V (nominal). When the charge pump achieves
regulation, charge pumping stops until the voltage drops
by 20mV. The charge pump is automatically disabled
during shutdown and during the measurement cycle to
eliminate charge-pump noise. The charge pump can also
be disabled manually by setting the HVCPDIS bit in the
DEVCFG2 register.
the HV charge pump (HVCPDIS = 1) and allowing V
HV
to decay while in acquisition mode. An overvoltage com-
parator disables the charge pump in the case where V
–
HV
V
exceeds 8.5V. This condition is indicated by the
DCIN
ALRTHVOV bit in the FMEA2 register. The ALRTHVOV
alert does not necessarily indicate a condition that affects
measurement accuracy. HV charge-pump diagnostics are
summarized in Table 18.
If V –V
drops below V
, the HV undervoltage
HVUV
HV DCIN
flag (ALRTHVUV) is set. If V
drops too low relative to
HV
Table 18. HV Charge-Pump Diagnostics
FAULT
CONDITION
ALERT BIT
ALRTHVUV
LOCATION
FMEA1[3]
FMEA2[0]
FMEA2[2]
V
undervoltage
overvoltage
V
V
–V
< V
HV
HV DCIN
HVUV
HVOV
V
–V
HV DCIN
> V
ALRTHVOV
HV
V
low headroom
V
–V
< V
(min.)
ALRTHVHDRM
HV
HV C12
HVHDRM
+
-
HVOV
TO ALRTHVOV
-
+
TO ALRTHVUV
8.5V
4.1V
+
-
+
-
20MV
HYST.
R
HV
HV
C
HV
CPP
INTERNAL POR/
32KHZ
SWITCH
LOGIC
5.5V
+
-
R
DCIN
DCIN
DISABLE
MEASURING
DISABLE
C
CP
CPN
HVOV
DEVCFG2.
HVCPDIS
+
C
DCIN
MAX17843
15MA
AGND
Figure 22. HV Charge Pump
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Oscillators
Power-On And Shutdown
Two factory-trimmed oscillators provide all timing require-
ments: a 16MHz oscillator for the UART and control logic,
and a 32.768kHz oscillator for HV charge pump and tim-
ers. A special diagnostic counter clocked by the 16MHz
signal is employed to check the 32kHz oscillator. Every two
periods of the 32kHz clock, the counter is sampled. If the
count varies more than 5% from the expected value, the
ALRTOSC1 bit is set, as shown in Table 19. A redundant
alert bit (ALRTOSC2) increases the integrity level. If the
16MHz oscillator varies by more than 5%, communication
errors are indicated.
Applications that remain connected continuously to the
power source rely on the SHDNL input to shut down and
reset the device. When V
< 0.6V, the regulator is
SHDNL
disabled, the POR signal asserted, and the device goes
into an ultra-low-power-shutdown mode. When V
SHDNL
> 1.8V, POR is deasserted, the regulator is enabled, and
the device becomes fully operational in the standby mode.
Power-On Method
The SHNDL input can be driven externally, or can be
controlled using UART communication only. In differential
mode, the signaling on the lower-port receiver drives an
internal charge pump that charges up the external 1nF
capacitor connected to the SHDNL input (see Figure 23).
Device ID Number
The ID1[15:0] register, together with ID2[7:0], contain a
24-bit manufacturing identification number (DEVID[23:0]).
The ID, combined with the manufacturing date, provides
a means of uniquely identifying each device. A device ID
of zero is invalid.
V
reaches 1.8V in 200μs (typ). The charge pump
SHDNL
then self-regulates to V
and can maintain
SHDNLIMIT
V
at a logic-one even with the UART in idle 98%
SHDNL
of the time.
Table 19. Oscillator Diagnostics
FAULT
CONDITION
ALERT BIT
LOCATION
FMEA115
32.768kHz oscillator
32.768kHz oscillator
16MHz oscillator
31.129kHz > f
> 34.406kHz
ALRTOSC1
ALRTOSC2
osc_32k
osc_32k
osc_32k
31.129kHz > f
15MHz > f
> 34.406kHz
> 17MHz
FMEA114
ALRTMAN or ALRTPAR
STATUS4, or STATUS2
DCIN
C42
R40
4.7kΩ
C40
15pF
2nF 600V
RXLP
RXLN
FROM DEVICE (n-1)
TRANSMITTER
CIRCUIT
R41
C43
TO RECEIVER
TO RECEIVER
2nF 600V
4.7kΩ
R42
100kΩ
R43
100KΩ
C41
15pF
GNDL
SHDNL
C44
1nF
FORCEPOR
10MΩ
(C
)
SHDNL
Figure 23. SHDNL Charge Pump
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
device is fully operational (standby mode) within 1ms from
the time communication is first received in the shutdown
mode. The power-on sequence is shown in Figure 24.
Power-On Sequence
Once V
> 1.8V, the regulator is enabled. After V
AA
SHNDL
reaches 3V (typ), the POR signal is deasserted, the oscil-
lators enabled, and the HV charge pump enabled. Once
the HV charge pump is stable, the logic is enabled. The
REGULATOR
DISABLED
POR CLEARED
VOLTAGE
32KHZ OSCILLATOR
APPLIED TO DCIN
ENABLED
DIE TEMP >
145°C
470USEC
DELAY
CHECK DIE
TEMPERATURE
SHUTDOWN
MODE
CHARGE PUMP AND
DIGITAL LOGIC
ENABLED
SHDN/
ACTIVE
CHECK SHDN\
ALRTRST BIT SET
3MS DELAY
REGULATOR ENABLED
DIE TEMP > 145°C
YES
SHDN\ ACTIVE
YES
STANDBY
MODE
VAA <
V
POR_RISING
CHECK VAA
CHARGE PUMP
SETTLED
REGULATOR
DISABLED
MAX17880 FULLY
FUNCTIONAL
Figure 24. Power-On Sequence
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
If only a reset is required, the host can issue a soft-reset
by setting the SPOR bit. This resets the device registers
and disables high-voltage operation, but low-voltage
operation remains enabled (the regulator is not disabled).
Shutdown Mode
Shutdown is performed by bringing V
Table 20 summarizes the methods by which this can be
achieved.
< 0.6V.
SHDNL
Note: For single-ended communication, SHDNL must
be driven externally since the charge-pump operation
requires a differential signal.
The quickest shutdown can be achieved by driving
SHDNL externally with a driver pulldown impedance not
exceeding 1kΩ. If SHDNL is not driven externally, the
host can discharge C
under software control by
SHDNL
Shutdown Sequence
setting the FORCEPOR bit. This will enable a pulldown
(4.7kΩ nominal) to discharge the capacitor with a 4.7μs
time constant.
The shutdown sequence and timing is shown in Figure 25,
Figure 26, and Figure 27. The ALRTSHDNL status bit is
set and the low-voltage regulator disabled as soon as
The slowest method is for the host to simply cease
communication. With the UART idle, there is no charge
pumping and the capacitor discharges through an internal
10MΩ resistor, with a 10ms time constant. If shutdown
faster than 10ms is desired when power is disconnected
from the device, a 200kΩ resistor can be connected
externally from SHDNL to AGND to create a 200μs time
constant.
V
< 0.6V. When the V
and V
decoupling
SHNDL
AA
DDL
capacitors discharge below the POR threshold (2.95V
typ), the device registers are reset and the HV charge
pump disabled. The device is then in an ultra-low-power
state until V
> 1.8V.
SHDNL
Table 20. Shutdown Timing
SHUTDOWN METHOD
R
C
RC
1µs
PULLDOWN
SHDNL
1. Host drives SHDNL pin low
2. Host sets FORCEPOR bit
3. Disconnect DCIN
1kΩ
5kΩ
External
Internal
External
Internal
5µs
1nF
200kΩ
10MΩ
200µs
10,000µs
4. Host places UART in idle mode
POR INACTIVE
V
> V
POR_RISING
AA
CHECK V
AA
V
< V
AA
POR_FALLING
POR ACTIVE
OSCILLATOR, CHARGE
PUMP, DIGITAL LOGIC
DISABLED
Figure 25. Shutdown Sequence
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
RXLP
RXLN
V
SHDNLIMIT
V
SHDNL
tRXFD-VAA
V
IL
t
RXRU-VAA
V
IH
V
PORRISE
V
PORFALL
V
AA
t
VAARU-POR
t
VAAFD-POR
POR
t
PORUP-TX
TXUP
TXUN
Figure 26. Power-On and Shutdown Timing (UART Control)
RXLP
RXLN
t
FRPOR
FORCEPOR
V
IH
V
V
SHDNL
IL
t
RXFD-VAA
V
PORFALL
V
AA
tVAAFD-POR
POR
Figure 27. Shutdown Timing (Software Control)
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Each device first receives data at its lower RX port and
immediately retransmits data from its upper TX port to the
lower RX port of the next upstack device. The last device
transmits data from its upper TX port directly into its upper
RX port and then immediately retransmits the data from
its lower TX port to the upper RX port of the next down-
stack device. The protocol supports fixed baud rates of
2Mb/s, 1Mb/s, or 0.5Mb/s. The baud rate is set by the host
and is automatically detected by the device.
UART Interface
The battery-management UART protocol allows up to
32 devices to be connected in daisy-chain fashion (see
Figure 28). The host initiates all communication with the
daisy-chain devices through a UART interface such as
the MAX17841B. The data flow is always unidirectional
from the host, up the daisy-chain (upstack) and then loops
back down the daisy-chain (downstack) to the host.
Figure 28. System Data Flow
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
UART Ports
UART Receiver
Two UART ports are utilized, a lower port (RXL/TXL) and
an upper port (RXU/TXU). Each port consists of a differ-
ential line driver and differential line receiver. DC-blocking
capacitors or transformers can be used to isolate daisy-
chain devices that are operating at different common-
mode voltages. During communication, the character
encoding provides a balanced signal (50% duty cycle)
that ensures charge neutrality on the isolation capacitors.
The UART receiver has a wide common-mode input
range to tolerate harsh EMC conditions, which can be
operated in differential mode or single-ended mode per
Table 21. By default, the UART receivers are configured
for differential mode. In single-ended mode, the RXP input
is grounded and the RXN input receives inverse data,
as described in the Applications Information section. In
single-ended mode, the receiver input threshold is nega-
tive so that a zero differential voltage (V
, V
= 0V)
RXP RXN
UART Transmitter
is considered to be a logic-one and a negative differential
voltage (V high) is a logic-zero.
When no data is being transmitted by the UART, the
differential outputs must be driven to a common level
to maintain a neutral charge difference between the
AC-coupling capacitors or to avoid saturation of the
isolation transformers. In the default idle mode (low-Z),
the transmitter drives both outputs to a logic-low level
to balance the charge on the capacitors; this also works
well with transformer coupling. The high-Z idle mode
(TXLHIZIDLE, TXUHIZIDLE = 1) places the TX pins in a
high-Z state in idle mode, which may be desirable to mini-
mize the effects of charging and discharging the isolation
capacitors. The idle mode for the upper and lower ports
can be controlled independently through the TXLHIZIDLE
and TXUHIZIDLE configuration bits.
RXN
UART RX Modes
During the first preamble received after a reset, the receiv-
er automatically detects if the received signal is single-
ended and if so, places the receiver in single-ended mode;
therefore, the device must be reset for any change in the
RX-mode hardware configuration to be detected.
The receiver mode is indicated by the ALRTCOMMSEL
bit (for lower port) and ALRTCOMMSEU bit (for upper
port) of the FMEA1 register, as shown in Table 21. If the
RXP input is open circuit, RX-mode detection places the
UART in single-ended mode so the port can still oper-
ate, albeit with reduced noise immunity. The host can
diagnose this condition by checking ALRTCOMMSEL and
ALRTCOMMSEU after any POR event. Any other faults
result in communication errors.
VDDL[2,3]
TX[U,L]IDLEHIZ
(UARTSTATE=IDLE?)
DRIVE HIGH
TX[U,L][P,N]
ESD CLAMP
DRIVE LOW
GNDL[2,3]
Figure 29. UART Transmitter
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
30kΩ
4pF
VDDL/60
1.18MΩ
HIGH
COMPARATOR
RXP
41.6kΩ
VCM =
VDDL/3
ZERO CROSSING
COMPARATOR
GNDL
DIGITAL CORE
LOW
COMPARATOR
41.6kΩ
4pF
1.18MΩ
RXN
VDDL/60
30kΩ
Figure 30. UART Receiver
Table 21. UART RX Modes
RXP
RXN
ALRTCOMMSEn
RX MODE
Connected to data
Grounded
Connected to inverse data
Connected to inverse data
Connected to inverse data
Open circuit (fault)
0
1
1
0
Differential mode (normal)
Single-ended mode (normal)
Open circuit (fault)
Connected to data
Single-ended mode (low noise immunity)
Differential mode (communication errors)
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
the baud rate. A simple way to do this is for the host to
start transmitting preambles and stop when a preamble
has been received back at the host RX port.
UART Loopback
For the last device in the stack, the data must be looped
back from the upper transmitter to the upper receiver. This
is known as loopback and can be configured externally
(default) or internally.
TX Adaptive Mode for Single-Ended Mode
To overcome the error tolerance limitation when connect-
ing a MAX17843 to a conventional UART port, an adaptive
transmit-timing feature has been added. The feature works
by monitoring the location of the incoming Manchester
transitions at the RXL port, with respect to the local clock,
to calculate a correction factor. This correction factor is
then applied to the TXL port so the outgoing downstack
signal has similar timing characteristics to the incoming
upstack signal. With this adaptive transmit timing, the
interface between a conventional UART node and a Maxim
proprietary battery-monitoring system node has a tolerance
for baud-rate mismatch that is much higher than that of
the conventional receiver port alone giving a high level of
timing margin for direct connection applications. TX adap-
tive mode should be enabled only on the bottom device
(device connected to BMS micro or Maxim SPI-to-UART
bridge IC).
External Loopback Mode
External loopback mode (default) uses a two-wire cable to
connect the upper transmitter (TXU) to the upper receiver
(RXU). The external loopback has two advantages:
1) It is quicker to determine device count for applica-
tions where the host does not assume what the
device count is.
2) It helps to match the supply current of the last device
to that of the other daisy-chain devices (because the
hardware configuration is identical).
Internal Loopback Mode
Internal-loopback mode (LASTLOOP = 1) routes the
upper-port transmit data internally to the upper-port receiv-
er. Any signal present on the upper-port receiver input
pins is ignored in the internal loopback mode; therefore,
when LASTLOOP is set, the write command that was
forwarded to any upstack devices is interrupted in the
downstack direction. The host should expect this and read
the LASTLOOP bit to verify that the write was successful. If
the MAX17841B interface is used, its receive buffer should
be cleared before changing LASTLOOP, and cleared again
after changing the loopback configuration because the
communication was interrupted.
Battery-Management UART Protocol
The battery-management UART protocol uses the follow-
ing features to maximize the integrity of the communica-
tions:
● All transmitted data bytes are Manchester-encoded,
where each data bit is transmitted twice with the 2nd
bit inverted (G.E. Thomas convention).
● Every transmitted character contains 12 bits that
Internal-loopback mode is useful to diagnose the location
of a daisy-chain signal break by enabling the internal-loop-
back mode on the first device, checking communication,
then moving the loopback mode to the next device, and
continuing up the stack until communication is lost.
include a start bit, a parity bit, and two stop bits.
● Read/write packets contain a CRC-8 packet error
checking (PEC) byte
● Each packet is framed by a preamble character and
STOP character.
Baud Rate Detection
● Read packets contain a data-check byte for verifying
The UART can operate at a baud rate of 2Mb/s (default),
1Mb/s, or 0.5Mb/s. The baud rate is controlled by the host
and is automatically detected by the device when the first
preamble character is received after reset. If the host
changes the baud rate after reset, it must issue another
reset, which can be done by setting the SPOR bit, and
resend a minimum of 2 x n preambles (where n is the
number of devices). The 2 x n preambles are necessary
since the transmitter for the upper port will not transmit
data until the lower-port receiver has detected the baud
rate; likewise, the transmitter on the lower port will not
transmit data until the upper-port receiver has detected
the integrity of the transmission.
The protocol is also designed to minimize power-
”consumption by allowing slave devices to shut down if
the UART is idle for a specified period of time. The host
must periodically transmit data to prevent shutdown,
unless the SHDNL input is driven externally.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Command Packet
Preamble Character
A command packet is defined as a sequence of UART
characters originating at the host. Each packet starts with
a preamble character, followed by data characters, and
ending with a stop character (see Figure 31). After send-
ing a packet, the host either goes into idle mode or sends
another packet.
The preamble is a framing character that signals the
beginning of a command packet. It is transmitted as an
unencoded 15h with a logic-one parity bit and a balanced
duty cycle. If any bit(s) other than the stop bits deviate
from the unique preamble sequence, the character is
not interpreted as a valid preamble, but rather as a data
character.
PREAMBLE
IDLE
MESSAGE
STOP
IDLE
TXP-TXN
Figure 31. Command Packet
OPTIONAL
IDLE
OPTIONAL
IDLE
S
1
0
1
0
1
0
0
0
E = 1
P
P
IDLE
ENABLE
IDLE
DISABLE
Figure 32. Preamble Character
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The parity is even, which means that the parity bit’s value
should always result in an even number of logic-one bits in
the character. Given that the data is Manchester encoded
and that there are two stop bits, the parity bit for data char-
acters is always transmitted as a logic-zero. If the UART
detects a parity error in any received data character it sets
the ALRTPAR bit in the STATUS register.
Data Characters
Each data character contains a single-nibble (4-bit) pay-
load, so two characters must be transmitted for each byte
of data. All data is transmitted least-significant bit, least-
significant nibble, and least-significant byte first. The data
itself is Manchester encoded, which means that each data
bit is followed by its complement. If the UART detects a
Manchester-encoding error in any received data character,
it will set the ALRTMAN bit in the STATUS register.
See Table 22 for a list of data characters and Figure 33 for
a graphical representation.
Table 22. Data Character
BIT
1
NAME
Start
SYMBOL
DESCRIPTION
S
—
—
—
—
—
—
—
—
E
First bit in character, always logic-zero
2
Data0
Data0/
Data1
Data1/
Data2
Data2/
Data3
Data3/
Parity
Stop
Least-significant bit of data nibble (true)
Least-significant bit of data nibble (inverted)
Data bit 1 (true)
3
4
5
Data bit 1 (inverted)
6
Data bit 2 (true)
7
Data bit 2 (inverted)
8
Most-significant bit of data nibble (true)
Most-significant bit of data nibble (inverted)
Always logic-zero (even parity)
Always logic-one
9
10
11
12
P
Stop
P
Last bit in character, always logic-one
DATA NIBBLE = 0h
0
0
0
0
OPTIONAL
IDLE
OPTIONAL
S
0
1
0
1
0
1
0
1
E = 0
P
P
IDLE
IDLE
ENABLE
IDLE
DISABLE
DATA NIBBLE = Ah
0
1
0
1
OPTIONAL
IDLE
OPTIONAL
IDLE
S
0
1
1
0
0
1
1
0
E = 0
P
P
IDLE
ENABLE
IDLE
DISABLE
Figure 33. Data Characters
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
packet is sent or it goes into keep-alive mode, send-
ing periodic stop characters to prevent the daisy-chain
device(s) from going into shutdown.
Stop Character
The stop character is a framing character that signals the
end of a command packet. It is transmitted as an unen-
coded 54h with a logic-one parity bit and a balanced duty
cycle (see Figure 34).
UART Communication Mode
When transitioning from idle mode to communication
mode, the TXnP pin must be pulled high (logic-one) prior
to signaling the start bit (logic-zero) (see Figure 35). The
duration of the logic-one is minimized to maintain a bal-
anced duty-cycle while still meeting the timing specifica-
tion. When transitioning from the stop bit back to idle
mode, the delay, if any, is also minimized.
UART Idle Mode
In the low-Z (default) idle mode, the transmitter outputs are
both driven to 0V (see Figure 35). In the high-Z idle mode,
the transmitter outputs are not driven by the UART. The
MAX17841B interface automatically places its transmitter
in idle mode immediately after each command packet
and remains in idle mode until either the next command
OPTIONAL
IDLE
OPTIONAL
IDLE
S
0
0
1
0
1
0
1
0
E = 1
P
P
IDLE
ENABLE
IDLE
DISABLE
Figure 34. Stop Character
IDLE
PREAMBLE
IDLE
TXnP
TXnN
t
STSU
TXnP-TXnN
Figure 35. Communication Mode
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The device ignores commands containing a device
address other than its own.
Data Types
The battery-management UART protocol employs several
different data types, as described in Table 23.
Register Addresses
All register addresses are single-byte quantities and are
defined in the Register Map. In general, if the register
or device address in a received command is not a valid
address for the device, the device ignores the read or write
and simply passes through the packet to the next device.
Command Bytes
The battery-management UART protocol supports six
command types summarized in Table 24.
Command-Byte Encoding
Command bytes encoding is described in Table 25.
For READDEVICE and WRITEDEVICE commands,
the device address is encoded in the command byte.
Register Data
All registers are 16-bit words (two data bytes) and are
defined in the Register Map
.
Table 23. Battery-Management UART Protocol (Data Types)
DATA TYPE
Command byte
Register address
Register data
Data-check byte
PEC byte
DESCRIPTION
A byte defining the command-packet type, generally either a read or a write.
A byte defining the register address to be read or written.
Register data bytes being read or written.
An error and alert status byte sent and returned with all reads.
A packet-error-checking byte sent and returned with every packet except for HELLOALL.
A byte functioning as a device counter on all reads and writes, if ALIVECNTEN = 1.
Bytes transmitted in READALL command packets for clocking purposes only.
Alive counter
Fill byte
Table 24. Battery-Management UART Protocol (Command Packet Types)
DATA
CHECK
ALIVE-
COUNTER
PACKET SIZE
(CHARACTERS)
COMMAND
DESCRIPTION
PEC
Writes a unique device address to each device in
the daisy-chain. Required for system initialization.
HELLOALL
No
No
No
8
WRITEALL
WRITEDEVICE
READALL
Writes a specific register in all devices.
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
14
14
Writes a specific register in a single device.
Reads a specific register from all devices.
Reads a specific register from a single device.
Reads a set of registers from a single device.
Yes
Yes
Yes
12 + (4z)
16
READDEVICE
READBLOCK
14 + (4 x BS)
Notes: z = Total number of devices, ALIVECNTEN = 1, packet size includes framing characters.
BS[4:0] = Block size[4:0] = 1–32, which is the number of registers read.
Table 25. Command-Byte Encoding
COMMAND
HELLOALL
BYTE*
57h
7
0
6
1
5
0
4
1
3
0
2
1
1
0
1
0
1
1
1
0
1
0
1
1
0
1
0
0
1
1
0
WRITEDEVICE
WRITEALL
04h
DA4
0
DA3
0
DA2
0
DA1
0
DA0
0
02h
READDEVICE
READALL
05h
DA4
0
DA3
0
DA2
0
DA1
0
DA0
0
03h
READBLOCK
06h
BS4
BS3
BS2
BS1
BS0
*Notes: Assumes DA[4:0] = 0x00 where DA[4:0] is the device address in the ADDRESS register.
BS[4:0] = Block size (1–32).
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bit is set in the DEVCFG1 register. The host typically
transmits the alive-counter seed value as 00h, but any
value is permitted. For WRITEALL or READALL com-
mands, each device retransmits the alive counter, incre-
mented by one. For WRITEDEVICE or READDEVICE
commands, only the addressed device will increment it.
The alive counter is not used in the HELLOALL command.
If the alive counter reaches FFh, the next device incre-
ments it to 00h.
Data-Check Byte
The host uses the returned data-check byte to promptly
determine if any communication errors occurred during
the packet transmission and to check if alert flags are set
in any devices, as shown in Table 26. The data-check
byte is returned by the READALL and READDEVICE
commands. For READDEVICE, the data-check byte is
updated only by the addressed device.
The data-check byte sent by the host is a seed value nor-
mally set to 00hN although nonzero values can be used
as a diagnostic. Each device logically ORs the received
data-check byte with its own status and transmits it to the
next device. A PEC error detected by any device will set
the ALRTPEC bit in the STATUS register and, by exten-
sion, the ALRTPEC and ALRTSTATUS bits in the data-
check byte.
Since the alive counter comes after the PEC byte, an
incorrect PEC value does not affect the incrementing of
the alive-counter byte. Also, the PEC calculation does
not include the alive-counter byte. The host should verify
that the alive counter equals the original seed value + the
number of devices, considering that if the alive-counter
reaches FFh, the next device increments it to 00h.
Fill Bytes
PEC Byte
In the READALL command, the host sends two fill bytes
for each device in the daisy-chain. The fill bytes are the
locations within the packet and are used by the device to
place the read data. The fill-byte values transmitted by the
MAX17841B interface alternate between C2h and D3h.
As the command packet propagates through the device,
the device overwrites the appropriate fill bytes with the
register data. The device uses the ADDRESS register to
determine which specific fill bytes in the packet are to be
overwritten.
The PEC byte is a CRC-8 packet-error check sent by
the host with all read and write commands. If any device
receives an invalid PEC byte, it sets the ALRTPEC bit in
the STATUS register. During any write transaction, a device
does not execute the write command internally unless the
received PEC matches the expected calculated value. For
read commands, the device must return its own calculated
PEC byte based on the returned data. The host should
verify that the received PEC byte matches the calculated
value and if an error is indicated, the data should be dis-
carded. See Applications Information section for details on
the PEC calculation.
For a READDEVICE command, only two fill bytes are
required since only one device responds (returning two
data bytes). Also, fill bytes are not required for write com-
mands because the data received is exactly the same as
the data retransmitted.
Alive-Counter Byte
The alive-counter byte is the last data byte of the com-
mand packets (except HELLOALL) if the ALIVECNTEN
Table 26. Data-Check Byte
BIT
7
NAME
ALRTPEC
ALRTFMEA
ALRTSTATUS
CHECK
DESCRIPTION
ALRTPEC is set.
6
ALRTFMEA1 or ALRTFMEA2 is set.
STATUS bit other than ALRTFMEA1, ALRTFMEA2, ALRTOV, and ALRTUV is set.
Check bit. Value received is forwarded.
Check bit. Value received is forwarded.
ALRTOV is set.
5
4
3
CHECK
2
ALRTOV
1
ALRTUV
ALRTUV is set.
0
CHECK
Check bit. Value received is forwarded.
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last address is known, the host can determine how many
devices are in the daisy-chain, which is required for sub-
sequent READALL commands. A READALL command
should be used to verify the ADDRESS registers.
Battery-Management
UART Protocol Commands
HELLOALL Command
The purpose of the HELLOALL command is to initialize the
device addresses of all daisy-chained devices. The device
address is stored in the DA[4:0] bits of the ADDRESS reg-
ister. The highest address possible is 0x1F, so a maximum
of 32 devices can be addressed. The command must be
issued after POR to reinitialize all device addresses.
Special considerations exist if the host desires to use
internal loopback instead of external loopback. The
first HELLOALL command is not returned to the host
because the internal loopback bit for the top device has
not yet been written. If the number of devices is known
to the host, the host can use a WRITEDEVICE to set the
internal loopback bit on the last device and then verify
with a READALL command. If the number of devices is
unknown, the internal loopback bit must be set on the first
device, verified, and then cleared. It can then be set on
the second device and verified, and so on incrementally
until there is no response (end of stack). With the number
of devices known, the loopback bit can be reset on the
last device and all ADDRESS registers verified.
When the HELLOALL command is first sent by the host,
the address specified in the HELLOALL command is
stored to the DA[4:0] bits of the ADDRESS register in the
first daisy-chained device. The command is then forward-
ed to the next device in the chain, with the DA[4:0] bits of
the address byte incremented by 1, as shown in Table 27.
This continues in the upstack direction for each device.
The downstack communication path does not increment
the address. The advantage of the host choosing a first
address of 0x00 is that it is not necessary to write the first
address FA[4:0] to all the devices since the default value
of FA[4:0] is 0x00. Note: The host should set the first
address so that no assigned device address increments
from 0x1F to 0x00 during the HELLOALL command.
When a device receives a valid HELLOALL command, it
clears the ADDRUNLOCK bit of the DEVCFG1 register.
When this bit is 0, HELLOALL commands are ignored to
prevent inadvertently changing any device address. To
reconfigure the device address, the ADDRUNLOCK bit
must first be set to 1, or a POR event must occur. After
configuring the device addresses, they should be verified
using the READALL or ROLLCALL commands.
The DA[4:0] value returned to the host is one greater
than the address assigned to the last device. Once this
Table 27. HELLOALL Sequencing (z = Total Number of Devices)
HOST TX
Preamble
57h
DEVICE (n) RXL
DEVICE (n) TXU
HOST RX
Preamble
Preamble
Preamble
57h
57h
57h
00h
00h
{0b000,ADDR[4:0]+n-1}
Stop
00h
{0b000,ADDR[4:0]+n}
Stop
00h
{0b000,ADDR[4:0]+z}
Stop
{0b000,ADDR[4:0]}
Stop
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WRITEALL Command
WRITEDEVICE Command
The WRITEALL command writes a 16-bit value to a speci-
fied register in all daisy-chained devices. Since most con-
figuration information is common to all the devices, this
command allows faster setup than writing to each device
individually. If the register address is not valid for the
device, the command is ignored. The command sequence
is shown in Table 28.
The WRITEDEVICE command writes a 16-bit value to
the specified register in the addressed device only. If the
register address is not valid for the device, the command
is ignored. The command sequence is shown in Table 29.
The register value is written immediately after the valid
PEC byte is received, or if NOPEC is set, after the last
byte is received. If the received PEC byte does not match
the internal calculation, the command is not executed,
but is still forwarded to the next device. The PEC is cal-
culated from the first four bytes of the command starting
after the preamble. A PEC error sets the ALRTPEC bit in
the STATUS register. A PEC error can only occur in the
addressed device.
The register value is written immediately after the valid
PEC byte is received, or if NOPEC is set, after the last
byte is received. If the received PEC byte does not match
the internal calculation, the command is not executed, but
is still forwarded to the next device. The PEC is calculated
from the first four bytes of the command starting after the
preamble. A PEC error will generate a PEC alert in the
device STATUS register.
Table 28. WRITEALL Sequencing (Unchanged by Daisy-Chain)
HOST TX
DEVICE (n) RXL
Preamble
02h
DEVICE (n) TXU
Preamble
02h
HOST RX
Preamble
02h
Preamble
02h
[REG ADDR]
[DATA LSB]
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
[DATA MSB]
[PEC]
[ALIVE]*
[ALIVE]*
[ALIVE]*
[ALIVE]*
Stop
Stop
Stop
Stop
*If alive-counter mode is enabled.
Table 29. WRITEDEVICE Sequencing (Unchanged by Daisy-Chain)
HOST TX
Preamble
DEVICE (N) RXL
Preamble
DEVICE (N) TXU
Preamble
HOST RX
Preamble
{(DA[4:0]),0b100}
[REG ADDR]
[DATA LSB]
{(DA[4:0]),0b100}
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
{(DA[4:0]),0b100}
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
{(DA[4:0]),0b100}
[REG ADDR]
[DATA LSB]
[DATA MSB]
[PEC]
[DATA MSB]
[PEC]
[ALIVE]*
[ALIVE]*
[ALIVE]*
[ALIVE]*
Stop
Stop
Stop
Stop
*If alive-counter mode is enabled.
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ensuring that the Manchester error is propagated through
the daisy-chain and back to the host.
READALL Command
The READALL command returns register data from the
specified register for all daisy-chain devices. The data
for the first device (connected to host) is returned last.
The command sequence is shown in Table 30. If the
received PEC byte does not match the calculated value,
the ALRTPEC bit of the data-check byte and ALRTPEC
bit of the STATUS register are set, but the command pro-
ceeds. A Manchester error immediately switches the data
propagation from read mode to write (pass-through) mode
The fill-byte values transmitted by the MAX17841B
interface alternate between C2h and D3h as shown.
As the packet propagates through the device, the device
retransmits it in the order shown in the sequencing table
(device TXU column). The device knows which bytes to
overwrite since its ADDRESS register contains the first
device address and its own device address and therefore
knows where in the data stream it belongs.
Table 30. READALL Command Sequencing (z = Number of Devices)
HOST TX
DEVICE (n) RXL
Preamble
03h
DEVICE (n) TXU
Preamble
03h
HOST RX
Preamble
Preamble
03h
03h
[REG ADDR]
[REG ADDR]
[DATA LSB(n-1)]
[DATA MSB(n-1)]
…
[DATA ADDR]
[DATA LSB(n)]
[DATA MSB(n)]
…
[REG ADDR]
[DC] = 0x00
[DATA LSB(z)]
[PEC]
[DATA MSB(z)]
[ALIVE]*
[DATA LSB(z-1)]
[FD(1) C2h]
…
…
[DATA MSB(z-1)]
[FD(1) D3h]
[DATA LSB(1)]
[DATA MSB(1)]
[DC]
[DATA LSB(1)]
[DATA MSB(1)]
[DC]
…
[FD(2) C2h]
…
[FD(2) D3h]
…
…
[PEC]
[PEC]
…
…
[ALIVE]*
[ALIVE]*
…
…
…
[FD(1) C2h]
[FD(1) D3h]
…
[FD(1) C2h]
[FD(1) D3h]
…
…
[DATA LSB(1)]
[DATA MSB(1)]
[DC]
…
…
[FD(z) C2h]
…
…
[FD(z-n) C2h]
[FD(z-n) D3h]
Stop
[FD(z-n-1) C2h]
[FD(z-n-1) D3h]
Stop
[PEC]
[FD(z) D3h]
[ALIVE]*
Stop
Stop
12+(4 x z) characters
*If alive-counter mode is enabled.
12+(4 x z) characters
12+(4 x z) characters
12+(4 x z) characters
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The command packet is forwarded up the daisy-chain until
it reaches the addressed device. The addressed device
overwrites the received fill bytes with the two bytes of reg-
ister data and forwards the packet to the next device. The
alive-counter byte is only incremented by the addressed
device. A Manchester error immediately switches the
data propagation from read mode to write (pass-through)
mode, ensuring that the Manchester error is propagated
through the daisy-chain and back to the host.
READDEVICE Command
The READDEVICE command returns a 16-bit word read
from the specified register in the addressed device only.
If the register address is not valid for the device, the com-
mand is ignored. The command sequence is shown in
Table 31.
Table 31. READDEVICE Sequencing
HOST TX
Preamble
DEVICE RXL
Preamble
{DA[4:0], 0b101}
[REG ADDR]
[DC]
DEVICE TXU
Preamble
{DA[4:0], 0b101}
[REG ADDR]
[DATA LSB]
[DATA MSB]
[DC]
HOST RX
Preamble
{DA[4:0], 0b101}
[REG ADDR]
[DATA LSB]
[DATA MSB]
[DC]
{DA[4:0], 0b101}
[REG ADDR]
[DC]
[PEC]
[PEC]
[ALIVE]*
[ALIVE]*
[FD(1) C2h]
[FD(1) D3h]
Stop
[FD(1) C2h]
[FD(1) D3h]
Stop
[PEC]
[PEC]
[ALIVE]*
[ALIVE]*
Stop
Stop
16 characters
*If alive-counter mode is enabled.
16 characters
16 characters
16 characters
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The command packet is forwarded up the daisy-chain
until it reaches the addressed device. The addressed
device overwrites the received fill bytes with the two bytes
of register data (from a single device) and forwards the
packet to the next device. The alive-counter byte is only
incremented by the addressed device. A Manchester error
immediately switches the data propagation from read
mode to write (pass-through) mode, ensuring that the
Manchester error is propagated through the daisy-chain
and back to the host.
READBLOCK Command
The READBLOCK command returns an 18-byte read
from the specified register for a block size of 1 in the
addressed device only. If the register address is not valid
for the device, it returns zero for any invalid addresses. If
the device address is not valid, the command is ignored.
The command sequences for a block size of 1 and for
a block size of 2 are shown in Table 32 and Table 33
respectively.
,
Table 32. READBLOCK Sequencing for Block Size = 1
HOST TX
Preamble
DEVICE RXL
Preamble
DEVICE TXU
Preamble
HOST RX
Preamble
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DATA LSB]
[DATA MSB]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DATA LSB]
[DATA MSB]
[DC]
[PEC]
[PEC]
[ALIVE]*
[ALIVE]*
[FD(1) C2h]
[FD(1) C2h]
[FD(1) D3h]
Stop
[PEC]
[PEC]
[FD(1) D3h]
[ALIVE]*
[ALIVE]*
Stop
Stop
Stop
18 characters
*If alive-counter mode is enabled.
18 characters
18 characters
18 characters
Table 33. READBLOCK Sequencing for Block Size = 2
HOST TX
Preamble
DEVICE RXL
Preamble
DEVICE TXU
Preamble
HOST RX
Preamble
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DATA0 LSB]
[DATA0 MSB]
[DATA1 LSB]
[DATA1 MSB]
[DC]
{BS[4:0], 3b110}
[DEVICE ADDR]
[REG ADDR]
[DATA0 LSB]
[DATA0 MSB]
[DATA1 LSB]
[DATA1 MSB]
[DC]
[PEC]
[PEC]
[ALIVE]*
[ALIVE]*
[FD(1) C2h]
[FD(1) C2h]
[FD(1) D3h]
[FD(1) C2h]
[FD(1) D3h]
Stop
[FD(1) D3h]
[FD(1) C2h]
[PEC]
[PEC]
[FD(1) D3h]
[ALIVE]*
[ALIVE]*
Stop
Stop
Stop
22 characters
*If alive-counter mode is enabled.
22 characters
22 characters
22 characters
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at key-on), or periodically during operation, as required by
the application. Diagnostics performed automatically by the
device are previously described in the relevant functional
sections. A description of the diagnostics requiring specific
configurations are provided in this section.
Diagnostics
Built-in diagnostics support ISO 26262 (ASIL) requirements
by detecting specific fault conditions, as shown in Table 34.
The device automatically performs some of the diagnostics
while the host can perform others during initialization (e.g.,
Table 34. Summary of Built-In Diagnostics
DIAGNOSTICS PERFORMED AUTOMATICALLY BY DEVICE, WITHOUT HOST INTERVENTION
FAULT
DIAGNOSTIC PROCEDURE
Continuous voltage comparison
OUTPUT
ALRTRST
V
V
undervoltage
undervoltage
overvoltage
AA
Continuous voltage comparison
ALRTHVUV
HV
V
Continuous voltage comparison
ALRTHVOV
HV
V
low headroom
Voltage comparison – updated during measurement
Continuous frequency comparison
Communication error checking
ALRTHVHDRM
HV
32kHz oscillator fault
16MHz oscillator fault
Communication fault
RX pin open/short
ALRTOSC1, ALRTOSC2
ALRTMAN, ALRTPAR
ALRTPEC, ALRTMAN, ALRTPAR
ALRTCOMMSEUn/ALRTCOMMSELn
ALRTVDDLx
Communication error checking
Verify RX mode after POR
VDDLx pin open/short
GNDLx pin open/short
Die over-temperature
Continuous voltage comparison
Continuous voltage comparison
ALRTGNDLx
temperature comparison – updated after measurement.
ALRTTEMP
DIAGNOSTICS PERFORMED DURING ACQUISITION MODE, AS SELECTED BY DIAGSEL OR BALSWDIAG
FAULT
DIAGNOSTIC PROCEDURE
DIAGSEL[2:0]
DIAGSEL = 1h
DIAGSEL = 2h
DIAGSEL = 2h
DIAGSEL = 3h
DIAGSEL = 4h
DIAGSEL = 5h
DIAGSEL = 6h
BALSWDIAG = 1h
BALSWDIAG = 2h
BALSWDIAG = 5h
BALSWDIAG = 6h
OUTPUT
Reference voltage fault
ALTREF diagnostic
DIAG[15:0] (ALTREF voltage)
V
V
voltage fault
voltage fault
V
V
diagnostic ADC1
diagnostic ADC2
DIAG[15:0] (V voltage)
AA
AA
AA
AA
DIAG[15:0] (V /2 voltage)
AA
AA
LSAMP Offset too high
ADC bit stuck high
ADC bit stuck low
LSAMP offset diagnostic
Zero-Scale ADC diagnostic
Full-Scale ADC diagnostic
Die Temperature diagnostic
BALSW diagnostic mode
BALSW diagnostic mode
BALSW diagnostic mode
BALSW diagnostic mode
DIAG[15:0] (LSAMP offset voltage)
DIAG[15:0] (Zero-scale)
DIAG[15:0] (Full-scale)
V
or ALRTTEMP fault
DIAG[15:0] (V
voltage), ALRTTEMP
PTAT
PTAT
Balancing switch short
Balancing switch open
Odd sense-wire open
Even sense-wire open
ALRTBALSW
ALRTBALSW
ALRTBALSW
ALRTBALSW
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Table 34. Summary of Built-In Diagnostics (continued)
PROCEDURAL DIAGNOSTICS
FAULT
DIAGNOSTIC PROCEDURE
Idle mode
OUTPUT
SHDNL stuck high
HVMUX switch open
HVMUX switch short
HVMUX test sources
Cn pin open
ALRTSHDNL
Acquisition with HVMUX test sources
ALTREF diagnostic
ALRTOV, ALRTUV
DIAG[15:0]
Acquisition with HVMUX test sources
Acquisition with cell-test sources
Acquisition with balancing switches
ALTMUX vs. HVMUX acquisition
ALTMUX acquisition with balancing switches
ALTMUX acquisition with balancing switches
Acquisition with HV charge pump disabled
Acquisition with cell-test sources
Acquisition with ADCTEST = 1
CELLn
ALRTOV, ALRTUV
Cnshort to SWn
CELLn
Cn pin leakage
CELLn
Voltage comparator fault
Voltage comparator fault
ALRTHVUV comparator
HVMUX sequencer
ALU Data Path
CELLn
CELLn
ALRTHVUV
CELLn
CELLn, VBLKP, DIAG, and AUXINn
AUXINn Pin Open
Calibration corruption
Acquisition with AUXIN test sources
Read CALx, IDx, perform CRC
AUXINn
ID2
Note: Pin faults such as an open pin or adjacent pins shorted to each other must be detectable. Pin faults do not result in device
damage, but have a specific device response such as a communication error, or are detectable through a built-in diagnostic.
Analyzing the effect of pin faults is referred to as a pin FMEA. Contact Maxim Applications to obtain pin FMEA results.
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Since 1.23V < V
< 1.254V and V
= 1.242V
ALTREF Diagnostic Measurement
ALTREF
ALTREF
nominally, the expected range for DIAG[15:2] is:
The ALTREF diagnostic measurement (DIAGSEL[2:0] =
0b001) checks the primary voltage reference of the ADC
(1.23V/5V) x 16384d = 4030d to (1.254V/5V) x 16384 =
4109d. Therefore, 0FBEh ≤ DIAG[15:2] ≤ 100Dh. To use
the 16-bit register value, the 14-bit values must be shifted
or multiplied by four, so that 3EF8h ≤ DIAG[15:0] ≤ 4034h.
by measuring the alternate reference voltage (V
).
ALTREF
The result is available in the DIAG register after a normal
acquisition.
The ALTREF voltage is computed from the result in the
DIAG register as follows:
V
= (DIAG[15:2]/16384d ) x 5V
ALTREF
HVMUX BUS
REF
THRM
G = 6/13
+
-
LSAMP
ADC IN +
LV
MUX
ADC
ADC IN -
ADC AUTOMATICALLY IN
UNIPOLAR MODE
ALTREF
AGND
Figure 36. ALTREF Diagnostic
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The result for V should fall within the range provided in
AA
V
Diagnostic Measurement
AA
The V
the Electrical Characteristics table for V
.
AA
diagnostic measurement (DIAGSEL[2:0] =
AA
0b010) verifies that V
is within specification This diag-
using REF as the ADC reference.
V
diagnostic for ADC2 is given by:
AA
AA
nostic measures V
REF
DIAG[15:2] = (3.3 x (5/8)/2.307) x (16384d) = 14648d
= (DIAG[15:2]/16384d) x 5V
V
AA
diagnostic for ADC1 is given by:
V
AA
DIAG[15:2] = (3.3/5) x (16384d) = 10813d
V
AA
(for ADC2) = 4.47V
V
AA
= (DIAG[15:2]/16384d) x 5V
V
AA
(for ADC1) =3.29V
Figure 37. V Diagnostic ADC1
AA
REF
THRM
ADC IN +
ADC IN -
(5/8) x VAA
AGND
LV
MUX2
ADC2
AGND
Figure 38. V Diagnostic ADC2
AA
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The LSAMP offset is computed from the result in the
DIAG register, as follows:
LSAMP Offset Diagnostic Measurement
The LSAMP diagnostic measurement (DIAGSEL[2:0] =
0b011) measures the level-shift amplifier offset by short-
ing the LSAMP inputs during the diagnostic portion of the
acquisition. The result is available in the DIAG register
after a normal acquisition. For this measurement, the
ADC polarity is automatically set to bipolar mode to allow
accurate measurement of voltages near zero. This mea-
surement eliminates the chopping phase to preserve the
offset error. If the diagnostic measurement exceeds the
LSAMP Offset = ( | DIAG[15:2] - 2000h |/16384d ) x 5V
The validity of measurements through LSAMP is further
confirmed by the ALTREF and V diagnostics, and com-
AA
parison of the V
measurements.
measurement to the sum of the cell
BLKP
Zero-Scale ADC Diagnostic Measurement
Stuck ADC output bits can be verified with a combination
of the zero-scale and full-scale diagnostics. The zero-
scale ADC diagnostic measurement (DIAGSEL[2:0] =
0b100) verifies that the ADC conversion results in 000h
valid range for V
, as specified in the Electrical
OS_LSAMP
Characteristics table, the chopping function may not be
able to cancel out all the offset error, and the acquisition
accuracy could be degraded accordingly. See Figure 39
for LSAMP Offset Diagnostics
when its input is at -V
in bipolar mode (since for an
AA
input ≤ -2.5V, DIAG[15:0] = 0000h). For this measure-
ment, the ADC is automatically set to bipolar mode (see
Figure 40).
G = 6/13
+
ADC IN +
LV
MUX
HVMUX
LSAMP
BUS
ADC
ADC IN -
-
ADC AUTOMATICALLY
IN BIPOLAR MODE
Figure 39. LSAMP Offset Diagnostic
REF
THRM
VAA
ADC IN +
LV
MUX
ADC
ADC IN -
AGND
ADC AUTOMATICALLY
IN BIPOLAR MODE
AGND
Figure 40. ADC Zero-Scale Diagnostic
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
abled. After BALSWDIAG[2:0] is cleared, the modified
configurations automatically return to their prior setting. The
same configurations and comparisons could be implement-
ed manually but at the expense of more host operations.
Full-Scale ADC Diagnostic Measurement
Stuck ADC output bits can be verified with a combination
of the zero-scale and full-scale diagnostics. The zero-
scale ADC diagnostic measurement (DIAGSEL[2:0] =
0b101) verifies that the ADC conversion results in FFFh
BALSW Short Diagnostic
when its input is at V in bipolar mode (since for an input
AA
A short-circuit fault in the balancing path could be a short
between SWn and SWn-1 (see Figure 42), or that the
balancing FET is stuck in the conducting state. In the
short circuit state, the voltage between SWn and SWn-1
(switch voltage) is less than the voltage between Cn and
Cn-1 (cell voltage).
≥ 2.5V, DIAG[15:0] = FFF0h). For this measurement, the
ADC is automatically set to bipolar mode.
BALSW Diagnostics
Four balancing switch diagnostic modes are available to
facilitate the following diagnostics:
When enabled, the balancing switch short diagnostic
mode (BALSWDIAG[2:0] = 0b001) functions as follows:
● Balancing switch shorted (BALSWDIAG[2:0] = 0b001)
● Balancing switch open (BALSWDIAG[2:0] = 0b010)
● Odd sense wire open (BALSWDIAG[2:0] = 0b101)
● Even sense wire open (BALSWDIAG[2:0] = 0b110)
● Disables the balancing switches automatically
● Configures the acquisition using ALTMUX path auto-
matically
Enabling any of these modes automatically preconfigures
the acquisition (e.g. enables the ALTMUX measurement
path). The host must initiate the acquisition but the diag-
nostic mode automatically compares the measurements
to the specific thresholds, and sets any corresponding
alerts. The host presets the thresholds as determined
by the minimum and maximum resistance of the switch
● Host initiates the acquisition
● Compares the measurement to the threshold value
BALSHRTTHR automatically
● If outside the threshold, sets the corresponding flag in
ALRTBALSW automatically
For the best sensitivity to leakage current, set the threshold
value based on the minimum cell voltage minus a small
noise margin (100mV), then update the threshold value
periodically or every time a measurement is taken, depend-
ing on how fast the cell voltages are expected to change.
(R ) specified in the Electrical Characteristics table and
SW
the intended cell-balancing current.
During any balancing switch diagnostic mode, ALRTOV,
ALRTUV and ALRTMSMTCH comparisons are dis-
REF
THRM
VAA
ADC IN +
LV
MUX
ADC
ADC IN -
AGND
ADC AUTOMATICALLY
IN BIPOLAR MODE
AGND
Figure 41. ADC Full-Scale Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Cn
TO HVMUX
TO ALTMUX
SWn
BALSWEN
HV
BALANCING
SWITCH (n)
SHORT
CIRCUIT
SWn-1
TO ALTMUX
TO HVMUX
Cn-1
AGND
Figure 42. Balancing Switch Short
MAX178xx FULLY
FUNCTIONAL AND
INITIALIZED
ENSURE BALSHRTTHR
SET TO DESIRED
VALUE
SET BALSWDIAG[2:0]
TO 0b001
WAIT 100µs
START ADC
MEASUREMENT
YES
ALRTFMEA DATACHECK
BIT SHOWS RESULT
SCANDONE = 1
NO
CLEAR BALSWDIAG[2:0] AND
SCANDONE
BALSW SHORT
CIRCUIT CHECK
INVALID
CHECK ALRTBALSW OR
CELLn REGISTERS FOR
DETAILED RESULT
BALSW SHORT CIRCUIT
CHECK DONE
Figure 43. BALSW Short Diagnostic
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
See Table 35 for BALSW Short-Diagnostic Auto-
configuration, Table 36 for BALSW Diagnostics. See
Table 37 for BALSW Open-Diagnostic Autoconfguration
and Figure 44 for BALSW Open Diagnostics.
BALSW Open Diagnostics
The BALSW open diagnostic (BALSWDIAG[2:0] = 0b010)
verifies that each enabled balancing switch is conducting
(not open) as follows:
Even/Odd Sense Wire Open Diagnostics
● Configures acquisition for bipolar mode (for measur-
ing voltages near zero) automatically
If enabled, the sense-wire open diagnostic modes detect
if a cell-sense wire is disconnected as follows:
● Configures acquisition for ALTMUX path automati-
cally
● Closes nonadjacent switches (even or odd
automatically)
● Configures acquisition to measure switch voltages for
those switches enabled by BALSWEN automatically
● Configures acquisition to use ALTMUX path
automatically
● Host initiates acquisition
● Host waits 100µs for settling and then initiates the
● Compares measurement to the threshold value
BALLOWTHR and BALHIGHTHR (Table 36) auto-
matically
acquisition
● Compares the result to the BALHIGHTHR and
BALLOWTHR registers automatically
● If outside the threshold, set the corresponding flag in
ALRTBALSW automatically
● If outside thresholds, sets flags in ALRTBALSW
automatically
Set the thresholds by taking into account the minimum
and maximum R
Electrical Characteristics table and the balancing current
of the switch itself as specified in the
SW
See Figure 45 for Cell Sense-Wire Open Diagnostics.
for the application.
Table 35. BALSW Short Diagnostic Autoconfiguration
CONFIGURATION BITS
MEASUREEN[14:12]
BALSWEN[11:0]
AUTOMATIC SETTING
PURPOSE
Disable AUXIN and V measurements
BLKP
0b000
000h
1
Disable all balancing switches
DIAGCFG.ALTMUXSEL
Enable ALTMUX measurement path
Table 36. BALSW Diagnostics
BALSW
V
FAULT INDICATED?
POSSIBLE FAULT CONDITION
SWn
> V(BALHIGHTHR)
> V(BALLOWTHR)
< V(BALHIGHTHR)
< V(BALLOWTHR)
> V(BALSHRTTHR)
< V(BALSHRTTHR)
Yes
Switch open circuit, or overcurrent
On
No
None
Yes
No
Path open circuit, or short circuit
None
Off
Yes
Short circuit, or leakage current
Table 37. BALSW Open-Diagnostic Autoconfiguration
CONFIGURATION BITS
MEASUREEN[14:12]
MEASUREEN[11:0]
AUTOMATIC SETTING
PURPOSE
0b000
Disable AUXINn and V
measurements
BLKP
BALSWEN[11:0]
Measure only active switch positions
Enable ALTMUX measurement path
Enable bipolar mode
DIAGCFG.ALTMUXSEL
SCANCTRL.POLARITY
1
1
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
MAX178xx FULLY
FUNCTIONAL AND
INITIALIZED
ENSURE BALLOWTHR
AND BALHIGHTHR SET
TO DESIRED VALUE
SET BALSWDIAG[2:0] TO
0b010
START ADC
MEASUREMENT
YES
ALRTFMEA DATACHECK BIT
SHOWS RESULT
SCANDONE = 1
NO
CLEAR BALSWDIAG[2:0]
AND SCANDONE
BALSW OPEN
CHECK INVALID
CHECK ALRTBALSW OR CELLn
REGISTERS FOR DETAILED
RESULT
BALSW OPEN
CHECK DONE
Figure 44. BALSW Open Diagnostics
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
TO CELL n+1
SENSE
WIRE
RFILTER
Cn
TO HVMUX
CFILTER
RBALANCE
SWn
TO ALTMUX
BALSWEN
HV
DETECT BREAK
IN DASHED-LINE
PATH
RBAL
FILTER
BALANCING
SWITCH (n)
CELL n
RBALANCE
RFILTER
SWn-1
TO ALTMUX
TO HVMUX
SENSE
WIRE
Cn-1
CFILTER
MAX17843
AGND
TO CELL n-1
Figure 45. Cell Sense-Wire Open Diagnostics
Table 38. Odd Sense-Wire Open Measurement Result
SENSE WIRE OPEN FAULT LOCATION
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
NC
C11
NC
C12
NC
Cell1
Cell2
Cell3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
0V
0V
NC
NC
NC
NC
NC
NC
NC
NC
cell1+ cell2+
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
UD
cell2
cell3
NC
0V
0V
NC
cell3+ cell4+
cell4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
cell5
NC
0V
cell5+ cell6+
cell6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
cell7
NC
0V
cell7+ cell8+
cell8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
cell9
NC
0V
cell9+ cell10+
cell10
Cell10 NC
Cell11 NC
Cell12 NC
NC
NC
NC
NC
NC
NC
cell11
NC
0V
cell11+
cell12
NC
NC
Note: NC = No Change; UD = Undefined; Maximum result is 5V.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
MAX178xx FULLY
FUNCTIONAL AND
INITIALIZED
ENSURE BALLOWTHR
AND BALHIGHTHR SET
TO DESIRED VALUE
0b101 FOR ODD SWITCHES
0b110 FOR EVEN SWITCHES
SET BALSWDIAG[2:0]
WAIT 100µs
START ADC
MEASUREMENT
YES
ALRTFMEA DATACHECK BIT
SCANDONE = 1
NO
SHOWS RESULT
CLEAR BALSWDIAG[2:0]
AND SCANDONE
BALSW CONDUCTING
CHECK INVALID
CHECK ALRTBALSW OR CELLn
REGISTERS FOR DETAILED
RESULT
BALSW CONDUCTING
CHECK DONE
Figure 46. Sense-Wire Open Diagnostic
Table 39. Sense-Wire Open-Diagnostic Configurations
CONFIGURATION BIT(S)
CONFIGURATION STATE
TASK
555h (BALSWDIAG = 0b101) or
AAAh (BALSWDIAG = 0b110)
Enable odd switches
Enable even switches
BALSWEN[11:0]
MEASUREEN[14:12]
MEASUREEN[11:0]
0b000
Disable AUXINn and V
measurements
BLKP
BALSWEN[11:0]
Measure only active switch positions
Enable ALTMUX measurement path
Enable bipolar mode
DIAGCFG.ALTMUXSEL
SCANCTRL.POLARITY
1
1
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
CTSTDAC[3:0] (applies to all enabled sources).
Diagnostic Test Sources
Diagnostic test current sources (see Figure 47) can be
enabled prior to the acquisition mode for detecting both
internal and external hardware faults in the measure-
ment path. One set of test sources are connected to the
HVMUX input side and another set are connected to the
HVMUX output side. See Table 40 for HVMUX output
assignments. The basic premise in these diagnostics
is that for a symmetrical measurement channel with no
faults, the test currents can be applied symmetrically to
the differential channel and there should be almost no
change in the channel measurement. On the other hand,
if an asymmetric fault exists on the channel, the resulting
change will indicate the nature of the fault (e.g., an open
or shorted pin).
● Test current sources from V or sinks to AGND
AA
per the CTSTSRC bit, except for C0 (applies to all
enabled sources). The test current sources from V
only for CTST0.
AA
For the two test current sources on the HVMUX output
side:
● The test currents are enabled by the MUXDIAGEN
bit.
● The test current always sources from the HV supply.
● The test current ranges from 3.125μA up to 50μA per
CTSTDAC[3:0] (applies to all enabled sources).
● The test current, by default, is applied to both
HVMUX outputs (even and odd outputs). However,
if MUXDIAGPAIR is set, the test current is applied to
only one of the output lines per MUXDIAGBUS. This
mode is used to test the test sources themselves.
For the 15 test current sources on the input channels (13
Cn and two AUXINn):
● The test currents individually enabled per
CTSTEN[12:0] and AUXINTSTEN[2:1].
See Figure 47 for test current sources diagram.
● The test current ranges from 6.25μA up to 100μA per
Table 40. HVMUX Output Assignment
INPUT SIGNAL
HVMUX OUTPUT
Even bus
Odd bus
C12
C11
C10
C9
Even bus
Odd bus
C8
Even bus
Odd bus
C7
C6
Even bus
Odd bus
C5
C4
Even bus
Odd bus
C3
C2
Even bus
Odd bus
C1
C0
Even bus
Odd bus
REF
ALTREF
AGND
Odd bus
Even bus
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
VAA
HV
HV
CELL TEST
CURRENT
SOURCE
HVMUX TEST SOURCES
CONTROLLED BY:
MUXDIAGEN
MUXDIAGPAIR
MUXDIAGBUS
R
HVMUX
RFILTER
Cn
X
X
CTSTDAC
CELL TEST SOURCES
CONTROLLED BY:
CTSTENn
AGND
CTSTSRC
CTSTDAC
AGND
VAA
CELL n
CELL TEST
CURRENT
SOURCE
RFILTER
R
HVMUX
Cn-1
X
X
+
AGND
TO ADC
LSAMP
AGND
-
Figure 47. Test Current Sources
Shutdown Diagnostic
HVMUX Switch Open Diagnostic
The shutdown diagnostic verifies that no hardware fault
is preventing the device from shutting down, such as
the SHDNL input being stuck at logic-one. To perform
the diagnostic, the host attempts a shutdown. The tim-
ing shown in Figure 48 is for a UART idle mode shut-
Since an open HVMUX switch causes the measured
voltage to go to either zero or full-scale, it is possible to
execute the test by looking for an overvoltage or under-
voltage alert following the diagnostic measurement with-
out analyzing the measurement data. It is possible to read
all voltage measurements and let the host compare the
results by splitting the test into several segments.
down. Once V
< 0.6V, the ALRTSHDNL bit is set
SHNDL
in the STATUS register and the regulator is disabled
(see Table 41); however, the STATUS register can still
The procedure in Figure 49 is quick and efficient. For
higher sensitivity to faults, each cell voltage measurement
in the diagnostic mode can be compared to a threshold
of 100mV by the host to determine if the HVMUX path is
working correctly. The threshold is derived from the worst
case HVMUX resistance mismatch and the worst-case
diagnostic current source value variation.
be read as long as V
has not decayed below 2.95V
AA
(typ), which takes about 1ms. The host should verify that
ALRTSHDNL is set. By reading the bit, the charge pump
will drive V
> 1.8V in about 200μs and enable
SHDNL
the regulator. The host must clear the ALRTSHDNL bit
to complete the diagnostic. The ALRTSHDNLRT bit is a
real-time version of ALRTSHDNL that automatically clears
when V
> 1.8V.
SHDNL
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Table 41. Shutdown Diagnostic
FAULT
COMPARISON
ALERT BIT
ALRTSHDNL
ALRTSHNDRT
LOCATION
STATUS[12]
STATUS[11]
SHDNL input stuck
SHDNL input stuck
V
V
< 0.6V?
< 0.6V?
SHDNL
SHDNL
Figure 48. Shutdown Diagnostic Timing
MAX178xx FULLY
FUNCTIONAL AND
INITIALIZED;
STORE
MEASUREMENT
VALUES IN HOST
MUXDIAGPAIR = 0
ENABLE VALID CELLS
FOR MEASUREMENT
SET TEST CURRENT
SOURCE VALUE
CTSTDAC[3:0] = 0xF
START ADC
MEASUREMENT
ENABLE MUX TEST
CURRENT SOURCE
MUXDIAGEN = 1
START ADC
MEASUREMENT
NO
ALRTOV OR
ALRTUV?
ALL MUX SWITCHES AND
PATHS FUNCTIONING
YES
MUX SWITCH PAIR
IS MALFUNCTIONING
Figure 49. HVMUX Switch Open Diagnostic
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
dently instead of as a pair setting the MUXDIAGPAIR
bit. MUXDIAGBUS controls which source is enabled
(MUXDIAGBUS = 1 for odd bus source). This causes every
measurement to have a definable change as the sources
are enabled and disabled. By taking measurements while
alternating which current source is enabled, it is possible to
verify that each current source is working.
HVMUX Switch Shorted Diagnostic
A shorted mux switch is detectable in two ways based on
corrupted measurement values. First, the ALTREF diag-
nostic reports a large error. Also, during normal cell mea-
surements, a shorted HVMUX switch causes the LSAMP
to saturate, which is also easily detectable
HVMUX Test Source Diagnostic
See Table 42 for HVMUX switch open diagnstics and Table
43 for HVMUX test-source diagnostic.
The two current sources attached to the HVMUX even
bus and the HVMUX odd bus can be enabled indepen-
Table 42. HVMUX Switch Open Diagnostic
HVMUX SWITCH OPEN FAULT LOCATION
C4 C5 C6 C7 C8
NC NC NC NC NC
C0
0V
C1
5V
C2
NC
5V
C3
NC
NC
5V
C9
NC
NC
NC
NC
NC
NC
NC
NC
5V
C10
NC
NC
NC
NC
NC
NC
NC
NC
NC
5V
C11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
5V
C12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
5V
Cell1
Cell2
Cell3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
Cell10
Cell11
Cell12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
5V
NC
NC
NC
5V
NC
NC
NC
NC
5V
NC
NC
NC
NC
NC
5V
NC
NC
NC
NC
NC
NC
5V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
0V
NC
NC
NC
0V
NC
NC
0V
NC
0V
Note: NC = No change.
Table 43. HVMUX Test-Source Diagnostic
HVMUX TEST-
SOURCE FAULT
EVEN TEST SOURCE
SHORTED TO HV
EVEN TEST SOURCE
OPEN CIRCUIT
ODD TEST SOURCE
SHORTED TO HV
ODD TEST SOURCE
OPEN CIRCUIT
Cell1:
0V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
5V
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
I x R
-I x R
Cell2:
Cell3:
Cell4:
Cell5:
Cell6:
Cell7:
Cell8:
Cell9:
Cell10:
Cell11:
Cell12:
Note: I = Test source current, R = HVMUX resistance.
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Cn Open Diagnostic
Cn Shorted to SWn Diagnostic
If the cell is disconnected from the input, the correspond-
ing cell-test source (sinking to AGND) pulls the cell input
Short circuits between the SWn pins and the cell input
pins are detectable. A shorted SWn pin can be detected
by an acquisition with the relevant cell-balancing switch
off and then again with it on. If the SWn pin is not shorted
to an adjacent cell input pin, no change in the measured
value should be observed for the two cases. If the SWn
pin is shorted to the Cn pin, then the measured value will
change by approximately 40% to 50% when the balancing
voltage toward 0V (except for C0, where source to V
AA
current source will pull the cell input voltage to V ). A new
AA
measurement is taken with the current sources enabled,
and a change in measurement value is detected. If no
open circuit exists, then the measurement value changes
by only the value of the test current across the application
circuit series resistor to the Cn pin (see Table 44).
switch is turned on based on the values of R
,
BALANCE
and the balancing switch resistance. A short circuit from
SWn to Cn-1 produces the same effect. By comparing
both the V
measurement value along with the
CELLn
V
and V
values, it is possible to deter-
CELLn+1
CELLn-1
mine exactly where the short circuit is located.
Table 44. Cn Pin Open Diagnostic
Cn PIN OPEN FAULT LOCATION
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
NC
C11
NC
C12
NC
Cell1-
3.3V
Cell1
Cell2
Cell3
Cell4
Cell5
Cell6
Cell7
Cell8
Cell9
Cell10
Cell11
Cell12
0V
NC
NC
NC
NC
NC
NC
NC
NC
Cell2+
Cell1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
0V
NC
NC
NC
0V
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
Cell3+
Cell2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0V
Cell4+
Cell3
NC
NC
NC
NC
NC
NC
NC
NC
NC
Cell5+
Cell4
NC
NC
NC
NC
NC
NC
NC
NC
Cell6+
Cell5
NC
NC
NC
NC
NC
NC
NC
Cell7+
Cell6
NC
NC
NC
NC
NC
NC
Cell8+
Cell7
NC
NC
NC
NC
NC
Cell9+
Cell8
NC
NC
NC
NC
Cell10+
Cell9
NC
NC
NC
Cell11+
Cell10
NC
NC
Cell12+
Cell11
NC
Note: I = Test source current, R = HVMUX resistance.
Maxim Integrated
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
TEST FOR SWn TO Cn
SHORT CIRCUIT
CONDITION
RFILTER
Cn
HV
RBALANCE
RFILTER
SWn
CONTROLLED BY
BALSWEN[n-1]
Cn-1
CELL #n
RBALANCE
SWn-1
Figure 50. SWn to Cn Short
TEST FOR SWn TO Cn-1
SHORT CIRCUIT
CONDITION
RFILTER
Cn
HV
RBALANCE
RFILTER
SWn
CONTROLLED BY
BALSWEN[n-1]
Cn-1
CELL #n
RBALANCE
SWn-1
Figure 51. SWn-1 to Cn Short
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Cn Leakage Diagnostic
Cell Overvoltage Diagnostic
Leakage at the Cn inputs can cause the voltage seen by
the ADC to be different than that at the voltage source
due to the resistance of the external filter circuit. By utiliz-
ing an alternate measurement path, any voltage errors
as a result of Cn pin leakage can be detected. The SWn
pins are connected to the cell sources through an alter-
nate path. Implementing an HVMUX connection from
the SWn pins to the LSAMP completes the redundant
measurement path. This alternate measurement path
for the cell measurements can be enabled by setting the
ALTMUXSEL bit of the DIAGCFG register. When this bit
is set and a measurement cycle started, all cell measure-
ments are taken using the alternate path instead of the Cn
pin HVMUX connections. Measurements taken with the
normal and alternate paths can be compared and should
be nearly identical for a system with no faults. Since the
SWn pins typically have a smaller external filter time
constant than the Cn pins, increasing the oversampling
setting for this diagnostic measurement may be beneficial
for reducing measurement noise when the measurement
is taken while the cells are exposed to transient loads.
Enabling balancing switches can be used to generate a
voltage up to 2 x V
at the ALTMUX inputs to test the
CELL
input-range capability, assuming the cell is sufficiently
charged.
A cell-position input voltage is elevated by approximately
1.5 x V
turning on either BALSWn+1 or BALSWn-1.
CELLn
When the adjacent switch is turned on, the SWn pin
shared with the switch is moved by 0.5 x V , which
CELL
causes V
to increase by that amount when mea-
CELLn
sured with the ALTMUX path. For the topmost cell posi-
tion, BALSWn-1 must be used, and for the bottom cell
position, BALSWn+1 must be used. By turning on two
adjacent switches instead of one, such as BALSWn+1
and BALSWn+2, the measured voltage is approximately
2 x V
, assuming all cells are at approximately the
CELL
same voltage. This technique can create an input voltage
that exceeds the overvoltage threshold to verify the higher
end of the input range and the overvoltage alert function.
Input range can also be verified by using the cell-test
sources to induce a higher cell-channel voltage. If the
change is as expected, it shows that the system can mea-
sure voltages above the present nominal input voltage.
TO CELL n+1
SENSE
RFILTER
Cn
WIRE
CFILTER
RBALANCE
SWn
TO
ADC
+
-
LSAMP
RBAL
FILTER
CELL n
SWn-1
Cn-1
RBALANCE
RFILTER
SENSE
WIRE
CFILTER
AGND
TO CELL n-1
HVMUX HVMUX ALTMUX ALTMUX
BUS BUS BUS BUS
Figure 52. Redundant HVMUX Paths
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
1) Perform an acquisition
2) Turn on a cell-test source
3) Wait for sufficient settling time
4) Perform an acquisition
Cell Undervoltage Diagnostic
Turning on the balancing switch can be used to generate
a near-zero voltage at any input channel to the ALTMUX
path. By successfully measuring this near-zero voltage,
the diagnostic verifies the lower-end of the input range
and the undervoltage alert function.
5) Check that the cell(s) sharing the pin whose current
source was turned on had the expected measure-
ment change and other cells had no changes.
Input range can also be verified by using the cell-test
sources to induce a lower cell-channel voltage. If the
change is as expected, it shows that the system can mea-
sure voltages below the present nominal input voltage.
6) Repeat steps 1–5 for other pins to confirm there are
no logic errors in the HVMUX control sequencer.
The cell-test sources can be turned on for individual pins
to create a detectable measurement variation that is deter-
mined by the current-source value and the series resis-
tance of the cell input-filter circuit. The settling time needed
for a certain change in measurement value depends on
the size of the external filter capacitors and the amplitude
of the test-current source. A longer settling time gives the
full voltage change, while a shorter settling time saves test
time and should still produce an easily detectable voltage
difference. By detecting the expected measurement varia-
tion for a given cell input pair and running a sequence of
tests to cover all cases, the HVMUX sequencer operation
is verified.
ALRTHVUV Comparator Diagnostic
The ALRTHVUV comparator functionality can be verified by
setting the CPEN bit (to disable the HV charge pump) and
then discharging the external HV capacitor by performing
an acquisition for 5ms (such as 12 cells, 32 oversamples),
or by enabling using one or more of the cell-test current
sources for an appropriate amount of time. The ALRTHVUV
bit should be set after the voltage has decayed.
HVMUX Sequencer Diagnostic
The HVMUX control sequence can be checked using the
sources attached to the Cn pins. The sources are con-
trolled by the CTSTEN bits of the CTSTCFG register. The
basic test method is as follows:
VAA
TEST SOURCE
R
HVMUX
R
FILTER
Cn
TEST SOURCES
CONTROLLED BY:
CTSTENn
AGND
CTSTSRC
CTSTDAC
AGND
VAA
CELL n
TEST SOURCE
R
FILTER
R
HVMUX
Cn-1
+
-
TO
ADC
LSAMP
AGND
AGND
Figure 53. HVMUX Sequencer Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
STANDBY MODE
STORE MEASUREMENT
VALUES
ENABLE VALID
CELLS FOR
MEASUREMENT
SET TEST SOURCE
CTSTDAC[3:0] = 0xF
CURRENT
INITIATE
ACQUISITION
SET TEST SOURCE
CTSTSRC = 0 FOR AGND
POLARITY
n = 12
n = n-1
ENABLE CELL TEST
CURRENT SOURCE n
CTSTENn = 1
WAIT FOR SETTLING
TIME
ONE APPS CIRCUIT
R x C TIME
INITIATE
ACQUISITION
COMPARE ALL
CELL MEASUREMENTS
TO SAVED
VALUES
NO
CTSTENn = 0
NO CHANGE
EXCEPT VCELLn
YES
YES
DISABLE CELL TEST
CURRENT SOURCE
,
n = 1?
PASS
VCELLn-1
NO
FAIL
Figure 54. HVMUX Sequencer Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The ADCTEST1n registers are used for all odd-numbered
samples in oversampling mode, as well as in single-sample
acquisitions. The ADCTEST2n registers are used for all
even-numbered samples (in oversampling mode). The A
registers are used in lieu of the first conversion of each
measurement and the B registers are used in lieu of the
second conversion. After the acquisition, the host can read
the measurement data registers and the alert registers and
compare the data to expected values to verify the ALU
functionality.
ALU Diagnostic
TheALUdiagnosticutilizestheADCtestmode(ADCTSTEN
= 1) to feed data from specific test registers directly into
the ALU instead of from the ADC conversion. The host
can write different data combinations to the test registers
in this mode to provide test coverage for all ALU and data
registers (CELLn, VBLKP, DIAG, and AUXINn), as well as
all alerts that are based on the measurement data and the
corresponding thresholds (e.g., overvoltage alerts).
ALU REGISTERS
USER REGISTER MAP
12
12
14
14
14
14
AIN1 REGISTER
AIN2 REGISTER
DIAG REGISTER
DIAG ALU
BLOCK ALU
ALU1
ADC IN +
VBLOCK
REGISTER
12
ADC
CELL1 REGISTER
CELLn REGISTER
ADC IN -
12
ALUn
12
14
CELL12
REGISTER
ALU12
ADCTSTEN
DATAMOVE
TRIGGER
12
ADCTEST1A[11:0]
12
ADCTEST1B[11:0]
12
12
UART COMMUNICATION
ADCTEST2A[11:0]
12
ADCTEST2B[11:0]
ADC_CHOP
OVSAMP_EVEN_ODD
Figure 55. ALU Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
For MAX17843, Maxim design team added a digital offset
trim to improve ADC accuracy. Because it is calculated
after the ADCTST data insertion, it will show up as an
offset to any ADCTST diagnostic. The offset value will be
constant for a given part, but varies from part to part.
Table 45 gives the mapping of expected read from the
diagnostic and block register.
AUXINn Open Diagnostic
The AUXINn open diagnostic can be used to detect if the
AUXINn pin is open circuit. The diagnostic procedure is
shown in Figure 56 and Figure 57.
Table 45. Expected ALU Diagnostic and Block Register Results
ALU DIAGNOSTIC RESULT WHEN ADCTSTST = 1, DIAGSEL = 6
OS SETTING
000
OVERSAMPLING
DIAGNOSTIC DATA ALU
1
ADCTST1A x 4
[ADCTST1A + ADCTST2A] x 2
001–111
4–128
ALU DIAGNOSTIC RESULT WHEN ADCTSTST = 1, DIAGSEL = 4, 5
OS SETTING
000
OVERSAMPLING
DIAGNOSTIC DATA ALU
1
ADCTST1B x 4
[ADCTST1B + ADCTST2B] x 2
001–111
4–128
ALU DIAGNOSTIC RESULT WHEN ADCTSTST = 1, DIAGSEL = 1, 2, 3
OS SETTING
000
OVERSAMPLING
DIAGNOSTIC DATA ALU
[ADCTST1A + ADCTST1B] x 2
1
001–111
4–128
[ADCTST1A + ADCTST1B ADCTST2A + ADCTST2B]
ALU BLOCK RESULT WHEN ADCTSTST = 1
OS SETTING
000
OVERSAMPLING
DIAGNOSTIC DATA ALU
[ADCTST1A + ADCTST1B] x 2
1
001–111
4–128
[ADCTST1A + ADCTST1B ADCTST2A + ADCTST2B]
V
AA
V
THRM
TEST THIS
NODE FOR AN
OPEN CIRCUIT
SET BY
CTSTDAC[3:0]
CONTROLLED BY
AUXINnTSTEN AND
CTSTSRC
R
RATIO
RFILTER
AUXINn
AGND
TO LVMUX
CFILTER
THERMISTOR
t
AGND
Figure 56. AUXINn Open Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
MAX178xx FULLY
FUNCTIONAL AND
INITIALIZED
ENABLE APPROPRIATE
INPUTS FOR
TESTED INPUTS OK;
REPEAT PROCEDURE
FOR OTHER INPUTS
MEASUREMENT
YES
START ADC
MEASUREMENT
ALL
VOLTAGES
WITHIN THRESHOLD
?
OUT OF TOLERANCE
INPUT HAS OPEN
CIRCUIT
NO
SAVE ADC MEASUREMENT
RESULT
COMPARE ADC
MEASUREMENT TO SAVED
VALUE
SET CTSTDAC[3:0] CURRENT
SOURCE VALUE
DETERMINE VOLTAGE
CHANGE THRESHOLD BASED
ON CURRENT AND INPUT
FILTER
SELECT CTSTSRC TO
SOURCE OR
SINK CURRENT
SET AUXINnTSTEN TO
ENABLE SOURCE
START ADC
MEASUREMENT
Figure 57. AUXINn Open Diagnostic
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The CRC for the calibration ROM uses the same poly-
nomial as the CRC-8 PEC byte and is performed on
addresses C0h to CAh, CFh, and D0 to D4h. ID2 is pro-
cessed in the order shown in Table 46, least-significant
bit first. Registers CAL11, CAL12, CAL13, and CAL14
are excluded from the calculation. Also, certain ROM bits
must be zeroed prior to performing the calculation using
the bit-wise AND masks in Table 46.
Calibration ROM Diagnostic
The CRC for the calibration ROM can be independently
computed by the host. Any mismatch between the calcu-
lated CRC and the factory CRC indicates that the measure-
ment accuracy may be compromised. The factory CRC,
ROMCRC[7:0], is stored in the ID2 register.
Table 46. CRC Bit Mask
ORDER
ADDRESS
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC7
0xC8
0xC9
0xCA
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0x0E
NAME
CAL0
CAL1
CAL2
CAL3
CAL4
CAL5
CAL7
CAL8
CAL9
CAL10
CAL15
CAL16
CAL17
CAL18
CAL19
CAL20
ID2
BIT-WISE AND MASK
0x003F
1
2
0x007F
3
0x001F
4
0x0FFF
0xFFFF
0x3F00
5
6
7
0x3F3F
8
0x003F
9
0x3FFF
0x000F
10
11
12
13
14
15
16
17
0x007F
0x3FFF
0x00FF
0x3F00
0x3F3F
0x003F
0x0001
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
A battery module is a number of cells connected in series
that can be connected with other modules to build a
high-voltage battery pack (see Figure 58). The modularity
allows for economy, configurability, quick assembly, and
serviceability. The minimum number of cells connected to
any one device is limited by the device’s minimum operat-
Applications Information
Vehicle Applications
Battery cells can use various chemistries such as NiMH,
Li-ion, SuperCap, or Lead-Acid. SuperCap cells are used
in fast-charge applications such as energy storage for
regenerative braking. An electric vehicle system may
require a high-voltage battery pack containing up to 200
Li-ion cells, or up to 500 NiMH cells.
ing voltage. The 9V minimum for V
usually requires
DCIN
at least two Li-ion, six NiMH or six SuperCap cells per
module.
BATTERY PACK
MAIN HV+
CONTACTOR
PLUG
PHASE 1
VEHICLE
VEHICLE
CONTROL
SYSTEM
(VCS)
12V PWR
BATTERY
MANAGEMENT
SYSTEM
COMM
BUS
PHASE 2
PHASE 3
CELL STACK
VEHICLE GND
M
INVERTER
(BMS)
COMM BUS
MAIN HV-
CONTACTOR
PLUG
CHASSIS GROUND
Figure 58. Electric Vehicle System
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Battery-Management Systems
Daisy-Chain System
A daisy-chain system (Figure 59) employs a single data link between the host and all the battery modules. The daisy-
chain method reduces cost and requires only a single isolator between the lowest module and the host.
MAIN HV+
CONTACTOR
INVERTER+
BATTERY
MODULE
SLAVE
MONITOR
AND
CONTROL
TEMP
TEMP
BATTERY
MODULE
SLAVE
MONITOR
AND
CONTROL
BATTERY PACK
HVAC
BATTERY
MODULE
VEHICLE
12V PWR
SLAVE
MONITOR
AND
MASTER
CONTROLLER
COMMUNICATION
ISOLATION
CONTROL
VEHICLE
COMM BUS
TEMP
MAIN HV-
CONTACTOR
INVERTER-
MICRO-Ω
SHUNT
GROUND
FAULT
CHECK
CHASSIS GROUND
Figure 59. Daisy-Chain System
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Distributed-Module Communication
A distributed-module system employs a separate data link and isolator between each battery module and the host, with
an associated increase in cost. Maxim battery-management ICs support the daisy-chain system (see Figure 60).
PACK
INVERTER+
SWITCHES
BATTERY
MODULE
SLAVE
MONITOR
AND
ISOLATOR
CONTROL
TEMP
BATTERY
MODULE
SLAVE
MONITOR
AND
ISOLATOR
ISOLATOR
CONTROL
TEMP
TEMP
BATTERY
MODULE
SLAVE
MONITOR
AND
CONTROL
BATTERY
MODULE
SLAVE
MONITOR
AND
MASTER
CONTROLLER
ISOLATOR
CONTROL
VEHICLE 12V PWR
VEHICLE GND
COMM BUS
TEMP
FAULT
CHECK
PACK
SWITCHES
CURRENT
SENSE
INVERTER-
Figure 60. Distributed System
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
External Cell Balancing Using BJT Switches
External Cell-Balancing Short-Circuit Detection
An application circuit for cell balancing that employs
A short-circuit fault in the external balancing path results
BJT switches is shown in Figure 61. Q
is
in continuous current flow through R
and
BALANCE
BALANCE
selected for power dissipation based on the I drive
Q
. To detect this fault, the voltage drop across
B
BALANCE
current available and the cell-balancing current. D
the sense-wire parasitic resistance must be measurable.
A very small series resistor can added for this purpose.
BASE
protects Q
from negative V
during hot-plug
BALANCE
GS
events. R
protects the device by limiting the hot-
BASE
pluginrush current. The cell-balancing current is limited by
R
. See Table 47 for BJT balancing components.
BALANCE
TO CELL
n+1
RFILTER
SENSE WIRE
Cn
TO HVMUX
CFILTER
RBIAS
SWn
TO ALTMUX
BALSWn
HV
RBALANCE
CBALFILTER
RBASE
BALANCING
SWITCH (n)
CELL n
QBALANCE
DBASE
CBASE
RBIAS
SWn-1
Cn-1
TO ALTMUX
TO HVMUX
RFILTER
SENSE WIRE
CFILTER
AGND
TO CELL n-1
Figure 61. External Cell Balancing (BJT)
Table 47. BJT Balancing Components
COMPONENT NAME
TYPICAL VALUE OR PART
FUNCTION
R
22Ω
15Ω
S1B
1nF
Voltage-divider for transistor bias
Hot-plug current-limiting resistor
BIAS
BASE
BASE
BASE
R
D
C
Reverse emitter-base voltage protection
Transient V suppression
BE
R
Q
Per balancing-current requirements
NST489AMT1
Balancing current-limiting resistor
External switch
BALANCE
BALANCE
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
idle mode. The application circuit shown in Figure 63 uses
UART Interface
a weak resistor-divider to bias the TX lines to V
during
DDL
The UART pins also employ both internal and external cir-
cuits to protect against noise. The recommended external
filters are shown in Figure 62. ESD protection is shown in
Figure 64 and Figure 65.
the high-Z idle period and pnp transistor clamps to limit
the maximum voltage at the TX pins during high noise
injection. The resistor-divider and pnp clamps are not
needed for applications utilizing only the low-Z mode. The
low-Z and high-Z idle modes both exhibit a similar immu-
nity to noise injection. Low-Z mode may be preferred for
ports driving inductive loads to minimize ringing.
High-Z Idle Mode
The high-Z idle mode lowers radiated emissions from wire
harnesses by minimizing the charging and discharging of
the AC-coupling capacitors when entering and exiting the
DAISY-CHAIN
DEVICE (n-1)
DAISY-CHAIN
DEVICE (n)
C42
R50
C40
15pF
R40
1.5kΩ
2.2nF
47Ω
600V
RXLP
RXLN
TXUP
C43
R41
R51
47Ω
2.2nF
1.5kΩ
600V
TXUN
C41
15pF
R43
100kΩ
SIGNAL TRACES
OR WIRE
HARNESS
R42
100kΩ
C50
2.2nF 600V
R44
47Ω
R54
1.5kΩ
C52
15pF
TXLP
TXLN
GNDL
RXUP
C51
2.2nF 600V
R55
R45
47Ω
C53
15pF
1.5kΩ
RXUN
GNDL
SIGNAL TRACES
OR WIRE
HARNESS
R52
100kΩ
R53
100kΩ
Figure 62. UART Connection
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The recommended circuits to meet ±8kV protection levels
are shown in Figure 64 and Figure 65. The protection
components should be placed as near as possible to the
signal’s entry point on the PCB.
UART Supplemental ESD Protection
The UART ports may require supplemental protection to
meet IEC 61000-4-2 requirements for contact discharge.
VDDL[2,3]
FMB3906
VAA
R46
10kΩ
R48
10kΩ
MAX17843
R44
47Ω
TX[U,L]P
TO REST OF TX CIRCUIT
OR RX CIRCUIT
R45
47Ω
TX[U,L]N
R49
10kΩ
R47
10kΩ
GNDL[2,3]
Figure 63. High-Z Idle Mode Application Circuit
47Ω
TXP
47Ω
TXN
TO RECEIVER
PESD1CAN
GNDL
Figure 64. External ESD Protection for UART TX Ports
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Transmitter operation is not affected. If the upstack device
is single-ended, so only the TXUN signal is required.
Note: in single-ended mode, SHDNL must be driven
externally; leave TXLP unconnected.
UART Supplemental ESD Protection
The UART ports may require supplemental protection to
meet IEC 61000-4-2 requirements for contact discharge.
The recommended circuits to meet ±8kV protection levels
are shown in Figures 64 and 65. The protection compo-
nents should be placed as near as possible to the signal’s
entry point on the PCB.
UART Isolation
The UART is expected to communicate reliably in noisy
high-power battery environments, where both high dV/dt
supply noise and common-mode current injection induced
by electromagnetic fields are prevalent. Common-mode
currents can also be induced by parasitic coupling of the
system to a reference node such as a battery or vehicle
chassis. The daisy-chain physical layer is designed for
maximum noise immunity.
Single-Ended RX Mode
To configure the lower port for single-ended RX mode, the
RXLP input is connected to digital ground and the RXLN
input receives the inverted signal, just as it does for dif-
ferential mode. If the host cannot transmit inverted data
then the signal must be inverted as shown in Figure 66.
15pF
50V
2.2nF
600V
100Ω
1.5kΩ
RXP
FROM
TRANSMITTER
2.2nF
600V
100Ω
1.5kΩ
RXN
15pF
50V
100kΩ
100kΩ
PESD1CAN
GNDL
Figure 65. External ESD Protection for UART RX Ports
ISOLATED OR
NON-ISOLATED
INVERTING LOGIC
DRIVER
RXLP
RXLN
Rf
1.5kΩ
UART
DATA
Cf
15pF
GNDL
Figure 66. Application Circuit for Single-Ended Mode
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The AC-coupled differential communication architecture
has a ±30V common-mode range and +6V differential
swing. This range is in addition to the static common-
mode voltage across the AC-coupling capacitors between
modules. Transmitter drivers have low internal impedance
and are source-terminated by the application circuit so
that impedances are well-matched in the high- and low-
driver states. This architecture minimizes differential noise
induced by common-mode current injection. The receiver
inputs are filtered above the fundamental communication
frequency to prevent high-frequency noise from entering
the device. The system is designed for use with isolation
transformers or optocouplers to provide an even higher
degree of common-mode noise rejection in circuit locations
where extremely large common-mode noise is present,
such as between vehicle chassis and high-voltage battery-
pack terminals.
Since a mid-pack service-disconnect safety switch is
present in many battery packs, the device is designed
to communicate with the entire daisy-chain, regardless
of whether the service-disconnect switch is engaged
or open. This is possible with daisy-chains that employ
capacitor isolation.
UART Transformer Isolation
The UART ports can be transformer-coupled because
of their DC-balanced differential design (see Figure 67).
Transformer coupling between the MAX17841B inter-
face and the MAX17843 provides excellent isolation
and common-mode noise rejection. The center tap of
a signal transformer can be used to enhance common-
mode rejection by AC-coupling the node to local ground.
Common-mode currents that are able to pass through
the parasitic coupling of the primary and secondary are
shunted to ground to make a very effective common-
mode noise filter.
MAX17841
DAISY-CHAIN
DEVICE 1
15pF
47Ω
1.5kΩ
TXP
RXLP
1.5kΩ
RXLN
47Ω
15pF
TXN
SIGNAL TRACES
GNDL
OR WIRE
1nF
HARNESS
GNDL
Figure 67. UART Transformer Isolation
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
UART Optical Isolation
Error Checking
The daisy-chain may use optical isolation instead of trans-
former or capacitor isolation (see Figure 68).
Data integrity is provided by Manchester encoding, par-
ity, character framing, and packet-error checking (PEC).
The combination of these features verify stage-to-stage
communication both in the write and read directions, with
a hamming distance (HD) value of 6 for commands with
a length up to 247 bits (counted prior to Manchester-
encoding and character framing. This is equivalent to the
longest possible command packet for a daisy-chain of
up to 13 devices. The data-check byte is present in the
READALL and READDEVICE commands to verify that
the entire command propagated without errors. Using the
data-check and PEC bytes, complete transaction integrity
for READALL and READDEVICE command packets can
be verified.
Device Initialization Sequence
Immediately after reset, all device addresses are set to
0x00 and the UART baud rate and receive modes have not
been autodetected; therefore, the following initialization
sequence is recommended after every reset or after any
change to the hardware configuration for differential mode:
After the daisy-chain is initialized, each device should be
configured for operation as follows:
1) Perform a READALL of the status registers:
The ALRTRST bit should be set in all devices to
signify a reset occurred.
PEC Errors
Check for other unexpected alerts.
If the device receiver receives an invalid PEC byte, the
ALRTPEC bit is set in the STATUS register. A device does
not execute any write command unless the received PEC
matches the calculated PEC so to verify the write com-
mand execution, the host should perform a READALL to
verify the contents of the written register.
2) Clear the ALRTRST bit on each device so that future
unintended resets can be detected.
3) Change configuration registers as necessary with
WRITEALL commands:
Configure the alert enables and alert thresholds
required by the application.
For returned read packets, the host should store the
received data, perform the PEC calculation, and compare
the results to the received PEC byte before considering the
data to be valid. To support PEC, the host must implement
an 8-bit cyclic redundancy check (CRC-8) encoding and
decoding algorithm based on the following polynomial:
Configure the acquisition mode.
4) Perform all necessary key-on diagnostics.
5) Start the acquisition cycle.
6) Continuously monitor diagnostic and alert status bits.
7) Periodically perform additional diagnostics, as
required by the application.
8
6
3
2
P(x) = x + x + x + x + 1
VAA
RXLP
RXLN
FROM UART
DATA SOURCE
RFILTER
1.5kΩ
CFILTER
15pF
ACPL-M72T
GNDL
3.3V
ROPTO
TXLN
TO UART
DATA SOURCE
ACPL-M72T
Figure 68. UART Optical Isolation
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
DEVICE(s) IN
SHUTDOWN MODE
DEVICE
COMMUNICATION
INITIALIZED
YES
HOST SENDS
PREAMBLES FOR 2ms
PER DEVICE TO
NO
ADDRESSES AS
EXPECTED?
ADDRESSING
ERROR
WAKE UP DAISY-CHAIN
NO
FAULT OR NOT
ENOUGH PREAMBLES
SENT
NO
HOST RECEIVED
PREAMBLE?
YES
COMMUNICATION FAULT
OR ADDRESSING ERROR
PEC ERRORS?
YES
HOST SELECTS FIRST
ADDRESS AND SENDS
HELLOALL
READALL ADDRESS
REGISTERS
WRITEALL FA[4:0]
(IF FIRST ADDRESS
USED ≠ 0)
NO
RETURN ADDRESS
AS EXPECTED?
FAULT OR DEVICE
COUNT ERROR
YES
Figure 69. Device Initialization Sequence in Differential Mode
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
INPUT DATA BITSTREAM
(LSB FIRST)
Figure 70. CRC Calculation
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
The host uses the algorithm to process all bytes received
in the command packet prior to the PEC byte itself.
Neither the PEC nor the alive-counter bytes are part of the
calculation. The bits are processed in the order they are
received, LSB first. A byte-wise pseudo-code algorithm is
shown in Figure 71, but lookup table solutions are also
possible to reduce host calculation time.
For commonly issued command packets, the host can
pre-calculate (hard-code) the PEC byte. For commonly
used partial packets, the CRC value of a partial calcula-
tion can be used as the initial value for a subsequent
run-time calculation.
Function PEC_Calculation(ByteList(), NumberOfBytes, CRCByte)
{
// CRCByte is initialized to 0 for each ByteList in this implementation, where
// ByteList contains all bytes of a single command. It is passed into the
// function in case a partial ByteList calculation is needed.
// Data is transmitted and calculated in LSb first format
// Polynomial = x^8+x^6+x^3+x^2+1
POLY = &HB2 // 10110010b for LSb first
//Loop once for each byte in the ByteList
For ByteCounter = 0 to (NumberOfBytes – 1)
(
//Bitwise XOR the current CRC value with the ByteList byte
CRCByte = CRCByte XOR ByteList(Counter1)
//Process each of the 8 CRCByte remainder bits
For BitCounter = 1 To 8
(
// The LSb should be shifted toward the highest order polynomial
// coefficient. This is a right shift for data stored LSb to the right
// and POLY having high order coefficients stored to the right.
// Determine if LSb = 1 prior to right shift
If (CRCByte AND &H01) = 1 Then
// When LSb = 1, right shift and XOR CRCByte value with 8 LSbs
// of the polynomial coefficient constant. “/ 2” must be a true right
// shift in the target CPU to avoid rounding problems.
CRCByte = ((CRCByte / 2) XOR POLY)
Else
//When LSb = 0, right shift by 1 bit. “/ 2” must be a true right
// shift in the target CPU to avoid rounding problems.
CRCByte = (CRCByte / 2)
End If
//Truncate the CRC value to 8 bits if necessary
CRCByte = CRCByte AND &HFF
//Proceed to the next bit
Next BitCounter
)
//Operate on the next data byte in the ByteList
Next ByteCounter
)
// All calculations done; CRCByte value is the CRC byte for ByteList() and
// the initial CRCByte value
Return CRCByte
}
Figure 71. PEC Calculation Pseudocode
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Register Map
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x07
0x08
0x0A
0x0B
0x0C
0x0D
0x0E
0x10
0x11
0x12
0x13
0x14
0x15
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
POR
NAME
VERSION
DESCRIPTION
xxxxh
0000h
8000h
0000h
0000h
0000h
0000h
0000h
0F0Fh
0000h
0000h
XXXXh
XXXXh
1002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
000Ch
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Device model and version
ADDRESS
STATUS
Device addresses
Status flags
FMEA1
Failure mode flags 1
ALRTCELL
ALRTOVCELL
ALRTUVCELL
ALRTBALSW
MINMAXCELL
FMEA2
Voltage-fault alert flags
Overvoltage alert flags
Undervoltage alert flags
Balancing switch alert flags
Cell number for the highest and lowest voltages measured
Failure mode flags 2
ADR
AUTOBALSWDIS Delay Register
Device ID 1
ID1
ID2
Device ID 2
DEVCFG1
GPIO
Device configuration 1
GPIO status and configuration
Measurement enables
MEASUREEN
SCANCTRL
ALRTOVEN
ALRTUVEN
TIMERCFG
ACQCFG
BALSWEN
DEVCFG2
BALDIAGCFG
BALSWDCHG
TOPCELL
CELL1
Acquisition control and status
Overvoltage alert enables
Undervoltage alert enables
Timer configuration
Acquisition configuration
Balancing switch enables
Device configuration 2
Balancing diagnostic configuration
Balancing switch discharge configuration
Top cell configuration
Cell 1 measurement result
Cell 2 measurement result
Cell 3 measurement result
Cell 4 measurement result
Cell 5 measurement result
Cell 6 measurement result
Cell 7 measurement result
Cell 8 measurement result
Cell 9 measurement result
Cell 10 measurement result
Cell 11 measurement result
Cell 12 measurement result
Block measurement result
CELL2
CELL3
CELL4
CELL5
CELL6
CELL7
CELL8
CELL9
CELL10
CELL11
CELL12
BLOCK
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Register Map (continued)
ADDRESS
0x2D
0x2E
0x2F
0x40
0x42
0x44
0x46
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x50
0x51
0x52
0x57
0x58
0x59
0x5A
POR
0000h
0000h
0000h
FFFCh
FFFCh
0000h
0000h
FFFCh
0000h
FFF0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
NAME
DESCRIPTION
AUXIN1 measurement result
AIN2
AUXIN2 measurement result
TOTAL
Sum of all cell measurements
OVTHCLR
OVTHSET
UVTHCLR
UVTHSET
MSMTCH
Cell overvoltage clear threshold
Cell overvoltage set threshold
Cell undervoltage clear threshold
Cell undervoltage set threshold
Cell mismatch threshold
AINOT
AUXIN overtemperature threshold
AUXIN undertemperature threshold
Balancing switch diagnostic, short-circuit threshold
Balancing switch diagnostic, on-state low threshold
Balancing switch diagnostic, on-state high threshold
Diagnostic measurement result
AINUT
BALSHRTTHR
BALLOWTHR
BALHIGHTHR
DIAG
DIAGCFG
CTSTCFG
ADCTEST1A
ADCTEST1B
ADCTEST2A
ADCTEST2B
Diagnostic configuration
Test source configuration
User-specified data for ALU diagnostic
User-specified data for ALU diagnostic
User-specified data for ALU diagnostic
User-specified data for ALU diagnostic
VERSION Register (address 0x00)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
843h
MOD[11:0]
Model number. Always reads 843h.
D8
D7
D6
D5
D4
D3
D2
Die version as below:
MAX17843 = 1h
1h
VER[3:0]
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ADDRESS Register (address 0x01)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Address of the device connected to the host (first address). If the host uses a first address
other than 0x00 in the HELLOALL command, then the host must write that first address
to all devices in the daisy-chain with a WRITEALL command. READALL commands
require that FA[4:0] and DA[4:0] be correct in order for the data-check and PEC features to
function as intended.
0
0
0
FA[4:0]
Reserved
DA[4:0]
D8
D7
D6
Always reads logic-zero.
D5
D4
Device address written by the HELLOALL command as it propagates up the daisy-chain
and is automatically incremented for each device. The host must choose a first address
so that the last device address does not exceed the maximum address of 0x1F during the
HELLOALL command. Writing has no effect except with a HELLOALL command while
ADDRUNLOCK = 1.
D3
D2
D1
D0
STATUS Register (address 0x02)
BIT
POR
NAME
DESCRIPTION
Indicates a power-on reset (POR) event occurred. Clear after power-on and after a
successful HELLOALL to detect future resets. Writing to a logic-one has no effect.
D15
1
ALRTRST
D14
D13
0
0
ALRTOV
ALRTUV
Bit-wise logical OR of ALRTOVCELL[15:0]. Read-only.
Bit-wise logical OR of ALRTUVCELL[15:0]. Read-only.
Indicates V
< V . Read during shutdown diagnostic when V > V
.
.
SHDNL
IL
AA
PORFALL
D12
D11
D10
0
0
0
ALRTSHDNL
ALRTSHDNLRT
ALRTMSMTCH
Cleared by writing to logic-zero or POR. Writing to a logic-one has no effect.
Indicates V
Read-only.
< V . Read during shutdown diagnostic when V > V
IL AA PORFALL
SHDNL
Indicates V
Read-only.
- V
> V
Cleared at next acquisition if the condition is false.
MAX
MIN
MSMTCH .
D9
D8
0
0
ALRTTCOLD
ALRTTHOT
Logical OR of ALRTOVAIN0 and ALRTOVAIN1. Read-only.
Logical OR of ALRTUVAIN0 and ALRTUVAIN1. Read-only.
Indicates a received character contained a PEC error. Cleared only by writing to logic-zero.
Writing to a logic-one has no effect.
D7
0
0
ALRTPEC
Reserved
D6
D5
Always reads logic-zero.
Indicates that a character received by the lower UART contained a Manchester error.
Cleared only by writing to logic-zero. Writing to a logic-one has no effect.
D4
D3
D2
0
0
0
ALRTMAN
0
Write ignored, Read back ‘0’.
Indicates that a character received by the lower UART contained a parity error.
Cleared only by writing to logic-zero. Writing to logic-one has no effect.
ALRTPAR
D1
D0
0
0
ALRTFMEA2
ALRTFMEA1
Bit-wise logical OR of FMEA2 [15:0]. Read-only.
Bit-wise logical OR of FMEA1 [15:0]. Read-only.
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
FMEA1 Register (address 0x03)
BIT
POR
NAME
DESCRIPTION
Indicates that the 32kHz oscillator frequency is not within ±5% of its expected value. The
status is updated every two cycles (32kHz). Cleared only by writing to logic-zero. Writing to
a logic-one has no effect.
D15
0
ALRTOSC1
Same as ALRTOSC1 (redundant alert). Cleared only by writing to logic-zero. Writing to a
logic-one has no effect.
D14
D13
0
0
ALRTOSC2
0
Always reads logic-zero.
Indicates that the UART has placed the upper-port receiver in single-ended mode based on
the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared.
Read-only.
D12
D11
0
0
ALRTCOMMSEU1
ALRTCOMMSEL1
Indicates that the UART has placed the lower-port receiver in single-ended mode based on
the first preamble received after POR. This bit is not set until the ALRTRST bit is cleared.
Read-only.
Same as ALRTCOMMSEU1 (redundant alert) except that it sets before ALRTRST is
cleared. Read-only.
D10
D9
0
0
ALRTCOMMSEU2
ALRTCOMMSEL2
Same as ALRTCOMMSEL2 (redundant alert) except that it sets before ALRTRST is
cleared. Read-only.
Indicates V
< V
. This bit is not set until the ALRTRST bit is cleared, and
DDL3
VDDL_OC
D8
0
ALRTVDDL3
cleared only by writing to logic-zero. Writing to a logic-one has no effect.
Indicates V < V . This bit is not set until the ALRTRST bit is cleared, and
cleared only by writing to logic-zero. Writing to a logic-one has no effect.
DDL2
VDDL_OC
D7
D6
D5
0
0
0
ALRTVDDL2
ALRTGNDL2
ALRTBALSW
Indicates an open circuit on the GNDL2 pin. This bit is not set until the ALRTRST bit is
cleared, and cleared only by writing to logic-zero. Writing to a logic-one has no effect.
Bit-wise logical OR of ALRTBALSW[15:0]. Cleared automatically if the fault is cleared, or by
writing it to logic-zero.
Indicates that T
> 115°C (120°C typ) or that the diagnostic measurement did not have
DIE
D4
0
ALRTTEMP
sufficient settling time (< 50µs) and therefore may not be accurate. Cleared only by writing
to logic-zero. Writing to a logic-one has no effect.
Indicates V
< V
. This bit is not set until the ALRTRST bit is cleared, and cleared
HV
HVUV
D3
D2
0
0
ALRTHVUV
only by writing to logic-zero. Writing to logic-one has no effect.
Indicates an open circuit on the GNDL3 pin. This bit is not set until the ALRTRST bit is
cleared, and cleared only by writing to logic-zero. Writing to a logic-one has no effect.
ALRTGNDL3
Indicates V
< V
. This bit is not set until the ALRTRST bit is cleared and
DDL1
VDDL_OC
D1
D0
0
0
ALRTVDDL1
ALRTGNDL1
cleared only by writing to logic-zero. Writing to a logic-one has no effect.
Indicates an open circuit on the GNDL1 pin. This bit is not set until the ALRTRST bit is
cleared, and cleared only by writing to logic-zero. Writing to a logic-one has no effect.
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ALRTCELL Register (address 0x04)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
0
0
ALRTAIN1
ALRTAIN0
Logical OR of ALRTOVAIN1 and ALRTUVAIN1. Read-only.
Logical OR of ALRTOVAIN0 and ALRTUVAIN0. Read-only.
D8
D7
D6
0
ALRTCELL[12:1]
ALRTCELL[n] is the logical OR of ALROVCELL[n] and ALRTUVCELL[n]. Read-Only.
D5
D4
D3
D2
D1
D0
ALRTOVCELL Register (address 0x05)
BIT
D15
D14
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Indicates V
Read-only.
> AINUT (cold). Cleared at next acquisition if the condition is false.
> AINUT (cold). Cleared at next acquisition if the condition is false.
AIN1
AIN0
D13
D12
0
0
ALRTOVAIN1
ALRTOVAIN0
Indicates V
Read-only.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALRTOV[n] indicates V
at next acquisition if the condition is false. Read-only.
> V
(OVTHRSET threshold) if ALRTOVEN[n] = 1 . Cleared
CELLn
OV
0
ALRTOV[12:1]
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ALRTUVCELL Register (address 0x07)
BIT
D15
D14
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Indicates V
Read-only.
< AINOT (hot). Cleared at next acquisition if the condition is false.
< AINOT (hot). Cleared at next acquisition if the condition is false.
AIN1
AIN0
D13
D12
0
0
ALRTUVAIN1
ALRTUVAIN0
Indicates V
Read-only.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALRTUV[n] indicates V
at next acquisition if the condition is false. Read-only.
< V
(UVTHRSET threshold) if ALRTUVEN[n] = 1 . Cleared
CELLn
UV
0
ALRTUV[12:1]
ALRTBALSW Register (address 0x08)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
ALRTBALSW[n] indicates the corresponding measurement result exceeds the threshold
specified by BALSWDIAG[2:0]. Cleared at next acquisition if the condition is false.
Read-only.
D6
0
ALRTBALSW[11:0]
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
MINMAXCELL Register (address 0x0A)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Cell number of the maximum cell voltage currently in the measurement registers. If
multiple cells have the same maximum value, this field contains the highest cell number
with that measurement. Read-only.
Fh
0
MAXCELL[3:0]
Reserved
D8
D7
D6
Always reads logic-zero.
D5
D4
D3
Cell number of the minimum cell voltage currently in the measurement registers. If multiple
cells have the same minimum value, this field contains the highest cell number with that
measurement. Read-only.
D2
Fh
MINCELL[3:0]
D1
D0
FMEA2 Register (address 0x0B)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
D5
D4
D3
Indicates that V
- V
was too low during the acquisition for an accurate
HV
C12
D2
D1
D0
0
0
0
ALRTHVHDRM
Reserved
measurement. Cleared only by writing to logic-zero. Writing to a logic-one has no effect.
Always reads logic-zero.
Indicates that V
> V
. This bit is not set until the ALRTRST bit is cleared and
HV
HVOV
ALRTHVOV
cleared only by writing to logic-zero. Writing to a logic-one has no effect.
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
AUTOBALSWDIS Delay Register (address 0x0C)
BIT
POR
NAME
DESCRIPTION
Time delay for cell recovery after diagnostic configuration. Default time is 96µs, with
maximum time of 24.576ms.
D15
D14
D13
D12
D11
D10
DIAGNOSTIC RECOVERY TIME[7:0]
DELAY TIME IN µs
00000000
00000001
00000010
00000011
00000100
...
96
192
288
384
480
Diagnostic Recovery
Time[7:0]
0
D9
11111110
11111111
24480
24576
D8
D7
Time delay for cell recovery from cell-balancing voltage drop. Default time is 100µs, with
maximum time of 24.576ms.
D6
D5
D4
D3
D2
D1
CELL RECOVERY TIME[7:0]
DELAY TIME IN µs
00000000
00000001
00000010
00000011
00000100
...
96
192
288
384
480
.
Cell Recovery
Time[7:0]
0
D0
11111110
11111111
24480
24576
ID1 Register (address 0x0D)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
The two least-significant bytes of the 24-bit factory-programmed device ID. A valid device
ID has two or more bits set to logic-one. Read-only.
xxxxh
DEVID[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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ID2 Register (address 0x0E)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
xxh
ROMCRC[7:0]
8-bit CRC value computed from the on-board read-only memory. Read-only.
D8
D7
D6
D5
D4
Most-significant byte of the 24-bit factory-programmed device ID. ID1[0] always reads
logic-one. A valid device ID has two or more bits set to logic-one. Read-only.
xxh
DEVID[23:16]
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
DEVCFG1 Register (address 0x10)
BIT
POR
NAME
DESCRIPTION
Enables bipolar mode for ADC (input range is -2.5V to 2.5V). Default is unipolar mode
(input range is 0V to 5V). The ADC logic latches the value of this bit at the start of the
measurement cycle. The DIAG measurement timeslot is controlled by the internal logic.
Changing the value of this bit takes effect at the next measurement cycle start.
D15
0
POLARITY
Configures which ADC is selected for measurements. Default is the ADC1 which is the
primary ADC. The ADC logic latches the value of this bit at the start of the measurement cycle.
Changing the value of this bit takes effect at the next measurement cycle start.
D14
0
ADCSELECT
ADCSELECT
SELECTED ADC
1 (Primary)
0
1
2 (Secondary)
IIR filter coefficient bits. User-selectable filter coefficients. The default value is 010 that has
a weight of 3/8. Setting these bits to 111 would turn the filter off. The ADC scan data is then
transferred from ALU to CELLn registers as is.
D13
D12
FILTER COEFFICIENT[2:0]
WEIGHT OF THE COEFFICIENT
000
001
010
011
100
101
110
111
1/8
2/8
010
FC[2:0]
3/8, Default value
1/2
5/8
.6/8
D11
7/8
1, Filter Off
D10
D9
D8
D7
D6
D5
0
0
0
0
0
0
EMGCYDCHG
HVCPDIS
Set to enable emergency cell-discharge mode (configured by BALSWDCHG).
Disables the HV charge pump. Used for ALRTHVUV diagnostic. If the HV charge pump is
disabled in normal operation, measurement errors will result due to V
undervoltage.
HV
Reserved
Reserved for future use.
Enables hard POR by pulling down SHDNL internally. If cleared before the POR occurs, it
disables the active pulldown on SHDNL.
FORCEPOR
ALIVECNTEN
ADCTSTEN
Enables inclusion of alive-counter byte at end of all write and read packets.
Enables the ALU test mode. This mode feeds 12-bit data from the ADCTEST registers
directly into the ALU, instead of from the ADC conversion.
Disables the acquisition watchdog but does not clear the SCANTIMEOUT flag in the
SCANCTRL register if it is set.
D4
0
SCANTODIS
Disables all the balancing switches conducting between SWn and Swn-1. This allows
disabling all the balancing switches without actually clearing the BALSWEN register.
D3
D2
D1
D0
0
0
1
0
BALSWDISABLE
NOPEC
Disables packet-error checking (PEC).
Disables write-protection of device address DA[4:0]. Cleared only by HELLOALL command
(write protected).
ADDRUNLOCK
SPOR
Enables soft POR. Writing to a logic-zero has no effect. Always reads logic-zero.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
GPIO Register (address 0x11)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
DIR[3:0]
Setting DIRn enables GPIOn as an output. Default state is high-impedance input.
Indicates the current logic state of each GPIOn pin input buffer. The logic state is sampled
at the end of the parity bit of the register address byte during a read of this register. Read-
only.
0
RD[3:0]
D8
Enables the GPIO3 timer mode. This mode overrides DIR3 and DRV3 and drives GPIO3
to logic-one when the timer is counting, and drives to logic-zero when the timer times out.
Emergency cell-discharge mode (EMGCYDCHG = 1) automatically enables the GPIO3
timer mode.
D7
0
0
GPIO3TMR
Reserved
D6
D5
D4
D3
D2
D1
D0
Always reads logic-zero.
0
DRV[3:0]
Setting DRVn sets GPIOn to logic-one if DIRn is set.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
MEASUREEN Register (address 0x12)
BIT
POR
NAME
DESCRIPTION
Connects the voltage-divider to the V
measurement. The ADC logic latches the value of this bit at the start of the measurement cycle.
pin. Must be enabled prior to the VBLOCK
BLKP
D15
0
BLKCONNECT
Changing the value of this bit takes effect at the next measurement cycle start.
Enables measurement of the V
the value of this bit at the start of the measurement cycle. Changing the value of this bit
takes effect at the next measurement cycle start.
input in the acquisition mode. The ADC logic latches
BLKP
D14
D13
D12
0
0
0
BLOCKEN
AIN2EN
Enables measurement of the AUXIN2 input in the acquisition mode. The ADC logic latches
the value of this bit at the start of the measurement cycle. Changing the value of this bit
takes effect at the next measurement cycle start.
Enables measurement of the AUXIN1 input in the acquisition mode. The ADC logic latches
the value of this bit at the start of the measurement cycle. Changing the value of this bit
takes effect at the next measurement cycle start.
AIN1EN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Enables measurement of the respective cell in the acquisition mode. Disabled channels
result in a measurement value of 0000h. The ADC logic latches the value of this bit at
the start of the measurement cycle. Changing the value of this bit takes effect at the next
measurement cycle start.
0
CELLEN[12:1]
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
SCANCTRL Register (address 0x13)
BIT
POR
NAME
DESCRIPTION
Indicates the acquisition has completed. Cleared only by writing it to logic-zero to detect
completion of the next acquisition. Writing to logic 1 has no effect. A new acquisition will not
commence if this bit is set.
D15
0
SCANDONE
Indicates the acquisition did not complete in the expected period of time. The timeout
depends on the oversampling configuration. Cleared only by writing it to logic-zero to allow
detection of future timeout events. The watchdog can be disabled by setting SCANTODIS
in the DEVCFG register.
D14
D13
0
0
SCANTIMEOUT
DATARDY
Indicates the measurement data from the acquisition has been transferred from the ALU to
the data registers and can now be read. Data for all measurement registers and MIN/MAX/
TOTAL is transferred at the same time. Cleared by writing it to logic-zero to allow detection
of the next data transfer. Writing to logic-one has no effect.
The delay after the start of the scan before the measurement is enabled only if
the AUTOBALSWDIS bit is set to 1. Sets the delay based on the setting in the
AUTOBALSWDIS Delay register (0x0C). The default bit setting is 0 which selects the delay
associated with cell recovery time in register 0x0C. Setting this bit to 1 selects the delay
setting of “Diagnostic Recovery time.” See AUTOBALSWDIS Delay Register (address
0x0C) table for details on delay timings.
D12
D11
0
0
DELAYSEL
Automatic disable of balancing switches during measurements. The delay for cell recovery
settling time and for the diagnostic recovery is set based on the AUTOBALSWDIS Delay
register (0x0C). Set this bit to zero for normal balancing switch operation.
AUTOBALSWDIS
Configures the cell-balancing switch diagnostic modes per table below. When selected,
these modes effectively override the BALSWEN, MEASUREEN, ALTMUXSEL, and
POLARITY configurations during the acquisition mode and update the ALRTBALSW
register per the BALHIGHTHR and BALLOWTHR thresholds. See the Diagnostics section
for details.
D10
D9
BALSWDIAG[2:0]
DIAGNOSTIC TEST
000
001
010
011
100
101
110
111
None
0
BALSWDIAG[2:0]
Balancing switch short
Balancing switch open
None
D8
D7
None
Cell sense open odds
Cell sense open evens
None
This bit chooses where the ADC scan data is read from. Writing this bit to ‘1’ enables the
read to occur from filtered CELLn registers. The default value is ‘0’ wherein the read of the
scanned data occurs from unfiltered ALU registers.
0
RDFILT
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
SCANCTRL Register (address 0x13) (continued)
BIT
POR
NAME
DESCRIPTION
D6
Configures for the number of oversamples in the acquisition, per table below:
OVSAMPL[2:0]
OVERSAMPLES
000
001
010
011
100
101
110
111
1
4
8
D5
0
OVSAMPL[2:0]
16
32
64
128
128
D4
D3
This bit when set to ‘1’ enables the automatic transfer of the new ADC conversion from
the ALU to CELLn registers through the IIR filter at the end of the scan. The scan result is
available in the ALU as well as the CELLn registers. The default value is ‘0’, which keeps
the scan conversion data in the ALU register as an unfiltered result.
0
AMENDFILT
D2
D1
0
0
SCANMODE
FILTDONE
Enables top-down scan mode. Default is pyramid scan mode.
Indicates the user register has been updated with the new ADC conversion values based on
filter coefficient bits when AMENDFILT = 1. Cleared only by writing it to logic-zero to detect
update of the user registers for the next acquisition. Writing to logic-one has no effect.
Enables the acquisition mode and (if in double-buffer mode) transfers previous acquisition
data from ALU to data registers. Acts as a strobe bit and therefore does not need to be
cleared. Always reads logic-zero. Ignored in acquisition mode.
D0
0
SCAN
ALRTOVEN Register (address 0x14)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
0
0
AINOVALRTEN1
AINOVALRTEN0
Enables the AIN1 overvoltage alert.
Enables the AIN0 overvoltage alert.
D8
D7
D6
Enables the overvoltage alert for the respective cell. Clearing also clears the associated
cell alert.
0
OVALRTEN[12:1]
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ALRTUVEN Register (address 0x15)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
0
0
AINUVALRTEN1
AINUVALRTEN0
Enables the AIN1 undervoltage alert.
Enables the AIN0 undervoltage alert.
D8
D7
D6
Enables the undervoltage alert for the respective cell. Clearing also clears the associated
cell alert.
0
UVALRTEN[12:1]
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
WATCHDOG Register (address 0x18)
BIT
D15
D14
D13
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Sets the step size of the cell-balancing timer LSB per table below:
CBPDIV[2:0]
000
STEP SIZE
Disabled
1s
TIMEOUT RANGE
No timeout
1–15s
001
010
4s
4–60s
0
CBPDIV[2:0]
011
16s
16–240s
D12
100
64s
64–960s
101
128s
256s
256s
128–1920s
256–3840s
256–3840s
110
111
Watchdog timer for the cell-balancing switches. The timer counts down at a rate set by
CBPDIVn. When the timer reaches ‘0’, all cell-balancing switches are disabled by a signal
separate from the BALCFGn enable bits. The timer should be periodically rewritten with a
timeout value to keep the cell-balancing switches enabled. When the timer value is read,
the value reported is latched during the stop bit time following the ACQCFG UART register
address of the READALL command. If the GPIO3TMR configuration is enabled, the GPIO3
pin is driven high, while CBTIMER[3:0] is nonzero and is driven low when the timer value is
zero. The cell-balancing timer is reset to zero when EMGCYDCHG = 1.
D11
D10
D9
0
CBTIMER[3:0]
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Reserved
Always reads logic-zero.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ACQCFG Register (address 0x19)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
Configures the THRM mode based on the table below:
THRMMODE[1:0]
OPERATION
00
01
10
11
Auto mode (on in acquisition mode)
Auto mode (on in acquisition mode)
Manual mode, THRM switch off
Manual mode, THRM switch on
0
0
0
THRMMODE[1:0]
Reserved
D8
D7
D6
D5
D4
D3
D2
D1
D0
Always reads logic-zero.
Configures the conversion time for each enabled AUXINn input from 6µs (default) up to
384µs (6µs/bit). This is to allow extra settling time if the application circuit requires it since
the THRM voltage is not driven out until the start of the acquisition (in auto mode).
AINTIME[5:0]
BALSWEN Register (address 0x1A)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
0
BALSWEN[11:0]
BALSWEN[n-1] enables the balancing switch (conducting) between SWn and SWn-1.
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
DEVCFG2 Register (address 0x1B)
BIT
POR
NAME
DESCRIPTION
Enables UART loopback mode, which internally connects upper-port transmitter to
upper-port receiver. The loopback mode allows the host to locate a break in daisy-chain
communication whether or not the last daisy-chain device uses an external wire loopback
wire or the internal loopback.
D15
0
LASTLOOP
D14
D13
D12
0
0
TXADPEN
Reserved
Enables TX adaptive mode. Leave in default state for normal operation.
Always reads logic-zero.
Enables high-Z idle mode, which causes the TX drivers of the lower UART to idle in the
high-Z state instead of idling in the logic-zero state (default mode). Leave in default state
for normal operation.
D11
D10
0
TXLIDLEHIZ
Enables high-Z idle mode, which causes the TX drivers of the upper UART to idle in the
high-Z state instead of idling in the logic-zero state (default mode). Leave in default state
for normal operation.
0
0
TXUIDLEHIZ
RESERVED
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reserved for future use. Reads the written value.
0
Reserved
Always reads logic-zero.
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
BALDIAGCFG1 Register (address 0x1C)
BIT
D15
D14
D13
POR
NAME
DESCRIPTION
0
0
Reserved
Always reads logic-zero.
ALTMUXSEL_M
Mirror for ALTMUXSEL bit.
Mirror for POLARITY bit. The ADC logic latches the value of this bit at the start of the
D12
0
POLARITY_M
measurement cycle. Changing the value of this bit takes effect at the next measurement-cycle
start.
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mirror for CELLEN[12:1] in the MEASUREEN register. Writing to this field also updates
CELLEN[12:1]. Reading this field reflects CELLEN[12:1].
0
CELLEN_M[12:1]
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
BALSWDCHG Register (address 0x1D)
BIT
D15
D14
POR
NAME
DESCRIPTION
Configuration for emergency cell-discharge mode (EMGCYDCHG = 1). Sets the duty-
cycle for each discharge cycle (even or odd) per the table below:
DCHGWIN[2:0] (LSb = 7.5s)
BEHAVIOR
Switches on for 7.5s, off for 52.5s
Switches on for 15s, off for 45s
…
0h
1h
…
7h
0
DCHGWIN[2:0]
D13
Switches on for 59.94s, off for 62.5ms
D12
D11
D10
D9
0
0
Reserved
Always reads logic-zero.
Discharge counter, which can be read to verify operation of the emergency cell-discharge
mode (EMGCYDCHG = 1). During the cell-discharge mode, the discharge counter counts
at 2Hz rolling over at Fh to 0h and continuing until the cell-discharge mode terminates.
Read-only.
DCHGCNTR[3:0]
D8
D7
Write to set the timeout value of the emergency cell-discharge mode (EMGCYDCHG = 1)
per the table below. Writing to 00h disables the timer and terminates the emergency cell-
discharge mode. The timer starts when EMGCYDCHG = 1 (and DCHGTIME[7:0] ≠ 00h)
and stops when it reaches the timeout. The timer is reset when EMGCYDCHG = 0.
D6
D5
D4
D3
DCHGTIME[7:0] (LSb = 2 HOURS)
TIMEOUT
Discharge mode disabled
0
DCHGTIME[7:0]
D2
00h
01h
02h
…
D1
Discharge mode disabled after 4 hours
Discharge mode disabled after 6 hours
…
D0
FFh
Discharge mode disabled after 512 hours
TOPCELL Register (address 0x1E)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
D5
D4
D3
Configures the top cell position if less than 12 channels are used. This is to properly
mask the ALRTBALSW diagnostic alerts. TOPCELL[3:0] = 0h is not a valid configuration.
TOPCELL[3:0]= Dh, Eh, or Fh is identical to Ch (12d).
D2
Ch
TOPCELL[3:0]
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
CELLn Register (addresses 0x20 to 0x2B)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
CELLn[15:2] contains the 14-bit measurement result for CELLn. CELLn[1:0] always reads
logic-zero. Read-only.
0
CELLn[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
VBLOCK Register (address 0x2C)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
VBLOCK[15:2] contains the 14-bit measurement result for V
logic-zero. Read-only.
. VBLOCK[1:0] always reads
BLKP
0
VBLOCK[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
AIN1 Register (address 0x2D)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
AIN1[15:4] contains the 12-bit measurement result for AUXIN1. AIN1[3:0] always reads logic-
zero. Read-only.
0
AIN1[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
AIN2 Register (address 0x2E)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
AIN2[15:4] contains the 12-bit measurement result for AUXIN2. AIN2[3:0] always reads logic-
zero. Read-only.
0
AIN2[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
TOTAL Register (address 0x2F)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
0
SUM[15:0]
16-bit sum of all cell voltages CELLn[15:4] that are enabled by MEASUREEN. Read-only.
D7
D6
D5
D4
D3
D2
D1
D0
OVTHCLR Register (address 0x40)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
FFFCh
OVTHCLR[15:0]
14-bit overvoltage-clear threshold. UVTHCLR[1:0] always reads logic-zero.
D7
D6
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
OVTHSET Register (address 0x42)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
FFFCh
OVTHSET[15:0]
14-bit overvoltage-set threshold. OVTHSET[1:0] always reads logic-zero.
D7
D6
D5
D4
D3
D2
D1
D0
UVTHCLR Register (address 0x44)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
0
UVTHCLR[15:0]
14-bit undervoltage-clear threshold. UVTHCLR[1:0] always reads logic-zero.
D7
D6
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
UVTHSET Register (address 0x46)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
0
UVTHSET[15:0]
14-bit undervoltage set threshold. UVTHSET[1:0] always reads logic-zero.
D7
D6
D5
D4
D3
D2
D1
D0
MSMTCH Register (address 0x48)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
FFFCh
MSMTCH[15:0]
14-bit voltage threshold for ALRTMSMTCH. MSMTCH[1:0] always reads logic-zero.
D7
D6
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
AINOT Register (address 0x49)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
12-bit undervoltage (over-temperature) threshold for AUXINn alerts. AINOT[3:0] always
reads logic-zero.
0
AINOT[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
AINUT Register (address 0x4A)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
12-bit overvoltage (undertemperature) threshold for AUXINn alerts. AINUT[3:0] always reads
logic-zero..
FFF0h
AINUT[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
BALSHRTTHR Register (address 0x4B)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
14-bit voltage threshold for the balancing-switch short-circuit diagnostic test. The ADC
results in this test mode are compared against the threshold. If any result is below the
threshold, it is flagged as a balancing-switch alert. Results above the threshold are
considered normal. The threshold should be set by the system controller prior to making
a diagnostic measurement. BALSHRTTHR[1:0] always reads logic-zero.
D8
0
BALSHRTTHR[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
BALLOWTHR Register (address 0x4C)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
14-bit low-voltage threshold for the balancing-switch conducting and cell sense-wire
diagnostic tests. The ADC results in this test mode are compared against the threshold.
If any result is below the threshold, it is flagged as a balancing-switch alert. Results
above the threshold are considered normal. The threshold should be set by the system
controller prior to making a diagnostic measurement. BALLOWTHR[1:0] always reads
logic-zero.
D8
0
BALLOWTHR[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
BALHIGHTHR Register (address 0x4D)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
14-bit high-voltage threshold for the balancing-switch conducting and cell sense-wire
diagnostic tests The ADC results in this test mode are compared against the threshold.
If any result is above the threshold, it is flagged as a balancing-switch alert. Results
below the threshold are considered normal. The threshold should be set by the system
controller prior to making a diagnostic measurement. BALHIGHTHR[1:0] always reads
logic-zero.
D8
0
BALHIGHTHR[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
DIAG Register (address 0x50)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
D8
DIAG[15:2] contains the 14-bit measurement result for the diagnostic selected by
DIAGCFG[2:0]. DIAG[1:0] always reads logic-zero. Read-only.
0
DIAG[15:0]
D7
D6
D5
D4
D3
D2
D1
D0
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MAX17843
12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
DIAGCFG Register (address 0x51)
BIT
D15
D14
POR
NAME
DESCRIPTION
Configures the current level for all enabled test sources per the table below (either 6.25µA
or 3.125µA per bit.
TEST SOURCE CURRENT
CTSTDAC{3:0]
D13
D12
Cx, AUXINn
6.25µA
12.5µA
18.75µA
….
Cx, AUXINn
3.125µA
6.25µA
9.375µA
….
0h
1h
2h
…
0
CTSTDAC[3:0]
Dh
Eh
Fh
87.5µA
93.75µA
100µA
43.75µA
46.875µA
50µA
Configures the cell input test-current sources to either source current from V (logic-one),
or sink current to AGND (logic-zero). For C0, configures the cell input test current to source
AA
D11
0
CTSTSRC
Reserved
from V only.
AA
D10
D9
0
0
Reserved for future use.
Enables the test current sources connected to the corresponding AUXINn input for
diagnostic testing. The current level is configured by the CTSTDAC[3:0] and the current
direction is configured by CTSTSRC.
AUXINTSTEN[2:1]
D8
0
Selects the HVMUX output to which the HVMUX test current source is connected, if
MUXDIAGPAIR is enabled, as shown below:
MUXDIAGBUS
HVMUX OUTPUT
Output used for even cells, C0, and AGND.
Output used for odd cells, REF, and ALTREF.
D7
0
MUXDIAGBUS
0
1
Configures a single HVMUX test-current source to be connected to only one HVMUX
output (as selected by MUXDIAGBUS). In the default configuration (MUXDIAGPAIR = 0),
both HVMUX test-current sources are connected to both HVMUX outputs.
D6
D5
0
0
MUXDIAGPAIR
Reserved
Always reads logic-zero.
Enables the HVMUX test-current source(s). The current level is configured by
CSTDAC[3:0] and the connectivity is configured by MUXDIAGPAIR and MUXDIAGBUS.
The ADC logic latches the value of this bit at the start of the measurement cycle. Changing the
value of this bit takes effect at the next measurement-cycle start.
D4
0
0
MUXDIAGEN
ALTMUXSEL
Enables cell measurements on the SWn inputs (ALTMUX data path) instead of the Cn
inputs (HVMUX data path). See the Diagnostics section.
D3
D2
Selects the diagnostic measurement for the acquisition per table below:
DIAGSEL[2:0]
0b000
DIAGNOSTIC MEASUREMENT
No measurement
D1
0b001
V
V
(with ADC reference = REF)
ALTREF
0b010
(with ADC reference = REF)
AA
0
DIAGSEL[2:0]
0b011
LSAMP offset
D0
0b100
Zero-scale ADC output (000h)
Full-scale ADC output (FFFh)
Die temperature
0b101
0b110
0b111
No measurement
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
CTSTEN Register (address 0x52)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
Enables the current sources connected to the corresponding cell input for diagnostic
testing. The current level is configured by the CTSTDAC[3:0] and the current direction is
configured by CTSTSRC in the DIAGCFG register.
D6
0
CTSTEN[12:0]
D5
D4
D3
D2
D1
D0
ADCTEST1A Register (address 0x57)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into
the ALU during the first conversion of odd-numbered samples (e.g., first sample).
ADCTEST1A[11:0]
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ADCTEST1B Register (address 0x58)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into
the ALU during the second conversion of odd-numbered samples (e.g., first sample).
ADCTEST1B[11:0]
D5
D4
D3
D2
D1
D0
ADCTEST2A Register (address 0x59)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into
the ALU during the first conversion of even-numbered samples in oversampling mode.
0
ADCTEST2A[11:0]
D5
D4
D3
D2
D1
D0
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
ADCTEST2B Register (address 0x5A)
BIT
D15
D14
D13
D12
D11
D10
D9
POR
NAME
DESCRIPTION
0
Reserved
Always reads logic-zero.
D8
D7
D6
User-specified test data for the ALU diagnostic (ADCTEST = 1). This 12-bit data is fed into
the ALU during the second conversion of even-numbered samples in oversampling mode.
0
ADCTEST2B[11:0]
D5
D4
D3
D2
D1
D0
Ordering Information
Package Information
For the latest package outline information and land patterns
PART
TEMP RANGE PIN-PACKAGE
-40° to +125°C 64 LQFP
-40° to +125°C 64 LQFP
(footprints), go to www.maximintegrated.com/packages. Note
MAX17843ACB+*
MAX17843ACB/V+
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
/V denotes an automotive qualified part.
+ Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product―contact factory for availability.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
64 LQFP
C64+13
21-0083
90-0141
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12-Channel, High-Voltage Smart Sensor
Data-Acquisition Interface
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
6/17
Initial release
—
Updated Benefits and Features, Absolute Maximum Ratings, Electrical
Characteristics, TX Adaptive Mode for Single-Ended Mode, UART
Communication Mode, SCANCTRL Register (address 0x13), and
OVTHSET Register (address 0x42) sections/tables
1, 14, 16, 53, 56,
111, 122
1
11/17
4/18
Changed Total-Acquisition Error (V
Input) in Electrical Characteristics
BLKP
2
table from "-125 (min) to +125 (max)" to "-110 (min) to +110 (max)" and
16, 87
changed Bit-Wise and Mask in rows 8 and 16 from "0x001F to 0x003F"
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 131
相关型号：
MAX178ACNG+
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, PDIP24, PLASTIC, DIP-24
MAXIM
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