MAX18066EWE+ [MAXIM]
High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches;
| 型号： | MAX18066EWE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, 4A, Step-Down DC-DC Regulators with Internal Power Switches |
| 文件： | 总22页 (文件大小：1207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
General Description
Benefits and Features
The MAX18066/MAX18166 current-mode, synchronous,
DC-DC buck converters deliver an output current up
to 4A with high efficiency. The devices operate from
an input voltage of 4.5V to 16V and provides an
adjustable output voltage from 0.606V to 90% of the
input voltage. The devices are ideal for distributed power
systems, notebook computers, nonportable consumer
applications, and preregulation applications.
● Feature Integration Shrinks Solution Size
• Integrated 40mΩ (High-Side) and 18.5mΩ
(Low-Side) R
Power MOSFETs
DS-ON
• Stable with Low-ESR Ceramic Output Capacitors
• Enable Input and Power-Good Output
• Cycle-by-Cycle Overcurrent Protection
• Fully Protected Against Overcurrent
(Hiccup Protection) and Overtemperature
● High Efficiency Conserves Power
The devices feature a PWM mode operation with
an internally fixed switching frequency of 500kHz
(MAX18066) and 350kHz (MAX18166) capable of 90%
maximum duty cycle. The devices automatically enter
skip mode at light loads. The current-mode control
architecture simplifies compensation design and ensures
a cycle-by-cycle current limit and fast response to line
and load transients. A high-gain transconductance error
amplifier allows flexibility in setting the external com-
pensation, simplifying the design and allowing for an all-
ceramic design.
• Up to 96% Efficiency (5V Input and 3.3V Output)
• Up to 93% Efficiency (12V Input and 3.3V Output)
• Automatic Skip Mode During Light Loads
● Safe, Reliable, Accurate Operation
• Continuous 4A Output Current
• ±1% Output Accuracy over Load, Line, and
Temperature
• Safe Startup Into Prebiased Output
• Programmable Soft-Start
• V
LDO Undervoltage Lockout
DD
● Well Suited to Distributed Power, Networking, and
The synchronous buck regulators feature inter-
nal MOSFETs that provide better efficiency than
asynchronous solutions, while simplifying the design
relative to discrete controller solutions. In addition to
simplifying the design, the integrated MOSFETs minimize
EMI, reduce board space, and provide higher reliability by
minimizing the number of external components.
Computing Applications
• 4.5V to 16V Input Voltage Range
• Adjustable Output Voltage Range from 0.606V
to (0.9 x V )
IN
● Available in EE-Sim® Design and Simulation Tool to
Slash Design Time
Additional features include an externally adjustable
soft-start, independent enable input and power-good
output for power sequencing, and thermal shutdown
protection. The devices offer overcurrent protection (high-
side sourcing) with hiccup mode during an output short-
circuit condition. The devices ensure safe startup when
powering into a prebiased output.
Ordering Information appears at end of data sheet.
Typical Application Circuit
INPUT
4.5V TO 16V
IN
BST
LX
The MAX18066/MAX18166 are available in a 2mm x
2mm, 16-bump (4 x 4 array), 0.5mm pitch wafer-level
package (WLP) and are fully specified from -40°C to
+85°C.
1.8V/4A
OUTPUT
EN
MAX18066
MAX18166
V
DD
FB
COMP
Applications
● Distributed Power Systems
PGOOD
SS
● Preregulators for Linear Regulators
● Home Entertainment (TV and Set-Top Boxes)
● Network and Datacom
GND
● Servers, Workstations, and Storage
EE-Sim is a registered trademark of Maxim Integrated
Products, Inc.
19-100202; Rev 0; 11/17
MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Absolute Maximum Ratings
IN to GND..............................................................-0.3V to +18V
Converter Output and V
DD
EN to GND .................................................-0.3V to (V + 0.3V)
Short-Circuit Duration .......................................... Continuous
IN
LX to GND.............-0.3V to the lower of +18V and (V + 0.3V)
Continuous Power Dissipation (T = +70°C)
IN
A
LX to GND (for 50ns) ....-1V to the lower of +18V and (V + 0.3V)
16-Bump WLP (derate 20.4mW/°C above +70°C)
IN
PGOOD to GND......................................................-0.3V to +6V
Multilayer Board ........................................................1500mW
V
to GND ............-0.3V to the lower of +6V and (V + 0.3V)
Thermal Resistance (θ ) (Note 2)..............................23.6°C/W
DD
IN
JA
COMP, FB, SS to
GND........................ -0.3V to the lower of +6V and (V
BST to LX ...............................................................-0.3V to +6V
BST to GND .........................................................-0.3V to +24V
Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature (Note 3) .......................................+150°C
Continuous Operating Temperature
at Full Current (Note 3)................................................+105°C
Storage Temperature Range ........................... -65°C to +150°C
Soldering Temperature (reflow)...................................... +260°C
+ 0.3V)
DD
BST to V
..........................................................-0.3V to +18V
DD
LX RMS Current (Note 1) ................................................0 to 9A
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed the
device’s package power dissipation.
Note 2: Package thermal resistances were obtained based on the MAX18066/MAX18166 evaluation kit.
Note 3: Continuous operation at full current beyond +105°C can degrade product life.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Information
PACKAGE TYPE: 16 WLP
Package Code
W162B2+1
Outline Number
21-0200
Land Pattern Number
Refer to Application Note 1891
For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-”
in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to
the package regardless of RoHS status.
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Electrical Characteristics
(V = 12V, C
= 1µF, C = 22µF, T = T = -40°C to +85°C, typical values are at T = T = +25°C, unless otherwise noted.) (Note 4)
A J
IN A J
IN
VDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STEP-DOWN CONVERTER
Input Voltage Range
V
4.5
16
2
V
IN
Quiescent Current
I
Not switching
1.1
2
mA
µA
IN
Shutdown Input Supply Current
ENABLE INPUT
V
= 0V
6
EN
EN Shutdown Threshold Voltage
V
V
rising
0.7
70
V
EN_SHDN
EN
EN Shutdown Voltage
Hysteresis
V
mV
V
EN_HYST
EN_LOCK
EN Lockout Threshold Voltage
V
V
rising
1.7
1.9
200
2.6
2.1
EN
EN Lockout Threshold
Hysteresis
V
EN_LOCK_
HYST
mV
µA
EN Input Current
I
V
V
= 12V
rising
0.8
5
EN
EN
POWER-GOOD OUTPUT
PGOOD Threshold
V
0.54
0.56
15
0.585
V
PGOOD_TH
FB
V
PGOOD_
HYST
PGOOD Threshold Hysteresis
mV
PGOOD Output Low Voltage
PGOOD Leakage Current
ERROR AMPLIFIER
V
I
= 5mA, V = 0.5V
35
100
100
mV
nA
PGOOD_OL
PGOOD
FB
I
V
= 5V, V = 0.7V
PGOOD
PGOOD FB
Error-Amplifier
Transconductance
g
1.6
mS
MV
Error-Amplifier Voltage Gain
FB Set-Point Accuracy
FB Input Bias Current
SOFT-START
A
90
dB
mV
nA
VEA
V
600
606
612
FB
FB
I
V
V
= 0.5V or 0.7V
-100
+100
FB
SS Current
I
= 0.45V, sourcing
= 10mA, sinking
4.5
5
6
5.5
µA
SS
SS
SS Discharge Resistance
CURRENT SENSE
R
I
Ω
SS
SS
Current Sense to COMP
Transconductance
g
9
S
V
MC
COMP Clamp Low
PWM CLOCK
V
= 0.7V
0.68
FB
MAX18066
MAX18166
450
315
500
350
90
550
385
Switching Frequency
f
kHz
SW
Maximum Duty Cycle
D
MAX
%
Minimum Controllable On-Time
140
ns
Slope Compensation Ramp
Valley
840
667
mV
mV
Slope Compensation Ramp
Amplitude
V
Extrapolated to 100% duty cycle
SLOPE
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Electrical Characteristics (continued)
(V = 12V, C
= 1µF, C = 22µF, T = T = -40°C to +85°C, typical values are at T = T = +25°C, unless otherwise noted.) (Note 4)
A J
IN A J
IN
VDD
PARAMETER
INTERNAL LDO OUTPUT (V
SYMBOL
CONDITIONS
= 1mA, V = 6.5V to 16V
MIN
TYP
MAX
UNITS
)
DD
I
I
4.75
4.75
30
5.1
5.1
90
5.45
5.45
VDD
VDD
IN
V
Output Voltage
V
V
DD
DD
= 1mA to 25mA, V = 6.5V
IN
V
DD
V
DD
V
DD
Short-Circuit Current
LDO Dropout Voltage
Undervoltage Lockout
V
= 6.5V
mA
mV
IN
I
= 5mA, V
drops by 2%
100
4.1
VDD
DD
V
V
rising, LX starts switching
3.7
3.9
V
UVLO_TH
DD
Threshold
V
Undervoltage Lockout
DD
V
150
mV
UVLO_HYST
Hysteresis
POWER SWITCH
High-side switch, I = 0.4A
40
LX
LX On-Resistance
mΩ
A
Low-side switch, I = 0.4A
18.5
LX
High-Side Switch Source
Current-Limit Threshold
I
5.5
7.7
HSCL
Low-Side Switch Zero-Crossing
Current-Limit Threshold
0.21
0.58
A
High-Side Switch Skip Sourcing
Current-Limit Threshold
A
V
V
V
= 21V, V = V = 16V
0.01
0.01
0.01
10
BST
BST
BST
BST
IN
LX
LX Leakage Current
µA
= 5V, V = 16V, V = 0V
IN
LX
BST Leakage Current
BST On-Resistance
= 21V, V = V = 16V
µA
IN
LX
I
= 5mA
Ω
HICCUP PROTECTION
21 x
soft-start
time
Blanking Time
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Rising
160
20
°C
°C
Note 4: Specifications are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design and characterization.
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Typical Operating Characteristics
(V = 12V, V
= 1.8V, C
= 1µF, C = 22µF, C
= 47µF, T = +25°C (Figure 1, MAX18066), unless otherwise noted.)
A
IN
OUT
VDD
IN
OUT
EFFICIENCY vs. LOAD CURRENT
(MAX18066)
EFFICIENCY vs. LOAD CURRENT
(MAX18066)
toc01
toc02
100
90
80
70
60
50
40
100
V
= 5.0V
V
OUT
= 3.3V
V
= 5.0V
OUT
OUT
V
= 3.3V
OUT
90
80
70
60
50
V
= 1.8V
OUT
V
= 2.5V
V
OUT
= 1.8V
OUT
V
OUT
= 1.2V
V
OUT
= 2.5V
V
= 1.2V
OUT
0.4
0
0.1
0.2
0.3
(A)
0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(A)
I
I
LOAD
LOAD
EFFICIENCY vs. LOAD CURRENT
(MAX18066)
EFFICIENCY vs. LOAD CURRENT
(MAX18066)
toc03
toc04
100
90
80
70
60
50
100
95
90
85
80
75
70
V
= 3.3V
OUT
V
= 3.3V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
V
= 1.8V
OUT
V
OUT
= 1.8V
V
= 1.2V
OUT
V
= 1.2V
OUT
0.2
V
= 5V
V = 5V
IN
IN
0
0.4
0.6
(A)
0.8
1.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(A)
I
I
LOAD
LOAD
LOAD-TRANSIENT RESPONSE
(MAX18066)
toc05
V
OUT
100mV/div
AC-COUPLED
I
LOAD
1A/div
0A
100µs/div
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Typical Operating Characteristics (continued)
(V = 12V, V
= 1.8V, C
= 1µF, C = 22µF, C = 47µF, T = +25°C (Figure 1, MAX18066), unless otherwise noted.)
OUT A
IN
OUT
VDD
IN
LOAD-TRANSIENT RESPONSE
(MAX18066)
LOAD-TRANSIENT RESPONSE
(MAX18066)
toc06
toc07
V
OUT
V
OUT
100mV/div
100mV/div
AC-COUPLED
AC-COUPLED
I
I
OUT
OUT
2A/div
2A/div
0A
100µs/div
100µs/div
EFFICIENCY (5V) vs. OUTPUT CURRENT
EFFICIENCY (12V) vs. OUTPUT CURRENT
(MAX18166)
(MAX18166)
toc08
toc09
100
90
80
70
60
100
90
80
70
60
V
= 1.2V
OUT
V
= 0.9V
OUT
V
= 1.2V
OUT
V
= 0.9V
V
= 1.8V
OUT
OUT
V
OUT
= 1.8V
V
= 2.5V
OUT
V
= 2.5V
OUT
V
OUT
= 3.3V
V
= 3.3V
OUT
V
3
= 5.0V
V
= 12.0V
IN
IN
0
1
2
4
0
1
2
3
4
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
LOAD-TRANSIENT RESPONSE
(MAX18166)
LOAD REGULATION
toc11
toc10
0.6
0.5
0.4
0.3
0.2
0.1
0
V
V
= 12V
IN
= 0.9V
OUT
dl/dt = 1A/µs
= 4 x 47µF
C
OUT
(SEE FIGURE 2 FOR
OTHER VALUES)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(A)
40µs/div
I
LOAD
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Typical Operating Characteristics (continued)
(V = 12V, V
= 1.8V, C
= 1µF, C = 22µF, C = 47µF, T = +25°C (Figure 1, MAX18066), unless otherwise noted.)
OUT A
IN
OUT
VDD
IN
SWITCHING FREQUENCY
vs. INPUT VOLTAGE (MAX18066)
FB SET POINT vs. TEMPERATURE
toc12
toc13
607.0
606.8
606.6
606.4
606.2
606.0
605.8
605.6
605.4
605.2
605.0
525
1A LOAD
515
T
A
= +85°C
T
A
= +25°C
505
495
485
475
T
A
= -40°C
-40
-15
10
35
60
85
4.5
6.5
8.5
10.5 12.5 14.5 16.5
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT CURRENT vs. INPUT VOLTAGE
(MAX18066)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
toc14
toc15
2.0
1.8
1.6
1.4
1.2
1.0
5
4
3
2
1
0
L = 2.2µH
NO LOAD
EN = 0V
4.5
6.5
8.5
10.5 12.5 14.5 16.5
4.5
6.5
8.5
10.5 12.5 14.5 16.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN WAVEFORM
toc16
toc17
3.0
2.8
2.6
2.4
2.2
2.0
V
EN
10V/div
V
OUT
1V/div
I
LOAD
2A/div
V
PGOOD
5V/div
-40
-15
10
35
60
85
1ms/div
TEMPERATURE (°C)
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Typical Operating Characteristics (continued)
(V = 12V, V
= 1.8V, C
= 1µF, C = 22µF, C = 47µF, T = +25°C (Figure 1, MAX18066), unless otherwise noted.)
OUT A
IN
OUT
VDD
IN
SWITCHING BEHAVIOR
OUTPUT SHORT-CIRCUIT WAVEFORM
(MAX18066)
toc18
toc19
V
OUT
V
LX
2V/div
10V/div
0V
0V
V
SS
1V/div
V
OUT
0V
AC-COUPLED
10mV/div
I
IN
0.5A/div
0A
I
L
I
OUT
2A/div
10A/div
0A
0A
20ms/div
1µs/div
SKIP MODE WAVEFORM
(MAX18066)
SOFT-START WAVEFORM
toc20
toc21
I
L
V
OUT
2A/div
AC-COUPLED
20mV/div
V
OUT
V
LX
1V/div
10V/div
0V
V
PGOOD
5V/div
I
LOAD
2A/div
V
EN
0A
10V/div
400µs/div
40µs/div
SOFT-START TIME vs. CAPACITANCE
STARTUP INTO PREBIAS (NO LOAD)
toc22
toc23
1000.0
100.0
10.0
1.0
V
OUT
1V/div
0V
I
L
1V/div
0A
0A
I
LOAD
2A/div
V
EN
10V/div
0V
0.1
1
10
100
1000
400µs/div
C
(nF)
SS
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Typical Operating Characteristics (continued)
(V = 12V, V
= 1.8V, C
= 1µF, C = 22µF, C = 47µF, T = +25°C (Figure 1, MAX18066), unless otherwise noted.)
OUT A
IN
OUT
VDD
IN
MAXIMUM LOAD CURRENT
vs. TEMPERATURE (V = 12V)
IN
STARTUP INTO PREBIAS (4A LOAD)
(MAX18066)
toc25
toc24
10
9
L = 2.2µH
V
OUT
V
OUT
= 1.2V
1V/div
V
OUT
= 1.8V
8
V
V
= 2.5V
= 3.3V
OUT
0V
I
LOAD
0A
7
5A/div
I
L
6
5A/div
V
= 5.0V
OUT
0A
0V
OUT
5
V
MAXIMUM CURRENT IS LIMITED BY
THERMAL SHUTDOWN OR CURRENT LIMIT
EN
10V/div
4
-40
-15
10
35
60
85
400µs/div
TEMPERATURE (°C)
MAXIMUM LOAD CURRENT
JUNCTION TEMPERATURE vs. AMBIENT TEMPERATURE
vs. TEMPERATURE (V = 5V)
(V = 12V, L = 2.2µH, LOAD CURRENT = 4A)
IN
IN
(MAX18066)
(MAX18066)
toc27
toc26
8
7
6
5
4
120
L = 2.2µH
V
= 1.8V
OUT
110
V
= 1.2V
OUT
V
= 2.5V
OUT
100
90
80
70
60
50
40
V
= 3.3V
OUT
V
OUT
= 1.2V
V
= 2.5V
OUT
V
= 5V
OUT
V
OUT
= 3.3V
V
= 1.8V
OUT
MAXIMUM CURRENT IS LIMITED BY
THERMAL SHUTDOWN OR CURRENT LIMIT
-40
-15
10
35
60
85
25
35
45
55
65
75
85
TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
JUNCTION TEMPERATURE vs. AMBIENT TEMPERATURE
(V = 5V, L = 2.2µH, LOAD CURRENT = 4A)
IN
(MAX18066)
toc28
120
110
100
90
V
= 2.5V
OUT
V
OUT
= 3.3V
80
V
OUT
= 1.2V
70
V
= 1.8V
OUT
60
50
40
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (°C)
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
+
GND
A1
GND
A2
IN
IN
A3
A4
LX
B1
LX
B2
LX
B3
V
DD
B4
BST
C1
I.C.
C2
I.C.
C3
EN
C4
PGOOD
D1
FB
D2
COMP
D3
SS
D4
WLP
Pin Description
BUMP
NAME
FUNCTION
A1, A2
GND
Ground. Connect A1 and A2 together as close as possible to the device.
Power-Supply Input. Input supply range is from 4.5V to 16V. Connect A3 and A4 together as close as
possible to the device. Bypass IN to GND with a minimum 22µF ceramic capacitor as close as
possible to the device.
A3, A4
IN
Inductor Connection. Connect an inductor between LX and the regulator output. LX is high
impedance when the device is in shutdown mode. Connect all LX nodes together as close as possible
to the device.
B1–B3
B4
LX
Internal 5V LDO Output. V
powers the internal analog core. Connect a minimum of 1µF ceramic
DD
V
DD
capacitor from V
to GND.
DD
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.01µF capacitor. BST is internally
connected to the V regulator through a pMOS switch.
C1
C2, C3
C4
BST
I.C.
EN
DD
Internal Connection. Leave unconnected.
Enable Input. Connect EN to GND to disable the device. Set EN to above 1.9V (typ) to enable the
device. EN can be shorted to IN for always-on operation.
Power-Good Output. PGOOD is an open-drain output that goes high impedance when V exceeds
FB
0.56V (typ). PGOOD is internally pulled low when V falls below 0.545V (typ). PGOOD is internally
FB
D1
PGOOD
pulled low when the device is in shutdown mode, V
thermal shutdown.
is below the UVLO threshold, or the device is in
DD
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to
set the output voltage from 0.606V to 90% of V
D2
D3
D4
FB
COMP
SS
.
IN
Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to GND
(see the Compensation Design Guidelines section).
Soft-Start Timing Capacitor Connection. Connect a capacitor from SS to GND to set the startup time
(see the Setting the Soft-Start Time section).
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Block Diagram
EN
V
DD
ENABLE CONTROL AND
THERMAL SHUTDOWN
5V LDO
UVLO
COMPARATOR
3.9V/3.75V
BST
BIAS GENERATOR
V
DD
CURRENT-SENSE AMPLIFIER
AND CURRENT LIMIT
VOLTAGE REFERENCE
IN
LX
LX
CONTROL
LOGIC
MAX18066
MAX18166
V
DD
1.6V
CLAMP
GND
5µA
ZERO-CROSSING
CURRENT LIMIT
PWM
COMPARATOR
0.606
SS
FB
ERROR
AMPLIFIER
COMP
OSCILLATOR
PGOOD
MAX18066 (500kHz)
MAX18166 (350kHz)
POWER-GOOD
COMPARATOR
0.560V RISING,
0.545V FALLING
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
INPUT
4.5V TO 16V
IN
BST
LX
2.2µH
C
22µF
10nF
OUTPUT
EN
MAX18066
MAX18166
270pF
R1
OUT
V
DD
COMPONENT
MAX18066
1 x 47µF
7.5kΩ
MAX18166
4 x 47µF
7.5kΩ
1µF
10kΩ
C
OUT
FB
COMP
R
COMP
PGOOD
SS
10kΩ
R
COMP
C
2700pF
20kΩ
2700pF
5.1kΩ
COMP
GND
10nF
R1
C
COMP
V
1.8V
0.9V
OUT
Figure 1. Reference Circuit
The devices also provide the ability to start up into a
prebiased output.
Detailed Description
The MAX18066/MAX18166 are high-efficiency, peak
current-mode, step-down DC-DC converters with
integrated high-side (40mΩ) and low-side (18.5mΩ)
power switches. The output voltage is set from 0.606V to
Controller Function—PWM Logic
and Skip Mode
The devices employ PWM control with a constant
switching frequency of 500kHz (MAX18066) or 350kHz
(MAX18166) at medium and heavy loads, and skip mode
at light loads. When EN is high, after a brief settling time,
0.9 x V by using an external resistive divider and can
IN
deliver up to 4A of load current. The input voltage range
is 4.5V to 16V, making these devices ideal for distrib-
uted power systems, notebook computers, nonportable
consumer applications, and preregulation applications.
PWM operation starts when V exceeds the FB voltage,
SS
at the beginning of soft-start.
The devices feature a PWM, internally fixed switching
frequency of 500kHz (MAX18066) and 350kHz
(MAX18166) with a 90% maximum duty cycle. PWM
current-mode control allows for an all-ceram-
ic capacitor solution. The devices include a high-gain
transconductance error amplifier. The current-mode
control architecture simplifies compensation design, and
ensures a cycle-by-cycle current limit and fast reaction to
The first operation is always a high-side turn-on at the
beginning of the clock cycle. The high side is turned off
when any of the following conditions occur:
1) COMP voltage exceeds the internal current-mode
ramp waveform, which is the sum of the slope
compensation ramp and the current-mode ramp
derived from the inductor current waveform (through
the current-sense block).
line and load transients. The low R
, internal MOSFET
DS-ON
switches ensure high efficiency at heavy loads and
2) The high-side current limit is reached.
minimize critical inductances, reducing layout sensitivity.
3) The maximum duty cycle of 90% is reached.
The devices feature thermal shutdown, overcurrent
protection (high-side sourcing and hiccup protection),
and an internal 5V (25mA) LDO with undervoltage
lockout. An externally adjustable voltage soft-start
gradually ramps up the output voltage and reduces
inrush current. At light loads, as soon as a low-side
MOSFET zero-crossing event is detected, the devices
automatically switch to pulse-skipping mode to keep the
quiescent supply current low and enhances the light load
efficiency. An independent enable input controls and the
power-good output allow for flexible power sequencing.
The low side turns off when the clock period ends or when
the zero-crossing current threshold is intercepted. The
devices monitor the inductor current during every switch
cycle and automatically enters discontinuous mode when
the inductor current valley intercepts the zero-crossing
threshold (under light loads); under very light load condi-
tions, skip mode is activated/deactivated on a cycle-by-
cycle basis.
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
The devices enter discontinuous mode when load current
ceramic capacitor. V
supplies the low-side switch driv-
DD
er, and the internal control logic. The V
output current
(I ) and inductor ripple current (ΔI ) are such that:
LOAD L
DD
limit is 90mA (typ) and a UVLO circuit inhibits switching
when V falls below 3.75V (typ).
∆I
2
1
2
V
− V
V
OUT
V
IN
L
IN
L× f
OUT
DD
I
−
= I
−
LOAD
×
×
= 0.21A (typ)
LOAD
SW
Error Amplifier
A high-gain error amplifier provides accuracy for the
voltage feedback loop regulation. Connect the necessary
compensation network between COMP and GND (see
the Compensation Design Guidelines for details). The
error-amplifier transconductance is 1.6mS (typ). COMP
clamp low is set to 0.68V (typ), just below the slope
compensation ramp valley, helping COMP to rapidly
return to correct set point during load and line transients.
During skip-mode operation, the devices skip switch
cycles, switching only as needed to service the load. This
reduces the switching frequency and associated losses
in the internal switch, the synchronous rectifier, and the
inductor. In skip mode, to avoid the occasional switch
cycle “bursts” (and reduce power losses), a fixed on-time
is forecasted using a skip current-limit flag (0.58A, typ).
The on-time, even if controlled by COMP, cannot be lower
than the time needed for the inductor current to reach
0.58A.
PWM Comparator
The PWM comparator compares COMP voltage to the
current-derived ramp waveform (LX current to COMP
voltage transconductance value is 9A/V, typ). To avoid
instability due to subharmonic oscillations when the duty
cycle is around 50% or higher, a slope compensation
ramp is added to the current-derived ramp waveform. The
compensation ramp (0.667V x 500kHz) for the MAX18066
and (0.667V x 350kHz) for the MAX18166 is equivalent to
half of the inductor current down slope in the worst case
(load 4A, current ripple 30%, and maximum duty-cycle
operation of 90%).
Starting into a Prebiased Output
The devices are capable of safely soft-starting into a pre-
biased output without discharging the output capacitor.
Starting up into a prebiased condition, both low-side and
high-side switches remain off to avoid discharging the pre-
biased output. PWM operation starts only when the SS volt-
age crosses the FB voltage. During soft-start, zero crossing
is activated to avoid reverse current in the device.
Enable Input and Power-Good Output
The devices feature independent device enable
control and power-good signals that allow for flexible
power sequencing. The enable input (EN) accepts a
digital input with a 1.9V (typ) threshold. Apply a voltage
exceeding the threshold on EN to enable the regulator, or
connect EN to IN for always-on operations. Power-good
(PGOOD) is an open-drain output that deasserts (goes
Overcurrent Protection and Hiccup Mode
When the converter output is shorted or the device
is overloaded, the high-side MOSFET current-limit
event (7.7A, typ) turns off the high-side MOSFET and
turns on the low-side MOSFET. In addition, the device
discharges the SS capacitor (C ) for a fixed period of
SS
time (70ns, typ) through the internal SS low-side switch
high impedance) when V
is above 0.56V (typ), and
FB
R
(R ). If the overcurrent condition persists,
asserts low if V is below 0.545V (typ).
DS-ON
SS
FB
the device continues discharging C
until V
drops
SS
SS
When the EN voltage is higher than 0.7V (typ) and lower
than 1.9V (typ), most of the internal blocks are disabled;
only an internal coarse preregulator, including the EN
accurate comparator, is kept on. An external voltage-
divider from IN to EN to GND can be used to set the
device turn-on threshold.
below 0.606V and a hiccup event is triggered. The
regulator softly resets by pulling COMP low, turning
off the high-side and turning on the low-side, until the
low-side zero-crossing current threshold is reached.
The high-side and low-side MOSFETs remain off and
COMP is pulled low for a period equal to 21 times the
nominal soft-start time (blanking time). This is obtained by
charging SS from 0 to 0.606V with a 5µA (typ) current, and
then slowly discharging it back to 0V with a 250nA (typ)
current. After the blanking time has elapsed, the device
attempts to restart. If the overcurrent fault has cleared,
the device resumes normal operation. Otherwise, a new
hiccup event is triggered (see the Output Short-Circuit
Waveform in the Typical Operating Characteristics).
Programmable Soft-Start (SS)
The devices utilize a soft-start feature to slowly ramp
up the regulated output voltage to reduce input inrush
current during startup. Connect a capacitor from SS to
GND to set the startup time (see the Setting the Soft-Start
Time section for capacitor selection details).
Internal LDO (V
)
DD
The devices include an internal 5V (typ) LDO. V
is
DD
externally compensated with a minimum 1µF, low-ESR
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
where D
= f
x t
; f
is 500kHz/350kHz
Thermal-Shutdown Protection
MIN
OSC
ON(MIN) OSC
for the MAX18066/MAX18166, respectively, and t
is typically 140ns. See the specifications in the Electrical
Characteristics table.
ON(min)
The devices contain an internal thermal sensor that limits
the total power dissipation in the device and protects it in
the event of an extended thermal fault condition. When
the die temperature exceeds +160°C (typ), the thermal
sensor shuts down the device, turning off the DC-DC con-
verter and the LDO regulator to allow the die to cool. The
regulator softly resets by pulling COMP low, discharging
soft-start, turning off the high-side and turning on the low-
side, until the low-side zero-crossing current threshold is
reached. After the die temperature falls by 20°C (typ), the
device restarts using the soft-start sequence.
Inductor Selection
A larger inductor value results in reduced inductor ripple
current, leading to a reduced output ripple voltage.
However, a larger inductor value results in either a larger
physical size or a higher series resistance (DCR) and
a lower saturation current rating. Typically, the inductor
value is chosen to have current ripple equal to 30% of
load current. Choose the inductor with the following for-
mula:
Applications Information
Setting the Output Voltage
V
V
OUT
OUT
× ∆I
L =
× 1−
Connect a resistive divider (R1 and R2, see Figure 3)
from OUT to FB to GND to set the DC-DC converter
output voltage. Choose R1 and R2 so that the DC errors
due to the FB input bias current do not affect the output-
voltage accuracy. With lower value resistors, the DC error
is reduced, but the amount of power consumed in the
resistive divider increases. A typical trade-off value for R2
is 10kΩ, but values between 5kΩ and 50kΩ are accept-
able. Once R2 is chosen, calculate R1 using:
f
V
SW
L
IN
where f
is the internally fixed switching frequency of
500kHz (MAX18066) or 350kHz (MAX18166), and ΔI is
the estimated inductor ripple current (ΔI = LIR x I
where LIR is the inductor current ratio). In addition, the
peak inductor current, I must always be below both
the minimum high-side current-limit value (7.7A, typ), and
the inductor saturation current rating, I
the following relationship is satisfied:
SW
L
,
L
LOAD
,
L_PK
. Ensure that
L_SAT
V
OUT
R1 = R2 ×
−1
1
V
FB
I
= I
+
× ∆I < min(I
, I
)
L_PK
LOAD
L
HSCL L_SAT
2
where the feedback threshold voltage V = 0.606V (typ).
FB
When regulating an output of 0.606V, short FB to OUT
and keep R2 connected from FB to GND.
Input Capacitor Selection
For a step-down converter, input capacitor C helps
reduce input ripple voltage, in spite of discontinuous input
AC current. Low-ESR capacitors are preferred to mini-
mize the voltage ripple due to ESR.
IN
Maximum/Minimum Voltage
Conversion Ratio
The maximum voltage conversion ratio is limited by the
For low-ESR input capacitors, size C using the following
IN
formula:
maximum duty cycle (D
):
MAX
V
D
× V
+ (1− D ) × V
MAX DROP1
V
IN
OUT
MAX
DROP2
< D
+
I
V
OUT
V
IN
MAX
LOAD
C =
IN
×
V
IN
f
x ∆V
SW
IN_RIPPLE
where V
is the sum of the parasitic voltage drops in
DROP1
the inductor discharge path, including synchronous recti-
For high-ESR input capacitors, the additional ripple
fier, inductor, and PCB resistances. V is an abso-
contribution due to ESR (ΔV
) is calculated
DROP2
IN_RIPPLE_ESR
lute value and the sum of the resistances in the charging
path, including the high-side switch, inductor, and PCB
resistances.
as follows:
ΔV
= R
(I
+ ΔI /2)
IN_RIPPLE
ESR_IN LOAD L
where R
is the ESR of the input capacitor. The
ESR_IN
The minimum voltage conversion ratio is limited by the
RMS input ripple current is given by:
× V − V
OUT
minimum duty cycle (D
):
MIN
V
(
V
)
OUT
IN
I
= I
×
LOAD
V
V
V
RIPPLE
OUT
DROP2
DROP1
> D
+ D
×
+ (1− D
) ×
MIN
IN
MIN
MIN
V
V
V
IN
IN
IN
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage, and
transient response of the DC-DC converter. The output
ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL as follows:
instantly changes by ESR x ΔI . Before the control-
LOAD
ler can respond, the output deviates further, depending
on the inductor and output capacitor values. After a short
time, the controller responds by regulating the output volt-
age back to the predetermined value.
Use higher C
values for applications that require light-
OUT
load operation or transition between heavy load and light
load, triggering skip mode, causing output undershooting
or overshooting. When applying the load, limit the output
V
= V
+ V
+ V
undershooting by sizing C
formula:
according to the following
RIPPLE
RIPPLE(C)
RIPPLE(ESR) RIPPLE(ESL)
OUT
where the output ripple due to output capacitance, ESR,
and ESL is:
∆I
LOAD
× ∆V
OUT
C
=
OUT
3f
CO
∆I
P−P
V
=
RIPPLE(C)
8× C
× f
where ΔI
is the total load change, f
is the unity-
CO
OUT
SW
×ESR
LOAD
gain bandwidth (or zero-crossing frequency), and ΔV
OUT
V
= ∆I
P−P
RIPPLE(ESR)
is the desired output undershooting. When removing the
load and entering skip mode, the device cannot control
output overshooting, since it has no sink current
capability; see the Skip Mode Frequency and Output
and V
can be approximated as an inductive
RIPPLE(ESL)
divider from LX to GND:
ESL
L
ESL
L
V
= V
×
= V
×
Ripple section to properly size C
under this
RIPPLE (ESL)
LX
IN
OUT
circumstance.
where V swings from V to GND.
LX
IN
A worst-case analysis in sizing the minimum out-
put capacitance takes the total energy stored in the
inductor into account, as well as the allowable sag/soar
(undershoot/overshoot) voltage as follows:
The peak-to-peak inductor current (ΔI ) is:
P-P
V
OUT
V
− V
×
OUT
(
)
IN
V
IN
∆I
=
P−P
2
2
L × I
−I
OUT MIN
L × f
(
)
OUT MAX
SW
(
)
(
)
C
=
, voltage soar (overshoot)
OUT (MIN)
2
2
V
+ V
− V
INIT
(
)
FIN
SOAR
When using ceramic capacitors, which generally have
low-ESR, ΔV dominates. When using electro-
RIPPLE(C)
lytic capacitors, ΔV
dominates. Use ceramic
RIPPLE(ESR)
2
2
L × I
−I
(
)
OUT MAX
OUT MIN
(
)
(
)
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to ESL
is negligible when using ceramic capacitors.
C
=
, voltage sag (undershoot)
OUT(MIN)
2
2
V
− V
(
− V
)
INIT
FIN SAG
where I
and I
are the initial and final
OUT(MAX)
OUT(MIN)
As a general rule, a smaller inductor ripple current results
in less output ripple voltage. Since inductor ripple current
depends on the inductor value and input voltage, the
output ripple voltage decreases with larger inductance
and increases with higher input voltages. However, the
inductor ripple current also impacts transient-response
values of the load current during the worst-case load
dump, V is the initial voltage prior to the transient,
INIT
V
V
V
is the steady-state voltage after the transient,
is the allowed voltage soar (overshoot) above
FIN
SOAR
FIN
, and V
The terms (V
is the allowable voltage sag below V
.
FIN
SAG
FIN
+ V
) and (V
SOAR
- V ) represent
SAG
FIN
performance, especially at low V to V
differentials.
IN
OUT
the maximum/minimum transient output voltage reached
during the transient, respectively.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step.
Use these equations for initial output-capacitor selection.
Determine final values by testing a prototype or an evalu-
ation circuit under the worst-case conditions.
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
or approximately as:
I
L
1
1
I
SKIP-LIMIT
t
= L ×I
×
SKIP−LIMIT
+
OFF2
V
− V
V
OUT
IN
OUT
I
LOAD
I
t
ON
SKIP−LIMIT
×
−I
LOAD
t
OFF1
2
V
OUT-RIPPLE
t
= n x T
CK
OFF2
I
LOAD
V
OUT
Finally, frequency in skip mode is:
1
f
=
SKIP
t
+ t
+ t
OFF1 OFF2
ON
Figure 2. Skip Mode Waveform
Output ripple in skip mode is:
Skip Mode Frequency and Output Ripple
V
= V
+ V
ESR−RIPPLE
In skip mode, the switching frequency (f
) and
OUT−RIPPLE
COUT−RIPPLE
SKIP
output ripple voltage (V
calculated as follows:
) shown in Figure 2 are
OUT_RIPPLE
I
−I
× t
(
)
SKIP−LIMIT LOAD
ON
=
+
C
OUT
t
is the time needed for the inductor current to reach
ON
R
× I
(
−I
SKIP−LIMIT LOAD
)
ESR,COUT
the SKIP current limit (0.58A, typ):
To limit output ripple in skip mode, size C
the above formula accordingly. All formulas above are
based on
L ×I
OUT
SKIP−LIMIT
t
=
ON
V
− V
IN
OUT
[1]
valid for I < I
.
SKIP-LIMIT
LOAD
t
is the time needed for the inductor current to reach
OFF1
Compensation Design Guidelines
the zero current limit (~0A):
The devices use a fixed-frequency, peak current-mode
control scheme to provide easy compensation and fast
transient response. The inductor peak current is moni-
tored on a cycle-by-cycle basis and compared to the
COMP voltage (output of the voltage error amplifi-
er). The regulator’s duty cycle is modulated based on
the inductor’s peak current value. This cycle-by-cycle
control of the inductor current emulates a controlled
current source. As a result, the inductor’s pole frequency
is shifted beyond the gain bandwidth of the regulator.
L ×I
SKIP−LIMIT
t
=
OFF1
V
OUT
[2]
During t
and t
the output capacitor stores a
ON
OFF1
charge equal to (see Figure 2):
1
2
∆Q
=
I
× t
(
+ t
)
OUT
SKIP−LIMIT
ON
OFF1
− I
× t
(
+ t
ON OFF1
)
LOAD
[3]
Combining [1], [2] and [3], and solving for ΔQ
:
System stability is provided with the addition of a simple
series capacitor-resistor from COMP to GND. This pole-
zero combination serves to tailor the desired response of
the closed-loop system.
OUT
I
SKIP−LIMIT
L ×I
×
−I
SKIP−LIMIT
LOAD
2
1
1
The basic regulator loop consists of a power modulator
(comprising the regulator’s pulse-width modulator, slope
compensation ramp, control circuitry, MOSFETs, and
inductor), the capacitive output filter and load, an output
feedback divider, and a voltage-loop error amplifier with
its associated compensation circuitry (see Figure 3).
×
+
V
− V
V
OUT
IN
OUT
2
∆Q
=
OUT
During t
(= n x t , number of clock cycles skipped),
CK
the output capacitor loses this charge or can approximate
OFF2
as:
∆Q
OUT
t
=
OFF2
I
LOAD
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
FEEDBACK
DIVIDER
ERROR AMPLIFIER
POWER MODULATOR
OUTPUT FILTER
AND LOAD
COMPENSATION
RAMP
V
IN
V
OUT
g
MC
FB
*C
V
FF
R1
COMP
Q
Q
FB
HS
I
L
V
OUT
L
DCR
I
OUT
CONTROL
LOGIC
V
COMP
PWM
COMPARATOR
LS
ESR
R
LOAD
R
C
g
R2
R
OUT
MV
C
OUT
C
C
V
V
OUT
COMP
G
MOD
I
L
AVEA(dB)/20
10
NOTE: THE G
INJECTED INTO THE OUTPUT LOAD, I , e.g., I = I
OUT
STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR, I ,
L
MOD
R
OUT
=
g
MV
.
OUT
L
REF
SUCH CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER STAGE
CIRCUITRY SHOWN WITHIN THE BOXED AREA.
*C IS OPTIONAL, DESIGNED TO EXTEND THE REGULATOR’S
FF
GAIN BANDWIDTH AND INCREASED PHASE MARGIN FOR SOME
LOW-DUTY CYCLE APPLICATIONS.
Figure 3. Peak Current-Mode Regulator Transfer Model
The average current through the inductor is expressed as:
The peak current-mode controller’s modulator gain is
attenuated by the equivalent divider ratio of the load resis-
I
= G
× V
MOD COMP
L
tance and the current-loop gain. G
becomes:
MOD
1
G
DC = g
×
MC
(
)
MOD
where I is the average inductor current and G
MOD
is
R
L
LOAD
1+
× K × 1− D − 0.5
S
(
)
the power modulator’s transconductance. For a buck
converter:
f
×L
SW
where R
= V is the switching
, f
LOAD
OUT/IOUT(MAX) SW
V
= R
×I
LOAD L
OUT
frequency, L is the output inductance, D is the duty cycle
(V /V , and K is the slope compensation factor cal-
culated from the following equation:
OUT IN)
S
where R
is the equivalent load resistor value.
LOAD
Combining the above two relationships, the power modu-
S
V
× f
×L × g
MC
SLOPE
S
N
SLOPE SW
lator’s transfer function in terms of V with respect to
OUT
K
= 1+
= 1+
S
V
− V
(
)
V
is:
IN OUT
COMP
where:
V
R
×I
LOAD L
OUT
=
= R
× G
LOAD MOD
V
V
SLOPE
I
COMP
L
S
=
= V
× f
SLOPE
SLOPE SW
t
SW
G
MOD
V
(
− V
OUT
)
IN
S
=
N
L × g
MC
Maxim Integrated
│ 17
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
As previously mentioned, the power modulator’s dominate
pole is a function of the parallel effects of the load resis-
tance and the current-loop gain’s equivalent impedance:
where the sampling effect quality factor, Q , is:
C
1
Q
=
C
π × K × 1− D − 0.5
(
)
S
1
f
=
PMOD
−1
and the resonant frequency is:
(s) =
K × 1− D − 0.5
(
)
1
S
2π × C
× ESR +
+
OUT
f
ωSAMPLING
π x
SW
R
f
×L
LOAD
SW
or:
f
Knowing that the ESR is typically much smaller than the
parallel combination of the load and the current loop,
SW
2
f
=
SAMPLING
e.g.,:
Having defined the power modulator’s transfer function,
the total system transfer can be written as follows
(Figure 3):
−1
K
× 1− D − 0.5
(
)
1
S
ESR <<
+
R
f
× L
LOAD
SW
Gain(s) = G (s)
G (s)
EA
G (DC)
MOD x
FF
x
x
G
(s)
G
(s)
FILTER
x
SAMPLING
1
f
≈
PMOD
−1
where:
K
× 1− D − 0.5
(
)
1
S
2π × C
×
+
OUT
sC R1+1
R2
R1+ R2
(
FF
)
FF
R
f
×L
G
s =
( )
×
LOAD
SW
FF
sC R1|| R2
+1
(
)
This can be expressed as:
1
Leaving C empty, G (s) becomes:
K
× 1− D − 0.5
FF
FF
(
)
S
f
≈
+
PMOD
2π × C
×R
2π × f
×L × C
R2
OUT
LOAD
SW
OUT
G
s =
( )
FF
R1+ R2
Note: Depending on the application’s specifics, the ampli-
tude of the slope compensation ramp could have a sig-
nificant impact on the modulator’s dominate pole. For low
duty-cycle applications, it provides additional
damping (phase lag) at/near the crossover frequency.
See the Closing the Loop: Designing the
Compensation Circuitry section. There is no equivalent
effect on the power modulator zero:
Also:
G
sC R +1
(
)
AVEA(dB)/20
C C
s = 10
( )
×
EA
AVEA(dB)/20
10
sC
R
+
+1
C
C
g
MV
AVEA(dB)/20
10
If R <<
C
, the equation simplifies to:
g
1
MV
f
= f
=
ZESR
ZMOD
2π × C
×ESR
OUT
sC R +1
(
)
The effect of the inner current loop at higher frequencies
is modeled as a double-pole (complex conjugate)
AVEA(dB)/20
C C
G
s = 10
×
( )
EA
AVEA(dB)/20
10
sC
+1
C
frequency term, G
(s), as shown:
SAMPLING
g
MV
1
G
s =
( )
SAMPLING
2
s
s
sC
ESR +1
(
)
OUT
+
+1
G
s = R
( )
×
FILTER
LOAD
2
−1
π × f
× Q
SW
C
π × f
(
)
K × 1− D − 0.5
S
(
)
1
SW
sC
+
+1
OUT
2π ×R
2π × f
×L
LOAD
SW
Maxim Integrated
│
18
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
1ST ASYMPTOTE
R2 x (R1 + R2) x 10
AVEA(dB)/20
-1
-1 -1
) }
SW
x g x R
MC
x {1 + R
x [K x (1 – D) – 0.5] x (L x f
S
LOAD
LOAD
2ND ASYMPTOTE
-1
-1
C ) x g x R
-1 -1
}
R2 x (R1 + R2) x g x (2
�
x {1 + R
x [K x (1 – D) – 0.5] x (L x f )
S SW
C
MV
MC
LOAD
LOAD
GAIN
3RD ASYMPTOTE
-1
-1
-1 -1
) }
SW
R2 x (R1 + R2) x g x (2
MV
�
C ) x g x R
x {1 + R
x [K x (1 – D) – 0.5] x (L x f
S
C
MC
LOAD
LOAD
-1
-1 -1 -1
x (2
�
C
OUT
x {R
+ [K (1 – D) – 0.5] x (L x f
)
}
)
LOAD
S
SW
4TH ASYMPTOTE
-1
-1 -1
) }
SW
R2 x (R1 + R2) x g x R x g x R
x {1 + R
x [K x (1 – D) – 0.5] x (L x f
MV
-1
C
MC
LOAD
LOAD
-1 -1 -1
) } )
SW
S
x (2�
C
x {R
+ [K (1 – D) – 0.5] x (L x f
S
OUT
LOAD
3RD POLE
0.5 x f
2ND ZERO
-1
(2�C ESR)
SW
OUT
UNITY
1ST ZERO
FREQUENCY
1ST POLE
(2�C R )-1
C
C
AVEA(dB)/20
[2�C (10
f
C
CO
x g -1)]-1
MV
2ND POLE
5TH ASYMPTOTE
-1
f
*
PMOD
-1 -1
) }
SW
R2 x (R1 + R2) x g x R x g x R
x {1 + R
x [K x (1 – D) – 0.5] x (L x f
MV
-1
C
MC
LOAD
LOAD
-1 -1 -1
) } ) x (0.5 x f )2 x (2�
SW SW
S
-2
f)
x [(2
�
C
x {R
+ [K (1 – D) – 0.5] x (L x f
S
OUT
LOAD
NOTE:
AVEA(dB)/20
-1
R
= 10
x g
OUT
MV
f
= [2�C
OUT
x (ESR + {R
-1 + [K (1 – D) – 0.5] x (L x f )-1}-1)]-1
SW
PMOD
LOAD
S
WHICH FOR
ESR << {R
6TH ASYMPTOTE
-1
-1 + [K (1 – D) – 0.5] x (L x f )-1}-1
SW
LOAD
S
-1 -1
) }
SW
R2 x (R1 + R2) x g x R x g x R
x {1 + R
-1 -1
x [K x (1 – D) – 0.5] x (L x f
MV
C
MC
LOAD
LOAD
S
-1
2
x (0.5·f )
SW
-2
x (2�f)
x ESR x {R
+ [K (1 – D) – 0.5] x (L x f
)
}
LOAD
S
SW
BECOMES
f
f
= [2
= (2
�
�
C
C
x {R
-1 + [K (1 – D) – 0.5] x (L x f )-1}-1]-1
PMOD
PMOD
OUT
LOAD
S
SW
-1
x R
)
-1 + [K (1 – D) – 0.5] x (2
S
�
C
OUT
x L x f
)
SW
OUT
LOAD
Figure 4. Asymptotic Loop Response of Peak Current-Mode Regulator
The dominant poles and zeros of the transfer loop gain
are shown below:
Figure 4 shows a graphical representation of the
asymptotic system closed-loop response, including domi-
nant pole and zero locations.
g
MV
AVEA dB /20
f
<<
The loop response’s fourth asymptote (in bold, Figure 4)
is the one of interest in establishing the desired crossover
frequency (and determining the compensation component
values). A lower crossover frequency provides for stable
closed-loop operation at the expense of a slower load
and line transient response. Increasing the crossover fre-
quency improves the transient response at the (potential)
cost of system instability. A standard rule of thumb sets
the crossover frequency ≤ 1/5 to 1/10 of the switching
frequency.
P1
(
)
2π × C × 10
C
1
f
=
P2
−1
K
× 1− D − 0.5
(
)
1
S
2π × C
+
OUT
R
f
×L
LOAD
SW
f
SW
2
f
=
P3
1
1
f
=
f
=
Z2
Z1
2π × C R
2π × C
ESR
OUT
C
C
First, select the passive power components that meet
the application’s requirements. Then, choose the small-
signal compensation components to achieve the desired
closed-loop frequency response and phase margin
as outlined in the Closing the Loop: Designing the
Compensation Circuitry section.
The order of pole-zero occurrences is:
< f ≤ f < f < f < f
Z2
f
P1 P2
Z1
CO
P3
Note: Under heavy load, f can approach f
.
Z1
P2
Maxim Integrated
│ 19
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Optional: For low duty-cycle applications, the addition of
Closing the Loop: Designing the
Compensation Circuitry
a phase-leading capacitor (C
in Figure 3) helps miti-
FF
gate the phase lag of the damped half-frequency double
pole. Adding a second zero near to but below the desired
crossover frequency increases both the closed-loop
phase margin and the regulator’s unity-gain bandwidth
(crossover frequency). Select the capacitor as follows:
1) Select the desired crossover frequency. Choose f
CO
between 1/5 to 1/10 of f
.
SW
2) Select R by setting the system transfer’s fourth
C
asymptote gain equal to unity (assuming f
> f
,
Z1
CO
f
, and f ). R becomes:
P2
P1 C
1
C
=
FF
R
K
1− D − 0.5
(
)
2π × f
× R1|| R2
LOAD
S
(
)
CO
1+
L × f
R1+ R2
R2
SW
This guarantees the additional phase-leading zero occurs
at a frequency lower than f from:
R
=
×
× 2πf
C
×
C
CO OUT
g
× g
×R
MV
MC
LOAD
CO
1
f
=
PHASE_LEAD
1
2π × C ×R1
FF
ESR +
K
1− D − 0.5
(
)
1
S
Using C , the zero-pole order is adjusted as follows:
FF
+
R
L × f
LOAD
SW
1
1
f
< f ≤ f
<
Z1
<
P1 P2
2πC R1 2πC (R1|| R2)
FF
FF
and where the ESR is much smaller than the parallel com-
bination of the equivalent load resistance and the current-
loop impedance, e.g.,:
≈ f
< f < f
P3 Z2
CO
Confirm the desired operation of C
empirically. The
FF
phase lead of C diminishes as the output voltage is a
smaller multiple of the reference voltage, e.g., below
1
FF
ESR <<
K
1− D − 0.5
(
)
1
S
about 1V. Do not use C when V
= V
.
+
FF
OUT
FB
R
L × f
LOAD
SW
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
R
becomes:
C
2πf
g
× C
R1+ R2
reducing input inrush current during startup. Size the C
CO
MV
OUT
MC
SS
R
=
×
C
capacitor to achieve the desired soft-start time (t ) using:
SS
R2
× g
3) Select C . C is determined by selecting the desired
I
× t
V
C
C
SS
SS
FB
C
=
SS
first system zero, f , based on the desired phase
Z1
margin. Typically, setting f
below 1/5 of f
Z1
CO
provides sufficient phase margin.
I
, the soft-start current, is 5µA (typ) and V , the output
FB
SS
f
1
CO
5
feedback voltage threshold, is 0.606V (typ). When using
large C capacitance values, the high-side current limit
f
=
≤
Z1
C
2π × C R
C
C
OUT
can trigger during soft-start period. To ensure the correct
therefore:
soft-start time t , choose C large enough to satisfy:
SS
SS
5
V
×I
OUT SS
− I
≥
C
C
>> C
×
OUT
SS
2π × f
×R
CO
C
(I
) × V
OUT FB
HSCL
I
is the typical high-side switch current-limit value.
HSCL
Maxim Integrated
│ 20
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
Layout Procedure
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX18066/MAX18166 evaluation kit layout for optimum
performance. If deviation is necessary, follow these guide-
lines for good PCB layout:
4) Connect IN, LX, and GND separately to large
copper areas to help cool the device to further improve
efficiency and long-term reliability.
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the
signal ground plane. Connect the signal ground plane
to the power ground plane at a single point adjacent to
the ground bump of the IC.
5) For better thermal performance, maximize the copper
trace widths for consecutive bumps (LX, IN, GND)
using solder mask (SMD) lands.
6) Ensure all feedback connections are short and direct.
Place the feedback resistors and compensation
components as close as possible to the device.
2) Place capacitors on V , IN, and SS as close as
DD
possible to the device and the corresponding pin using
direct traces. Keep the power ground plane and signal
ground plane separate. Connect all GND bumps at
only one common point near the input bypass capaci-
tor return terminal.
7) Route high-speed switching nodes (such as LX and
BST) away from sensitive analog areas (such as SS,
FB, and COMP).
Ordering Information
PART NUMBER
MAX18066EWE+
MAX18166EWE+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 WLP
FREQUENCY
500kHz
16 WLP
350kHz
+Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
│ 21
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MAX18066/MAX18166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
11/17
Initial release
—
For information on other Maxim Integrated products, visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 22
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