MAX1816ETM+T [MAXIM]
Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, CQCC48, 7 X 7 MM, 0.80 MM HEIGHT, THIN, QFN-48;
| 型号： | MAX1816ETM+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, CQCC48, 7 X 7 MM, 0.80 MM HEIGHT, THIN, QFN-48 电脑 控制器 |
| 文件： | 总49页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2569; Rev 0; 10/02
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
General Description
Features
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. BUCK1 is a CPU
core regulator with dynamically adjustable output, ultra-
fast transient response, high DC accuracy, and high effi-
ciency. BUCK2 is an adjustable step-down regulator for
I/O and memory supplies. Both regulators employ Maxim’s
proprietary Quick-PWM™ control architecture. This fast-
response, constant-on-time PWM control scheme handles
wide input/output voltage ratios with ease and provides
100ns “instant” on-response to load transients, while main-
taining a relatively constant switching frequency. The
MAX1816/MAX1994 also have a linear-regulator controller
for low-voltage auxiliary power supplies.
o Dual Quick-PWM Architecture
o ±±1 ꢀ Accuracy
OUT
o 5-Bit On-Board D/A Converter
o +0.60ꢀ to +±.75ꢀ Output Adjust Range (MAX±8±6)
o +0.70ꢀ to +2.00ꢀ Output Adjust Range (MAX±994)
o ꢀoltage-Positioning Gain and Offset Control
o +2ꢀ to +28ꢀ Battery Input Range
o Differential Remote Sense (BUCK±)
o Linear-Regulator Controller
o 200/300/550/±000kHz Switching Frequency
The CPU regulator supports “active voltage positioning”
to reduce output bulk capacitance and lower power dis-
sipation. A programmable gain amplifier allows the use
of lower value sense resistors. Four fixed-gain settings
are available (0, 1.5, 2, and 4). A differential remote-
sense amplifier is also included to more accurately con-
trol the voltage at the load. Accuracy is further
enhanced with an internal integrator.
o 2.2mA (typ) I
Supply Current
CC
o 20µA (max) Shutdown Supply Current
o Independent Power-Good Outputs
(PGOOD, LINGOOD)
Ordering Information
The MAX1816/MAX1994 include a specialized digital
interface that makes them suitable for mobile CPU and
video processor applications. The power-good
(PGOOD) output for the core regulator is forced high
during VID transitions, and the LINGOOD output for the
linear regulator includes a 1ms (min) turn-on delay.
PART
MAX±8±6ETM
MAX±994ETM
TEMP RANGE
-40°C to +100°C
-40°C to +100°C
PIN-PACKAGE
48 Thin QFN
48 Thin QFN
Pin Configuration
BUCK1, BUCK2, and the linear regulator feature overvolt-
age protection (OVP). The detection threshold for BUCK1
is adjusted with an external resistive voltage-divider, while
the OVP thresholds for BUCK2 and the linear regulator
TOP VIEW
are fixed. Connecting the OVPSET pin to V
disables
CC
OVP for BUCK1 and BUCK2, but not the linear regulator.
36
35
34
33
32
31
30
29
28
27
26
25
ILIM1
CC
1
2
3
4
5
6
7
8
9
ILIM2
CS2
The MAX1816 features an output-voltage adjustment
range from 0.6V to 1.75V. Similarly, the MAX1994 is
adjustable from 0.925V to 2.0V, using an alternate VID
code set. While in suspend mode, the adjustment range
is 0.7V to 1.075V for both the MAX1816 and MAX1994.
Both parts are available in 48-pin thin QFN packages.
CS1+
CS1-
FBS
GDS
GAIN
OFS0
OFS1
OUT2
FB2
REF
V
CC
MAX1816
MAX1994
AGND
LINBSE
LINGOOD
LINFB
Applications
Mobile CPU Core and Video Processors
OFS2 10
SUS 11
TIME
Memory I/O and VID Supplies
OVPSET
DPSLP 12
3- to 4-Cell Li+ Battery to CPU Core Supply
Small Notebook Computers
THIN QFN 7mm × 7mm
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
V+ to AGND............................................................-0.3V to +30V
DH2 to LX2 ..............................................-0.3V to (V
+ 0.3V)
BST2
V
, V
to AGND...................................................-0.3V to +6V
BST1 to LX1..............................................................-0.3V to +6V
BST2 to LX2..............................................................-0.3V to +6V
LX1, LX2, CS2 to AGND............................................-2V to +30V
REF Short Circuit to AGND.........................................Continuous
LINBSE Short Circuit to +6V.......................................Continuous
CC DD
PGND, GDS to AGND ......................................................... 0.3V
SKP1/SDN, SKP2/SDN, LIN/SDN to AGND............-0.3V to +16V
LINBSE, SUS, PERF, DPSLP, PGOOD,
LINGOOD, CS1+, CS1-, FBS, D0–D4,
OUT2 to AGND.....................................................-0.3V to +6V
OFS0, OFS1, OFS2, ILIM1, ILIM2,
FB2, REF, TON, TIME, OVPSET, S0, S1,
Continuous Power Dissipation (T = +70°C)
A
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .2105mW
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
GAIN, CC, LINFB to AGND ....................-0.3V to (V + 0.3V)
CC
DL1, DL2 to PGND .....................................-0.3V to (V + 0.3V)
DD
BST1
DH1 to LX1 ..............................................-0.3V to (V
+ 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V
LIN/SDN
= 5.0V,
UNITS
V
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
TON = REF, open, or V
TON = GND
2
2
28
16
CC
Battery voltage V+
, V
Input Voltage Range
V
4.5
5.5
CC DD
V+ = 4.5V to 28V,
includes load
regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
DAC codes from 0.600V to
1.750V (MAX1816)
BUCK1 DC Output Voltage
Accuracy
-1
+1
%
V
DAC codes from 0.700V to
2.000V (MAX1994)
FB2 = GND
2.475
1.782
0.990
1.0
2.500
1.800
1.000
2.525
1.818
1.010
5.5
BUCK2 Error Comparator Threshold
(DC Output Voltage Accuracy)
(Note 1)
V+ = 4.5V to 28V
FB2 = V
CC
FB2 = OUT2
OUT2 Adjust Range
FB2 GND Level
V
V
Voltage level to enable internal feedback for BUCK2
with V = 2.5V
0.05
1.90
OUT2
Voltage level to enable external feedback for BUCK2
with FB2 regulated to 1.0V nominal
FB2 External Feedback Level
0.15
2.10
V
V
Voltage level to enable internal feedback for BUCK2
FB2 V
Level
CC
with V
= 1.8V
OUT2
GAIN = GND
GAIN = REF
GAIN = open
0
1.425
1.900
3.800
1.500
2.000
4.000
1.575
2.100
4.200
Voltage-Positioning Gain
V/V
GAIN = V
CC
2
_______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current-Sense Differential Input
Range (CS1+, CS1-)
200
300
200
mV
Remote-Sense Differential Input
Range (CS1+, FBS)
mV
mV
Remote-Sense Differential Input
Range (GDS, AGND)
CS1+, FBS Input Bias Current
CS1- Input Bias Current
GDS Input Bias Current
FB2 Input Bias Current
OUT2 Input Resistance
-300mV < V
-100mV < V
- V
- V
< +300mV
-60
-60
-3
+60
+60
+3
µA
µA
µA
µA
kΩ
CS1+
CS1+
FBS
< +100mV, V
= V
FBS
CS1-
CS1-
-0.2
70
+0.2
252kHz nominal, R
= 143kΩ
-8
+8
TIME
TIME Frequency Accuracy
%
53kHz nominal to 530kHz nominal,
= 680kΩ to 68kΩ
-12
+12
R
TIME
V+ = 5V, CS1- = 1.2V
V+ = 12V, CS1- = 1.2V
V+ = 5V, OUT2 = 2.5V
V+ = 12V, OUT2 = 2.5V
TON = GND (1000kHz)
TON = REF (550kHz)
TON = open (300kHz)
230
165
320
465
630
495
495
740
260
190
355
515
720
550
550
825
425
325
290
215
390
565
810
605
605
910
500
375
BUCK1 On-Time (Note 2)
ns
TON = V
(200kHz)
CC
TON = GND (715kHz)
TON = REF (390kHz)
TON = open (390kHz)
BUCK2 On-Time (Note 2)
Minimum Off-Time
ns
TON = V
(260kHz)
CC
TON = open, TON = V (Note 2)
CC
ns
TON = GND, TON = REF (Note 2)
Measured at V , with FBS, OUT2, FB2, and LINFB
CC
forced above the no-load regulation point
Quiescent Supply Current (V
)
CC
2200
3800
µA
V
= 0V, V
= 0V, V
= 5V;
SKP1/SDN
SKP2/SDN
LIN/SDN
Partial Shutdown Supply Current
(Linear Regulator On Only)
measured at V , with FBS and LINFB forced above
CC
the no-load regulation point
425
650
µA
µA
V
= 5V, V
= 0V, V
= 5V;
SKP1/SDN
SKP2/SDN
LIN/SDN
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
measured at V , with FBS and LINFB forced above
CC
the no-load regulation point
1825
3000
V
= 0V, V
= 5V, V
= 0V;
SKP1/SDN
SKP2/SDN
LIN/SDN
Partial Shutdown Supply Current
(BUCK2 Only)
measured at V , with OUT2 and FB2 forced above
CC
the regulation point
600
<1
1100
5
µA
µA
Measured at V , with FBS, OUT2, and FB2 forced
DD
above the no-load regulation point
Quiescent Supply Current (V
)
DD
_______________________________________________________________________________________
3
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
25
4
MAX
UNITS
µA
Quiescent Battery Current
Shutdown Supply Current (V
Shutdown Supply Current (V
Measured at V+
40
10
5
)
)
V
= 0V, V
= 0V, V
= 0V, and V
= 0V, and V
= 0V
µA
CC
SKP1/SDN
SKP1/SDN
SKP2/SDN
LIN/SDN
V
= 0V
<1
µA
DD
SKP2/SDN
LIN/SDN
V
V
= V
= 0V, measured at V+, with
= 50µA sourcing
REF
SKP1/SDN
SKP2/SDN
Shutdown Battery Current
Reference Voltage
<1
5
µA
V
= V
= 0V or 5V
DD
CC
V
= 4.5V to 5.5V, I
= 0 to 50µA
1.98
0
2.00
2.02
7
CC
REF
REF
I
I
Reference Load Regulation
Reference Sink Current
mV
µA
V
= 50µA to 100µA
0
7
REF in regulation
10
Voltage at OVPSET above which the OVP functions
are disabled for BUCK1 and BUCK2
V
-
V
-
CC
0.5
CC
OVPSET Disable Mode Threshold
1.5
OVPSET Default Mode Threshold
for BUCK1
Voltage at OVPSET below which the OVP thresholds
are set to their default values
0.4
0.6
V
V
MAX1816
MAX1994
MAX1816
MAX1994
MAX1816
MAX1994
1.95
2.20
0.95
1.075
1.95
2.20
2.00
2.25
1.00
1.125
2.00
2.25
2.05
2.30
1.05
1.175
2.05
2.30
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS
V
= 1.0V,
OVPSET
measured at FBS
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold)
V
V
= 2.0V,
OVPSET
measured at FBS
Overvoltage Trip Threshold for
BUCK2
Measured at OUT2 (or FB2 if external feedback is
used)
113
115
117
%
nA
µs
OVPSET Bias Current
0V < V
< V
-100
+100
OVPSET
CC
Overvoltage Fault Propagation
Delay
FBS, OUT2, FB2, and LINFB forced 2% above the
no-load trip threshold
10
70
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage, FBS, and
OUT2 (FB2 in external feedback)
65
75
%
Output Undervoltage Fault
Propagation Delay
FBS, OUT2, FB2, and LINFB forced 2% below trip
threshold
10
µs
Output Undervoltage Protection
Blanking Time for FBS
From SKP1/SDN signal going high; clock speed set
256
4096
Clks
Clks
by R
(Note 3)
TIME
Output Undervoltage Protection
Blanking Time for OUT2
From SKP2/SHDN signal going high; clock speed set
by R (Note 3)
TIME
Linear Regulator (LINFB)
Undervoltage Protection Blanking
Time
Linear regulator; from LIN/SDN signal going high;
clock speed set by R (Note 3)
512
Clks
TIME
4
_______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
1.5
-
V
1.0
-
V
0.5
-
CC
CC
CC
ILIM1 Default Threshold
V
BUCK1 Current-Limit Threshold
(Fixed)
CS1+ - CS1-; V
CS1+ - CS1-; V
CS1+ - CS1-; V
CS1+ - CS1-; V
= V
40
50
60
mV
mV
mV
ILIM1
ILIM1
ILIM1
ILIM1
CC
= 0.5V
= 2.0V
40
160
-90
50
200
-72
60
240
-55
BUCK1 Current-Limit Threshold
(Adjustable)
BUCK1 Negative Current-Limit
Threshold (Fixed)
= V
CC
ILIM1 Input Bias Current
CS2 Input Bias Current
0 to 2V
-100
-1
+100
+1
nA
µA
0 to 28V
V
1.5
-
V
1.0
-
V
0.5
-
CC
CC
CC
ILIM2 Default Threshold
V
BUCK2 Current-Limit Threshold
(Fixed)
AGND - CS2; V
AGND - CS2; V
AGND - CS2; V
= V
40
40
50
50
60
mV
ILIM2
ILIM2
ILIM2
ILIM2
CC
= 0.5V
= 2.0V
60
240
-55
BUCK2 Current-Limit Threshold
(Adjustable)
mV
160
200
-72
BUCK2 Negative Current-Limit
Threshold (Fixed)
AGND - CS2; V
0 to 2V
= V
-90
mV
CC
ILIM2 Input Bias Current
-100
+100
nA
oC
Thermal-Shutdown Threshold
15°C hysteresis
160
V
Undervoltage Lockout
CC
Rising edge, hysteresis = 20mV
4.10
4.45
V
Ω
Ω
Threshold
DH1 Gate-Driver On-Resistance
BST1–LX1 forced to 5V (Note 4)
DL1 high state (pullup) (Note 4)
DL1 low state (pulldown) (Note 4)
1
1
4.5
4.5
2
DL1 Gate-Driver On-Resistance
0.35
DH1 Gate-Driver Source/Sink
Current
DH1 forced to 2.5V, BST–LX forced to 5V
1.5
A
DL1 Gate-Driver Sink Current
DL1 Gate-Driver Source Current
DL1 forced to 2.5V
5
1.5
35
26
2
A
A
DL1 forced to 2.5V
DL1 rising
Dead Time
ns
Ω
DH1 rising
DH2 Gate-Driver On-Resistance
DL2 Gate-Driver On-Resistance
BST2–LX2 forced to 5V (Note 4)
DL2 high state (pullup) (Note 4)
DL2 low state (pulldown) (Note 4)
8
8
3
2
Ω
0.7
_______________________________________________________________________________________
5
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
0.75
2.5
MAX
UNITS
DH2 Gate-Driver Source/Sink Current DH2 forced to 2.5V, BST2–LX2 forced to 5V
A
A
A
DL2 Gate-Driver Sink Current
DL2 Gate-Driver Source Current
DL2 forced to 2.5V
DL2 forced to 2.5V
DL2 rising
0.75
35
Dead Time
ns
nA
mA
DH2 rising
26
LINFB Input Bias Current
LINBSE Drive Current
V
V
V
V
V
= 1.035V
-100
+100
0.4
LINFB
LINFB
LINFB
LINBSE
LINBSE
= 1.05V, V
= 5V
LINBSE
= 0.965V, V
= 0.5V
20
0.988
-2.2
2.4
LINBSE
LINFB Regulation Voltage
LINFB Load Regulation
Logic Input High Voltage
Logic Input Low Voltage
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
= 5V, I
= 5V, I
= 4mA (sink)
1.000
-1.2
1.017
0.8
V
%
V
LINBSE
LINBSE
= 2mA to 10mA (sink)
D0–D4, SUS, PERF, LIN/SDN
D0–D4, SUS, PERF, LIN/SDN
V
DPSLP
0.8
-1
V
DPSLP
0.4
+1
V
D0–D4, SUS, PERF, LIN/SDN, DPSLP = 0V or 5V
µA
V
0.4
-
CC
Four-Level Logic V
Level
TON, S0, S1, GAIN logic input high level
V
CC
Four-Level Logic Float Level
Four-Level Logic REF Level
Four-Level Logic GND Level
TON, S0, S1, GAIN logic input upper midlevel
TON, S0, S1. GAIN logic input lower midlevel
TON, S0, S1, GAIN logic input low level
3.15
1.65
3.85
2.35
0.5
V
V
V
SKP1/SDN, SKP2/SDN, S0, S1,
GAIN, and TON Logic-Input Current GND or V
SKP1/SDN, SKP2/SDN, TON, S0, S1, GAIN forced to
-3
+3
µA
CC
SKP1/SDN, SKP2/SDN Skip Level
SKP1/SDN, SKP2/SDN PWM Level
SKP1/SDN, SKP2/SDN logic input high level
SKP1/SDN, SKP2/SDN logic input float level
2.8
1.4
V
V
2.2
0.4
SKP1/SDN, SKP2/SDN Shutdown
Level
SKP1/SDN, SKP2/SDN logic input low level
V
V
SKP1/SDN Test Mode Input Voltage
Range
To enable no-fault mode, 4.5V < V < 5.5V
CC
10.8
13.2
-8.0
Measured at FBS, OUT2, and FB2 with respect to
unloaded output voltage, falling edge, typical
hysteresis = 1%
PGOOD Lower Trip Threshold
-12.0
-10.0
-10.0
10.0
%
%
%
LINGOOD Lower Trip Threshold
and LINFB Undervoltage Protection
Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
-12.0
8.0
-8.0
Measured at FBS, OUT_, FB2 with respect to
unloaded output voltage, rising edge, typical
hysteresis = 1%
PGOOD Upper Trip Threshold
12.0
6
_______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V
= 5.0V,
UNITS
%
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
LIN/SDN
T
A
= 0°C to +85°C. Typical values are at T = +25°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5)
8.0
10.0
10
12.0
OUT_, FB2 forced 2% above or below PGOOD trip
threshold
PGOOD Propagation Delay
LINGOOD Turn-On Delay
LINGOOD Turn-Off Delay
µs
ms
µs
LINFB forced 2% above LINGOOD lower trip
threshold
1
LINFB forced 2% below LINGOOD lower trip
threshold
10
4
After the output-voltage transition on BUCK1 is
complete (PGOOD blanking is enabled for N + 4
clocks, blanking is excluded in startup and
shutdown)
PGOOD Transition Delay
Clk
After the output-voltage transition on BUCK1 is
Forced-PWM Mode Transition Delay complete (forced-PWM mode persists for N + 32
clocks for all transitions)
32
Clk
V
Open-Drain Output Low Voltage
I
= 3mA
0.4
SINK
(PGOOD, LINGOOD)
Open-Drain Leakage Current
(PGOOD, LINGOOD)
High state, forced to 5.5V
1
+0.1
2
µA
µA
mV
Input Current
OFS0–OFS2
-0.1
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with
OFS_ connected to REF
∆V
∆V
/ ∆V
/ ∆V
∆V
= (0.8V - 0V)
0.119
0.119
0.125
0.125
0.131
0.131
OUT
OUT
OFS,
OFS
OFS
OFS Gain
V/V
, ∆V
= (2.0V - 1.2V)
OFS
_______________________________________________________________________________________
7
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V
LIN/SDN
= 5.0V,
UNITS
V
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
28
TON = REF, open, or V
TON = GND
2
2
CC
Battery voltage V+
, V
Input Voltage Range
16
V
4.5
5.5
CC DD
DAC codes from 0.600V to
1.750V (MAX1816)
V+ = 4.5V to 28V, includes
load regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
BUCK1 DC Output-Voltage
Accuracy
-1.5
+1.5
%
DAC codes from 0.700V to
2.000V (MAX1994)
FB2 = GND
2.463
1.773
0.985
1.0
2.538
1.827
1.015
5.5
BUCK2 Error Comparator
Threshold (DC Output-Voltage
Accuracy) (Note 1)
V+ = 4.5V to 28V
FB2 = V
V
V
CC
FB2 = OUT2
OUT2 Adjust Range
GAIN = REF
GAIN = open
1.425
1.900
3.800
1.575
2.100
4.200
Voltage-Positioning Gain
V/V
GAIN = V
CC
Current-Sense Differential Input
Range (CS1+, CS1-)
200
300
200
mV
mV
mV
Remote-Sense Differential Input
Range (CS1+, FBS)
Remote-Sense Differential Input
Range (GDS, AGND)
CS1+, FBS Input Bias Current
CS1- Input Bias Current
-300mV < V
-100mV < V
- V
- V
< +300mV
-60
-60
-8
+60
+60
+8
µA
µA
CS1+
CS1+
FBS
< +100mV, V
= V
FBS
CS1-
CS1-
252kHz nominal; R
=143kΩ
TIME
TIME Frequency Accuracy
%
53kHz nominal to 530kHz nominal; R
= 680kΩ to 68kΩ
-12
230
165
320
465
630
495
495
740
+12
290
215
390
565
810
605
605
910
500
375
TIME
V+ = 5V, CS1- = 1.2V
V+ = 12V, CS1- = 1.2V
V+ = 5V, OUT2 = 2.5V
V+ = 12V, OUT2 = 2.5V
TON = GND (1000kHz)
TON = REF (550kHz)
TON = open (300kHz)
BUCK1 On-Time (Note 2)
ns
TON = V
(200kHz)
CC
TON = GND (715kHz)
TON = REF (390kHz)
TON = open (390kHz)
BUCK2 On-Time (Note 2)
Minimum Off-Time
ns
TON = V
(260kHz)
CC
TON = open, TON = V (Note 2)
CC
ns
TON = GND, TON = REF (Note 2)
Measured at V , with FBS, OUT2, FB2, and LINFB
CC
forced above the no-load regulation point
Quiescent Supply Current (V
)
CC
4500
µA
8
_______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V
LIN/SDN
= 5.0V,
UNITS
µA
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
V
= 0V, V
= 0V, V
= 5V;
SKP1/SDN
SKP2/SDN LIN/SDN
Partial Shutdown Supply Current
(Linear Regulator On Only)
measured at V , with FBS and LINFB forced above the
CC
no-load regulation point
750
V
= 5V, V
= 0V, V
= 5V;
SKP1/SDN
SKP2/SDN
LIN/SDN
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
measured at V , with FBS and LINFB forced above the
CC
no-load regulation point
3400
1400
µA
µA
V
= 0V, V
= 5V, V
= 0V;
SKP1/SDN
SKP2/SDN
LIN/SDN
Partial Shutdown Supply Current
(BUCK2 Only)
measured at V , with OUT2 and FB2 forced above the
CC
regulation point
Measured at V , with FBS, OUT2, and FB2 forced above
DD
Quiescent Supply Current (V
Quiescent Battery Current
)
5
µA
µA
µA
DD
the no-load regulation point, T = -40°C to +85°C
A
Measured at V+
40
10
V
= 0V, V
= -40°C to +85°C
= 0V, and V
= 0V, and V
= 0V,
= 0V,
SKP1/SDN
SKP2/SDN
LIN/SDN
Shutdown Supply Current (V
)
CC
T
A
V
= 0V, V
SKP2/SDN
SKP1/SDN
LIN/SDN
Shutdown Supply Current (V
)
5
5
µA
DD
T
A
= -40°C to +85°C
V
V
= V
= 0V, measured at V+, with
SKP1/SDN
SKP2/SDN
Shutdown Battery Current
Reference Voltage
µA
V
= V
= 0V or 5V, T = -40°C to +85°C
A
CC
DD
V
= 4.5V to 5.5V, I
= 0 to 50µA
= 50µA sourcing
REF
1.98
0
2.02
7
CC
REF
REF
I
I
Reference Load Regulation
Reference Sink Current
mV
µA
V
= 50µA to 100µA
0
7
REF in regulation
10
Voltage at OVPSET above which the OVP functions are
disabled for BUCK1 and BUCK2
V
-
V
-
CC
0.5
CC
OVPSET Disable Mode Threshold
1.5
OVPSET Default Mode Threshold Voltage at OVPSET below which the OVP thresholds are
0.4
0.6
V
V
for BUCK1
set to their default values
MAX1816
MAX1994
MAX1816
MAX1994
MAX1816
MAX1994
1.95
2.20
0.95
1.075
1.95
2.20
2.05
2.30
1.05
1.175
2.05
2.30
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS
V
= 1.0V,
OVPSET
measured at FBS
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold)
V
V
= 2.0V,
OVPSET
measured at FBS
Overvoltage Trip Threshold for
BUCK2
Measured at OUT2 (or FB2 if external feedback is used)
113
65
117
75
%
%
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage FBS and OUT2
(FB2 in external feedback)
_______________________________________________________________________________________
9
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
-
UNITS
V
-
V
CC
CC
ILIM1 Default Threshold
V
1.5
0.5
BUCK1 Current-Limit Threshold
(Fixed)
CS1+ - CS1-; V
= V
40
40
60
mV
mV
mV
V
ILIM1
CC
CS1+ - CS1-; V
CS1+ - CS1-; V
= 0.5V
= 2.0V
60
ILIM1
ILIM1
BUCK1 Current-Limit Threshold
(Adjustable)
160
240
BUCK1 Negative Current-Limit
Threshold (Fixed)
CS1+ - CS1-; V
AGND - CS2; V
= V
= V
-90
-55
ILIM1
CC
V
-
V
-
CC
0.5
CC
1.5
ILIM2 Default Threshold
BUCK2 Current-Limit Threshold
(Fixed)
40
60
mV
mV
mV
ILIM2
CC
AGND - CS2; V
AGND - CS2; V
= 0.5V
= 2.0V
40
60
ILIM2
ILIM2
BUCK2 Current-Limit Threshold
(Adjustable)
160
240
BUCK2 Negative Current-Limit
Threshold (Fixed)
AGND - CS2; V
= V
-90
-55
ILIM2
CC
V
Undervoltage Lockout
CC
Rising edge, hysteresis = 20mV
4.10
4.45
V
Threshold
DH1 Gate-Driver On-Resistance
BST1–LX1 forced to 5V (Note 4)
DL1 high state (pullup) (Note 4)
DL1 low state (pulldown) (Note 4)
BST2–LX1 forced to 5V (Note 4)
DL2 high state (pullup) (Note 4)
DL2 low state (pulldown) (Note 4)
4.5
4.5
2
Ω
Ω
Ω
Ω
DL1 Gate-Driver On-Resistance
DH2 Gate-Driver On-Resistance
DL2 Gate-Driver On-Resistance
8
8
3
V
V
V
V
= 1.05V, V
= 5V
0.4
LINFB
LINBSE
LINBSE Drive Current
mA
= 0.965V, V
= 0.5V
20
0.988
-2.2
2.4
LINFB
LINBSE
LINFB Regulation Voltage
LINFB Load Regulation
Logic Input High Voltage
Logic Input Low Voltage
Logic Input High Voltage
Logic Input Low Voltage
= 5V, I
= 5V, I
= 4mA (sink)
1.017
V
%
V
LINBSE
LINBSE
LINBSE
LINBSE
= 2mA to 10mA (sink)
D0–D4, SUS, PERF, LIN/SDN
D0–D4, SUS, PERF, LIN/SDN
DPSLP
0.8
0.4
V
0.8
V
DPSLP
V
V
0.4
-
CC
Four-Level Logic V
Level
TON, S0, S1, GAIN logic input high level
V
CC
Four-Level Logic Float Level
Four-Level Logic REF Level
Four-Level Logic GND Level
TON, S0, S1, GAIN logic input upper midlevel
TON, S0, S1, GAIN logic input lower midlevel
TON, S0, S1, GAIN logic input low level
3.15
1.65
3.85
2.35
0.5
V
V
V
10 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= 1.20V, V
= 2.50V, V
= V
= 5.0V, V
= V
= V = 5.0V,
LIN/SDN
OUT1
OUT2
CC
DD
SKP1/SDN
SKP2/SDN
T
A
= -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SKP1/SDN, SKP2/SDN Skip
Level
SKP1/SDN, SKP2/SDN logic input high level
SKP1/SDN, SKP2/SDN logic input float level
SKP1/SDN, SKP2/SDN logic input low level
2.8
1.4
V
SKP1/SDN, SKP2/SDN PWM
Level
2.2
0.4
V
V
SKP1/SDN, SKP2/SDN Shutdown
Level
Measured at FBS, OUT2, and FB2 with respect to unloaded
output voltage, falling edge, typical hysteresis = 1%
PGOOD Lower Trip Threshold
-12.5
-12.5
7.5
-7.5
%
LINGOOD Lower Trip Threshold
and LINFB Undervoltage
Protection Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
-7.5
12.5
12.5
%
%
%
Measured at FBS, OUT_, FB2 with respect to unloaded
output voltage, rising edge, typical hysteresis = 1%
PGOOD Upper Trip Threshold
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5)
7.5
1
LINGOOD Turn-On Delay
LINFB forced 2% above LINGOOD lower trip threshold
ms
V
Open-Drain Output Low Voltage
(PGOOD, LINGOOD)
I
= 3mA
0.4
2
SINK
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with OFS_
connected to REF
mV
V/V
∆V
∆V
/ ∆V
/ ∆V
, ∆V
, ∆V
= (0.8V - 0V)
0.119
0.119
0.131
0.131
OUT
OUT
OFS
OFS
OFS
OFS
OFS Gain
= (2.0V - 1.2V)
Note 1: DC output accuracy specifications for BUCK2 refer to the trip level of the error amp. The output voltage has a DC regulation
higher than the trip level by 50% of the ripple. In SKIP mode, the output rises by approximately 1.5% when transitioning from
continuous conduction to no load.
Note 2: On-time and minimum off-time specifications for both BUCK1 and BUCK2 are measured from 50% to 50% at the DH_ pin
with LX_ forced to zero, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate
capacitance. Actual in-circuit times can be different due to MOSFET switching speeds.
Note 3: This does not include the time for REF to start up if required.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin
QFN package.
Note 5: The LINGOOD signal is latched low under a fault condition of LINFB dropping below 90% or rising above 110% of the nomi-
nal set point. The LINGOOD signal does not go high again until the fault latch is reset.
Note 6: Specifications from -40°C to +100°C are guaranteed by design, not production tested.
______________________________________________________________________________________ 11
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
V +
T O N 2 4
P G O O D
3 7
3 8
3 9
B S T 2
L X 2
2 3
2 2
L I N / S D N
S K P 2 2 / 1 S D N
4 0 D H 2
2 0
S K P 1 / S D N
4 1
4 2
4 3
D L 2
D D
S 1 1 9
V
S 0
1 8
D 4 1 7
P G N D
4 4 D L 1
D 3
D 2
P E R F
1 6
1 5
4 5
4 6 D H 1
D 1 1 4
D 0
4 7
4 8
L X 1
B S T 1
1 3
Figure 1. Standard Application Circuit
12 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
V +
T O N 2 4
P G O O D
3 7
3 8
3 9
B S T 2
L X 2
2 3
2 2
L I N / S D N
T R I G
I L I M
C O M P
P O L
S K P 2 2 / 1 S D N
S K P 1 2 / 0 S D N
S 1 1 9
4 0 D H 2
4 1
4 2
4 3
D L 2
D D
G N D
L I M I T
V
S 0
V +
B S T
P G N D
D L
1 8
D 4 1 7
P G N D
4 4 D L 1
D 3
D 2
P E R F
1 6
1 5
4 5
4 6 D H 1
4 7 L X 1
D 1 1 4
D 0
1 3
4 8
B S T 1
Figure 2. High-Current Master-Slave Application Circuit
______________________________________________________________________________________ 13
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
EFFICIENCY vs. LOAD CURRENT
(BUCK2 V = 2.5V)
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK1)
EFFICIENCY vs. LOAD CURRENT
(BUCK1 V = 1.25V)
OUT2
OUT1
100
90
80
70
60
1.26
1.25
1.24
1.23
1.22
1.21
1.20
100
90
V
V
V
= 7V
IN
IN
IN
SKIP MODE
SKIP MODE
= 12V
= 20V
SKIP MODE
80
70
60
50
FORCED PWM
V
V
V
= 7V
IN
IN
IN
= 12V
= 20V
FORCED PWM
FORCED PWM
1
50
0.01
0.1
10
0
5
10
15
20
25
30
0.01
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK2)
FREQUENCY vs. LOAD CURRENT
(BUCK1 AND BUCK2)
FREQUENCY vs. INPUT VOLTAGE
(BUCK1 AND BUCK2)
2.58
2.56
2.54
400
300
200
100
0
400
350
BUCK2 PWM MODE
BUCK2 SKIP MODE
BUCK2 I
= 8A
OUT2
BUCK2 I
= 1A
OUT2
BUCK1 PWM MODE
BUCK1 SKIP MODE
SKIP MODE
BUCK1 I
= 20A
OUT1
300
250
2.52 FORCED PWM
BUCK1 I
= 3A
OUT1
2.50
0
2
4
6
8
10
0
5
10
15
20
5
10
15
INPUT VOLTAGE (V)
20
25
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
(BUCK1 AND BUCK2)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP MODE)
40
30
20
10
0
450
400
350
300
250
3000
2700
2400
2100
1800
1500
1200
900
I + I
CC DD
BUCK1
BUCK2 I
= 8A
OUT2
BUCK2
BUCK1 I
= 20A
OUT1
600
300
I+
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
5
10
15
INPUT VOLTAGE (V)
20
25
°
°
TEMPERATURE ( C)
TEMPERATURE ( C)
14 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PWM MODE)
BUCK1 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc11
50
I
+ I
CC DD
20A
0
A
40
30
20
10
0
I+
1.35V
1.25V
1.15V
B
20A
0
C
5
10
15
INPUT VOLTAGE (V)
20
25
20µs/div
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
BUCK1 LOAD TRANSIENT RESPONSE
(PWM MODE)
BUCK2 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc12
MAX1816 toc13
20A
0
2.6V
2.5V
2.4V
A
A
1.35V
1.25V
1.15V
B
10A
5A
0
B
20A
0
C
20µs/div
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
20µs/div
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
______________________________________________________________________________________ 15
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
BUCK1 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
BUCK2 LOAD TRANSIENT RESPONSE
(PWM MODE)
MAX1816 toc15
MAX1816 toc14
2V
1V
2.6V
2.5V
2.4V
A
A
0
10A
0
B
10A
5A
0
B
2V
0
C
100µs/div
20µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
BUCK1 STARTUP WAVEFORM
BUCK2 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
(PWM MODE, I
= 20A)
OUT1
MAX1816 toc16
MAX1816 toc17
2V
1V
4V
2V
A
A
0
0
20A
10A
10A
0
B
B
0
2V
0
2V
0
C
C
100µs/div
40µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
16 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
BUCK2 STARTUP WAVEFORM
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(PWM MODE, I
= 8A)
OUT2
(PWM MODE)
MAX1816 toc18
MAX1816 toc19
4V
2V
1.5V
A
A
0
1V
10A
B
10A
0
0
5V
B
C
0
2V
0
5V
C
D
0
40µs/div
100µs/div
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
V
= 1.40V TO 1.00V TO 1.40V
OUT1
OUT1
I
= 3A, R
= 143kΩ
TIME
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(SKIP MODE)
(SKIP MODE)
MAX1816 toc20
MAX1816 toc21
1.5V
1V
A
A
1V
0.5V
10A
10A
B
B
0
5V
0
5V
C
C
0
0
5V
5V
D
D
0
0
100µs/div
100µs/div
V
I
= 1.40V TO 1.00V TO 1.40V
V
I
= 1.00V TO 0.60V TO 1.00V
OUT1
OUT1
= 1A, R
= 143kΩ
= 1A, R
= 143kΩ
OUT1
TIME
OUT1
TIME
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: SUS SIGNAL, 5V/div
______________________________________________________________________________________ 17
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
BUCK1 SHUTDOWN WAVEFORM
BUCK1 SHUTDOWN WAVEFORM
(PWM MODE, I = 20A)
(SKIP MODE, NO LOAD)
OUT2
MAX1816 toc22
MAX1816 toc23
2V
1V
2V
1V
A
A
0
0
20A
10A
0
10A
0
B
B
-10A
5V
5V
0
C
C
0
100µs/div
100µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
OUTPUT OFFSET
vs. OFS INPUT VOLTAGE
200
BUCK1 OUTPUT-VOLTAGE DISTRIBUTION
(V = 1.25V, SAMPLE SIZE = 55)
OUT1
30
100
0
20
10
0
-100
UNDEFINED
REGION
-200
0
0.5
1.0
(V)
1.5
2.0
1.248
1.249
1.250
1.251
1.252
V
BUCK1 OUTPUT VOLTAGE (V)
OFS
18 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= V
= V
= V
= 5V; V
= 3.3V, V
= 1.25V,
OUT(BUCK1)
DD
CC
SKP1/SDN
SKP2/SDN
LIN/SDN
IN(LDO)
V
= 2.5V; T = +25°C, unless otherwise noted.)
OUT(BUCK2)
A
REFERENCE VOLTAGE DISTRIBUTION
LINEAR REGULATOR LINE REGULATION
LINEAR REGULATOR LOAD REGULATION
(V
REF
= 2.0V, SAMPLE SIZE = 55)
1.22
1.21
1.20
1.19
1.18
1.17
1.16
30
20
10
0
1.210
1.208
1.206
1.204
1.202
1.200
0
2
4
6
8
10
12
1.999
2.000
2.001
2.002
0.1
1
10
100
1000
INPUT VOLTAGE (V)
REFERENCE VOLTAGE (V)
LOAD CURRENT (mA)
LINEAR REGULATOR LOAD
TRANSIENT RESPONSE
LINEAR REGULATOR STARTUP WAVEFORM
MAX1816 toc30
MAX1816 toc29
5V
400mA
200mA
0
A
0
A
B
2V
1V
0
B
1.2V
400mA
200mA
C
1.19V
0
20µs/div
20µs/div
A: LOAD CURRENT, 200mA/div
B: OUTPUT VOLTAGE, 10mV/div, AC-COUPLED
A: V
, 5V/div
LIN/SDN
LIN
B: V = 1.2V, 1V/div
C: I = 300mA, 200mA/div
LIN
______________________________________________________________________________________ 19
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Pin Description
PIN
NAME
FUNCTION
BUCK1 Current-Limit Adjustment. The CS1+ - CS1- current-limit threshold defaults to 50mV if ILIM1 is
1
ILIM1
connected to V . In adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage
CC
at ILIM1. The logic threshold for switchover to the default value is approximately V - 1V.
CC
Integrator Time Constant Control Input. This pin allows the integrator to be compensated independent of
the voltage-positioning sense feedback path. Connect a 47pF to 1000pF capacitor from this pin to ground
to control the integration time constant.
2
3
CC
Positive Voltage-Positioning and Current-Sense Input for BUCK1. The current-limit sense voltage for
CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input. The CS1+ and CS1- inputs are also used for active
voltage positioning, with the voltage-positioning gain set with the GAIN pin. Connecting the GAIN pin to
ground disables voltage positioning. Positive and negative current limits are always active.
CS1+
Negative Voltage-Positioning and Current-Sense Input for BUCK1. CS1- is also the output sense input for
calculating TON. The current-limit sense voltage for CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input.
The CS1+ and CS1- inputs are also used for active voltage positioning, with the voltage-positioning gain
set with the GAIN pin. Connecting the GAIN pin to ground disables voltage positioning. Positive and
negative current limits are always active.
4
CS1-
Output Feedback Remote-Sense Input for BUCK1. Connect FBS directly to the load. FBS internally
connects to an amplifier that fine-tunes the output voltage, compensating for voltage drops from the
regulator output to the load.
5
6
FBS
Ground Remote-Sense Input for BUCK1. Connect GDS directly to the load. GDS internally connects to an
amplifier that fine-tunes the output voltage, compensating for voltage drops from the regulator ground to
the load ground.
GDS
Voltage-Positioning Gain Control. GAIN is a four-level logic input that selects the voltage-positioning gain
(see CS1+, CS1- pins). The gain setting does not affect current-limit functions. Connecting GAIN to GND
disables the voltage positioning by setting the gain to zero. Connecting GAIN to REF sets the gain to 1.5.
7
GAIN
Leaving GAIN open sets the gain to 2. Connecting GAIN to V
sets the gain to 4.
CC
GND = 0; REF = 1.5; open = 2; V
= 4.
CC
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
8
9
OFS0
OFS1
OFS2
SUS
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
10
11
Suspend Mode Control Input. The SUS signal causes the S0 and S1 inputs to take precedence over the
VID code setting and OFS inputs. When SUS is high, the state of the S0 and S1 inputs are decoded to
select the appropriate DAC code and the offset is forced to zero (see the DAC Inputs and Internal
Multiplexer section).
Deep Sleep Control Input. This logic control input goes to the offset selection multiplexer that determines
which, if any, offset control inputs are read (OFS0–OFS2). This input is compatible with 1.5V logic (see
Table 7).
12
13
DPSLP
D0
VID Code Input. D0 is the least significant bit (LSB).
20 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Pin Description (continued)
PIN
14
15
16
17
NAME
D1
FUNCTION
VID Code Input
VID Code Input
VID Code Input
D2
D3
D4
VID Code Input. D4 is the most significant bit (MSB).
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
18
19
S0
S1
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
Combined Shutdown and Skip-Mode Control Input for BUCK1. Always start BUCK2 before starting BUCK1.
Connect SKP1/SDN to V
or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
CC
PFM/PWM operation. Connect SKP1/SDN to GND or drive the pin below 0.5V to shut down BUCK1. In
shutdown mode, DL1 is forced to V in order to enforce overvoltage protection when the regulator is
DD
20
SKP1/SDN powered down. Leave SKP1/SDN floating for the low-noise forced PWM operation. Low-noise forced-PWM
mode causes the inductor current to reverse at light loads and suppresses pulse-skipping operation.
SKP1/SDN can also be used to disable both over- and undervoltage protection circuits and clear the fault
latch. This test mode is enabled by forcing the pin to 10.8V < V
< 13.2V. While in the test mode,
SKP1/SDN
the regulator performs the normal PFM/PWM operation. SKP1/SDN cannot withstand the battery voltage.
Combined Shutdown and Skip-Mode Control Input for BUCK2. Always start BUCK2 before starting BUCK1.
Connect SKP2/SDN to V
or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
CC
PFM/PWM operation. Connect SKP2/SDN to GND or drive the pin below 0.5V to shut down BUCK2. In
shutdown mode, DL2 is forced to V if the overvoltage protection is enabled. This is done in order to
enforce overvoltage protection even when the regulator is powered down. Leave SKP2/SDN floating for the
DD
21
SKP2/SDN
low-noise forced PWM operation. Low-noise forced-PWM mode causes the inductor current to recirculate
at light loads and suppresses pulse-skipping operation. If OVPSET = V , then DL2 is forced LOW in
CC
shutdown mode. SKP2/SDN cannot withstand the battery voltage.
Linear Regulator Shutdown Control Input. Connect LIN/SDN to V
or drive the pin above 2.4V to turn on
CC
the linear regulator. Connect LIN/SDN to GND or drive the pin below 0.8V to shut down the linear regulator.
In shutdown mode, LINBSE is forced to a high-impedance state preventing sufficient drive to the external
PNP power transistor in the regulator. LIN/SDN cannot withstand the battery voltage.
22
23
24
LIN/SDN
PGOOD
TON
Open-Drain Power-Good Output. PGOOD is forced low during power-up and power-down transitions on
BUCK1. In normal operation, if FBS and OUT2 (FB2) are in regulation, then PGOOD is high. PGOOD is
forced low when SKP1/SDN is low. If SKP2/SDN is low, OUT2 (FB2) does not affect PGOOD. Normally,
PGOOD is forced high for all VID transitions, and stays high for 4 TIME clock periods after the D/A count is
equalized. If OUT2 is enabled during these conditions and a fault occurs on BUCK2, then PGOOD goes
low. A pullup resistor on PGOOD causes additional finite shutdown current.
On-Time Selection Control Input. This four-level input sets the K factor that determines the DH on-time. The
TON times for BUCK2 are shifted to minimize beating between the two regulators. GND = 1000kHz
(BUCK1) and 715kHz (BUCK2), REF = 550kHz (BUCK1) and 390kHz (BUCK2), open = 300kHz (BUCK1)
and 390kHz (BUCK2), V
= 200kHz (BUCK1) and 260kHz (BUCK2).
CC
______________________________________________________________________________________ 21
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Pin Description (continued)
PIN
NAME
FUNCTION
Overvoltage Protection Control Input. This pin controls the OVP functions for BUCK1 and BUCK2. LINFB is
not affected by OVPSET. Connect OVPSET to V
to disable overvoltage protection for both BUCK1 and
CC
BUCK2. Connect OVPSET to GND for default overvoltage threshold of 2.0V (MAX1816) or 2.25V (MAX1994)
for BUCK1, measured at FBS. The OVP threshold for BUCK2 is always at 115% of the nominal output
voltage. The OVP threshold for BUCK1 can be adjusted by connecting OVPSET between 1.0V and 2.0V. An
25
OVPSET
overvoltage condition occurs if V
> V
(MAX1816) or V
> 1.125 × V
(MAX1994).
OVPSET
FBS
OVPSET
FBS
Undervoltage protection thresholds are always enabled and are not affected by this pin.
Slew Rate Adjustment Input. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
680kΩ to 68kΩ resistor to GND sets the clock from 53kHz to 530kHz, f = 252kHz × (143kΩ / R
26
27
TIME
).
TIME
SLEW
Linear Regulator Feedback Input. The linear regulator’s feedback set point is 1.0V. Connect a resistive
voltage-divider from the collector of the external PNP pass transistor to LINFB. The DC bias current in the
LINFB
voltage-divider should be greater than 10µA. The linear regulator is active whenever LIN/SDN is high.
Open-Drain Power-Good Output for the Linear Regulator. As soon as LINFB is in regulation, LINGOOD
goes high after a 1ms minimum delay. When the output goes out of regulation or LIN/SDN goes low,
LINGOOD is forced low within approximately 10µs. A pullup resistor on LINGOOD causes additional
shutdown current.
28
LINGOOD
Linear Regulator Base Drive. Connect LINBSE to the base of an external PNP power transistor. Add a 220Ω
pullup resistor between the base and the emitter.
29
30
LINBSE
AGND
Analog Ground. Connect the MAX1816/MAX1994s’ exposed backside pad and low-current ground
terminations to AGND. The current-limit comparator’s ground sense for BUCK2 also connects to AGND.
Analog Supply Voltage Input for BUCK1, BUCK2, and the Linear Regulator. This pin supplies all power to
31
32
V
the device except for the MOSFET drivers. The range for V is 4.5V to 5.5V. Bypass V
to GND with a
CC
CC
CC
minimum capacitance of 1µF. The maximum resistance between V
and V
should be 10Ω.
DD
CC
2.0V Reference Output. Bypass REF to GND with a minimum capacitance of 0.22µF. The reference is
trimmed with a nominal 50µA load, and can source a total of 100µA for external loads. Loading REF greater
or less than 50µA decreases output-voltage accuracy according to the limits defined in the Electrical
Characteristics table.
REF
Adjustable Feedback Input for BUCK2. In adjustable mode, FB2 regulates to 1.00V. It also selects default
33
34
FB2
voltage. Connect FB2 to GND for 2.5V output, or connect FB2 to V
for 1.8V output.
CC
Output Voltage Connection for BUCK2. Connect directly to the junction of the output filter capacitors. OUT2
senses the output voltage to determine the on-time and also serve as the feedback input in fixed-output
modes.
OUT2
Current-Sense Input for BUCK2. For accurate current limit, connect CS2 to a sense resistor between the
source of the low-side MOSFET and ground. Alternatively, CS2 can be connected to LX2 for lossless
current sensing across the low-side MOSFET. The current-limit sense voltage for CS2 is set at the ILIM2
35
36
CS2
BUCK2 Current-Limit Adjustment Input. The current-limit threshold measured between AGND and CS2
defaults to 50mV when ILIM2 is connected to V . In adjustable mode, the current-limit threshold voltage is
CC
precisely 1/10th of the voltage at ILIM2. The logic threshold for switchover to the default value is
ILIM2
approximately V
- 1V.
CC
Battery Voltage Sense Input. V+ is used only for PWM one-shot timing. DH1 and DH2 on-times are inversely
proportional to input voltage over a 2V to 28V range.
37
38
V+
BUCK2 Boost Flying Capacitor Connection. An optional resistor in series with BST2 allows the DH1 pullup
current to be adjusted.
BST2
22 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Pin Description (continued)
PIN
39
NAME
LX2
FUNCTION
BUCK2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
BUCK2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2.
40
DH2
BUCK2 Low-Side Gate-Driver Output. DL2 swings from PGND to V . DL2 is forced high when
DD
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL2 is forced high if
OVP is enabled, and is forced low if OVP is disabled.
41
DL2
Supply Voltage Input for DL1 and DL2 Gate Drivers. Connect V to the system supply voltage (4.5V to
DD
42
43
44
V
DD
5.5V). Bypass V
to PGND with a 2.2µF or greater ceramic capacitor.
DD
PGND
DL1
Power Ground. Ground connection for low-side gate drivers DL1 and DL2.
BUCK1 Low-Side Gate-Driver Output. DL1 swings from PGND to V . DL1 is forced high when
DD
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL1 is forced high.
Performance Mode Control Input. This logic-control input goes to the offset selection mux that determines
which, if any, offset control inputs are read (OFS0–OFS2). This input is compatible with 3.3V logic (see
Table 7).
45
PERF
46
47
DH1
LX1
BUCK1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1.
BUCK1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
BUCK1 Boost Flying Capacitor Connection. An optional resistor in series with BST1 allows the DH1 pullup
current to be adjusted.
48
BST1
5V Bias Supply (V
and V
)
CC
DD
Detailed Description
The MAX1816/MAX1994 require an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook computer’s 5V system supply.
Keeping the bias supply external to the IC improves effi-
ciency and eliminates the cost associated with the 5V
linear regulator that would otherwise be needed to sup-
ply the PWM controllers and gate drivers of BUCK1 and
BUCK2. If stand-alone capability is needed, the 5V sup-
ply can be generated with an external linear regulator.
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. The controllers
include a CPU regulator (BUCK1) that features a
dynamically adjustable output with offset control and a
programmable suspend mode voltage. This regulator is
capable of delivering very large currents at the high
efficiencies needed for leading-edge CPU core appli-
cations. A second step-down regulator (BUCK2) is
included to generate I/O or memory supplies. Both reg-
ulators employ Maxim’s proprietary Quick-PWM control
architecture. A linear-regulator controller is also includ-
ed for low-voltage auxiliary power supplies. All of the
regulators have independent shutdown control inputs.
The linear regulator includes a power-good output that
is independent of the combined power-good output for
BUCK1 and BUCK2.
The 5V bias supply must provide V
for the PWM con-
CC
troller’s internal reference, bias, and logic; and V
for
DD
the gate drivers. The maximum bias supply current is:
I
= I + f (Q + Q + Q + Q
)
G4
BIAS
CC
G1
G2
G3
= 20mA to 80mA (typ)
where I
is 2.2mA (typ), f is the switching frequency,
CC
G1
and Q , Q , Q , and Q are the total gate charge
G2
G3
G4
specifications at V = 5V in the MOSFET data sheets.
GS
V+ and V
can be connected if the input power source
DD
is a fixed 4.5V to 5.5V supply. If the 5V bias supply is
powered up prior to the battery supply, the enable signals
(SKP_/SDN) must be delayed until the battery voltage is
present to ensure startup.
______________________________________________________________________________________ 23
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Table 1. Component Selection for Standard Applications
BUCK1 (CIRCUITS OF
FIGURES 1 AND 2)
BUCK2 (CIRCUITS OF
FIGURES 1 AND 2)
COMPONENT
Input Voltage Range
Output Voltage
SLAVE (CIRCUIT OF FIGURE 2)
7V to 24V
7V to 24V
7V to 24V
0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994)
0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994)
2.5V
Output Current
Frequency
20A
7A
20A
300kHz
300kHz
300kHz
(2) N-channel
International Rectifier IRF7811W
N-channel
International Rectifier IRF7811W
(2) N-channel
International Rectifier IRF7811W
High-Side MOSFET
(2) N-channel
N-channel
(2) N-channel
International Rectifier IRF7822
Fairchild FDS7764A
International Rectifier IRF7822
Fairchild FDS7764A
International Rectifier IRF7822
Fairchild FDS7764A
Low-Side MOSFET
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
Input Capacitor
(3) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
(1) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
(3) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
Output Capacitor
0.6µH
1.2µH
0.6µH
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
Toko EH125C-1R2N
Sumida CDEP134H-1R2
Panasonic ETQP6F1R2BFA
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
Inductor
1mΩ 1%, 1W
Panasonic ERJM1WTJ1M0U
5mΩ 1%, 1W
Panasonic ERJM1WSF5M0U
1mΩ 1%, 1W
Panasonic ERJM1WTJ1M0U
Current-Sense Resistor
Table 2. Component Suppliers
SUPPLIER
CAPACITORS
Panasonic
PHONE
WEBSITE
847-468-5624
619-661-6835
408-573-4150
847-803-6100
www.panasonic.com
www.sanyovideo.com
Sanyo
Taiyo Yuden
TDK
www.t-yuden.com
www. tdk.com
INDUCTORS
Panasonic
847-468-5624
408-982-9660
www.panasonic.com
www.sumida.com
Sumida
MOSFETs
Fairchild Semiconductor
International Rectifier
Siliconix
888-522-5372
310-322-3331
203-268-6261
www.fairchildsemi.com
www.irf.com
www.vishay.com
24 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The on-times for BUCK1 have nominal frequency set-
tings of 200kHz, 300kHz, 550kHz, or 1000kHz, while the
on-times for BUCK2 are shifted to minimize beating
between the two regulators. The corresponding fre-
quency settings for BUCK2 are 260kHz, 390kHz,
390kHz, and 715kHz. The BUCK2 on-times for TON =
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
Both BUCK1 and BUCK2 employ Maxim’s proprietary
Quick-PWM control architecture. The control scheme is
a pseudo fixed-frequency, constant-on-time current-
mode type with voltage feed forward (Figures 3, 4, and
5). It relies on the output ripple voltage to provide the
PWM ramp signal. This signal can come from the out-
put filter capacitor’s ESR or a dedicated sense resistor.
The control algorithm is simple: the high-side switch on-
time is determined solely by a one-shot whose period is
inversely proportional to input voltage and directly pro-
portional to output voltage. Another one-shot sets a
minimum off-time (425ns, typ). The on-time one-shot is
triggered if the error comparator is low, the low-side
switch current is below the current-limit threshold, and
the minimum off-time one-shot has timed out.
open and TON = V
are shifted down to improve the
CC
efficiency. The BUCK2 on-times for TON = GND and
TON = REF are shifted up to avoid beating, yet maintain
the efficiency. The latter settings were not shifted down
because the resulting frequencies would be too high.
The on-time one-shot has good accuracy at the operat-
ing points specified in the Electrical Characteristics
( 10% at 200kHz and 300kHz, 12.5% at 550kHz and
1000kHz for BUCK1). On-times at operating points far
removed from the conditions specified in the Electrical
Characteristics can vary over a wider range.
For example, the 1000kHz setting typically runs about
10% slower with inputs much greater than 5V due to the
very short on-times required.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time (Figures 4 and 5). This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltages. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: first, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output-voltage ripple:
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external high-
side MOSFETs. Resistive losses, including the inductor,
both MOSFETs, output capacitor ESR, and PC board
copper losses tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only in PWM mode (SKP_/SDN =
open) and during dynamic output-voltage transitions
(BUCK1) when the inductor current reverses at light or
negative load currents. With reversed inductor current,
the inductor’s EMF causes LX to go high earlier than
normal, extending the on-time by a period equal to the
DH_ low-to-high dead time.
On-Time = K (V
+ 0.075V) / V
IN
OUT
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate for the
expected drop across the low-side MOSFET switch
(Table 3).
Table 3. Approximate K-Factor Errors
BUCK1
K-FACTOR
(µs)
BUCK1
FREQUENCY
(kHz)
BUCK1
K-FACTOR ERROR
(%)
BUCK2
K-FACTOR
(µs)
BUCK2
FREQUENCY
(kHz)
BUCK2
K-FACTOR
ERROR (%)
TON
GND
Open
REF
1.0
1.8
3.3
5.0
1000
550
300
200
12.5
12.5
10
1.4
715
390
390
260
12.5
10
2.56
2.56
3.84
10
V
10
10
CC
______________________________________________________________________________________ 25
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
INPUT
7V TO 24V
5V BIAS
SUPPLY
V+
V
V
DD
REF
MAX1816
MAX1994
CC
REF
2V REF
BUCK2
SKP1/SDN
SKP2/SDN
LIN/SDN
AGND
LIN/SDN
BST2
DH2
BST1
DH1
BUCK1
V+
V+
DH1
DL1
DH2
I_OFFSET
I_OFFSET
V
OUT2
2.5V
V
OUT1
LX1
DAC
BITS
DAC
BITS
LX2
DD
V
REF
DL1
DL2
CS2
REF
REF
DL2
CS2
PGND
TON1
TON2
TON1
TON2
GAIN
GAIN
CS1+
CS1-
CS1+
CS1-
OVPEN
OVPEN
OVPEN
FBS
FBS
GDS
GDS
OUT2
FB2
OUT2
FB2
ILIM1
CC
ILIM1
CC
SKP1/SDN
PGOOD1
SKP2/SDN
PGOOD2
REF
REF
ILIM2
ILIM2
P GOOD
PRESENT-STATE
DAC BITS
REGISTER
PGOOD
DAC BITS
ON-TIME
SELECTOR
5
TON
5
TON1
TON2
TON1
N.C.
TON2
VID MUX
VID ROM
X
D0-D4
S0-S1
DAC
X = Y
D0–D4
INPUTS
MUX
OUT
BITS
BITS
OUT
5
2
OSCILLATOR
Y
TIME
IN
5
5
FOUR-LEVEL
DECODE
REGISTER
RTIME
DIGITAL
SUSPEND
INPUTS
COMPARATOR
VID0–VID4
SUS
OSC OUT
5
CLOCK
UP/DOWN
COUNTER
SUS
X > Y
X < Y
DOWN
SUS
DAC BITS
DAC
BITS OUT
OFS
CONTROL
STATE
PERF
DPSLP
UP
CONTROL
INPUTS
PERF
DPSLP MACHINE
LINGOOD
LINGOOD
OFS_SEL
3.3V
BIAS SUPPLY
OFFSET CONTROL
INPUT
OFFSET
CONTROL
FAULTLR
SEL
I_OFFSET
3
I_OFFSET
OFS0–OFS2
FAULT
LINBSE
LINFB
THRESHOLD
CONTROL
LIN/SDN
LINEAR
REG
0Ω
V
LIN
OVPSET
OVPSET
OVPEN
PGND
AGND
Figure 3. Functional Diagram
26 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
V+
OUT1
TON1
TO DH1 DRIVER
INPUT
Q
Q
TRIG
ON-TIME
COMPUTE
TOFF
TO DL1 DRIVER
INPUT
ONE-SHOT
S
R
TON ONE-SHOT
Q
S
R
Q
TRIG
Q
ZERO CROSSING
ILIM1
∑
8.6R1
ERROR
AMPLIFIER
∑
REF
CC
0.4R1
R1
70kΩ
10kΩ
GM
I_OFFSET
FBS
10kΩ
10kΩ/A
10kΩ/A
VPS
VPS
DAC
AMPLIFIER
CS1+
CS1-
REF - 10%
REF + 10%
10kΩ
GAIN-
STATE
DECODER
GAIN
R-2R
DAC
GND
GDS
PGOOD1
I_GDS
GM
OVP/UVP
DETECTOR
ON/OFF
CONTROL
TIMER
RESET
OUT
SKP1/SDN
FBS
OVPEN
OVPEN
DAC BITS
Figure 4. BUCK1 PWM Control Diagram
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency is:
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V is
DROP2
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and t
ed by the MAX1816/MAX1994.
V
+ V
DROP1
OUT
f =
is the on-time calculat-
ON
t
(V + V
)
ON IN
DROP2
______________________________________________________________________________________ 27
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
V+
OUT2
TON2
TO DH2 DRIVER
INPUT
Q
Q
TRIG
TOFF
ONE-SHOT
ON-TIME
COMPUTE
TO DL2 DRIVER
INPUT
S
R
TON ONE-SHOT
Q
S
R
Q
TRIG
Q
ZERO CROSSING
CS2
GND
ILIM2
∑
ERROR
AMPLIFIER
REF
OUT2
DUAL-MODE FEEDBACK MUX
FIXED 1.5V
FIXED 1.8V
REF - 10%
REF + 10%
R
R
FB2
PGOOD2
1V
2V
OVP/UVP
DETECTOR
ON/OFF
CONTROL
TIMER
RESET
OVPEN
OUT
SKP2/SDN
OVPEN
Figure 5. BUCK2 PWM Control Diagram
The differential input voltage range for the amplifier is at
least 60mV total, including DC offset and AC ripple.
The integration time constant can be easily set with a
capacitor at the CC pin. Use a capacitance of 47pF to
1000pF (47pF typ). The transconductance of the ampli-
fier is 80µS (typ).
BUCK1 Integrator
BUCK1 includes a transconductance integrator (Figure
4) that provides a fine adjustment to the output regula-
tion point. The integrator forces the DC average of the
feedback voltage to equal the VID DAC setting. The cir-
cuit has the ability to lower the output voltage by 3%
and raise it by 3%.
28 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
is not allowed to initiate a new cycle. The actual peak
current is greater than the current-limit threshold by an
amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the sense resistance, induc-
tor value, and battery voltage.
BUCK1 Differential Remote-Sense
Amplifier (FBS, GDS)
The MAX1816/MAX1994 include differential remote-
sense inputs to eliminate the effect of voltage drops
down the PC board traces and through the processor’s
power leads. The FBS and GDS inputs enable true differ-
ential remote sense of the load voltage. The two inputs
measure the voltage directly across the load to provide a
signal that is summed with the feedback signals that set
the voltage-positioned output. Connect the feedback
sense input (FBS) directly to the positive load terminal
and connect the ground sense input (GDS) directly to
the negative load terminal. Modern microprocessors now
There is also a negative current limit that prevents
excessive reverse inductor currents when V
sinking current in PWM mode.
is
OUT1
The negative current-limit threshold is set to approxi-
mately 140% of the positive current limit and therefore
tracks the positive current limit when ILIM1 is adjusted.
The GAIN pin controls the voltage-positioning gain. The
slope of the output voltage as a function of load current
is set by measuring the output current with a sense
include dedicated V
and ground-sense pins to
CC
facilitate the measurement of the chip’s supply voltage.
BUCK1 Voltage-Positioning and
Current-Sense Inputs (CS1+, CS1-)
resistor (R
) in series with the inductor. An ampli-
SENSE
fied version of this signal is fed back into the loop to
decrease the output voltage. The required offset is
added through the OFS0–OFS2 inputs (see the BUCK1
Output-Voltage Offset Control section). The exact rela-
tionship for the output of BUCK1 can be described with
the following equation:
The CS1+ and CS1- pins are differential inputs that
measure the voltage drop across the sense resistor of
BUCK1 for current-limiting, zero-crossing detection and
active voltage positioning (Figure 4). The current-limit
threshold is adjusted with an external resistive voltage-
divider at ILIM1. A 10µA (min) divider current is recom-
mended. The current-limit threshold adjustment range
is from 25mV to 250mV. In adjustable mode, the cur-
rent-limit threshold is precisely 1/10th of the voltage at
ILIM1. The default current limit is 50mV when ILIM1 is
V
OUT1
= V
- A
× (V
- V
) + V × SF
CS1- OS
SET
VPS
CS1+
where V
is the programmed output voltage (see
is the offset voltage generated
SET
Tables 5 and 6), V
OS
from the selected OFS_ pin, SF is a scale factor (0.125)
for the offset voltage, and A is the differential volt-
connected to V . The logic threshold for switchover to
CC
VPS
the default value is approximately V
- 1V.The default
CC
age-positioning gain set with the GAIN pin.
current limit accommodates the low voltage drop
expected across the sense resistor.
Since V - V = I × R , substituting the
CS1+
CS1-
LOAD
SENSE
differential sense voltage yields:
The current-limit circuit of BUCK1 employs a unique
“valley” current-sensing algorithm (Figure 6). If the
magnitude of the current-sense voltage between CS1+
and CS1- is above the current-limit threshold, the PWM
V
OUT1
= V - A × I
× R + V × SF
SENSE OS
SET
VPS
LOAD
The GAIN pin is a four-level logic input. When GAIN is
set to GND, REF, open, and V , the differential volt-
CC
age gains are 0, 1.5, 2, and 4, respectively. Grounding
GAIN disables the voltage-positioning function but
does not disable the current limit.
I
PEAK
BUCK2 Current-Sense Input (CS2)
BUCK2 uses the voltage at the CS2 pin to estimate the
inductor current and determine the zero crossing for
controlling pulse-skipping operation (Figure 5).
Connect CS2 to the current-sense resistor (Figure 1) for
the best possible current-limit accuracy. However, the
improved accuracy is achieved at the expense of the
additional power loss in the sense resistor. CS2 can be
connected to LX2 for lossless current sensing. In this
case, the trade-off is that the current limit becomes
I
I
LOAD
LIMIT
0
TIME
dependent on the low-side MOSFET’s R
with its
DS(ON)
inherent inaccuracies and thermal drift.
Figure 6. “Valley” Current-Limit Threshold Point
_______________________________________________________________________________________ 29
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Like BUCK1, the current-limit circuit of BUCK2 also
employs “valley” current sensing (Figure 6). If the magni-
tude of the current-sense voltage at CS2 is above the
current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit character-
istic and maximum load capability are a function of the
sense resistance, inductor value, and battery voltage.
rent can be 20mA to 80mA total for both BUCK1 and
BUCK2, depending on the external MOSFETs and
switching frequency.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
providing sink-current capability for dynamic-output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback trans-
former or coupled inductor. BUCK1 uses PWM mode
during all output transitions, while the slew-rate con-
troller is active and for 32 clock cycles thereafter.
There is also a negative current limit that prevents
excessive reverse inductor currents when V
is
OUT2
sinking current in PWM mode. The negative current-
limit threshold is set to approximately 140% of the posi-
tive current limit and therefore tracks the positive
current limit when ILIM2 is adjusted.
Automatic Pulse-Skipping Mode
In skip mode (SKP_/SDN = high), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation
(also known as the “critical conduction” point).
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM2. A 10µA (min) divider
current is recommended. The current-limit threshold
adjustment range is from 25mV to 250mV. In adjustable
mode, the current-limit threshold voltage is precisely
1/10th of the voltage at ILIM2. The threshold defaults to
50mV when ILIM2 is connected to V . The logic
CC
In low duty-cycle applications, this threshold is relative-
ly constant, with only a minor dependence on battery
voltage.
threshold for switchover to the 50mV default value is
approximately V
- 1V. The default current limit
CC
accommodates the low voltage drop expected across
the sense resistor.
KV
V
− V
OUT_
IN OUT_
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS2. Because CS2 is not a
real differential current-sense input, minimize the return
impedance from the sense resistor to the power ground
to reduce voltage errors when measuring the current.
I
=
×
LOAD_(SKIP)
2L_
V
IN
where K is the on-time scale factor (Table 3). The load
current level at which PFM/PWM crossover occurs,
I , is equal to 1/2 the peak-to-peak ripple cur-
LOAD(SKIP)
rent, which is a function of the inductor value (Figure 7).
For example, in the standard application circuit with K
In Figure 1, the Schottky diode (D2) provides a current
path parallel to the Q4/R2 current path. Accurate cur-
rent sensing demands D2 to be off while Q4 conducts.
Avoid large current-sense voltages. The combined volt-
age across Q4 and R2 can cause D2 to conduct. If very
large sense voltages are used, connect D2 directly
from Q4’s source to drain.
= 3.3µs (Table 3), V
= 1.25V, V = 12V, and L1 =
IN
OUT1
0.68µH, switchover to pulse-skipping operation occurs
at I = 2.7A. The crossover point occurs at an
LOAD1
even lower value if a swinging (soft-saturation) inductor
is used.
The switching waveforms can appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response, especially at low-input-voltage levels.
Forced-PWM Mode
BUCK1 and BUCK2 operate in forced-PWM mode
when SKP1/SDN and SKP2/SDN are unconnected. The
low-noise forced-PWM mode disables the zero-cross-
ing comparator, allowing the inductor current to reverse
at light loads. This causes the low-side gate-drive
waveform to become the complement of the high-side
gate-drive waveform. This in turn causes the inductor
current to reverse at light loads while DH_ maintains a
duty factor of V
/V . The benefit of forced-PWM
OUT_ IN
mode is to keep the switching frequency fairly constant,
but it comes at a cost: the no-load 5V bias supply cur-
30 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The 1ms (min) LINGOOD delay is necessary to allow
the PLLs in the CPU to power up and stabilize before
turning on the main regulator. The delay time is com-
∆i
∆t
V
- V
BATT OUT
=
L
I
PEAK
puted based on 1024 R
clock cycles. As such, the
TIME
TIME
delay varies based on the R
period.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving mod-
erate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
I
= I
/2
LOAD PEAK
V
- V
_ differential exists. Two adaptive dead-time
IN
OUT
circuits monitor the DH_ and DL_ outputs and prevent
the opposite side FET from turning on until DL_ or DH_ is
fully off. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET gates
for the adaptive dead-time circuits to work properly.
Otherwise, the sense circuitry in the MAX1816/MAX1994
interprets the MOSFET gate as “off” while there is actual-
ly still charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50 mils to 100 mils wide if
the MOSFET is 1in from the MAX1816/MAX1994).
0
ON-TIME
TIME
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
DC output accuracy specifications for BUCK2 refer to
the threshold of the error comparator. When the induc-
tor is in continuous conduction, BUCK2 output voltage
has a DC regulation level higher than the trip level by
50% of the ripple. In discontinuous conduction
(SKP2/SDN = high, light-loaded), BUCK2 output volt-
age has a DC regulation level higher than the error-
comparator threshold by approximately 1.5% due to
slope compensation.
The internal pulldown transistor that drives DL_ low is
robust, with a very low pulldown resistance. For DL1,
this resistance is 0.35Ω (typ), while the resistance for
DL2 is slightly higher at 0.7Ω (typ). This helps prevent
DL_ from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs can cause
excessive gate-drain coupling, which can lead to effi-
ciency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series
with BST_, which increases the turn-on time of the high-
side FET without degrading the turn-off time (Figure 8).
Note that BUCK1 automatically enters forced-PWM
mode during all output voltage transitions and stays in
forced-PWM mode until the transition is completed and
for 32 clock cycles thereafter. The reason for that is the
forced-PWM operation provides current sinking capa-
bility required during output-voltage transitions.
Linear-Regulator Controller
The linear-regulator controller of the MAX1816/MAX1994
is an analog gain block with an open-drain N-channel
output. It drives an external PNP pass transistor with a
220Ω base-to-emitter resistor (Figure 1). The controller
is guaranteed to provide at least 20mA sink current. The
linear regulator is typically used to provide a
1.2V/500mA VID logic supply. The controller is designed
to be stable with an output capacitor of 10µF or more.
+5V
V
BATT
5Ω TYP
LX_
The output voltage can be adjusted with a resistive volt-
age-divider between the linear regulator output and
analog ground with the center tap connected to LINFB.
The set point of LINFB is 1.0V. The regulator is enabled
when LIN/SDN is high. As soon as LINFB is in regula-
tion, the open-drain power-good output LINGOOD goes
high after a 1ms (min) delay. When the output goes out
of regulation or LIN/SDN goes low, LINGOOD is forced
low within approximately 10µs.
DH_
BST_
MAX1816
MAX1994
Figure 8. Reducing the Switching-Node Rise Time
______________________________________________________________________________________ 31
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The PGOOD output goes low if FBS or OUT2 (FB2) is
outside a window of 10% about the nominal set point
(see the DAC Inputs and Internal Multiplexers and
Adjusting BUCK2 Output Voltage sections).
SDN
Shutdown Control (SKP1/
,
SDN SDN
SKP2/
, and LIN/
)
If BUCK2 is used, always start BUCK2 before starting
BUCK1. When SKP1/SDN goes below 0.5V, BUCK1
enters low-power shutdown mode. PGOOD goes low
immediately. The output voltage ramps down to zero in
PGOOD is forced low when SKP1/SDN is low. If
SKP2/SDN is low, then OUT2 (FB2) does not affect
PGOOD. Normally, PGOOD is forced high during all
VID transitions, and stays high for 4 clock periods after
the DAC count is equalized. If BUCK2 goes out of regu-
lation during these conditions, then PGOOD goes low
as a consequence. A pullup resistor on PGOOD caus-
es additional finite shutdown current.
25mV steps at the clock rate set by R
. Thirty-two
TIME
clocks after the DAC reaches the zero setting, DL1 is
forced to V , and DH1 is forced low. When SKP1/SDN
DD
goes above 1.4V or floats, the DAC target is evaluated
and switching begins. The slew-rate controller ramps
up from zero in 25mV steps to the selected DAC code
value. There is no traditional soft-start (variable current-
limit) circuitry, so full output current is available immedi-
ately. Floating SKP1/SDN causes BUCK1 to operate in
low-noise forced-PWM mode. Forcing SKP1/SDN
above 2.8V enables skip mode operation.
The following conditions must all be met for PGOOD to
go high:
•
•
•
V
must be above UVLO.
CC
SKP1/SDN must be greater than 1.4V or unconnected.
When SKP2/SDN goes below 0.5V, BUCK2 enters shut-
The output of BUCK1 must be within a window of
10% about the nominal set point.
down mode. In shutdown mode, DL2 is forced to V
if
DD
overvoltage protection is enabled. If OVPSET is con-
•
PGOOD is forced high during DAC code transitions
nected to V , overvoltage protection is disabled and
CC
of BUCK1. The “blanking” period persists for N+4
DL2 is forced low in shutdown mode.
R
TIME
clock cycles. Blanking does not occur during
When LIN/SDN goes below 0.8V, the linear regulator of
the MAX1816/MAX1994 enters shutdown mode. In
shutdown mode, LINBSE is forced to a high-impedance
state preventing sufficient drive to the external PNP
pass transistor in the regulator. LINGOOD is forced low
within 10µs (typ) when LIN/SDN goes low. Forcing
LIN/SDN above 2.4V turns on the linear regulator.
power-up and power-down.
•
•
If SKP2/SDN is not low, then OUT2 (FB2) must be
within a window of 10% about the nominal set point.
When enabled, a fault on OUT2 overrides the blank-
ing on BUCK1.
LINGOOD is an open-drain power-good output for the
linear regulator. LINGOOD goes high at least 1ms after
the internal comparator signals that the output is in reg-
ulation. In normal operation, if the internal comparator
signals that the circuit is out of regulation, LINGOOD
goes low within approximately 10µs (typ). If LIN/SDN
goes low, LINGOOD is immediately forced low.
Power-On Reset
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and preparing
the MAX1816/MAX1994 for operation. V undervoltage
CC
lockout (UVLO) circuitry inhibits switching, forces
PGOOD low, and forces the DL1 gate driver high (to
enforce output overvoltage protection). The DL2 gate
Note that all three regulators are forced off when a fault is
detected. DL_ are forced high, DH_ are forced low, and
the linear regulator is turned off. (See the Output
Overvoltage Protection, Output Undervoltage Protection,
UVLO, and Thermal Fault Protection sections).
driver is also forced high if OVP is enabled. When V
CC
rises above 4.25V, the DAC inputs are sampled and the
output voltage begins to slew to the DAC setting. For
automatic startup, the battery voltage should be present
before V . If the MAX1816/MAX1994 attempt to bring
CC
DAC Inputs and Internal
Multiplexers (SUS)
the output into regulation without the battery voltage
present, the fault latch will trip. Toggling any of the shut-
down control pins resets the fault latch.
The MAX1816/MAX1994 have a unique internal VID input
multiplexer (mux) that can select one of two different VID
DAC code settings for different processor states. When
the logic level at SUS is low, the mux selects the VID DAC
code settings from the D0–D4 inputs (Table 5). Do not
leave D0–D4 floating—use 100kΩ pullup resistors if the
inputs float. When SUS is high, the suspend mode mux
selects the VID DAC code settings from the S0/S1 input
decoder. The outputs of the decoder are determined by
Power Valid Outputs
(PGOOD and LINGOOD)
PGOOD is an open-drain power-good output. Table 4
describes the behavior of PGOOD with respect to the
logic inputs. Window comparators on FBS and OUT2
(FB2) control the PGOOD output. If BUCK1 and BUCK2
are in regulation then PGOOD is high, except during
power-up and power-down.
32 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Table 4. BUCK1 and BUCK2 Operating Mode Truth Table
OVP
X
SKP1/SDN SKP2/SDN
GND
DL1
DL2
Switching
HIGH
MODE
PGOOD
V
HIGH
BUCK2
LOW
CC
Enabled
Disabled
Enabled
Disabled
X
V
V
GND
GND
GND
GND
Switching
Switching
HIGH
BUCK1
Monitor BUCK1 only
Monitor BUCK1 only
LOW
CC
CC
LOW
BUCK1
GND
GND
HIGH
Shutdown
Shutdown
HIGH
LOW
LOW
V
V
Switching
Switching
Switching
Switching
Switching
HIGH
Both in skip mode
Monitor both
CC
CC
Enabled
Disabled
X
>10.8V
>10.8V
>10.8V
GND
GND
BUCK1 no-fault test mode
BUCK1 no-fault test mode
No-fault test mode
Monitor BUCK1 only
Monitor BUCK1 only
Monitor both
LOW
V
Switching
CC
Switching in
forced PWM
mode
X
>10.8V
Float
GND
GND
Switching
No-fault test mode
Monitor both
Switching in
forced PWM
mode
BUCK1 in forced PWM
mode
Enabled
Float
Float
Float
Float
GND
HIGH
Monitor BUCK1 only
Monitor BUCK1 only
Monitor both
Switching in
forced PWM
mode
BUCK1 in forced PWM
mode
Disabled
LOW
Switching in
forced PWM
mode
BUCK1 in forced PWM
mode, BUCK2 in skip
mode
X
X
X
V
Switching
CC
Switching in
forced PWM
mode
Switching in
forced PWM
mode
BUCK1 and BUCK2 in
forced PWM Mode
Float
Float
Float
Monitor both
Switching in
forced PWM
mode
BUCK1 off, BUCK in
forced PWM mode
HIGH
LOW
Switching in
forced PWM
mode
BUCK1 in skip mode,
BUVK2 in forced PWM
mode
X
V
Switching
Monitor both
CC
V
float
or
V
float
or
CC
CC
Enabled
HIGH
HIGH
HIGH
HIGH
OVP and UVP faults
UVP faults only
LOW
LOW
V
float
or
V
float
or
CC
CC
Disabled
X = Don’t care.
inputs S0 and S1, which are four-level digital inputs
(Table 6). All code transitions (even those asking for the
exact same code) activate the slew-rate controller. In
other words, up-going or down-going transitions from one
code to another, soft-start and soft-stop are all handled in
the same way.
BUCK1 Output-Voltage Offset Control
DPSLP,
The MAX1816/MAX1994 support three independent off-
sets to the voltage-positioned load line. The offsets are
adjusted using resistive voltage-dividers at the
OFS0–OFS2 inputs (see Figure 10). For inputs from 0 to
0.8V, a negative offset is added to the output that is
(SUS, PERF,
and OFS_)
______________________________________________________________________________________ 33
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Table 5. Output Voltage vs. DAC Codes
Table 6. Output Voltage vs. Suspend
Mode DAC Codes
V
(V)
V
(V)
OUT
OUT
D4
D3
D2
D1
D0
MAX1816
MAX1994
V
(V)
OUT
S1
S0
MAX1816/MAX1994
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
2.000
1.950
1.900
1.850
1.800
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
No CPU
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
No CPU
GND
GND
GND
GND
REF
GND
REF
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
OPEN
V
CC
GND
REF
REF
REF
OPEN
REF
V
CC
OPEN
OPEN
OPEN
OPEN
GND
REF
OPEN
V
CC
V
V
V
V
GND
REF
CC
CC
CC
CC
OPEN
V
CC
The regions of the transfer function below zero, above
2.0V, and between 0.8V and 1.2V are undefined. OFS
inputs are disallowed in these regions, and the respec-
tive effects on the output are not specified.
The offset control inputs are selected using a combina-
tion of the three logic inputs (SUS, PERF, and DPSLP),
which also define the operating mode for the
MAX1816/MAX1994. Table 7 details which OFS input is
selected based on these control inputs.
BUCK1 Output-Voltage Transition Timing
The MAX1816/MAX1994 are designed to perform out-
put voltage transitions in a controlled manner, automati-
cally minimizing input surge currents. This feature
allows the regulator to perform nearly ideal transitions,
guaranteeing just-in-time arrival at the new output volt-
age level with the lowest possible peak currents for a
given output capacitance.
equal to 1/8th the voltage appearing at the selected
). For inputs from
1.2V to 2V, a positive offset is added to the output that
is equal to 1/8th the difference between the reference
voltage and the voltage appearing at the selected OFS
Modern mobile CPUs operate at multiple clock frequen-
cies that require multiple VID settings. It is common
when transitioning from one clock frequency to another
for the CPU to go into a low-power state before chang-
ing the output voltage and clock frequency. The change
must be accomplished within a fixed time interval—often
less than 100µs.
OFS input (∆V
= -0.125 × V
OFS_
OUT
input (∆V
= 0.125 × (V
- V
)). With this
OFS_
OUT
REF
scheme, both positive and negative offsets can be
achieved with a single voltage-divider. The piecewise
linear transfer function is shown in Figure 9.
34 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The output voltage transition is performed in 25mV steps,
UNDEFINED
preceded by a 4µs delay and followed by one additional
clock period. The total time for a transition depends on
0.15
R , the voltage difference, and the accuracy of the
TIME
MAX1816/MAX1994s’ slew-rate clock, and is not depen-
dent on the total output capacitance. The greater the out-
put capacitance, the higher the surge current required
for the transition. The MAX1816/MAX1994 automatically
control the current to the minimum level required to com-
plete the transition in the calculated time. As long as the
surge current is less than the current limit set by ILIM1,
the transition time is given by:
0.10
0.05
0
-0.05
-0.10
-0.15
V
− V
NEW
25mV
1
OLD
t
≤ 4µs +
1+
SLEW
f
0
0.5
0.8 1.0 1.2
1.5
2.0
SLEW
OFS_ INPUT VOLTAGE (V)
where f
= 252kHz × 143kΩ / R
, V
is the
OLD
SLEW
TIME
original DAC setting, and V
is the new DAC setting.
NEW
Figure 9. Offset-Control Transfer Function
See Time Frequency Accuracy in the Electrical
Characteristics table for f accuracy. The practical
SLEW
range of R
is 68kΩ to 680kΩ, corresponding to
TIME
REF OR V
REF OR V
OUT1
OUT1
1.9µs to 19µs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transi-
tions relatively smooth. The average inductor current
required to make an output voltage transition is:
OFS0
OFS1
OFS2
I ≅ C
✕
✕ f
SLEW
L
OUT
25mV
OFS0
OFS1
The slew-rate controller also performs a soft-start and
soft-stop function. The soft-start function works by
counting up from zero, in order to minimize turn-on
surge currents. The soft-stop executes this process in
reverse, eliminating the negative output voltages and
the need for an external Schottky output clamp diode
that would otherwise be required if DL1 were simply
forced high.
OR
OFS1
Setting BUCK2 Output Voltage
BUCK2’s Dual Mode™ operation allows the selection of
common voltages without requiring external compo-
nents (Figure 1). In fixed mode, connect FB2 to AGND
Figure 10. Simplified Offset-Control Circuits
At the beginning of an output voltage transition, the regu-
lator is placed in forced-PWM mode and the PGOOD
output is high. If there is a fault on BUCK2 during this
period, PGOOD goes low. The output voltage follows the
internal DAC code, which changes in 25mV increments
until it reaches the programmed VID code. The regulator
remains in forced-PWM mode for 32 clock cycles after
the transition to ensure that the output settles properly.
The PGOOD output is forced high for 4 clock cycles after
the transition also to allow the output to settle. The slew-
for 2.5V output, or connect FB2 to V
for 1.8V output.
CC
In adjustable mode, the output voltage can be adjusted
from 1.0V to 5.5V using a resistive voltage-divider from
the BUCK2 output to AGND with the center tap con-
nected to FB2 (Figure 11). The equation for adjusting
the output voltage is:
R1
R2
V
= V
1+
OUT2
FB2
rate clock frequency (set by the R
resistor) must be
TIME
where V
is 1.0V.
FB2
set fast enough to ensure that the longest transition is
completed within the allotted time interval.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________ 35
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Table 7. Offset Selection Truth Table
INPUTS
ACTIVE OFS INPUTS
MODE
SUS
PERF
DPSLP
OFS2
OFS1
OFS0
Battery Sleep
Battery
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Performance Sleep
Performance
Suspend
Suspend
Suspend
Suspend
0 = Logic low or input not selected.
1 = Logic high or input selected.
Output Overvoltage Protection
Output overvoltage protection (OVP) is available on
BUCK1, BUCK2, and the linear regulator. The LINFB
input is always monitored for overvoltage. The FBS and
OUT2 inputs are only monitored for overvoltages when
OVP is enabled. When any output exceeds the desired
OVP threshold, the fault latch is set and the regulator is
turned off. In the fault mode, DL1 and DL2 are forced
high, DH1 and DH2 are forced low, and the linear regu-
lator is turned off. For BUCK1 and BUCK2, if the condi-
tion that caused the overvoltage (such as a shorted
high-side MOSFET) persists, the battery fuse will blow.
V
BATT
DH2
V
OUT
MAX1816
MAX1994
DL2
CS2
R1
R2
OUT2
FB2
DL1 is also kept high continuously when V
UVLO is
CC
active, as well as in shutdown mode (Table 4). The
device remains in the fault mode until V is cycled, or
either SKP_/SDN or LIN/SDN is toggled. The triggering
of the reset condition occurs on the rising edge of the
SKP_/SDN or LIN/SDN signals.
PGND
AGND
CC
Figure 11. Adjusting BUCK2 Output Voltage with a Resistive
Voltage-Divider
For BUCK1, the default OVP threshold is 2V for the
MAX1816 and 2.25V for the MAX1994. For BUCK2, the
OVP threshold is 115% of the nominal voltage for OUT2
(FB2 if external feedback is used for BUCK2). The over-
voltage detection level for FBS can be adjusted through
an external resistive voltage-divider. Connecting OVPSET
to a voltage between 1.0V and 2.0V sets the OVP thresh-
old for FBS. For the MAX1816, the fault latch is set when
Output Undervoltage Protection
The output undervoltage protection (UVP) is available on
BUCK1, BUCK2, and the linear regulator. The protection
is similar to foldback current limiting, but employs a timer
rather than a variable current limit. If the output voltage is
under 70% of the nominal value for BUCK1 and BUCK2,
and under 90% for the linear regulator (see the Electrical
Characteristics table for the respective UVP thresholds),
the fault latch is set. In the fault mode, DL1 and DL2 are
forced high, DH1 and DH2 are forced low, and the linear
regulator is turned off. The controller does not restart until
V
> V
FBS
. For the MAX1994, the fault latch is set
FBS
when V
OVPSET
✕
> 1.125
V
. The OVP threshold on
OVPSET
OUT2 is not adjustable and remains at the default value
of 115%. Connecting OVPSET to V disables OVP for
CC
BUCK1 and BUCK2. The operation of the linear regulator
is not affected by OVPSET. Overvoltage protection can
be disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
V
CC
power is cycled, or either SKP_/SDN or LIN/SDN is
toggled. The triggering of the reset condition occurs on
the rising edge of the SKP_/SDN or LIN/SDN signals.
36 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
To allow startup, UVP is ignored during the undervoltage
BUCK1/BUCK2
Design Procedure
blanking time (the first 256 cycles of the slew rate after
startup for BUCK1, the first 4096 cycles for BUCK2 and
Firmly establish the input voltage range and maximum
load current for BUCK1 and BUCK2 before choosing a
switching frequency and inductor operating point (rip-
ple-current ratio). The primary design trade-off lies in
choosing a good switching frequency and inductor
operating point, and the following four factors dictate
the rest of the design:
the first 512 cycles for the linear regulator). UVP can be
disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
UVLO
The MAX1816/MAX1994 provide input undervoltage lock-
out (UVLO) protection. If the V
voltage drops low
CC
enough to trip the UVLO comparator, it is assumed that
there is not enough supply voltage to make valid deci-
sions. In order to protect the output from overvoltage
faults, DL1 and DL2 are forced high if OVP is enabled,
DH_ is forced low, and the linear regulator is turned off. If
OVP is disabled, DL1 is forced high, DL2 is forced low,
DH_ is forced low, and the linear regulator is turned off.
For BUCK1 (and also for BUCK2 if OVP is enabled), this
condition rapidly forces the outputs to zero since the
slew-rate controller is not active. The fault results in large
negative inductor currents and possibly small negative
1) Input Voltage Range. The maximum value
(V
) must accommodate the worst-case high
IN(MAX)
AC adapter voltage. The minimum value (V
)
IN(MIN)
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice, lower input volt-
ages result in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (I
) deter-
LOAD(MAX)
mines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
output voltages. If V
is likely to drop in this fashion, the
CC
outputs can be clamped with Schottky diodes to PGND to
reduce the negative excursions.
ous load current (I
) determines the thermal
LOAD
Thermal Fault Protection
The MAX1816/MAX1994 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch, which
pulls DL_ high, DH_ low, and turns off the linear regula-
tor. The device remains in fault mode until the junction
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit I
= I
✕ 80%.
LOAD
LOAD(MAX)
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
temperature cools by 15°C, and either V
power is
CC
cycled, or SKP_/SDN or LIN/SDN is toggled.
are proportional to frequency and V . The optimum
IN
NO FAULT Test Mode
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable the OVP, UVP, and thermal shut-
down features, and clear the fault latch if it has been
set. Test mode applies to BUCK1, BUCK2, and the lin-
ear regulator. In the test mode, BUCK1 operates as if
SKP1/SDN was high (skip mode). Set the voltage on
SKP1/SDN between 10.8V to 13.2V to enable the NO
FAULT test mode.
frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
4) Inductor Operating Point. This choice provides
tradeoffs between size and efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of criti-
cal conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit. The MAX1816/MAX1994s’ pulse-
skipping algorithm initiates skip mode at the critical
conduction point. So, the inductor operating point
also determines the load current value at which
PFM/PWM switchover occurs. The optimum point is
usually found between 20% and 50% ripple current.
______________________________________________________________________________________ 37
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
5) Inductor Ripple Current. The inductor ripple cur-
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
rent also impacts transient response performance,
especially at low V - V
differentials. Low induc-
IN
OUT
tor values allow the inductor current to slew faster,
replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty
factor, which can be calculated from the on-time
and minimum off-time:
ley of the inductor current occurs at I
minus
LOAD(MAX)
half of the ripple current; therefore:
LIR
2
I
>I
× 1−
LIMIT(MIN) LOAD(MAX)
The current-sense resistor value (R1 in Figure 1) is cal-
culated according to the worst-case (minimum) current-
limit threshold voltage (see the Electrical Characteristics
V
V
2
OUT
(I
−I
) ×L × K
+ t
LOAD1 LOAD2
OFF(MIN)
IN
table) and the valley current-limit threshold I
described above:
LIMIT(MIN)
V
=
SAG
V
− V
OUT
IN
2×C
× V
× K
OUT
− t
OUT
OFF(MIN)
V
IN
50mV × 0.8
R
R
=
=
(Fixed Mode)
SENSE
SENSE
I
LIMIT(MIN)
where t
is the minimum off-time (see the
Electrical Characteristics table) and K is from Table 3.
OFF(MIN)
V
× 0.1× 0.8
ILIM1
(Adjustable Mode)
I
LIMIT(MIN)
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
where 0.8 is a factor for the worst-case low current-limit
threshold.
To protect against component damage during short-cir-
V
×(V − V )
IN OUT
OUT
L =
cuit conditions, use the calculated value of R
to
SENSE
V
× f ×LIR×I
LOAD(MAX)
IN SW
size the MOSFET switches and specify inductor satura-
tion-current ratings according to the worst-case high
current-limit threshold:
Example: I
SW
= 19A, V = 7V, V
= 1.25V,
OUT
LOAD(MAX)
IN
f
= 300kHz, 30% ripple current or LIR = 0.30:
50mV ×1.2
I
=
× (1+ LIR)
PEAK(MAX)
R
1.25V ×(7V −1.25V)
7V × 300kHz× 0.30×19A
SENSE
L =
= 0.60µH
(Fixed Mode)
V
× 0.1×1.2
ILIM1
I
=
× (1+ LIR)
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered iron
is inexpensive and can work well at 200kHz. The core
must be large enough not to saturate at the peak induc-
PEAK(MAX)
R
SENSE
(Adjustable Mode)
where 1.2 is a factor for worst-case high current-limit
threshold.
tor current (I
):
PEAK
Low-inductance resistors, such as surface-mount metal
film, are recommended.
LIR
2
I
=I
× 1+
PEAK LOAD(MAX)
Setting the Current Limit for BUCK2
Connect ILIM2 to V
for a default 50mV CS2 to GND
CC
Setting the Current Limit for BUCK1
Connect ILIM1 to V for a default 50mV (CS1+ to CS1-)
current-limit threshold. For an adjustable threshold,
connect a resistive voltage-divider from REF to GND,
with ILIM2 connected to the center tap. The current-
limit threshold is precisely 1/10th of the voltage at
ILIM2. When adjusting the current limit, use 1% toler-
ance resistors for the divider and a 10µA divider cur-
rent to prevent a significant increase of errors in the
current-limit threshold.
CC
current-limit threshold. For an adjustable threshold, con-
nect a resistive voltage-divider from REF to GND, with
ILIM1 connected to the center tap. The current-limit
threshold is precisely 1/10th of the voltage at ILIM1. When
adjusting the current limit, use 1% tolerance resistors for
the divider and a 10µA divider current to prevent a signifi-
cant increase of errors in the current-limit threshold.
38 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
Output Capacitor Selection
(BUCK1 and BUCK2)
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. Also, the capacitance
value must be high enough to absorb the inductor ener-
gy going from a full-load to no-load condition without
tripping the OVP circuit.
ley of the inductor current occurs at I
half of the ripple current; therefore:
minus
LOAD(MAX)
LIR
2
I
>I
× 1−
LIMIT(MIN) LOAD(MAX)
where I
equals the minimum current-limit
LIMIT(MIN)
In CPU core voltage regulators and other applications
where the output is subject to violent load transients,
the output capacitor’s size typically depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
threshold voltage divided by the current-sense resistor.
The sense resistor (R2 in Figure 1) determines the achiev-
able current-limit accuracy. There is a trade-off between
current-limit accuracy and sense-resistor power dissipa-
tion. Most applications employ a current-sense voltage of
50mV to 100mV. Choose a sense resistor so that:
50mV × 0.8
V
DIP
I
LOAD(MAX)
R
R
=
=
(Fixed Mode)
SENSE
SENSE
R
≤
ESR
I
LIMIT(MIN)
V
× 0.1× 0.8
ILIM2
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output-voltage ripple:
(Adjustable Mode)
I
LIMIT(MIN)
where 0.8 is a factor for worst-case low current-limit
threshold.
V
P−P
R
≤
ESR
Extremely cost-sensitive applications that do not require
high-accuracy current sensing can use the on-resis-
tance of the low-side MOSFET switch in place of the
sense resistor by connecting CS2 to LX2. Use the worst-
case maximum value for R
data sheet taking into account the rise in R
temperature. A good general rule is to allow 0.5% addi-
tional resistance for each °C temperature rise.
Assume the current-sense resistor in the application cir-
cuit in Figure 1 is removed and CS2 is directly tied to
LIR ×I
LOAD(MAX)
The actual microfarad capacitance value required often
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OSCONs, and other electrolytics).
from the MOSFET
DS(ON)
with
DS(ON)
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually deter-
LX2. The Q4 maximum R
= 3.8mΩ at T = +25°C
J
DS(ON)
mined by the capacity needed to prevent V
and
SAG
and 5.7mΩ at T = +125°C.
J
V
from causing problems during load transients.
SOAR
The minimum current-limit threshold is:
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
500mV × 0.1× 0.8
I
=
= 7A
LIMIT(MIN)
5.7mΩ
and the required valley current limit is:
> 7A ✕ (1 - 0.30/2) = 5.95A
The amount of overshoot due to stored inductor energy
can be calculated as:
I
LIMIT(MIN)
2
L ×I
PEAK
V
=
SOAR
since 7A is greater than the required 5.95A, the circuit
can deliver the 7A full-load current.
2×C
× V
OUT
OUT
where I
is the peak inductor current.
PEAK
______________________________________________________________________________________ 39
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
When the local capacitance time constant is either
much greater or much smaller than that of the remote
capacitance, the stability criteria is:
BUCK1 Stability Considerations
BUCK1 is fundamentally different from previous Quick-
PWM controllers in two respects: it uses a current-sense
amplifier to obtain the current feedback signal (ramp),
and it uses differential remote sense to compensate for
voltage drops along the high-current path. The regulator
adds the differential remote-sense signal to the current-
feedback signal to correct the output voltage. As long
as the amplitude of the resulting signal is greater than
1% of the output voltage, the regulator remains stable.
Stability can be determined by comparing the zero
formed with the current-sense feedback network to the
switching frequency.
R
C
× C
+ C
+ R
×
(
)
DROOP
OUT1
REMOTE
LOCAL
1
+ R
× C
≥
REMOTE
OUT1
REMOTE
2 × f
SW
In applications where these two time constants are
approximately equal, the criteria for stable operation
reduces to:
1
2× f
R
(
+R
+R
×C ≥
OUT1
and
1
)
DROOP
LOCAL
The boundary condition of stability is given by the fol-
lowing expression:
SW
R
(
×C
≥
)
DROOP
REMOTE
REMOTE
f
SW
π
2× f
SW
f ≤
Z
The standard application circuit (Figure 1) operating at
300kHz easily achieves stable operation because the
time constant of the local capacitors is much greater
than that of the remote capacitors.
1
f
≈
Z
R
× C
+ C
+
REMOTE
(
)
DROOP
LOCAL
OUT1
2π ×
In this example, C
REMOTE
1mΩ = 2mΩ:
= 990µF, R
REMOTE
= 3.3mΩ,
LOCAL
OUT1
= 10µF, R
R
× C
+ R
× C
REMOTE REMOTE
OUT1
C
= 5mΩ, and R
= 2 x
DROOP
where C
C
is the local output capacitance (Figure 1),
OUT1
2mΩ × 990µF +10µF + 3.3mΩ
is the remote output capacitance, R
is
(
)
REMOTE
LOCAL
is the ESR of
is the effective
the ESR of the local capacitors, R
REMOTE
1
× 990µF + 5mΩ ×10µF ≥
the remote capacitors, and R
DROOP
2× 300kHz
voltage-positioning resistance, which is determined by
the voltage-positioning gain A and current-sense
VPS
resistor R
:
5.32µs ≥1.67µs
SENSE
R
= A
x R
DROOP
VPS SENSE
When voltage positioning is not used (A
= 0) and the
VPS
Like previous Quick-PWM controllers, larger values of
ESR and sense resistance increase stability. The volt-
age-positioning gain A
sense resistance, which further enhances stability.
ESR of the output capacitors alone cannot meet the sta-
bility requirement, the current feedback signal must be
generated from a different source. The current ramp sig-
nal at CS1+ and the output voltage must be summed at
the FBS input. For stable operation, a 3.3µF feed-for-
ward capacitor is added from the CS1+ input to FBS
and a 10Ω resistor is inserted from the remote load to
FBS forming an RC filter (Figure 12). The cutoff frequen-
cy of the RC filter should be approximately an order of
magnitude lower than the regulator’s switching frequen-
cy to prevent sluggish transient response. To avoid
input-bias current-induced offset errors, the resistor
should be less than 20Ω.
effectively increases the
VPS
The RC time constants of the local and remote capaci-
tors affect the stability criteria. These two time con-
stants are defined as follows:
τ
= (R
+ R
+ R
) x C
LOCAL
DROOP
LOCAL
PCB_TRACE
OUT1
) x C
REMOTE REMOTE
τ
= (R
+ R
REMOTE
DROOP
where R
_
is the PC board trace resistance
PCB TRACE
shown in Figure 1.
40 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Therefore:
PC BOARD TRACE
RESISTANCE
R
SENSE
1mΩ × 990µF +10µF + 3.3mΩ
(
)
1
× 990µF + 5mΩ ×10µF ≥
CS1+
CS1-
2× 300kHz
REMOTE
LOAD
3.3µF
C
OUT
PC BOARD TRACE
RESISTANCE
4.32µs ≥1.67µs
10Ω
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability. Double-pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output-voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum off-
time period has expired. Double-pulsing is more annoy-
ing than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability, which is caused
by insufficient current feedback signal.
FBS
GDS
Figure 12. Output Feed Forward for Nonvoltage-Positioned
Applications
For nonvoltage-positioned applications using a feed-
forward circuit, the RC time constants of the local and
remote capacitors are defined as:
τ
= (R
+ R
) x C
LOCAL
SENSE
LOCAL
OUT1
)
PCB_TRACE
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit. The easiest method for check-
ing stability is to apply a very fast zero-to-max load
transient and carefully observe the output-voltage rip-
ple envelope for overshoot and ringing. It can help to
simultaneously monitor the inductor current with an AC
current probe. Do not allow more than one cycle of
ringing after the initial step-response under/overshoot.
τ
= (R
+ R + R
REMOTE
REMOTE
SENSE
x C
REMOTE
The new stability criteria for nonvoltage-positioned
applications using feed forward becomes:
R
× C
(
+ R
+ C
+ R
×
)
SENSE
OUT1
REMOTE
LOCAL
1
C
× C
REMOTE
≥
OUT1
REMOTE
2 × f
SW
for τ
much greater or much smaller than
LOCAL
BUCK2 Stability Considerations
The stability criterion for BUCK2 is the same as previous
Quick-PWM controllers like the MAX1714. Stability is
determined by comparing the value of the ESR zero to
the switching frequency. The point of stability is given by
the following expression:
τ
, and
REMOTE
1
R
(
+R
+R
×C ≥
OUT1
and
)
SENSE
LOCAL
2× f
SW
1
R
(
×C
≥
)
SENSE
REMOTE
REMOTE
2× f
SW
f
SW
f
≤
when τ
and τ
are approximately equal.
ESR
LOCAL
REMOTE
π
If the voltage-positioning gain in the standard applica-
tion circuit (Figure 1) is set to zero and the feed-forward
compensation circuit shown in Figure 12 is used, stable
operation can still be easily achieved.
1
where
f
=
ESR
2π × R
× C
OUT
ESR
For good phase margin, it is recommended to increase
the equivalent RC time constant by a factor of two. The
standard application circuit (Figure 1) operating at
In this example, C
= 990µF, R
REMOTE
= 3.3mΩ,
LOCAL
OUT1
= 10µF, R
C
= 5mΩ, R
= 1mΩ,
SENSE
REMOTE
390kHz with C
meets this requirement.
= 330µF and R
= 10mΩ, easily
and R
_
= 2mΩ, and the local time constant is
OUT
ESR
PCB TRACE
much greater than the remote time constant.
______________________________________________________________________________________ 41
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
issue for the low-side MOSFET, since it is a zero-voltage
switched device when used in the buck topology.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents
defined by the following equation:
RMS
MOSFET Power Dissipation
The high-side MOSFET conduction power dissipation
due to on-state channel resistance is:
V
(V − V )
OUT IN OUT
I
=I
RMS LOAD
V
IN
V
V
2
OUT
PD(Q1_Conduction) =
×I
× R
LOAD DS(ON)1
The RMS input currents for BUCK1 and BUCK2 can be
calculated using the above equation. Use the sum
of these two currents as the total RMS current. Note
that this is a very conservative estimation because the
two regulators are never in phase 100% of the time.
The actual RMS current is always lower than the
calculated value.
IN
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
required to stay within package
DS(ON)
power-dissipation limits often constrains how small the
MOSFET can be.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
For most applications, nontantalum chemistries (ceramic
or OSCON) are preferred due to their resilience to
inrush surge currents typical of systems with a switch
or a connector in series with the battery. If the
MAX1816/MAX1994 operate as the second stage of a
two-stage power conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
CV2f
switching-loss equation. If the high-side MOSFET
SW
chosen for adequate R
becomes extraordinarily hot when subjected to V
reconsider the MOSFET selection.
at low battery voltages
DS(ON)
,
IN(MAX)
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induct-
ance, and PC board layout characteristics. The follow-
ing switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation and thermal measurements:
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET (Q1 in Figure1) must be able to
dissipate the resistive losses plus the switching losses
2
C
× V
× f ×I
SW LOAD
RSS
IN(MAX)
PD(Q1_Switching) =
at both V
and V
. Calculate both of these
IN(MAX)
IN(MIN)
I
GATE
sums. Ideally, the losses at V
equal to the losses at V
between. If the losses at V
er than the losses at V
size of Q1. Conversely, if the losses at V
nificantly higher than the losses at V
should be roughly
, with lower losses in
are significantly high-
IN(MIN)
IN(MAX)
IN(MIN)
IN(MAX)
where C
and I
is the reverse transfer capacitance of Q1
is the peak gate-drive source/sink current
(1.5A typ for BUCK1, 0.75A typ for BUCK2).
RSS
GATE
, consider increasing the
are sig-
IN(MAX)
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
, consider
IN(MIN)
reducing the size of Q1. If V does not vary over a
IN
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
V
2
OUT
PD(Q2) = 1−
×I
× R
LOAD DS(ON)2
V
IN(MAX)
Choose a low-side MOSFET (Q2) that has the lowest
possible R
, comes in a moderate-sized package
DS(ON)
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than I
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, “overdesign” the circuit to tolerate:
(i.e., two or more 8-pin SOs, DPAKs, or D2PAKs), and is
reasonably priced. Ensure that the MAX1816/MAX1994
DL_ gate driver can drive Q2; in other words, check that
the dV/dt caused by Q1 turning on does not pull up the
gate of Q2 due to drain-to-gate capacitance, causing
cross-conduction problems. Switching losses are not an
LOAD(MAX)
I
= I
+ (LIR/2) ✕ I
LOAD
LIMIT(HIGH ) LOAD(MAX)
42 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
where I
is the maximum valley current
limit the usable maximum input-to-output voltage differ-
ential. The maximum power dissipation capability of the
transistor’s package and mounting must exceed the
actual power dissipation in the device.
LIMIT(HIGH)
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation.
The MOSFETs must have a good-sized heat sink to
handle the overload power dissipation. If short-circuit
protection without overload protection is enough, a
The power dissipation equals the maximum load current
times the maximum input-to-output voltage differential:
normal I
value can be used for calculating compo-
LOAD
nent stresses.
P = I
x (V
- V ) = I
x V
LOAD(MAX)
LDOIN
LIN
LOAD(MAX) CE
Choose a Shottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Linear Regulator Stability Requirements
The MAX1816/MAX1994 linear-regulator controller uses
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifi-
er, the pass transistor, the emitter-base resistor, and
the output capacitor determine the loop stability. If the
output capacitor and pass transistor are not properly
selected, the linear regulator is unstable.
Linear Regulator
Design Procedure
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain is
approximately:
Output Voltage Selection
Adjust the linear regulator’s output voltage by connect-
ing a resistive voltage-divider from V
to AGND with
LIN
the center tap connected to LINFB (Figure 1). Select R9
in the range of 10kΩ to 100kΩ. Calculate R8 with the
following equation:
V
I
h
REF
BIAS FE
A
=
1+
5.5
V(LDO)
R8 = R9 [(V
/ 1.00V) - 1]
V
I
LIN
T
LOAD
Pass Transistor Selection
where V is 26mV at room temperature, I
is the cur-
BIAS
T
The PNP pass transistor must meet specifications for
rent though the emitter-base resistor (R ), and V
=
REF
EB
current gain (h ), input capacitance, emitter-collector
FE
1.0V. This bias resistor is typically 220Ω, providing
approximately 3.2mA of bias current.
saturation voltage, and power dissipation. The
transistor’s current gain limits the guaranteed maximum
output current to:
The output capacitor and the load resistance create the
dominant pole in the system. However, the pass tran-
sistor’s input capacitance creates a second pole in the
system. Additionally, the output capacitor’s ESR gener-
ates a zero. To achieve stable operation, use the follow-
ing equations to verify that the linear regulator is
properly compensated:
V
EB
I
= I
h
FE(MIN)
− R
LOAD(MAX)
DRV
EB
where I
is the minimum base-drive current, and R
EB
DRV
is the pullup resistor connected between the transis-
tor’s emitter and base. Furthermore, the transistor’s cur-
rent gain increases the linear regulator’s DC loop gain
(see the Linear Regulator Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 300A/A at
the maximum output current are not recommended.
The transistor’s input capacitance and input resistance
also create a second pole, which could be low enough
to make the output unstable when heavily loaded.
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
I
1
LOAD(MAX)
f
=
=
POLE(CLDO)
2πC
R
2πC
V
LDO LOAD
LDO LDO
The unity gain crossover of the linear regulator is:
= A
f
f
V(LDO) POLE(CLDO)
CROSSOVER
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package’s power dissipation could
2) Next, determine the second pole set by the emitter-
base capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the emitter-base pullup resistor:
______________________________________________________________________________________ 43
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
ment. Setting the no-load output voltage slightly higher
R
I
+ V h
1
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor’s ESR can be increased.
EB LOAD T FE
f
=
=
POLE(CEB)
2πC (R ||R )
2πC R V h
EB EB T FE
EB EB
IN
3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance between LINFB
and GND, including the stray capacitance:
Adding a series output resistor positions the full-load
output voltage below the actual DAC programmed volt-
age. Connect FB directly to the inductor side of the
voltage-positioning resistor (R1, 1mΩ). The other side
of the voltage-positioning resistor should be connected
directly to the output filter capacitor with a short, wide
PC board trace. With the gain pin floating (GAIN = 2), a
20A full-load current causes a 40mV drop in the output.
This 40mV is a -3.2% droop.
1
f
=
POLE(FB)
2πC (R8 ||R9)
FB
4) If the second and third poles occur well after unity
gain crossover, the linear regulator remains stable:
f
> 2f
A
POLE(CLDO) V(LDO)
POLE(CEB)
However, if the ESR zero occurs before the unity gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in R1.
For a nominal 1.25V, 20A output, reducing the output
voltage by 3.2% gives an output voltage of 1.21V and
an output current of 19.4A. Given these values, CPU
power consumption is reduced from 25W to 23.5W. The
additional power consumption of R1 is:
1
f
≈
POLE(FB)
2πC
R
LDO ESR
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
Output Capacitor Selection
Typically, more output capacitance provides the best
performance, since this also reduces the output voltage
drop immediately after a load transient. Connect at
least a 10µF capacitor between the linear regulator’s
output and ground, as close to the external pass tran-
sistor as possible. Depending on the selected pass
transistor, larger capacitor values may be required
for stability (see the Linear Regulator Stability
Requirements section). Furthermore, the output capaci-
tor’s ESR affects stability. Use output capacitors with an
ESR less than 200mΩ to ensure stability and optimum
transient response. Once the minimum capacitor value
for stability is determined, verify that the linear regula-
tor’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can pro-
vide too much bandwidth, making the linear regulator
sensitive to noise. Larger capacitor values reduce the
bandwidth, thereby reducing the regulator’s noise sen-
sitivity.
1mΩ ✕ (19.4A)2 = 0.38W
And the overall power savings is as follows:
25W - (23.5W + 0.38W)= 1.12W
In effect, 1.5W of CPU dissipation is saved, and the
power supply dissipates some of the power savings,
but both the net savings and the transfer of dissipation
away from the hot CPU are beneficial.
High-Current Master-Slave Applications
The MAX1816/MAX1994 can be used in high-current
applications using additional slave regulators. Figure 2
illustrates a 40A master-slave application using this
technique. The MAX1994 is placed in forced PWM
mode to simplify operation with the slave. Refer to the
MAX1980 data sheet for a detailed description of the
master-slave architecture and how to configure correctly
the slave circuit.
Applications Information
Dropout Performance
The output voltage adjustment range for continuous-
conduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot (375ns max at
550kHz and 1000kHz). For best dropout performance,
use the slower (200kHz) on-time settings.
Voltage Positioning
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
44 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
When working with low-input voltages, the duty-factor limit
(1.2V + 0.1V)
V
=
+ 0.1V − 0.1V =1.74V
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propaga-
tion delays introduce an error to the TON K factor. This
error is greater at higher frequencies (Table 3).
IN(MIN)
0.5µs ×1.5
2.97µs
1−
Calculate again with h = 1 gives the absolute limit of
dropout:
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
(1.2V + 0.1V)
the V
equation in the Design Procedure section).
SAG
V
=
+ 0.1V − 0.1V =1.56V
IN(MIN)
0.5µs ×1
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
1−
2.97µs
)
DOWN
as much as it ramps up during the on-time (∆I ). The
UP
ratio h = ∆I /∆I
is an indicator of ability to slew
UP DOWN
Since 1.56V is less than the lower limit of the input volt-
age range (2V), the practical minimum input voltage
with reasonable output capacitance would be 2V.
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
One-Stage (Battery Input) vs.
Two-Stage (5V Input) Conversion
The MAX1816/MAX1994 can be used with a direct bat-
tery connection (one stage) or can obtain power from a
regulated 5V supply (two stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
switching cycle and V
greatly increases, unless
SAG
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this can
be adjusted up or down to allow trade-offs between
V
, output capacitance, and minimum operating volt-
SAG
age. For a given value of h, the minimum operating volt-
age can be calculated as:
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp up
the inductor current faster. The total efficiency of a sin-
gle stage is better than the two-stage approach.
(V
+ V
)
OUT
DROP1
V
=
+ V
− V
IN(MIN)
DROP2 DROP1
T
×h
OFF(MIN)
1−
K
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
where V
and V
are the parasitic voltage
DROP2
DROP1
drops in the discharge and charge paths, respectively
(see the On-Time One-Shot (TON) section), T
OFF(MIN)
is from the Electrical Characteristics table, and K is
taken from Table 3. The absolute minimum input volt-
age is calculated with h = 1.
If the calculated V
is greater than the required
IN(MIN)
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytic
capacitors, creating a need for a DC-DC design that
uses nothing but ceramic capacitors.
an acceptable V
. If operation near dropout is
SAG
anticipated, calculate V
transient response.
to be sure of adequate
SAG
Dropout Design Example
V
OUT
= 1.2V
f
= 300kHz
SW
K = 3.3µs, worst-case K = 2.97µs
= 500ns
T
OFF(MIN)
V
= V
= 100mV
DROP1
DROP2
h = 1.5
______________________________________________________________________________________ 45
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
The MAX1816/MAX1994 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the posi-
tioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
5) Tie AGND and PGND together close to the IC. Do
not connect them together anywhere else. Carefully
follow the grounding instructions in the Layout
Procedure.
6) In high-current master-slave applications, the mas-
ter controller should have a separate analog
ground. Return the appropriate noise-sensitive
components to this plane. Since the reference in
the master is sometimes connected to the slave, it
may be necessary to couple the analog ground in
the master to the analog ground in the slave to pre-
vent ground offsets. A low value (≤10Ω) resistor is
sufficient to link the two grounds.
Output overshoot (V
) determines the minimum
SOAR
output capacitance requirement (see the Output
Capacitor Selection section). Often the switching fre-
quency is increased to 550kHz or 1000kHz, and the
inductor value is reduced to minimize the energy trans-
ferred from inductor to capacitor during load-step
recovery. The efficiency penalty for operating at
550kHz is about 2% to 3% and about 5% at 1000kHz
when compared to the 300kHz voltage-positioned cir-
cuit, primarily due to the high-side MOSFET switching
losses.
7) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 13). Refer to the MAX1816/MAX1994 EV kit data
sheet for a specific layout example.
8) Keep the high-current gate-driver traces (DL_, DH_,
LX_, and BST_) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
9) CS1+, CS1-, CS2, and AGND connections for cur-
rent limiting must be made using Kelvin-sense con-
nections to guarantee the current-limit accuracy.
Kelvin connections to LX2 and AGND must also be
1) Isolate the power components on the top side from
the sensitive analog components on the bottom
side with a ground shield. Use a separate PGND
plane under the BUCK1 and BUCK2 sides (called
PGND1 and PGND2). Avoid the introduction of AC
currents into the PGND1 and PGND2 ground
planes.
made if the synchronous rectifier R
of
DS(ON)
BUCK2 is used for current limiting. With 8-pin SO
MOSFETs, this is best done by routing power to the
MOSFETs from the outside using the top copper
layer, while connecting GND and LX inside (under-
neath) the 8-pin SO package.
2) Use a star ground connection on the power plane
to minimize the crosstalk between BUCK1 and
BUCK2.
10) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
3) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
4) Connect all analog grounds to a separate solid
copper plane, which connects to the AGND pin of
the MAX1816/MAX1994. This includes the V
CC
bypass capacitor, REF bypass capacitor, compen-
sation components, the TIME resistor, as well as
any other resistive dividers.
11) Route high-speed switching nodes away from sen-
sitive analog areas (CC, REF, ILIM_). Make all pin-
strap control input connections (SKP_/SDN, ILIM_,
etc.) to analog ground or V
rather than power
CC
ground or V
.
DD
46 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
C
OUT1
C
OUT1
C
OUT1
C
OUT1
POWER GROUND
TOP LAYER
V
OUT1
VIA TO POWER GROUND
REF CAP
POWER GROUND
V
DD
CAP
C
C
OUT2
OUT2
L1
V
OUT2
L2
LX1
LX2
ANALOG
GROUND
MAX1816
MAX1994
V
CC
CAP
POWER GROUND
BOTTOM LAYER
C
IN
C
IN
C
C
C
IN
C
IN
IN
IN
INPUT (V+)
LX1
LX2
Figure 13. Power-Stage PC Board Layout Example
power components go; the power ground plane,
where the PGND pin and V bypass capacitors
Layout Procedure
1) Place the power components first, with ground ter-
DD
go; and an analog ground plane where sensitive
analog components go. The analog ground plane
and power ground plane must meet only at a single
point close to the IC. These two planes are then
connected to the high-power output ground with a
short connection from PGND to the source of the
low-side MOSFET (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
minals adjacent (low-side MOSFET sources, C
,
IN_
C
OUT
_, D1/D2 anodes). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side MOS-
FET, preferably on the backside in order to keep LX_,
PGND_, and the DL_ drive lines short and wide. The
DL_ gate traces must be short and wide, measuring
10 to 20 squares (50 mils to 100 mils wide if the
MOSFET is 1in from the controller IC).
5) Connect the output power planes (V
and sys-
CORE
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit
as close to the CPU as is practical.
3) Group the gate-drive components (BST_ diodes
and capacitors, V
bypass capacitor) together
DD
near the controller IC.
4) Make the MAX1816/MAX1994 controllers’ ground
connections as shown in Figure 13. This diagram
can be viewed as having three separate ground
planes: input/output ground, where all the high-
Chip Information
TRANSISTOR COUNT: 13,313
______________________________________________________________________________________ 47
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
A
A1
A2
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0144
A
2
48 ______________________________________________________________________________________
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0144
A
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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