MAX1844ETP-T [MAXIM]
Switching Controller, Current-mode, 3A, 600kHz Switching Freq-Max, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, THIN, QFN-20;
| 型号： | MAX1844ETP-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 3A, 600kHz Switching Freq-Max, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, THIN, QFN-20 信息通信管理 开关 |
| 文件： | 总24页 (文件大小：854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1993; Rev 3; 9/02
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
General Description
Features
The MAX1844 pulse-width modulation (PWM) controller
provides high efficiency, excellent transient response,
and high DC output accuracy needed for stepping
down high-voltage batteries to generate low-voltage
CPU core or chipset/RAM supplies in notebook com-
puters.
o Ultra-High Efficiency
o Accurate Current-Limit Option
o Quick-PWM with 100ns Load-Step Response
o 1% V Accuracy Over Line and Load
OUT
o 1.8V/2.5V Fixed or 1V to 5.5V Adjustable Output
Maxim’s proprietary Quick-PWM™ quick-response,
constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides
100ns “instant-on” response to load transients while
maintaining a relatively constant switching frequency.
Efficiency is enhanced by an ability to drive very large
synchronous-rectifier MOSFETs. Accurate current sens-
ing to ensure reliable overload protection is available
using an external current-sense resistor in series with
the synchronous rectifier. Alternatively, the synchronous
rectifier itself can be used for less accurate current
sensing at the lowest possible power dissipation.
Range
o 2V to 28V Battery Input Range
o 200/300/450/600kHz Switching Frequency
o Adjustable Overvoltage Protection
o Adjustable Undervoltage Protection
o 1.7ms Digital Soft-Start
o Drives Large Synchronous-Rectifier FETs
o 2V 1% Reference Output
Single-stage buck conversion allows the MAX1844 to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the 5V system supply instead of the
battery) at a higher switching frequency allows the mini-
mum possible physical size.
o Power-Good Window Comparator
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 QSOP
MAX1844EEP
MAX1844EGP*
MAX1844ETP
The MAX1844 is intended for CPU core, chipset,
DRAM, or other low-voltage supplies as low as 1V. It is
available in 20-pin QSOP, and QFN packages and
includes both adjustable overvoltage and undervoltage
protection.
20 QFN
20 Thin QFN
Minimal Operating Circuit
For a dual step-down PWM controller with accurate cur-
rent limit, refer to the MAX1845. The MAX1714/ MAX1715
single/dual PWM controllers are similar to the MAX1844/
MAX1845 but do not use current-sense resistors.
BATTERY
4.5V TO 28V
5V INPUT
V
V
DD
V+
CC
SHDN
Applications
UVP
Notebook Computers
BST
DH
ILIM
CPU Core Supplies
OUTPUT
2.5V
MAX1844
REF
Chipset/RAM Supplies as Low as 1V
1.8V and 2.5V Supplies
LX
DL
CS
PGOOD
LATCH
OVP
OUT
*Contact factory for availability.
FB
SKIP
Quick-PWM is a trademark of Maxim Integrated Products.
Pin Configuration appears at end of data sheet.
GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +28V
REF Short Circuit to GND...........................................Continuous
V
, V
to GND .....................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
CC DD
A
OUT, PGOOD, SHDN to GND..................................-0.3V to +6V
FB, ILIM, LATCH, OVP, REF, SKIP,
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
✕
20-Pin 5mm 5mm QFN (derate 20.0mW/°C
TON, UVP to GND ..................................-0.3V to (V
BST to GND............................................................-0.3V to +34V
CS to GND.................................................................-6V to +30V
DL to GND..................................................-0.3V to (V
DH to LX .....................................................-0.3V to (BST + 0.3V)
LX to BST..................................................................-6V to +0.3V
+ 0.3V)
above +70°C).................................................................1.60W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
+ 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
T = +25°C.)
A
= V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at
DD A
CC
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
28
UNITS
Battery voltage, V+
, V
Input Voltage Range
V
V
4.5
5.5
CC
DD
FB = OUT
FB = GND
0.99
2.475
1.782
1.01
2.525
1.818
Error Comparator Threshold
(DC Output Voltage Accuracy)
(Note 1)
V+ = 4.5V to 28V,
SKIP = V
V
2.5
1.8
9
CC
FB = V
CC
Load Regulation Error
Line Regulation Error
FB Input Bias Current
Output Adjustment Range
I
= 0 to 3A, SKIP = V
mV
mV
µA
V
LOAD
CC
V
= 4.5V to 5.5V, V+ = 4.5V to 28V
5
CC
-0.1
1
+0.1
5.5
FB = GND
FB = V or adjustable feedback mode
90
70
190
145
1.7
160
200
290
425
400
550
<1
350
270
OUT Input Resistance
Soft-Start Ramp Time
kΩ
CC
Rising edge of SHDN to full current limit
ms
TON = GND (600kHz)
140
175
260
380
180
225
320
470
500
800
5
V+ = 24V,
TON = REF (450kHz)
V
= 2V
On-Time
ns
OUT
TON = unconnected (300kHz)
TON = V (200kHz)
(Note 2)
CC
Minimum Off-Time
(Note 2)
ns
µA
µA
µA
µA
µA
µA
V
Quiescent Supply Current (V
Quiescent Supply Current (V
)
)
FB forced above the regulation point
FB forced above the regulation point
CC
DD
Quiescent Supply Current (V+)
25
40
Shutdown Supply Current (V
Shutdown Supply Current (V
)
SHDN = GND
SHDN = GND
<1
5
CC
)
<1
5
DD
Shutdown Supply Current (V+)
Reference Voltage
SHDN = GND, V+ = 28V, V
= V
= 0 or 5V
DD
<1
5
CC
V
= 4.5V to 5.5V, no external REF load
1.98
2.00
2.02
0.01
CC
Reference Load Regulation
I
= 0 to 50µA
V
REF
2
_______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
T = +25°C.)
A
= V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at
DD A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µA
REF Sink Current
REF in regulation
10
REF Fault Lockout Voltage
Falling edge, hysteresis = 40mV
1.6
V
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
With respect to error comparator threshold, no load
OVP = GND, rising edge, hysteresis = 1%
12
14.5
17
%
External feedback, measured at FB with respect to
-30
+30
mV
V
, 1V < V
OVP
< 1.8V, rising edge, hysteresis =1%
OVP
Overvoltage Comparator Offset
(Adjustable-Threshold Mode)
Internal feedback, measured at OUT with respect to the
nominal OUT regulation voltage, 1V < V
rising edge, hysteresis = 1%
< 1.8V,
-3.5
+3.5
%
OVP
OVP Input Leakage Current
1V < V
< 1.8V
-100
0
+100
nA
µs
OVP
Overvoltage Fault
Propagation Delay
FB forced 2% above trip threshold
1.5
Output Undervoltage Protection
Trip Threshold (Fixed-Threshold
Mode)
With respect to error comparator threshold, UVP = V
External feedback, measured at FB with respect to
65
70
75
%
CC
-40
+40
mV
Output Undervoltage Protection
Trip Threshold (Adjustable-
Threshold Mode)
V
, 0.4V < V
< 1V
UVP
UVP
Internal feedback, measured at OUT with respect to the
nominal OUT regulation voltage, 0.4V < V < 1V
-5
-100
10
+5
+100
30
%
nA
ms
UVP
UVP Input Leakage Current
0.4V < V
< 1V
UVP
<1
Output Undervoltage Protection
Blanking Time
From rising edge of SHDN
With respect to error comparator threshold, no load
With respect to error comparator threshold, no load
FB forced 2% beyond PGOOD trip threshold, falling
PGOOD Trip Threshold (Lower)
PGOOD Trip Threshold (Upper)
PGOOD Propagation Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
-12.5
8
-10
10
10
-8
%
%
12.5
µs
V
I
= 1mA
0.4
1
SINK
High state, forced to 5.5V
µA
V
ILIM Adjustment Range
0.25
90
3
Current-Limit Threshold (Fixed)
GND - V , ILIM = V
100
50
110
60
230
mV
CS
CC
V
V
= 0.5V
= 2V
40
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
GND - V
mV
mV
CS
170
200
Current-Limit Threshold
(Negative Direction)
GND - V , SKIP = V , ILIM = V
,T = +25°C
A
-140
-117
-95
4.4
CS
CC
CC
Current-Limit Threshold
(Zero Crossing)
GND - V
SKIP = GND
3
mV
°C
V
CS,
Thermal Shutdown Threshold
Hysteresis = 10°C
150
V
Undervoltage
Rising edge, hysteresis = 20mV,
PWM disabled below this level
CC
4.1
Lockout Threshold
_______________________________________________________________________________________
3
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
T = +25°C.)
A
= V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted. Typical values are at
DD A
CC
PARAMETER
CONDITIONS
MAX1844EEP
MIN
TYP
1.5
1.5
1.5
1.5
0.5
0.5
MAX
5
UNITS
DH Gate-Driver On-Resistance
(Note 4)
BST - LX forced to 5V
Ω
MAX1844EGP, MAX1844ETP
MAX1844EEP
6
5
DL Gate-Driver On-Resistance
(Note 4)
DL, high state
Ω
Ω
A
MAX1844EGP, MAX1844ETP
MAX1844EEP
6
1.7
2.7
DL Gate-Driver On-Resistance
(Note 4)
DL, low state
MAX1844EGP, MAX1844ETP
DH Gate-Driver Source/Sink
Current
DH forced to 2.5V, BST-LX forced to 5V
1
DL Gate-Driver Source Current
DL Gate-Driver Sink Current
DL forced to 2.5V
DL forced to 5V
DL rising
1
3
A
A
35
26
Dead Time
ns
DH rising
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
LATCH, SHDN, SKIP
LATCH, SHDN, SKIP
LATCH, SHDN, SKIP
OVP, UVP, FB
OVP, UVP
2.4
V
V
0.8
+1
-1
µA
V
Dual Mode Threshold, Low
0.15
0.20
2.0
0.25
V
V
- 1.5
V
- 0.4
CC
CC
Dual Mode Threshold, High
V
FB
1.9
- 0.4
CC
2.1
TON V
Level
V
V
CC
TON Float Voltage
3.15
1.65
3.85
2.35
0.5
TON Reference Level
TON GND Level
V
V
TON Input Current
Forced to GND or V
-3
+3
µA
nA
CC
ILIM Input Leakage Current
-100
0
+100
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
DD A
CC
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
28
UNITS
Battery voltage, V+
, V
Input Voltage Range
V
V
4.5
5.5
CC
DD
FB = OUT
FB = GND
0.985
2.462
1.773
140
175
260
380
1.015
2.538
1.827
180
Error Comparator Threshold
(DC Output Voltage Accuracy)
(Note 1)
V+ = 4.5V to 28V,
SKIP = V
V
CC
FB = V
CC
TON = GND
(600kHz)
V+ = 24V,
= 2V
TON = REF(450kHz)
225
On-Time
V
ns
OUT
TON = Unconnected (300kHz)
TON = V (200kHz)
320
(Note 2)
470
CC
4
_______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
DD A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
500
800
5
UNITS
ns
Minimum Off-Time
(Note 2)
Quiescent Supply Current (V
Quiescent Supply Current (V
)
)
FB forced above the regulation point
FB forced above the regulation point
Measured at V+
µA
µA
µA
µA
µA
µA
V
CC
DD
Quiescent Supply Current (V+)
40
5
Shutdown Supply Current (V
Shutdown Supply Current (V
)
SHDN = GND
CC
)
SHDN = GND
5
DD
Shutdown Supply Current (V+)
Reference Voltage
SHDN = GND, V+ = 28V, V
= V
= 0 or 5V
DD
5
CC
V
= 4.5V to 5.5V, no external REF load
1.98
12
2.02
CC
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
With respect to error comparator threshold, no load
OVP = GND, rising edge, hysteresis = 1%
17
%
mV
%
External feedback, measured at FB with respect to
-30
-3.5
-12.5
7.5
+30
+3.5
-7.5
12.5
V
, 1V < V
OVP
1.8V, rising edge, hysteresis = 1%
OVP
Overvoltage Comparator Offset
(Adjustable-Threshold Mode)
Internal feedback, measured at OUT with respect to the
nominal OUT regulation voltage, 1V < V < 1.8V
OVP
With respect to error comparator threshold, no load
OUT falling edge, hysteresis = 1%
PGOOD Trip Threshold (Lower)
PGOOD Trip Threshold (Upper)
%
With respect to error comparator threshold, no load
OUT rising edge, hysteresis = 1%
%
PGOOD Output Low Voltage
PGOOD Leakage Current
I
= 1mA
0.4
1
V
SINK
High state, forced to 5.5V
GND - V , ILIM = V
µA
mV
Current-Limit Threshold (Fixed)
85
35
115
65
CS
CC
GND - V , V
= 0.5V
= 2V
CS ILIM
Current-Limit Threshold
(Adjustable)
mV
V
GND - V , V
160
240
CS ILIM
V
Undervoltage
Rising edge, hysteresis = 20mV,
PWM disabled below this level
CC
4.1
2.4
4.4
Lockout Threshold
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
LATCH, SHDN, SKIP
LATCH, SHDN, SKIP
LATCH, SHDN, SKIP
V
V
0.8
1
-1
µA
Note 1: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error com-
parator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage will have a
DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V
= 5V,
BST
and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 3: Specifications to -40°C are guaranteed by design, not production tested.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN
package. The MAX1844EEP, MAX1844EGP, and MAX1844ETP contain the same die and the QFN package imposes no
additional resistance in-circuit.
_______________________________________________________________________________________
5
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, V = 15V, SKIP = GND, TON = unconnected, T = +25°C, unless otherwise noted.)
A
IN
EFFICIENCY vs. LOAD CURRENT
FREQUENCY vs. LOAD CURRENT
FREQUENCY vs. INPUT VOLTAGE
100
95
350
300
320
310
300
290
280
V
V
= 7V, SKIP = V
CC
IN
90
250
= 15V, SKIP = V
IN
CC
85
80
V
= 7V
IN
200
150
V
= 12V
IN
V
= 20V
IN
75
70
65
60
V
= 7V, SKIP = GND
IN
100
I
= 1A
LOAD
50
0
V
= 15V, SKIP = GND
1
IN
0.01
0.1
1
10
0.01
0.1
10
0
5
10
15
20
25
30
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
CONTINUOUS-TO-DISCONTINUOUS INDUCTOR
CURRENT vs. INPUT VOLTAGE
FREQUENCY vs. TEMPERATURE
CURRENT LIMIT vs. INPUT VOLTAGE
800
330
8
7
6
5
4
3
2
1
0
CONTINUOUS INDUCTOR CURRENT
700
I
I
= 4A
LOAD
600
500
400
300
200
100
0
320
310
300
290
DISCONTINUOUS INDUCTOR CURRENT
= 1A
LOAD
0
5
10
15
20
25
30
-40 -25 -10
5
20 35 50 65 80
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
NORMALIZED OVERVOLTAGE
OVERVOLTAGE TRIP THRESHOLD
vs. TEMPERATURE
CURRENT LIMIT vs. TEMPERATURE
TRIP THRESHOLD vs. V
OVP
6
1.8
1.6
1.4
1.2
1.0
120
118
116
114
112
110
OVERVOLTAGE TRIP THRESHOLD
OUTPUT VOLTAGE SET POINT
5
4
3
1.0
1.2
1.4
(V)
1.6
1.8
-40 -25 -10
5
20 35 50 65 80
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
TEMPERATURE (°C)
OVP
6
_______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 15V, SKIP = GND, TON = unconnected, T = +25°C, unless otherwise noted.)
A
IN
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PWM MODE)
LOAD-TRANSIENT RESPONSE
(PWM MODE)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP MODE)
MAX1844 toc12A
10
8
0.8
0.6
0.4
0.2
0
I
IN
V
OUT
AC COUPLED
100mV/div
6
I
CC
INDUCTOR
CURRENT
2A/div
I
I
DD
CC
4
2
DL
5V/div
I
DD
I
IN
0
0
5
10
15
20
25
30
20µs/div
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD-TRANSIENT RESPONSE
(SKIP MODE)
OUTPUT OVERLOAD WAVEFORM
(UVP = GND)
OUTPUT OVERLOAD WAVEFORM
(UVP = V , OVP = GND)
CC
MAX1844 toc12B
MAX1844 toc13A
MAX1844 toc13B
V
V
OUT
1V/div
V
OUT
1V/div
OUT
AC COUPLED
100mV/div
INDUCTOR
CURRENT
5A/div
INDUCTOR
CURRENT
5A/div
INDUCTOR
CURRENT
2A/div
DL
5V/div
DL
5V/div
DL
5V/div
R
= 112mΩ
LOAD
R
= 112mΩ
LOAD
20µs/div
40µs/div
40µs/div
SHUTDOWN WAVEFORM
(OVP = GND)
SHUTDOWN WAVEFORM
(OVP = V
STARTUP WAVEFORM
)
CC
MAX1844 toc15A
MAX1844 toc14
MAX1844 toc15B
V
V
OUT
1V/div
V
OUT
1V/div
OUT
1V/div
INDUCTOR
CURRENT
5A/div
INDUCTOR
CURRENT
5A/div
INDUCTOR
CURRENT
5A/div
DL
5V/div
DL
5V/div
DL
5V/div
SHDN
5V/div
R
= 1Ω
LOAD
R
= 1Ω
LOAD
100µs/div
500µs/div
100µs/div
_______________________________________________________________________________________
7
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Pin Description
PIN
NAME
FUNCTION
QSOP
QFN
Current-Sense Input. Connect a low-value current-sense resistor between CS and GND for accurate
current sensing. For lower power dissipation (less accurate) current sensing, connect CS to LX to
use the synchronous rectifier as the sense resistor. The PWM controller will not begin a cycle unless
the current sensed at CS is less than the current-limit threshold programmed at ILIM.
1
18
CS
Overvoltage Protection Latch Control Input. The synchronous rectifier MOSFET is always forced to
the on state when an overvoltage fault is detected. If LATCH is low, the synchronous rectifier remains
2
3
19
20
LATCH
SHDN
on until either OVP is brought high, SHDN is toggled, or V
is cycled below 1V. If LATCH is high,
CC
normal operation resumes when the overvoltage condition ends.
Shutdown Control Input. Drive SHDN to GND to force the MAX1844 into shutdown. Drive or connect
to
for normal operation. A rising edge on SHDN clears the overvoltage and undervoltage
VCC
protection fault latches.
Overvoltage Protection Control Input. An overvoltage fault occurs if the internal or external feedback
voltage exceeds the voltage at OVP. Apply a voltage between 1V and 1.8V to set the overvoltage
limit between 100% and 180% of nominal output voltage. Connect to GND to assert the default
4
1
OVP
overvoltage limit at 114% of the nominal output voltage. Connect to V
detection and clear the overvoltage protection fault latch.
to disable overvoltage fault
CC
Feedback Input. Connect to V
adjustable output (1V to 5.5V), connect FB to a resistive-divider from the output voltage. The FB
regulation level is 1V.
for a 1.8V fixed output or to GND for a 2.5V fixed output. For an
CC
5
6
2
3
FB
Output Voltage Sense Connection. Connect directly to the junction of the external output filter
capacitors. OUT senses the output voltage to determine the on-time for the high-side switching
MOSFET. OUT also serves as the feedback input in fixed-output modes.
OUT
Current-Limit Threshold Adjustment. The current-limit threshold at CS is 0.1 times the voltage at ILIM.
Connect ILIM to a resistive-divider (typically from REF) to set the current-limit threshold between
7
8
4
5
ILIM
REF
25mV and 300mV (with 0.25V to 3V at ILIM). Connect to V to assert the 100mV default current-limit
CC
threshold.
2V Reference Voltage Output. Bypass to GND with a 0.22µF (min) bypass capacitor. Can supply
50µA for external loads. Reference turns off in shutdown.
Undervoltage Protection Control Input. An undervoltage fault occurs if the internal or external
feedback voltage is less than the voltage at UVP. Apply a voltage between 0.4V and 1V to set the
undervoltage limit between 40% and 100% of the nominal output voltage. Connect to V
to assert
9
6
UVP
CC
the default undervoltage limit of 70% of the nominal output voltage. Connect to GND to disable
undervoltage fault detection and clear the undervoltage protection latch.
Power-Good Open-Drain Output. PGOOD is low when the output voltage is more than 10% above or
below the normal regulation point or during soft-start. PGOOD is high impedance when the output is
in regulation and the soft-start circuit has terminated. PGOOD is low in shutdown.
10
7
PGOOD
11
12
8
9
GND
DL
Analog and Power Ground
Synchronous Rectifier Gate-Driver Output. Swings from GND to V
.
DD
Supply Input for the DL Gate Drive. Connect to the system supply voltage, 4.5V to 5.5V. Bypass to
GND with a 1µF (min) ceramic capacitor.
V
13
10
DD
8
_______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Pin Description (continued)
PIN
NAME
FUNCTION
QSOP
QFN
Analog Supply Input. Connect to the system supply voltage, 4.5V to 5.5V, with a series 20Ω resistor.
Bypass to GND with a 1µF (min) ceramic capacitor.
V
14
11
CC
On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect to
GND, REF, V , or leave TON unconnected to select the following nominal switching frequencies:
15
12
TON
V+
CC
GND = 600kHz, REF = 450kHz, floating = 300kHz, and V
= 200kHz.
CC
Battery Voltage Sense Connection. Connect to input power source. V+ is used only to set the PWM
one-shot timing.
16
17
18
13
14
15
Pulse-Skipping Control Input. Connect to V
enable pulse-skipping operation.
for low-noise, forced-PWM mode. Connect to GND to
CC
SKIP
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the
Standard Application Circuit (Figure 1). See the MOSFET Gate Drivers (DH, DL) section.
BST
External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the
lower supply rail for the DH high-side gate driver.
19
20
16
17
LX
DH
High-Side Gate-Driver Output. Swings from LX to BST.
Table 2. Component Suppliers
Table 1. Component Selection for
Standard Applications
SUPPLIER
Coilcraft
USA PHONE
847-639-6400
FACTORY FAX
1-847-639-1469
COMPONENT
2.5V AT 4A
Dale-Vishay
Fairchild
IRC
203-452-5664
408-822-2181
800-752-8708
408-986-0424
805-867-2555*
619-661-6835
847-956-0666
408-573-4150
847-390-4461
1-203-452-5670
1-408-721-1635
1-828-264-7204
1-408-986-1442
81-3-3494-7414
81-7-2070-1174
81-3-3607-5144
1-408-573-4159
1-847-390-4405
10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
C1 Input Capacitor
Kemet
330µF, 6V
Kemet T510X477108M006AS or
Sanyo 6TPB330M
NIEC (Nihon)
Sanyo
C2 Output Capacitor
D1 Schottky
Sumida
Nihon EP10QY03
Taiyo Yuden
TDK
4.7µH
Coilcraft DO33116P-682 or
L1 Inductor
Sumida CDRH124-4R7MC
*Distributor
Fairchild Semiconductor
1/2 FDS6982A
Q1 High-Side MOSFET
Q2 Low-Side MOSFET
Standard Application Circuit
The standard application circuit (Figure 1) generates a
2.5V rail for general-purpose use in a notebook computer.
Fairchild Semiconductor
1/2 FDS6982A
0.015Ω 1%, 0.5W resistor
IRC LR2010-01-R015F or
Dale WSL-2010-R015F
See Table 1 for component selections. Table 2 lists com-
ponent manufacturers.
R
SENSE
_______________________________________________________________________________________
9
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
V
IN
7V TO 20V
5V
C5
4.7µF
C6
3.3µF
R1
20Ω
BIAS SUPPLY
C1
10µF
D2
CMPSH-3
V
V
DD
CC
UVP
V+
BST
DH
ON/OFF
CONTROL
SHDN
SKIP
Q1
Q2
L1
4.7µH
LOW-NOISE
CONTROL
C7
0.1µF
V
OUT
2.5V
MAX1844
C2
330µF
LX
DL
CS
D1
ILIM
R
SENSE
OVP
FB
15mΩ
TON
REF
LATCH
OUT
C4
0.22µF
270kΩ
130kΩ
5V
GND
R2
100kΩ
POWER-GOOD
INDICATOR
PGOOD
SEE TABLE 1 FOR OTHER COMPONENT SELECTIONS.
Figure 1. Standard Application Circuit
5V Bias Supply (V
and V
)
CC
DD
Detailed Description
The MAX1844 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply. Keeping
the bias supply external to the IC improves efficiency
and eliminates the cost associated with the 5V linear reg-
ulator that would otherwise be needed to supply the
PWM circuit and gate drivers. If stand-alone capability is
needed, the 5V supply can be generated with an exter-
nal linear regulator such as the MAX1615.
The MAX1844 buck controller is targeted for low-voltage
power supplies for notebook computers. Maxim’s propri-
etary Quick-PWM pulse-width modulator in the MAX1844
is specifically designed for handling fast load steps while
maintaining a relatively constant operating frequency
and inductor operating point over a wide range of input
voltages. The Quick-PWM architecture circumvents the
poor load-transient timing problems of fixed-frequency
current-mode PWMs while also avoiding the problems
caused by widely varying switching frequencies in con-
ventional constant-on-time and constant-off-time PWM
schemes.
The battery and 5V bias inputs can be connected
together if the input source is a fixed 4.5V to 5.5V supply.
If the 5V bias supply is powered up prior to the
10 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
IN
2V TO 28V
V+
5V
TOFF
MAX1844
1-SHOT
TON
FROM
OUT
ON-TIME
COMPUTE
TRIG
Q
BST
DH
LX
TON
S
R
Q
Q
TRIG
1-SHOT
SKIP
OUTPUT
ERROR
AMP
SHDN
V
+5V
DD
REF
OVP
DL
1.14V
S
R
Q
0.1V
V
CC
- 1V
R
9R
LATCH
OVP/UVP
LATCH
ILIM
POR
20ms
TIMER
0.1V
CURRENT
LIMIT
V
- 1V
CS
CC
Σ
1.0V
0.7V
V
CC
- 1V
ZERO CROSSING
x2
GND
OUT
UVP
5V
CHIP
SUPPLY
REF
+10%
REF
-10%
V
CC
FEEDBACK
MUX
(SEE FIGURE 6)
PGOOD
2V REF
REF
FB
Figure 2. MAX1844 Functional Diagram
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
battery supply, the enable signal (SHDN) must be
delayed until the battery voltage is present in order to
ensure startup. The 5V bias supply provides V
and
The Quick-PWM control architecture is a pseudo-fixed-fre-
quency, constant-on-time on-demand PWM with voltage
feed-forward (Figure 2). This architecture relies on the out-
put filter capacitor’s ESR to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp sig-
nal. The control algorithm is simple: the high-side switch
on-time is determined solely by a one-shot whose pulse
CC
gate-drive power, so the maximum current drawn is:
I
= I + f (Q + Q ) = 5mA to 30mA (typ)
BIAS
CC
G1
G2
where I
is 550µA (typ), f is the switching frequency,
CC
and Q
and Q
are the MOSFET data sheet total
G1
G2
gate-charge specification limits at V = 5V.
GS
______________________________________________________________________________________ 11
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Table 3. Operating Mode Truth Table
DL
MODE
COMMENTS
SHDN SKIP
High or
Low
Low-power shutdown state. DL is forced to V if OVP is enabled and to GND if OVP is
DD
0
1
X
Shutdown
disabled. I
< 1µA typ.
CC
Low-noise operation with no automatic switchover. Fixed-frequency PWM action is
forced regardless of load. Inductor current reverses at light load levels. Low noise,
Run (PWM),
Low Noise
V
Switching
CC
high I .
Q
Run
Normal operation with automatic PWM/PFM switchover for pulse skipping at light loads.
1
1
GND Switching
High
(PFM/PWM) Best light-load efficiency.
Fault latch has been set by overvoltage protection, output UVLO, or thermal shutdown.
Device will remain in FAULT mode until V power is cycled or SHDN is toggled.
X
Fault
CC
easy design methodology and predictable output volt-
age ripple. The on-time is given by:
Table 4. Frequency Selection Guidelines
FREQUENCY
(kHz)
TYPICAL
APPLICATION
COMMENTS
On-Time = K (V
+ 0.075V) / V
IN
OUT
200
TON = V
Use for absolute best
efficiency.
where K (switching period) is set by the TON pin-strap
connection (Table 4), and 0.075V is an approximation to
accommodate for the expected drop across the low-side
MOSFET switch. One-shot timing error increases for the
shorter on-time settings due to fixed propagation delays;
it is approximately 12.5% at 600kHz and 450kHz, and
10% at the two slower settings. This translates to
reduced switching-frequency accuracy at higher frequen-
cies (Table 5). Switching frequency increases as a func-
tion of load current due to the increasing drop across the
low-side MOSFET, which causes a faster inductor-current
discharge ramp. The on-times guaranteed in the
Electrical Characteristics are influenced by switching
delays in the external high-side power MOSFET.
4-cell Li+ notebook
4-cell Li+ notebook
CC
300
TON = Float
Considered mainstream
by current standards.
Useful in 3-cell systems
for lighter loads than the
CPU core or where size is
key.
450
TON = REF
3-cell Li+ notebook
+5V input
Good operating point for
compound buck designs
or desktop circuits.
600
TON = GND
width is inversely proportional to input voltage and directly
proportional to output voltage. Another one-shot sets a
minimum off-time (400ns typ). The on-time one-shot is trig-
gered if the error comparator is low, the low-side switch
current is below the current-limit threshold, and the mini-
mum off-time one-shot has timed out.
Two external factors that influence switching-frequency
accuracy are resistive drops in the two conduction loops
(including inductor and PC board resistance) and the
dead-time effect. These effects are the largest contribu-
tors to the change of frequency with changing load cur-
rent. The dead-time effect increases the effective
on-time, reducing the switching frequency as one or
both dead times are added to the effective on-time. It
occurs only in PWM mode (SKIP = high) when the induc-
tor current reverses at light or negative load currents.
With reversed inductor current, the inductor’s EMF caus-
es LX to go high earlier than normal, extending the on-
time by a period equal to the low-to-high dead time.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V+ input, and proportional
to the output voltage. This algorithm results in a nearly
constant switching frequency despite the lack of a fixed-
frequency clock generator. The benefits of a constant
switching frequency are twofold: first, the frequency can
be selected to avoid noise-sensitive regions such as the
455kHz IF band; second, the inductor ripple-current
operating point remains relatively constant, resulting in
For loads above the critical conduction point, the actual
switching frequency is:
V
+ V
OUT
DROP1
f =
t
(V + V
)
ON IN
DROP2
12 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
I
PEAK
∆i
∆t
V
-V
BATT OUT
=
L
I
PEAK
I
I
LOAD
LIMIT
I
= I
/2
LOAD PEAK
0
ON-TIME
TIME
0
TIME
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
Figure 4. ‘‘Valley’’ Current-Limit Threshold Point
where V
is the sum of the parasitic voltage drops
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response
(especially at low input voltage levels).
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
the sum of the resistances in the charging path, and t
is the on-time calculated by the MAX1844.
is
DROP2
ON
Automatic Pulse-Skipping Switchover
In skip mode (SKIP low), an inherent automatic
switchover to PFM takes place at light loads (Table 3).
This switchover is effected by a comparator that trun-
cates the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between continu-
ous and discontinuous inductor-current operation (also
known as the “critical conduction” point; see the
Continuous to Discontinuous Inductor Current vs. Input
Voltage graph in the Typical Operating Characteristics).
In low-duty-cycle applications, this threshold is relatively
constant, with only a minor dependence on battery
voltage.
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the output voltage will have a DC regu-
lation level higher than the trip level by 50% of the ripple.
In discontinuous conduction (SKIP = GND, light load),
the output voltage will have a DC regulation level higher
than the error-comparator threshold by approximately
1.5% due to slope compensation.
Forced-PWM Mode (SKIP = High)
The low-noise forced-PWM mode (SKIP = high) disables
the zero-crossing comparator, which controls the low-
side switch on-time. This causes the low-side gate-drive
waveform to become the complement of the high-side
gate-drive waveform. This in turn causes the inductor
current to reverse at light loads while DH maintains a
KV
2L
V -V
IN OUT
OUT
I
≈
×
LOAD(SKIP)
V
IN
where K is the on-time scale factor (Table 5). The load-
current level at which PFM/PWM crossover occurs,
duty factor of V
/V . The benefit of forced-PWM
OUT IN
mode is to keep the switching frequency fairly constant,
but it comes at a cost: the no-load battery current can be
10mA to 40mA, depending on the external MOSFETs.
I
, is equal to 1/2 the peak-to-peak ripple cur-
LOAD(SKIP)
rent, which is a function of the inductor value (Figure 3).
For example, in the standard application circuit with
K = 3.3µs (Table 5), V
= 2.5V, V = 15V, and L =
IN
OUT
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response, pro-
viding sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of
multiple-output applications that use a flyback trans-
former or coupled inductor.
6.8µH, switchover to pulse-skipping operation occurs at
= 0.51A or about 1/8 full load. The crossover point
I
LOAD
occurs at an even lower value if a swinging (soft-satura-
tion) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
______________________________________________________________________________________ 13
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Current-Limit Circuit (ILIM)
+5V
V
IN
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm (Figure 4). If the magnitude of the
current-sense voltage at CS is above the current-limit
threshold, the PWM is not allowed to initiate a new cycle.
The actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the sense
resistance, inductor value, and battery voltage.
5Ω
BST
DH
LX
MAX1844
There is also a negative current limit that prevents exces-
sive reverse inductor currents when V
is sinking cur-
OUT
rent. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
Figure 5. Reducing the Switching-Node Rise Time
properly; otherwise, the sense circuitry in the MAX1844
will interpret the MOSFET gate as “off” while there is
actually still charge left on the gate. Use very short, wide
traces measuring no more than 20 squares (50 to 100
mils wide if the MOSFET is 1 inch from the MAX1844).
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 1µA (min) divider current is
recommended. The current-limit threshold adjustment
range is from 25mV to 300mV. In the adjustable mode,
the current-limit threshold voltage is precisely 1/10 the
voltage seen at ILIM. The threshold defaults to 100mV
The dead time at the other edge (DH turning off) is deter-
mined by a fixed 35ns (typ) internal delay.
when ILIM is connected to V . The logic threshold for
CC
The internal pulldown transistor that drives DL low is
robust, with a 0.5Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, there
are still some combinations of high- and low-side FETs
that will cause excessive gate-drain coupling, which can
lead to efficiency-killing, EMI-producing shoot-through
currents. This is often remedied by adding a resistor in
series with BST, which increases the turn-on time of the
high-side FET without degrading the turn-off time
(Figure 5).
switchover to the 100mV default value is approximately
V
CC
- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS. Mount or place the IC
close to the low-side MOSFET and sense resistor with
short, direct traces, making a Kelvin sense connection to
the sense resistor.
In Figure 1, the Schottky diode (D1) provides a current
path parallel to the Q2/R
current path. Accurate
SENSE
current sensing demands D1 to be off while Q2 con-
ducts. Avoid large current-sense voltages that, com-
bined with the voltages across Q2, would allow D1 to
conduct. If very large sense voltages are used, connect
D1 in parallel with Q2.
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and soft-start
counter, and preparing the PWM for operation. Until V
CC
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moder-
ate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
reaches 4.2V, V
undervoltage lockout (UVLO) circuitry
CC
inhibits switching. DL is held low if overvoltage protec-
tion is disabled, and held high if overvoltage protection is
enabled. See the Output Overvoltage Protection section.
seen in the notebook environment, where a large V
OUT
-
BATT
When V
rises above 4.2V, an internal digital soft-start
CC
V
differential exists. An adaptive dead-time circuit
timer begins to ramp up the maximum allowed current
limit. The ramp occurs in five steps: 20%, 40%, 60%,
80%, and 100%; 100% current is available after 1.7ms
50%.
monitors the DL output and prevents the high-side FET
from turning on until DL is fully off. There must be a low-
resistance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
14 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
OUT
V
BATT
DH
TO ERROR AMP
MAX1844
FIXED
1.8V
V
OUT
MAX1844
DL
CS
FB
FIXED
2.5V
R1
R2
OUT
FB
GND
0.2V
2V
Figure 7. Setting V
with a Resistor-Divider
OUT
DL is kept high continuously in shutdown mode or
when UVLO is active.
Note that forcing DL high in shutdown causes the out-
put voltage to go slightly negative when energy has
been previously stored in the LC tank circuit (see the
shutdown waveforms in the Typical Operating
Characteristics). If the load cannot tolerate being
forced to a negative voltage, it may be desirable to
place a power Schottky diode across the output to act
as a reverse-polarity clamp.
Figure 6. Feedback Mux
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors
the output. PGOOD is actively held low in shutdown,
standby, and soft-start. After digital soft-start terminates,
PGOOD is released if the output is within 10% of the
nominal output voltage setting. Note that the PGOOD
window detector is completely independent of the over-
voltage and undervoltage protection fault detectors.
Output Undervoltage Protection
UVP controls the output undervoltage protection func-
tion. Connect UVP to GND to disable undervoltage pro-
tection. The output undervoltage protection function is
similar to foldback current limiting but employs a timer
and latch rather than a variable current limit. If the output
voltage is below the undervoltage protection threshold
after the output undervoltage protection blanking time
has elapsed, the PWM is latched off and does not restart
Output Overvoltage Protection
OVP controls the output overvoltage protection func-
tion. Connect OVP to V
to disable overvoltage pro-
CC
tection. If overvoltage protection is enabled, the output
is continuously monitored. If the output exceeds the
overvoltage protection threshold, overvoltage protec-
tion is triggered and the DL low-side gate-driver output
is forced high. This turns on the low-side MOSFET
switch to rapidly discharge the output capacitor and
reduce the output voltage.
until V
power is cycled. SHDN is toggled, or UVP is
CC
brought low.
Connect UVP to V
to enable the default undervoltage
CC
trip threshold of 70% of nominal. To select a different
threshold, drive UVP to a voltage between 0.4V and 1V
for a threshold between 40% and 100% of nominal.
If LATCH is high, normal operation resumes when the
overvoltage condition ends. If LATCH is low, the DL
gate-driver output remains high until OVP is brought
high, SHDN is toggled, or V
is cycled below 1V.
CC
When the condition that caused the overvoltage per-
sists (such as a shorted high-side MOSFET), the bat-
tery fuse will open. If overvoltage protection is enabled,
______________________________________________________________________________________ 15
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
ues lower than this grant no further size-reduction
benefit.
Fixed Output Voltages
The MAX1844’s Dual ModeTM operation allows the selec-
tion of common voltages without requiring external com-
ponents (Figure 6). Connect FB to GND for a fixed 2.5V
The MAX1844’s pulse-skipping algorithm initiates skip
mode at the critical conduction point. So, the inductor
operating point also determines the load-current value
at which PFM/PWM switchover occurs.
output or to V
for a 1.8V output, or connect FB directly
CC
to OUT for a fixed 1V output.
These four factors impact the component selection
process. Selecting components and calculating their
effect on the MAX1844’s operation is best done with a
spreadsheet. Using the formulas provided, calculate the
LIR (the ratio of the inductor ripple current to the
designed maximum load current) for both the minimum
and maximum input voltages. Maintaining an LIR within a
20% to 50% range is recommended. The use of a
spreadsheet allows quick evaluation of component
selection.
Setting V
with a Resistor-Divider
OUT
The output voltage can be adjusted from 1V to 5.5V with
a resistor-divider if desired (Figure 7). The equation for
adjusting the output voltage is:
R1
R2
V
= V 1 +
FB
OUT
where V is 1V.
FB
Design Procedure
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
Component selection for the MAX1844 is primarily dictat-
ed by the following four criteria:
1) Input voltage range. The maximum value (V
)
IN(MAX)
V
(V - V
)
must accommodate the worst-case high AC-adapter
voltage. The minimum value (V ) must account
OUT IN
OUT
L =
V
× f × LIR × I
LOAD(MAX)
IN(MIN)
IN
for the lowest battery voltage after drops due to con-
nectors, fuses, and battery selector switches. Lower
input voltages result in better efficiency.
Example: I
= 8A, V
7V, V
= 1.5V,
OUT
LOAD(MAX)
f = 300kHz, 33% ripple current or LIR = 0.33.
IN =
2) Maximum load current. There are two values to con-
1.5V (7V-1.5V)
7V × 300kHz× 0.33× 8A
sider. The peak load current (I
) determines
LOAD(MAX)
L =
= 1.49µH
the instantaneous component stresses and filtering
requirements and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered iron
is inexpensive and can work well at 200kHz. The core
must be large enough not to saturate at the peak induc-
(I ) determines the thermal stresses and thus dri-
LOAD
ves the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
tor current (I
).
PEAK
3) Switching frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
✕
I
= I
+ [(LIR / 2)
I
]
PEAK
LOAD(MAX)
LOAD(MAX)
Most inductor manufacturers provide inductors in stan-
dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage range.
If using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values.
2
proportional to frequency and V . The optimum fre-
IN
quency is also a moving target, due to rapid improve-
ments in MOSFET technology that are making higher
frequencies more practical (Table 4).
4) Inductor operating point. This choice provides
trade-offs between size vs. efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output rip-
ple. The minimum practical inductor value is one that
causes the circuit to operate at the edge of critical
conduction (where the inductor current just touches
zero with every cycle at maximum load). Inductor val-
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V - V
dif-
OUT
IN
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
Dual Mode is a trademark of Maxim Integrated Products.
16 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
a)
b)
2
LX
DL
CS
LX
DL
CS
(∆I
) × L
LOAD(MAX)
V
=
SAG
MAX1844
MAX1844
2 × C
× DUTY (V
- V
)
OUT
IN(MIN)
OUT
where
DUTY =
K (V
+ 0.075V)/ V
IN
OUT
K (V
+ 0.075V)/ V
+ min off - time
OUT
OUT
and minimum off-time = 400ns (typ) (see Table 5 for K
values).
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculated
as:
Figure 8. Current-Sense Circuits
2
Output Capacitor Selection
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to sat-
isfy stability requirements.
L × ∆I
(
)
LOAD(MAX)
V
≈
SOAR
2C
V
OUT OUT
Setting the Current Limit
For most applications, set the MAX1844 current limit by
the following procedure:
For CPU core voltage converters and other applications
where the output is subject to violent load transients, the
output capacitor’s size depends on how much ESR is
needed to prevent the output from dipping too low under
a load transient. Ignoring the sag due to finite capaci-
tance:
1) Determine the minimum (valley) inductor current
I
under conditions when V is small, V
is
L(MIN)
IN
OUT
large, and load current is maximum. The minimum
inductor current is I
rent (Figure 4).
minus half the ripple cur-
LOAD
V
DIP
LOAD(MAX)
R
≤
ESR
2) The sense resistor determines the achievable
current-limit accuracy. There is a trade-off between
current-limit accuracy and sense-resistor power dis-
sipation. Most applications employ a current-sense
voltage of 50mV to 100mV. Choose a sense resistor
so that:
I
In non-CPU applications, the output capacitor’s size often
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
V
P-P
R
≤
ESR
LIR ×I
R
= CS Threshold Voltage / I
L(MIN)
LOAD(MAX)
SENSE
Extremely cost-sensitive applications that do not
require high-accuracy current sensing can use the on-
resistance of the low-side MOSFET switch in place of
the sense resistor by connecting CS to LX (Figure 8b).
The actual microfarad capacitance value required relates
to the physical size needed to achieve low ESR, as well
as to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums,
OS-CONs, and other electrolytics).
Use the worst-case value for R
from the MOSFET
DS(ON)
Q2 data sheet, and add a margin of 0.5%/°C for the
rise in R with temperature. Then use that
DS(ON)
value and I
When using low-capacity filter capacitors, such as
ceramic or polymer types, capacitor size is usually deter-
R
from step 1 above to deter-
DS(ON)
L(MIN)
mine the CS threshold voltage. If the default 100mV
threshold is unacceptable, set the value as in step 2
above.
mined by the capacity needed to prevent V
SOAR
and
SAG
V
from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
In all cases, ensure an acceptable CS threshold volt-
age despite inaccuracies in resistor values.
edge is no longer a problem (also, see the V
SOAR
and
SAG
V
equation in the Transient Response section).
______________________________________________________________________________________ 17
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
allow more than one cycle of ringing after the initial
step-response under- or overshoot.
Output Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The point of instability is
given by the following equation:
Input Capacitor Selection
The input capacitor must meet the ripple current
f
π
requirement (I
) imposed by the switching currents.
RMS
f
=
ESR
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power-up
surge currents.
where:
1
f
=
V
V
- V
ESR
OUT IN OUT
(
)
2× π ×R
×C
OUT
ESR
I
= I
LOAD
RMS
V
IN
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the peak ripple
current.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequencies
of 25kHz. In the design example used for inductor selec-
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
tion, the ESR needed to support 60mV
ripple is
P-P
60mV/2.7A = 22mΩ. Two 470µF/4V Kemet T510 low-ESR
tantalum capacitors in parallel provide 22mΩ (max) ESR.
Their typical combined ESR results in a zero at 27kHz,
well within the bounds of stability.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at minimum input
voltage do not exceed the package thermal limits or
violate the overall thermal budget. Check to ensure that
conduction losses plus switching losses at the maxi-
mum input voltage do not exceed the package ratings
or violate the overall thermal budget.
Do not put high-value ceramic capacitors directly across
the feedback sense point without taking precautions to
ensure stability. Large ceramic capacitors can have a
high ESR zero frequency and cause erratic, unstable
operation. However, it’s easy to add enough series resis-
tance by placing the capacitors a couple of inches
downstream from the feedback sense point, which
should be as close as possible to the inductor.
Unstable operation manifests itself in two related but dis-
tinctly different ways: double-pulsing and fast-feedback
loop instability.
Choose a low-side MOSFET (Q2) that has the lowest
possible R , comes in a moderate to small pack-
DS(ON)
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1844 DL gate driver can drive Q2; in other
words, check that the gate is not pulled up by the high-
side switch turn on, due to parasitic drain-to-gate capac-
itance, causing cross-conduction problems. Switching
losses are not an issue for the low-side MOSFET since it
is a zero-voltage switched device when used in the buck
topology.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immediately
after the 400ns minimum off-time period has expired.
Double-pulsing is more annoying than harmful, resulting
in nothing worse than increased output ripple. However,
it can indicate the possible presence of loop instability,
which is caused by insufficient ESR.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to monitor simultaneously
the inductor current with an AC current probe. Don’t
2
✕
✕
PD(Q1 Resistive) = (V
/ V
)
I
R
DS(ON)
OUT
IN(MIN)
LOAD
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages. However,
the R
required to stay within package power-dissi-
DS(ON)
18 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
pation limits often limits how small the MOSFET can be.
Applications Information
Again, the optimum occurs when the switching (AC)
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slower (200kHz) on-time settings.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on-
and off-times. Manufacturing tolerances and internal
propagation delays introduce an error to the TON K-
factor. This error is greater at higher frequencies (Table
5). Also, keep in mind that transient response perfor-
mance of buck regulators operated close to dropout is
poor, and bulk output capacitance must often be
losses equal the conduction (R ) losses. High-side
DS(ON)
switching losses do not usually become an issue until
the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2f switching loss equation. If the high-side MOSFET
chosen for adequate R
at low battery voltages
DS(ON)
becomes extraordinarily hot when subjected to
, reconsider the choice of MOSFET.
V
IN(MAX)
Calculating the power dissipation in Q1 due to switching
losses is difficult, since it must allow for difficult-to-quanti-
fy factors that influence the turn-on and turn-off times.
These factors include the internal gate resistance, gate
charge, threshold voltage, source inductance, and PC
board layout characteristics. The following switching loss
calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including
a sanity check using a thermocouple mounted on Q1.
added (see the V
Response section).
equation in the Transient
SAG
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
)
DOWN
as much as it ramps up during the on-time (∆I ). The
UP
ratio h = ∆I /∆I
indicates the circuit’s ability to
UP DOWN
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current will be less able to increase during
2
C
× V
× f × I
LOAD
RSS
IN(MAX)
PD(Q1 switching)=
I
GATE
each switching cycle, and V
will greatly increase
SAG
where C is the reverse transfer capacitance of Q1,
RSS
unless additional output capacitance is used.
and I
typ).
is the peak gate-drive source/sink current (1A
GATE
A reasonable minimum value for h is 1.5, but this may
be adjusted up or down to allow trade-offs between
, output capacitance, and minimum operating
voltage. For a given value of h, the minimum operating
voltage can be calculated as:
V
For the low-side MOSFET, Q2, the worst-case power dis-
sipation always occurs at maximum battery voltage:
SAG
2
✕
✕
PD(Q2) = (1 - V
/ V
)
I
R
DS(ON)
OUT
IN(MAX)
LOAD
V
+ V
DROP1
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
LOAD(MAX)
(
1-
OUT
)
V
=
+ V
- V
IN(MIN)
DROP2 DROP1
t
× h
OFF(MIN)
K
I
but are not quite high enough to exceed the
current limit. To protect against this possibility, you must
“overdesign” the circuit to tolerate I
= I
+
LOAD
LIMIT(HIGH)
is the maxi-
✕
[(LIR / 2)
I
], where I
LOAD(MAX)
LIMIT(HIGH)
where V
and V
are the parasitic voltage
DROP2
DROP1
mum valley current allowed by the current-limit circuit,
including threshold tolerance and sense-resistance vari-
ation. If short-circuit protection without overload protec-
tion is adequate, enable undervoltage protection, and
drops in the discharge and charge paths, t
is
OFF(MIN)
from the Electrical Characteristics table, and K is taken-
from Table 5. The absolute minimum input voltage is cal-
culated with h = 1.
use I ) to calculate component stresses.
LOAD(MAX
If the calculated V
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
is greater than the required
IN(MIN)
Choose a Schottky diode D1 having a forward voltage
drop low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional, and if
efficiency isn’t critical it can be removed.
acceptable V
. If operation near dropout is anticipat-
SAG
ed, calculate V
response.
to be sure of adequate transient
SAG
______________________________________________________________________________________ 19
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
BOTTOM SIDE
TOP SIDE
V
IN
Q1
Q2
AGND PLANE
VIA R
VIA TO IC
CS PIN
S
C1
Q
V
CC
BYPASS
REF
BYPASS
D1
V
DD
L1
VIA TO PGND PLANE
AND IC GND PIN
BYPASS
PGND
PLANE
VIA TO POWER
GROUND
C2
USE AGND PLANE TO:
V
POWER
GROUND
OUT
- BYPASS V AND REF
CC
VIA TO IC OUT
- TERMINATE EXTERNAL FB, ILIM,
OVP, UVP DIVIDERS
- PIN-STRAP CONTROL INPUTS
USE PGND PLANE TO:
- BYPASS V
DD
- CONNECT IC GND PIN
TO TOP-SIDE POWER GROUND
Figure 9. Power-Stage PC Board Layout Example
V
= V
= 100mV
DROP1
DROP2
Table 5. Approximate K-Factor Errors
h = 1.5
TON
K
APPROXIMATE
K-FACTOR
ERROR (%)
MINIMUM V
IN
SETTING FACTOR
AT V
= 2V
OUT
(V)
(kHz)
200
300
450
600
(µs)
5
2.5V + 0.1V
(
)
V
=
+ 0.1V - 0.1V = 3.48V
IN(MIN)
10
10
2.6
2.9
3.2
3.6
0.5µs × 1.5
2.97µs
1-
3.3
2.2
1.7
12.5
12.5
Calculating again with h = 1 gives the absolute limit of
dropout:
Dropout Design Example:
= 2.5V
2.5V + 0.1V
(
)
V
V
=
- 0.1V + 0.1V = 3.13V
OUT
IN(MIN)
0.5µs × 1
fsw = 300kHz
1-
2.97µs
K = 1.8µs, worst-case K = 2.97µs
t
= 500ns
OFF(MIN)
20 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Therefore, V must be greater than 3.13V, even with
IN
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 3.48V.
4) Make the DC-DC controller ground connections as
shown in Figure 9. This diagram can be viewed as
having two separate ground planes: power ground,
where all the high-power components go; and an ana-
log ground plane for sensitive analog components.
The analog ground plane and power ground plane
must meet only at a single point directly at the IC.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The switch-
ing power stage requires particular attention (Figure 9). If
possible, mount all of the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
5) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
Pin Configuration
TOP VIEW
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
CS
LATCH
SHDN
OVP
1
2
3
4
5
6
7
8
9
20 DH
19 LX
18 BST
17 SKIP
16 V+
15 TON
14
MAX1844EEP
FB
OUT
ILIM
REF
• Minimize current sensing errors by connecting CS
V
V
CC
DD
directly to the R
terminal.
SENSE
13
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
UVP
12 DL
PGOOD 10
11 GND
20 QSOP
20 19
16
18
17
• Route high-speed switching nodes (BST, LX, DH, and
15 BST
14 SKIP
DL) away from sensitive analog areas (REF, FB, CS).
1
OVP
FB
2
3
4
5
Layout Procedure
1) Place the power components first, with ground termi-
V+
13
12
OUT
ILIM
REF
nals adjacent (Q2 source, C , C
, D1 anode). If
OUT-
IN-
MAX1844EGP
MAX1844ETP
TON
possible, make all these connections on the top layer
with wide, copper-filled areas.
V
CC
11
2) Mount the controller IC adjacent to MOSFET Q2,
preferably on the back side opposite Q2 in order to
keep LX, GND, and the DL gate-drive lines short and
wide. The DL gate trace must be short and wide,
measuring 10 to 20 squares (50 to 100 mils wide if the
MOSFET is 1 inch from the controller IC GND pin.
8
6
7
9
10
20 THIN QFN
3) Group the gate-drive components (BST diode and
Chip Information
capacitor, V
bypass capacitor) together near the
DD
controller IC.
TRANSISTOR COUNT: 2963
PROCESS: BiCMOS
______________________________________________________________________________________ 21
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
22 ______________________________________________________________________________________
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 23
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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