MAX1858EEG [MAXIM]
Dual 180∑ Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR; 异相的双180 °的PWM降压型控制器，带有电源顺序控制及POR
| 型号： | MAX1858EEG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 180∑ Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR |
| 文件： | 总21页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2432; Rev 0; 7/02
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
General Description
Features
The MAX1858 dual, synchronized, step-down controller
generates two outputs from input supplies ranging from
4.75V to 23V. Each output is adjustable from sub-1V to
18V and supports loads of 10A or higher. Input voltage
ripple and total RMS input ripple current are reduced by
synchronized 180° out-of-phase operation.
o Two Independent Output Voltages
o 180° Out-of-Phase Operation
o 90° Out-of-Phase Operation
(Using Two MAX1858s)
o Foldback Current Limit
The switching frequency is adjustable from 100kHz to
600kHz with an external resistor. Alternatively, the con-
troller can be synchronized to an external clock gener-
ated to another MAX1858 or a system clock. One
MAX1858 can be set to generate an in-phase, or 90°
out-of-phase, clock signal for synchronization with addi-
tional controllers. This allows two controllers to operate
either as an interleaved two- or four-phase system with
each output shifted by 90°. The device also features
“first-on/last-off” power sequencing for compatibility
with DSPs, ASICs, and FPGAs, as well as soft-start and
soft-stop to ensure reliable and repeatable power
sequencing.
o 4.75V to 23V Input Supply Range
o 0 to 18V Output-Voltage Range (Up to 10A)
o >90% Efficiency
o Fixed-Frequency Pulse-Width Modulation (PWM)
Operation
o Adjustable 100kHz to 600kHz Switching
Frequency
o External SYNC Input
o Clock Output for Master/Slave Synchronization
o Power-On/-Off Sequencing with Soft-Start and
The MAX1858 eliminates the need for current-sense
resistors by utilizing the low-side MOSFET’s on-resistance
as a current-sense element. This protects the DC-DC
components from damage during output-overload condi-
tions or when output short-circuit faults without requiring a
current-sense resistor. Adjustable foldback current limit
reduces power dissipation during short-circuit condition.
A power-on reset output signals the system when both
outputs reach regulation.
Soft-Stop
o RST Output with 140ms Minimum Delay
o Lossless Current Limit (No Sense Resistor)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
The MAX1858 is available in a 24-pin QSOP package.
An evaluation kit is available to speed designs.
MAX1858EEG
-40°C to +85°C
24 QSOP
Applications
Pin Configuration
Network Power Supplies
Telecom Power Supplies
DSP, ASIC, and FPGA Power Supplies
Set-Top Boxes
TOP VIEW
COMP2
FB2
1
2
3
4
5
6
7
8
9
24 EN
23 DH2
22 LX2
21 BST2
20 DL2
ILIM2
OSC
V+
Broadband Routers
Servers
REF
19 V
L
MAX1858
GND
CKO
SYNC
18 PGND
17 DL1
16 BST1
15 LX1
14 DH1
13 RST
Typical Operating Circuit appears at end of data sheet.
ILIM1 10
FB1 11
COMP1 12
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +25V
PGND to GND .......................................................-0.3V to +0.3V
FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V
V to GND Short Circuit..............................................Continuous
L
V to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V)
L
REF to GND Short Circuit...........................................Continuous
BST1, BST2 to GND ...............................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
Continuous Power Dissipation (T = +70°C)
A
24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DH1 to LX1 ..............................................-0.3V to (V
DH2 to LX2 ..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
BST1
BST2
DL1, DL2 to PGND........................................-0.3V to (V + 0.3V)
L
CKO, REF, OSC, ILIM1, ILIM2,
COMP1, COMP2 to GND..........................-0.3V to (V + 0.3V)
L
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C
= 0.22µF, C = 4.7µF (ceramic), R = 60kΩ,
OSC
L
VL
REF
VL
compensation components for COMP_ are from Figure 1, T = -40°C to +85°C (Note 1), unless otherwise noted.)
A
PARAMETER
GENERAL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 2)
V = V+ (Note 2)
4.75
4.75
23
5.5
6
V+ Operating Range
V
L
V+ Operating Supply Current
V+ Standby Supply Current
Thermal Shutdown
V unloaded, no MOSFETs connected
L
3.5
0.3
160
100
50
mA
mA
°C
EN = LX_ = FB_ = 0V
Rising temperature, typical hysteresis = 10°C
ILIM_ = V
R
= 60kΩ
0.6
OSC
75
32
125
62
L
Current-Limit Threshold
PGND - LX_
mV
R
R
= 100kΩ
= 600kΩ
ILIM_
ILIM_
225
300
375
V REGULATOR
L
Output Voltage
5.5V < V+ < 23V, 1mA < I
< 50mA
4.75
4.4
5
5.25
4.7
V
V
LOAD
V Undervoltage Lockout
L
Trip Level
4.55
REFERENCE
Output Voltage
Reference Load Regulation
SOFT-START
I
= 0µA
1.98
0
2.00
4
2.02
10
V
REF
0µA < I
< 50µA
mV
REF
Internal 6-bit DAC for one converter to ramp from 0V to
full scale (Note 3)
DC-DC
Clocks
Digital Ramp Period
1024
64
Soft-Start Steps
Steps
FREQUENCY
0°C to +85°C
84
80
100
100
600
250
115
120
660
303
Low End of Range
R
= 60kΩ
kHz
OSC
-40°C to +85°C
High End of Range
R
R
= 10kΩ
= 10kΩ
540
kHz
ns
OSC
OSC
DH_ Minimum Off-Time
2
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C
= 0.22µF, C = 4.7µF (ceramic), R = 60kΩ,
OSC
L
VL
REF
VL
compensation components for COMP_ are from Figure 1, T = -40°C to +85°C (Note 1), unless otherwise noted.)
A
PARAMETER
SYNC Range
CONDITIONS
MIN
TYP
MAX
UNITS
Internal oscillator nominal frequency must be set to half
of SYNC frequency
200
1200
kHz
High
100
100
SYNC Input Pulse Width
(Note 3)
Low
ns
ns
SYNC Rise/Fall Time
ERROR AMPLIFIER
FB_ Input Bias Current
(Note 3)
100
250
1.015
1.02
2.70
2.9
nA
V
0°C to +85°C
-40°C to +85°C
0°C to +85°C
-40°C to +85°C
0.985
0.98
1.25
1.2
1.00
1.00
1.8
FB_ Input Voltage Set Point
FB_ to COMP_ Transconductance
mS
1.8
DRIVERS
DL_, DH_ Break-Before-Make Time
C
= 5nF
30
1.5
3
ns
LOAD
Low
High
Low
High
2.5
5
DH_ On-Resistance
DL_ On-Resistance
Ω
0.6
3
1.5
5
Ω
LOGIC INPUTS (EN, SYNC)
Input Low Level
Typical 15% hysteresis, V = 4.75V
0.8
+1
0.4
V
V
L
Input High Level
V = 5.5V
L
2.4
-1
Input High/Low Bias Current
LOGIC OUTPUTS (CKO)
Output Low Level
V
= 0 or 5.5V
0.1
µA
EN
V = 5V, sinking 5mA
L
V
V
Output High Level
COMP_
V = 5V, sourcing 5mA
L
4.0
Pulldown Resistance During
Shutdown and Current Limit
17
Ω
RST OUTPUT
Both FBs must be over this to allow the reset timer to
start; there is no hysteresis
Output-Voltage Trip Level
0.87
140
0.9
0.93
V
V
V = 5V, sinking 3.2mA
L
0.4
0.3
1
Output Low Level
V = 1V, sinking 0.4mA
L
Output Leakage
V+ = V = 5V, V
= 5.5V, V = 1V
µA
ms
µs
L
RST
FB
Reset Timeout Period
FB_ to Reset Delay
V
=1V
FB_
315
4
560
FB_ overdrive from 1V to 0.85V
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range is guaranteed by V line regulation test. Connect V+ to V for 5V operation.
L
L
Note 3: Guaranteed by design and not production tested.
_______________________________________________________________________________________
3
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Typical Operating Characteristics
(Circuit of Figure 1, V = 12V, T = +25°C, unless otherwise noted.)
IN
A
EFFICIENCY vs. LOAD
OUTPUT-VOLTAGE ACCURACY vs. LOAD
100
90
80
70
60
50
40
30
20
10
0
1.0
0.8
OUT2
OUT1
0.6
0.4
0.2
OUT2
OUT1
0
-0.2
-0.4
-0.6
-0.8
-1.0
0.1
1
10
100
0
5
10
15
LOAD (A)
LOAD (A)
V VOLTAGE ACCURACY
L
vs. LOAD CURRENT
SWITCHING FREQUENCY vs. R
OSC
0.5
0
600
500
400
300
200
100
0
-0.5
-1.0
-1.5
-2.0
0
50
100
150
0
10
20
30
(kΩ)
40
50
60
LOAD CURRENT (mA)
R
OSC
LOAD TRANSIENT RESPONSE (OUTPUT 2)
LOAD TRANSIENT RESPONSE (OUTPUT 1)
MAX1858 toc06
MAX1858 toc05
V
OUT1
50mV/div
AC-COUPLED
V
OUT2
50mV/div
V
OUT2
AC-COUPLED
50mV/div
V
OUT1
AC-COUPLED
50mV/div
AC-COUPLED
10A
10A
I
I
OUT2
OUT1
0A
0A
10µs/div
10µs/div
4
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V = 12V, T = +25°C, unless otherwise noted.)
IN
A
RESET TIMEOUT
OUT-OF-PHASE WAVEFORM
SOFT-START AND SOFT-STOP WAVEFORM
MAX1858 toc08
MAX1858 toc09
MAX1858 toc07
5V
5V/div
V
OUT1
V
EN
20mV/div
0V
EN
0V
12V
V
LX1
V
OUT2
V
OUT2
0V
12V
0V
1V/div
V
OUT1
0V
V
LX2
0V
0V
V
RST
V
OUT2
0V
V
OUT1
1V/div
20mV/div
0V
100ms/div
1µs/div
1ms/div
EXTERNALLY SYNCHRONIZED
SWITCHING WAVEFORM
CKO OUTPUT WAVEFORM
MAX1858 toc10
MAX1858 toc11
5V
V
SYNC = GND
SYNC
0V
5V
V
5V
V
CK0
CK0
0V
0V
10V
LX1
0V
10V
LX1
0V
V
V
V
V
OUT1
10mV/div
OUT1
10mV/div
AC-COUPLED
AC-COUPLED
400ns/div
400ns/div
SHORT-CIRCUIT CURRENT
FOLDBACK AND RECOVERY
CKO OUTPUT WAVEFORM
MAX1858 toc12
MAX1858 toc13
SYNC = V
L
I
= 10A (5A/div)
= 1.8V (1V/div)
OUT1
5V
V
OUT1
V
CK0
0V
10V
LX1
0V
V
V
OUT2
= 2.5V (1V/div)
OUT2
SHORT
OUT2
I
= 10A (5A/div)
V
V
OUT1
10mV/div
400ns/div
_______________________________________________________________________________________
5
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Pin Description
PIN
NAME
FUNCTION
Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series
1
COMP2
resistor (R ) and capacitor (C ) to GND in parallel with a second compensation capacitor
COMP2
COMP2A
(C
) as shown in Figure 1.
COMP2B
Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB2 to a resistive voltage-divider from REF to REG2’s output. See the Setting the Output
Voltage section.
2
3
FB2
Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to
100mV if ILIM2 is connected to V . Connect a resistor (R
) from ILIM2 to GND to adjust the
ILIM2
L
ILIM2
REG2’s current-limit threshold (V
) from 50mV (R
= 100kΩ) to 300mV (R
= 600kΩ). See
ITH2
ILIM2
ILIM2
the Setting the Valley Current Limit section.
Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the
oscillator, so the switching frequency equals half the synchronization frequency (f = f /2).
SW
OSC
4
OSC
Connect a resistor from OSC to GND (R
) to set the switching frequency from 100kHz (R
=
OSC
OSC
60kΩ) to 600kHz (R
= 10kΩ). The controller still requires R
when an external clock is
OSC
OSC
connected to SYNC. When using SYNC, set R
for one half of the SYNC input.
OSC
5
6
7
V+
Input Supply Voltage. 4.75V to 23V.
REF
GND
2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.
Analog Ground
Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization
(SYNC, CKO) section).
8
CKO
Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect
SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase
operation as a master controller. Connect SYNC to V for 4-phase operation as a master controller
L
9
SYNC
(see the Clock Synchronization (SYNC, CKO) section).
Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to
100mV if ILIM1 is connected to V . Connect a resistor (R
) from ILIM1 to GND to adjust REG1’s
ILIM1
L
10
ILIM1
current-limit threshold (V
) from 50mV (R
= 100kΩ) to 300mV (R
= 600kΩ). See the
ITH1
ILIM1
ILIM1
Setting the Valley Current Limit section.
Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB1 to a resistive voltage-divider from REF and REG1’s output. See the Setting the Output
Voltage section.
11
12
FB1
Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series
resistor (R
) and capacitor (C
) to GND in parallel with a second compensation capacitor
COMP1A
COMP1
COMP1
(C
) as shown in Figure 1.
COMP1B
Open-Drain Reset Output. RST is low when either output voltage is more than 10% below its
regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output
13
RST
voltage (V _ > 0.9V), RST becomes high impedance after a 140ms delay and remains high
FB
impedance as long as both outputs maintain regulation. Connect a resistor between RST and the
logic supply for logic-level voltages.
6
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Pin Description (continued)
PIN
NAME
FUNCTION
14
DH1
High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1.
External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the
inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.
15
16
LX1
Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic
capacitor and diode according to Figure 1.
BST1
17
18
DL1
Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to V .
L
PGND
Power Ground
Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers
and external boost circuitry for the high-side gate drivers.
19
20
21
V
L
DL2
Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to V .
L
Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic
capacitor and diode according to Figure 1.
BST2
External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the
inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.
22
23
24
LX2
DH2
EN
High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2.
Active-High Enable Input. A logic low shuts down both controllers. Connect to V for always-on
L
operation.
tor current exceeds the selected valley current-limit
Detailed Description
(see the Current-Limit Circuit (ILIM_) section), the high-
DC-DC PWM Controller
side MOSFET does not turn on at the appropriate clock
edge and the low-side MOSFET remains on to let the
inductor current ramp down.
The MAX1858 step-down converters use a PWM volt-
age-mode control scheme (Figure 2) for each out-of-
phase controller. The controller generates the clock
signal by dividing down the internal oscillator or SYNC
input when driven by an external clock, so each con-
troller’s switching frequency equals half the oscillator
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1858 oper-
ate 180° out-of-phase to reduce input filtering require-
ments, reduce electromagnetic interference (EMI), and
improve efficiency. This effectively lowers component
cost and saves board space, making the MAX1858
ideal for cost-sensitive applications.
frequency (f
= f
/2). An internal transconductance
OSC
SW
error amplifier produces an integrated error voltage at
the COMP pin, providing high DC accuracy. The volt-
age at COMP sets the duty cycle using a PWM com-
parator and a ramp generator. At each rising edge of
the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty
cycle or until the maximum duty cycle is reached.
REG2 operates out-of-phase, so the second high-side
MOSFET turns on at each falling edge of the clock.
During each high-side MOSFET’s on-time, the associat-
ed inductor current ramps up.
Dual-switching regulators typically operate both con-
trollers in-phase, and turn on both high-side MOSFETs
at the same time. The input capacitor must then sup-
port the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current when compared to a single switch-
ing regulator. The higher RMS ripple current lowers effi-
ciency due to power loss associated with the input
capacitor’s effective series resistance (ESR). This typi-
cally requires more low-ESR input capacitors in parallel
to minimize input voltage ripple and ESR-related loss-
es, or to meet the necessary ripple-current rating.
During the second-half of the switching cycle, the high-
side MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
_______________________________________________________________________________________
7
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
V
IN
6V - 23V
R
V+
4.7Ω
0.1µF
V+
V
L
C
C
VL
4.7µF
V+
0.22µF
4.7Ω
4.7Ω
C
C
2
IN1
10µF
IN2
×
10µF
BST1
BST2
×
2
C
C
BST2
0.1µF
BST1
0.1µF
N
DH1
LX1
DH2
LX2
DL2
H1*
N
N
H2*
OUTPUT1
= 1.8V
L1
L2
1.2µH
OUTPUT2
OUT
V
1µH
OUT
V
= 2.5V
C
OUT1
C
4
OUT2
220µF
×
4
220µF
×
**
N
DL1
**
L1*
R1A
R2A
15kΩ
L2*
8.06kΩ
PGND
FB1
FB2
R
R
COMP2
8.2kΩ
COMP1
5.9kΩ
R2B
10kΩ
R1B
10kΩ
COMP1
COMP2
C
C
C
C
COMP2A
6.8nF
COMP1B
100pF
COMP2B
100pF
COMP1A
10nF
D2
CMSSH-3
D3
CMSSH-3
MAX1858
REF
C
REF
0.22µF
OSC
GND
CLOCK OUTPUT
RESET OUTPUT
ON
CKO
RST
118kΩ
SYNC
ILIM1
ILIM2
V
L
96.5kΩ
EN
*IRF7811W
**OPTIONAL
OFF
140kΩ
84.5kΩ
Figure 1. Standard Application Circuit
With dual synchronized out-of-phase operation, the
MAX1858’s high-side MOSFETs turn on 180° out-of-
phase. The instantaneous input current peaks of both
regulators no longer overlap, resulting in reduced RMS
ripple current and input voltage ripple. This reduces the
required input capacitor ripple-current rating, allowing
fewer or less expensive capacitors, and reduces shield-
ing requirements for EMI. The Out-of-Phase Waveforms
in the Typical Operating Characteristics demonstrate
synchronized 180° out-of-phase operation.
Internal 5V Linear Regulator (V )
L
All MAX1858 functions are internally powered from an
on-chip, low-dropout 5V regulator. The maximum regu-
lator input voltage (V+) is 23V. Bypass the regulator’s
output (V ) with a 4.7µF ceramic capacitor to PGND.
L
The V dropout voltage is typically 500mV, so when V+
L
is greater than 5.5V, V is typically 5V. The MAX1858
L
also employs an undervoltage lockout circuit that dis-
ables both regulators when V falls below 4.5V. V
L
should also be bypassed to GND with 0.1µF.
L
8
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
REF
V+
5V LINEAR
REGULATOR
V
REF
2V
MAX1858
GND
COMP1
FB1
V
L
BST1
DH1
LX1
CONVERTER 1
SOFT-START
DAC
SEQUENCING
R
S
Q
Q
DL1
PGND
OSC
SYNC
CK0
OSCILLATOR
5µA
RST
ILIM1
RESET
EN
UVLO
AND
SHUTDOWN
V
REF
V - 0.5V
L
V
L
BST2
DH2
LX2
CONVERTER 2
COMP2
FB2
DL2
ILIM2
Figure 2. Functional Diagram
The internal V linear regulator can source over 50mA
L
when switched at 600kHz, a single large FET with 18nC
total gate charge requires 18nC x 600kHz = 11mA. To
drive larger MOSFETs, or deliver larger loads, connect
to supply the IC, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving large FETs, little or no regulator cur-
rent may be available for external loads. For example,
V to an external power supply from 4.75V to 5.5V.
L
_______________________________________________________________________________________
9
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
High-Side Gate-Drive Supply (BST_)
Gate-drive voltages for the high-side N-channel switch-
es are generated by the flying-capacitor boost circuits
(Figure 3). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-
sensing algorithm that uses the on-resistance of the
low-side MOSFET as a current-sensing element. If the
current-sense signal is above the current-limit thresh-
old, the MAX1858 does not initiate a new cycle (Figure
4). Since valley current sensing is employed, the actual
peak current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the low-side
MOSFET’s on-resistance, current-limit threshold, induc-
tor value, and input voltage. The reward for this uncer-
tainty is robust, lossless overcurrent sensing that does
not require costly sense resistors.
On startup, the synchronous rectifier (low-side
MOSFET) forces LX_ to ground and charges the boost
capacitor to 5V. On the second half-cycle, after the low-
side MOSFET turns off, the high-side MOSFET is turned
on by closing an internal switch between BST_ and
DH_. This provides the necessary gate-to-source volt-
age to turn on the high-side switch, an action that
boosts the 5V gate-drive signal above V . The current
IN
required to drive the high-side MOSFET gates
(f
✕ Q ) is ultimately drawn from V .
SWITCH
G
L
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). The current-limit thresh-
old is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, cor-
responding to resistor values of 100kΩ to 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moder-
ate-size N-channel high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor seen
with large V - V
differential. The DL_ low-side drive
IN
OUT
waveform is always the complement of the DH_ high-side
drive waveform (with controlled dead time to prevent
cross-conduction or “shoot-through”). An adaptive dead-
time circuit monitors the DL_ output and prevents the
high-side FET from turning on until DL_ is fully off. There
must be a low-resistance, low-inductance path from the
DL_ driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1858 interprets the MOSFET gate as
“off” while there is actually charge still left on the gate.
Use very short, wide traces (50mils to 100mils wide if the
MOSFET is 1in from the device). The dead time at the
DH-off edge is determined by a fixed 30ns internal delay.
to 100mV when ILIM is tied to V . The logic threshold
L
for switchover to this 100mV default value is approxi-
mately V - 0.5V. Adjustable foldback current limit
L
reduces power dissipation during short-circuit condi-
tions (see the Design Procedure section).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1858 uses the synchronous rectifi-
er to ensure proper startup of the boost gate-driver cir-
cuit and to provide the current-limit signal.
Undervoltage Lockout and Startup
If V drops below 4.5V, the MAX1858 assumes that the
L
supply and reference voltages are too low to make
valid decisions and activates the undervoltage lockout
(UVLO) circuitry which forces DL and DH low to inhibit
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω (typ) on-resistance. This low on-
resistance helps prevent DL_ from being pulled up dur-
ing the fast rise-time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5Ω) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 3).
switching. RST is also forced low during UVLO. After V
rises above 4.5V, the controller powers up the outputs.
L
Enable (EN), Soft-Start, and Soft-Stop
Pull EN high to enable or low to shutdown both regula-
tors. During shutdown the supply current drops to 1mA
(max), LX enters a high-impedance state (DH_ con-
nected to LX_, and DL_ connected to PGND), and
COMP_ is discharged to GND through a 17Ω resistor.
V and REF remain active in shutdown. For “always-on”
L
operation, connect EN to V .
L
10 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ply voltage. A 100kΩ resistor works well for most appli-
cations. If unused, leave RST grounded or unconnected.
INPUT
IN
(V
)
Clock Synchronization (SYNC, CKO)
SYNC serves two functions: SYNC selects the clock out-
put (CKO) type used to synchronize slave controllers, or
it serves as a clock input so the MAX1858 can be syn-
chronized with an external clock signal. This allows the
MAX1858 to function as either a master or slave. CKO
provides a clock signal synchronized to the MAX1858’s
switching frequency, allowing either in-phase (SYNC =
V
L
5Ω
BST_
DH_
LX_
GND) or 90° out-of-phase (SYNC = V ) synchronization
L
of additional DC-DC controllers (Figure 5). The
MAX1858 supports the following three operating modes:
• SYNC = GND: The CKO output frequency equals
MAX1858
REG1’s switching frequency (f
= f
) and the
DH1
CKO
CKO signal is in phase with REG1’s switching fre-
quency. This provides 2-phase operation when syn-
chronized with a second slave controller.
Figure 3. Reducing the Switching-Node Rise Time
• SYNC = V : The CKO output frequency equals two
L
On the rising edge of EN both controllers enter soft-
start. Soft-start gradually ramps up to the reference
voltage seen by the error amplifier in order to control
the outputs’ rate of rise and reduce input surge cur-
rents during startup. The soft-start period is 1024 clock
times REG1’s switching frequency (f
= 2f
)
DH1
CKO
and the CKO signal is phase shifted by 90° with
respect to REG1’s switching frequency. This pro-
vides 4-phase operation when synchronized with a
second MAX1858 (slave controller).
cycles (1024/f ), and the internal soft-start DAC
SW
• SYNC Driven by External Oscillator: The controller
generates the clock signal by dividing down the
SYNC input signal, so the switching frequency equals
ramps up the voltage in 64 steps. The output reaches
regulation when soft-start is completed. On the falling
edge of EN both controllers simultaneously enter soft-
stop, which reverses the soft-start ramp. The part
enters shutdown after soft-stop is complete.
half the synchronization frequency (f
= f /2).
SYNC
SW
REG1’s conversion cycles initiate on the rising edge
of the internal clock signal. The CKO output frequen-
cy and phase match REG1’s switching frequency
Output-Voltage Sequencing
After the startup circuitry enables the controller, the
MAX1858 begins the startup sequence. Regulator 1
(OUT1) powers up with soft-start enabled. Once the first
converter’s soft-start sequence ends, Regulator 2 (OUT2)
powers up with soft-start enabled. Finally, when both con-
verters complete soft-start and both output voltages
exceed 90% of their nominal values, the reset output
(RST) goes high (see the Reset Output section). Soft-stop
is initiated by pulling EN low. Soft-stop occurs in reverse
order of soft-start, allowing last-on/first-off operation.
(f
= f
) and the CKO signal is in phase. Note
CKO
DH1
that the MAX1858 still requires R
when SYNC is
OSC
externally clocked and the internal oscillator frequen-
cy should be set to 50% of the synchronization fre-
quency (f
= 0.5f ).
SYNC
OSC
Thermal Overload Protection
Thermal overload protection limits total power dissipation
in the MAX1858. When the device’s die-junction tempera-
ture exceeds T = +160°C, an on-chip thermal sensor
J
shuts down the device, forcing DL_ and DH_ low, allow-
ing the IC to cool. The thermal sensor turns the part on
again after the junction temperature cools by 10°C.
During thermal shutdown, the regulators shut down, RST
Reset Output
RST is an open-drain output. RST pulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regula-
tion voltages and both soft-start cycles are completed,
RST goes high impedance. To obtain a logic-voltage out-
put, connect a pullup resistor from RST to the logic sup-
goes low, and soft-start is reset. If the V linear-regulator
L
output is short-circuited, thermal-overload protection is
triggered.
_______________________________________________________________________________________ 11
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
where t
is 100ns. The minimum input voltage is
ON(MIN)
limited by the switching frequency and minimum off-
time, which determine the maximum duty cycle
-I
PEAK
(D
= 1 - f
t
):
MAX
SW OFF(MIN)
I
LOAD
V
1-f
+ V
DROP1
OUT
V
=
+ V
-V
IN(MIN)
DROP2 DROP1
t
SW OFF(MIN)
I
LIMIT
where V
is the sum of the parasitic voltage drops in
DROP1
the inductor discharge path, including synchronous recti-
fier, inductor, and PC board resistances. V is the
DROP2
sum of the resistances in the charging path, including
high-side switch, inductor, and PC board resistances.
0
TIME
Setting the Output Voltage
For 1V or greater output voltages, set the MAX1858 out-
put voltage by connecting a voltage-divider from the
output to FB_ to GND (Figure 6). Select R_B (FB_ to
GND resistor) to between 1kΩ and 10kΩ. Calculate
R_A (OUT_ to FB_ resistor) with the following equation:
Figure 4. “Valley” Current-Limit Threshold Point
Design Procedure
Effective Input Voltage Range
Although, the MAX1858 controller can operate from
input supplies ranging from 4.75V to 23V, the input volt-
age range can be effectively limited by the MAX1858’s
duty-cycle limitations. The maximum input voltage is
V
V
OUT
R_A = R_B
-1
SET
where V
= 1.00V (see the Electrical Characteristics)
SET
limited by the minimum on-time (t
):
ON(MIN)
and V
can range from V
to 18V.
OUT
SET
V
OUT
V
≤
IN(MAX)
t
f
ON(MIN) SW
MAX1858
MAX1858
MAX1858
CK0
SYNC
CK0
SYNC
OSC
OSC
OSC
SYNC
SYNC
V
V
L
L
SLAVE
SLAVE
MASTER
MASTER
2-PHASE SYSTEM
4-PHASE SYSTEM
180° PHASE SHIFT
90° PHASE SHIFT
DH1
MASTER
DH1
MASTER
DH2
DH2
DH1
DH1
SLAVE
SLAVE
DH2
DH2
Figure 5. Synchronized Controllers
12 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
For output voltages below 1V, set the MAX1858 output
voltage by connecting a voltage-divider from the output
to FB_ to REF (Figure 6). Select R_C (FB to REF resis-
tor) in the 1kΩ to 10kΩ range. Calculate R_A with the
following equation:
between size and loss is a 30% peak-to-peak ripple
current to average-current ratio (LIR = 0.3). The switch-
ing frequency, input voltage, output voltage, and
selected LIR determine the inductor value as follows:
V
(V -V
)
OUT IN OUT
L =
V
V
-V
SET OUT
V f
I
LIR
R_A = -R_C
IN SW OUT
-V
REF SET
where V , V
, and I
are typical values (so that
IN OUT
OUT
where V
= 1V, V
= 2V (see the Electrical
REF
efficiency is optimum for typical conditions). The switch-
ing frequency is set by R (see the Setting the
SET
Characteristics), and V
can range from 0 to V
.
SET
OUT
OSC
Switching Frequency section). The exact inductor value
is not critical and can be adjusted in order to make
trade-offs among size, cost, and efficiency. Lower
inductor values minimize size and cost, but also
improve transient response and reduce efficiency due
to higher peak currents. On the other hand, higher
inductance increases efficiency by reducing the RMS
current. However, resistive losses due to extra wire turns
can exceed the benefit gained from lower AC current
levels, especially when the inductance is increased
without also allowing larger inductor dimensions.
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or SYNC input signal when
driven by an external oscillator, so the switching frequen-
cy equals half the oscillator frequency (f
= f
/2).
SW
OSC
The internal oscillator frequency is set by a resistor
(R
) connected from OSC to GND. The relationship
OSC
between f
and R
is:
SW
OSC
Ω -Hz
S
9
6×10
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The
inductor’s saturation rating must exceed the peak-
inductor current at the maximum defined load current
R
=
OSC
f
SW
where f
is in Hz, f
is in Hz, and R
is in Ω. For
SW
OSC
OSC
example, a 600kHz switching frequency is set with
(I
):
LOAD(MAX)
R
= 10kΩ. Higher frequencies allow designs with
OSC
lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gate-
charge currents, and switching losses increase.
LIR
2
I
= I
+
I
LOAD(MAX)
PEAK
LOAD(MAX)
Setting the Valley Current Limit
A rising clock edge on SYNC is interpreted as a syn-
chronization input. If the SYNC signal is lost, the inter-
nal oscillator takes control of the switching rate,
The minimum current-limit threshold must be high enough
to support the maximum expected load current with the
worst-case low-side MOSFET on-resistance value since
the low-side MOSFET’s on-resistance is used as the cur-
rent-sense element. The inductor’s valley current occurs
returning the switching frequency to that set by R
.
OSC
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
at I
minus half of the ripple current. The cur-
rent-sense threshold voltage (V ) should be greater
than voltage on the low-side MOSFET during the ripple-
current valley:
LOAD(MAX)
is used, R
should set the switching frequency to
OSC
ITH
one half SYNC rate (f
).
SYNC
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX1858: inductance value (L),
LIR
2
V
>R
×I
× 1-
ITH
DS(ON,MAX) LOAD(MAX)
peak-inductor current (I
DC
), and DC resistance
PEAK
(R ). The following equation assumes a constant ratio
where R
is the on-resistance of the low-side
MOSFET (N ). Use the maximum value for R
DS(ON)
of inductor peak-to-peak AC current to DC average
current (LIR). For LIR values too high, the RMS currents
are high, and therefore I2R losses are high. Large
inductances must be used to achieve very low LIR val-
ues. Typically inductance is proportional to resistance
(for a given package type) which again makes I2R loss-
es high for very low LIR values. A good compromise
L
DS(ON)
from the low-side MOSFET’s data sheet, and additional
margin to account for R rise with temperature is
DS(ON)
also recommended. A good general rule is to allow
0.5% additional resistance for each °C of the MOSFET
junction temperature rise.
______________________________________________________________________________________ 13
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Connect ILIM_ to V for the default 100mV (typ) current-
L
limit threshold. For an adjustable threshold, connect a
resistor (R
_) from ILIM_ to GND. The relationship
ILIM
OUT_
REF
FB_
between the current-limit threshold (V _) and R
_ is:
ITH
ILIM
R_A
R_C
R_A
V
ITH_
R
=
FB_
ILIM_
0.5µA
_ is in Ω and V _ is in V. An R resis-
ILIM
R_B
where R
ILIM
ITH
OUT_
tance range of 100kΩ to 600kΩ corresponds to a current-
limit threshold of 50mV to 300mV. When adjusting the
current limit, 1% tolerance resistors minimizes error in the
current-limit threshold. For foldback current limit, a resis-
MAX1858
MAX1858
V
OUT_
> 1V
V
< 1V
OUT_
tor (R ) is added from ILIM pin to output. The value of
FBI
R
ILIM
and R can then be calculated as follows:
Figure 6. Adjustable Output Voltage
FBI
Output Capacitor
First select the percentage of foldback (P ) from 15%
FB
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing in to and out of
the capacitor.
to 30%, then:
P
× V
FB
OUT
R
=
FBI
-6
5 × 10 (1 - P
)
FB
10 × V
(1 - P ) × R
ITH
FB FBI
and
R
=
ILIM
[V
- 10 × V
(1 - P )]
OUT
ITH FB
Input Capacitor
V
≅ V
+ V
RIPPLE
RIPPLE(ESR) RIPPLE(C)
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
The output voltage ripple as a consequence of the ESR
and output capacitance is:
V
=I
R
requirement (I
) imposed by the switching currents
as defined by the following equation:
RMS
RIPPLE(ESR) P-P ESR
I
P-P
V
=
RIPPLE(C)
8C
f
OUT SW
V
(V -V
)
OUT IN OUT
I
=I
V
IN
RMS LOAD
V
-V
V
OUT
IN OUT
V
I
=
IN
P-P
f
L
SW
I
has a maximum value when the input voltage
RMS
equals twice the output voltage (V = 2V
), so
IN
OUT
where I
is the peak-to-peak inductor current (see the
P-P
I
= I
/ 2. For most applications, nontanta-
RMS(MAX)
LOAD
Inductor Selection section). These equations are suitable
for initial capacitor selection, but final values should be
verified by testing in a prototype or evaluation circuit.
lum capacitors (ceramic, aluminum, polymer, or
OSCON) are preferred at the input due to their robust-
ness with high inrush currents typical of systems that can
be powered from very low impedance sources.
Additionally, two (or more) smaller-value low-ESR capaci-
tors can be connected in parallel for lower cost. Choose
an input capacitor that exhibits less than +10°C tem-
perature rise at the RMS input current for optimal long-
term reliability.
As a general rule, a smaller inductor ripple current
results in less output ripple voltage. Since inductor rip-
ple current depends on the inductor value and input
voltage, the output ripple voltage decreases with larger
inductance and increases with higher input voltages.
However, the inductor ripple current also impacts tran-
sient-response performance, especially at low
V
IN
- V
differentials. Low inductor values allow the
OUT
inductor current to slew faster, replenishing charge
14 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
removed from the output filter capacitors by a sudden
V
V
V
OUT
1+sR C
ESR OUT
FB
SET
load step. The amount of output-voltage sag is also a
function of the maximum duty factor, which can be cal-
culated from the minimum off-time and switching fre-
quency:
A
=
≅
=
FB/LX
2
V
S LC
+ SR
C
+1
LX
OUT
ESR OUT
V
1+ SR
C
SET
ESR OUT
2
V
V
S LC
+1
OUT
OUT
OUT
V
2
OUT
Therefore:
g
L(I
-I
)
+ t
OFF(MIN)
LOAD1 LOAD2
V f
IN SW
V
=
1+ SR
C
SAG
V
M _COMP
COMP COMP _A
IN
A
≅
×
×
V
-V
L
IN OUT
2C
V
-t
OFF(MIN)
SC
1+ SR
C
V
RAMP
OUT OUT
COMP _A
COMP COMP _B
V f
IN SW
V
V
1+ SR
C
ESR OUT
SET
×
×
2
OUT
S LC
+1
OUT
where t
is the minimum off-time (see the
Electrical Characteristics), and f
the Setting the Switching Frequency section).
OFF(MIN)
is set by R
(see
SW
OSC
For an ideal integrator, this loop gain approaches infini-
ty at DC. In reality the g amplifier has a finite output
M
impedance which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accura-
cy. The dominant pole occurs due to the integrator, and
for this analysis, it can be approximated to occur at DC.
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control
loop is shown in Figure 7. For frequencies much lower
than Nyquist, the PWM block can be simplified to a
R
creates a zero at:
COMP
1
voltage amplifier. Connect R
and C
from
COMP_
COMP_A
f
=
Z_COMP_A
2π ×R
C
COMP to GND to compensate the loop (see Figure 7).
The inductor, output capacitor, compensation resistor,
and compensation capacitors determine the loop sta-
bility. Since the inductor and output capacitor are cho-
sen based on performance, size, and cost, select the
compensation resistor and capacitors to optimize con-
trol-loop stability.
COMP_ COMP_A
The inductor and capacitor form a double pole at:
1
f
=
LC
2π × LC
OUT
To determine the loop gain (A ), consider the gain from
L
At some higher frequency the output capacitor’s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
FB to COMP (A
), from COMP to LX
COMP/FB
), and from LX to FB (A
(A
). The total loop
FB/LX
LX/COMP
gain is:
A = A
× A
× A
LX/COMP FB/LX
L
COMP/FB
1
where:
f
=
ESR
2π ×R
C
g
V
ESR OUT
M_COMP
COMP
A
=
≅
COMP/FB
V
SC
COMP
FB
A final pole is added using C
gain and attenuate noise after crossover. This pole
(f ) occurs at:
to reduce the
COMP_B
1+sR
1+sR
C
COMP COMP_A
×
COMP_B
C
COMP COMP_B
1
assuming an ideal integrator, and assuming that
is much less than C
f
=
COMP_B
C
.
COMP_A
COMP_B
2π ×R
C
COMP COMP_B
V
V
IN
LX
A
=
=
Figure 8 shows a Bode plot of the poles and zeros in
their relative locations.
LX/COMP
V
V
COMP
RAMP
Near crossover the following approximations can be
made to simplify the loop-gain equation:
for frequencies lower than Nyquist.
______________________________________________________________________________________ 15
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
GAIN = +V /V
FOR
IN RAMP
FREQUENCIES LOWER
THAN NYQUIST
DH
DL
FB
N
N
P
L
L
V
OUT
W
M
LX
LX
V
C
R
R
ESR
ESR
=
FB
C
C
OUT
OUT
COMP_
COMP_
g
g
M_GROUP
M_GROUP
V
V
SET
R
R
COMP_
SET
COMP_
C
C
COMP_A
COMP_A
C
C
COMP_B
COMP_B
Figure 7. Fixed-Frequency Voltage-Mode Control Loop
• R
has much higher impedance than C
.
COMP_A
• Unity-gain crossover must occur below 1/5th of the
COMP
This is true if, and only if, crossover occurs above
. If this is true, C can be ignored
switching frequency.
f
Z_COMP_A
(as a short to ground).
COMP_A
• For reasonable phase margin using type 1 compen-
sation, f
must be larger than 5 ✕ f
.
CO
ESR
• R is much higher impedance than C
. This is
OUT
ESR
Choose C
so that f
equals half f
Z_COMP_A LC
COMP_A
using the following equation:
true if, and only if, crossover occurs well after the out-
put capacitor’s ESR zero. If this is true, C
OUT
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
2 × LC
OUT
C
=
COMP_A
R
COMP
• C
is much higher impedance than R
COMP
COMP_B
and can be ignored (as an open circuit). This is true
if, and only if, crossover occurs far below f
Choose C
CO
so that f
occurs at 3 times
COMP_B
COMP_B
using the following equation:
.
COMP_B
f
The following loop-gain equation can be found by using
these previous approximations with Figure 7:
1
C
=
COMP_B
2π × 3× f
×R
COMP
(
)
CO
g
×R
×R
V
V
SET
M_COMP
COMP ESR
IN
A ≅
×
×
L
V
V
sL
RAMP
OUT
MOSFET Selection
The MAX1858’s step-down controller drives two exter-
nal logic-level N-channel MOSFETs as the circuit switch
elements. The key selection parameters are:
Setting the loop gain to 1 and solving for the crossover
frequency yields:
• On-resistance (R
)
DS(ON)
V
V
SET
IN
f
= GBW =
×
CO
• Maximum drain-to-source voltage (V
)
DS(MAX)
V
V
RAMP
×R
COMP ESR
OUT
• Minimum threshold voltage (V
)
TH(MIN)
g
×R
M_COMP
×
• Total gate charge (Q )
g
2π ×L
• Reverse transfer capacitance (C
• Power dissipation
)
RSS
To ensure stability, select R
criteria:
to meet the following
COMP
16 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Calculate MOSFET temperature rise according to pack-
BODE PLOT FOR VOLTAGE-
MODE CONTROLLERS
age thermal-resistance specifications to ensure that
both MOSFETs are within their maximum junction tem-
50
perature at high ambient temperature. The worst-case
f
LC
40
30
20
10
0
dissipation for the high-side MOSFET (P ) occurs at
NH
both extremes of input voltage, and the worst-case dis-
sipation for the low-side MOSFET (P ) occurs at maxi-
NL
f
ESR
mum input voltage.
f
Z-COMP_A
f
CO
f
SWITCH
V I
f
Q
+Q
GD
INLOAD OSC
2
GS
I
P
=
NH(SWITCHING)
GATE
-10
-20
-30
-40
f
COMP_B
0.1
I
is the average DH driver output current capability
GATE
determined by:
V
0.001
0.01
1
L
I
=
GATE
FREQUENCY (MHz)
2 R
+R
GATE
DS(ON)DH
Figure 8. Voltage-Mode Loop Analysis
where R
is the high-side MOSFET driver’s on-
DS(ON)DH
resistance (5Ω max), and R
is any series resis-
GATE
All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V
4.5V. For maximum efficiency, choose a high-side
MOSFET (N _) that has conduction losses equal to the
H
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
tance between DH and BST (Figure 3).
≥
GS
V
OUT
2
P
=I
R
NH(CONDUCTION) LOAD DS(ON)NH
V
IN
P
=P
+P
NH(TOTAL)
NH(SWITCHING) NH(CONDUCTION)
V
2
OUT
P
=I
R
1-
NL LOAD DS(ON)NL
V
IN
where P
is the conduction power loss
NH(CONDUCTION)
in the high-side MOSFET, and P is the total low-side
Ensure that the MAX1858 DL_ gate driver can drive
NL
N _. In particular, check that the dv/dt caused by N _
L
H
power loss.
turning on does not pull up the N _ gate through N _’s
L
L
drain-to-gate capacitance. This is the most frequent
cause of cross-conduction problems.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs’ turn-on
and turn-off times.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that V can
L
power all four drivers without overheating the IC:
Applications Information
P
= V ×Q × f
G_TOTAL SW
VL
IN
Dropout Performance
When working with low input voltages, the output-voltage
adjustable range for continuous-conduction operation is
MOSFET package power dissipation often becomes a
dominant design factor. I2R power losses are the great-
est heat contributor for both high-side and low-side
restricted by the minimum off-time (t ). For best
OFF(MIN)
dropout performance, use the lowest (100kHz) switching-
frequency setting. Manufacturing tolerances and internal
propagation delays introduce an error to the switching
frequency and minimum off-time specifications. This error
is more significant at higher frequencies. Also, keep in
mind that transient response performance of buck regula-
tors operated close to dropout is poor, and bulk output
MOSFETs. I2R losses are distributed between N _ and
H
N _ according to duty factor as shown in the equations
L
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
______________________________________________________________________________________ 17
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
capacitance must often be added (see the V
equa-
SAG
5V +100mV
1-(600kHz)(250ns)
tion in the Design Procedure section).
V
=
IN(MIN)
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
)
DOWN
+100mV -100mV= 6V
as much as it ramps up during the maximum on-time
(∆I ). The ratio h = ∆I /∆I is an indicator of the
Therefore, V must be greater than 6V, even with very
IN
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 6.58V.
UP
UP DOWN
ability to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
Improving Noise Immunity
Applications where the MAX1858 must operate in noisy
environments can typically adjust their controller’s com-
pensation to improve the system’s noise immunity. In par-
ticular, high-frequency noise coupled into the feedback
loop causes jittery duty cycles. One solution is to lower
the crossover frequency (see the Compensation section).
each switching cycle and V
greatly increases
SAG
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between V
, output
SAG
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX1858 EV kit data sheet for a
specific layout example.
V
1-hf
+ V
DROP1
OUT
V
=
+ V
-V
IN(MIN)
DROP2 DROP1
t
SW OFF(MIN)
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
DROP2
tances; and t
is from the Electrical
OFF(MIN)
• Isolate the power components on the top side from
the analog components on the bottom side with a
ground shield. Use a separate PGND plane under
the OUT1 and OUT2 sides (referred to as PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run the
power plane ground currents on the top side only.
Characteristics. The absolute minimum input voltage is
calculated with h = 1.
If the calculated V+
is greater than the required min-
(MIN)
imum input voltage, then reduce the operating frequency
or add output capacitance to obtain an acceptable
V . If operation near dropout is anticipated, calculate
SAG
V to be sure of adequate transient response.
SAG
• Use a star ground connection on the power plane to
Dropout Design Example:
= 5V
minimize the crosstalk between OUT1 and OUT2.
V
OUT
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
f
t
= 600kHz
SW
OFF(MIN)
= 250ns
• Connect GND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
step 4 of the Layout Procedure section.
V
= V
= 100mV
DROP1
DROP2
h = 1.5
5V +100mV
1-1.5(600kHz)(250ns)
V
=
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency by 1% or more.
IN(MIN)
+100mV -100mV = 6.58V
Calculating again with h = 1 gives the absolute limit of
dropout:
• LX_ and PGND connections to the synchronous rec-
tifiers for current limiting must be made using Kelvin
sense connections to guarantee the current-limit
accuracy. With 8-pin SO MOSFETs, this is best done
18 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
by routing power to the MOSFETs from outside
using the top copper layer, while connecting PGND
and LX_ underneath the 8-pin SO package.
all these connections on the top layer with wide, cop-
per-filled areas (2oz copper recommended).
2) Mount the controller IC adjacent to the synchronous
• When trade-offs in trace lengths must be made,
allow the inductor-charging path to be made longer
than the discharge path. Since the average input
current is lower than the average output current in
step-down converters, this minimizes the power dis-
sipation and voltage drops caused by board resis-
tance. For example, allow some extra distance
between the input capacitors and the high-side
MOSFET rather than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
rectifier MOSFETs (N _), preferably on the back
L
side in order to keep LX_, PGND_, and DL_ traces
short and wide. The DL_ gate trace must be short
and wide, measuring 50mils to 100mils wide if the
low-side MOSFET is 1in from the controller IC.
3) Group the gate-drive components (BST_ diodes and
capacitors, and V bypass capacitor) together near
L
the controller IC.
4) Make the DC-DC controller ground connections as
follows: create a small analog ground plane near the
IC. Connect this plane to GND and use this plane for
the ground connection for the reference (REF), V+
bypass capacitor, compensation components, feed-
back dividers, OSC resistor, and ILIM_ resistors (if
any). Connect GND and PGND together under the
IC (this is the only connection between GND and
PGND).
• Ensure that the feedback connection to C
is
OUT_
short and direct.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas
(REF, COMP_, ILIM_, and FB_). Use PGND1 and
PGND2 as EMI shields to keep radiated noise away
from the IC, feedback dividers, and analog bypass
capacitors.
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
• Make all pin-strap control input connections (ILIM_,
SYNC, and EN) to analog ground (GND) rather than
power ground (PGND).
Chip Information
TRANSISTOR COUNT: 6688
Layout Procedure
1) Place the power components first, with ground termi-
PROCESS: BiCMOS
nals adjacent (N _ source, C _, and C _). Make
OUT
L
IN
______________________________________________________________________________________ 19
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Typical Operating Circuit
V
4.75V TO 23V
IN
V+
V
L
BST1
BST2
DH1
LX1
DH2
LX2
DL2
N
N
H2
OUTPUT1 = 1.8V, 10A
OUTPUT2 = 2.5V, 10A
MAX1858
N
L1
DL1
L2
PGND
FB1
FB2
COMP1
COMP2
REF
OSC
GND
CLOCK OUTPUT
RESET OUTPUT
ON
CK0
RST
SYNC
ILIM1
ILIM2
V
L
EN
OFF
20 ______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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