MAX186CMJP [MAXIM]
Low-Power, 8-Channel, Serial 12-Bit ADCs; 低功耗， 8通道，串行12位ADC
| 型号： | MAX186CMJP |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, 8-Channel, Serial 12-Bit ADCs |
| 文件： | 总24页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0123; Rev. 4; 8/96
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX186/MAX188 are 12-bit data-acquisition sys-
tems that combine an 8-channel multiplexer, high-band-
width track/hold, and serial interface together with high
conversion speed and ultra-low power consumption.
The devices operate with a single +5V supply or dual
±5V supplies. The analog inputs are software config-
urable for unipolar/bipolar and single-ended/differential
operation.
♦ 8-Channel Single-Ended or 4-Channel
Differential Inputs
♦ Single +5V or ±5V Operation
♦ Low Power: 1.5mA (operating mode)
2µA (power-down mode)
♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference (MAX186)
♦ SPI-, QSPI-, Microwire-, TMS320-Compatible
The 4-wire serial interface directly connects to SPI™,
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320
family digital signal processors. The MAX186/MAX188
use either the internal clock or an external serial-interface
clock to perform successive-approximation A/D conver-
sions. The serial interface can operate beyond 4MHz
when the internal clock is used.
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP, SO, SSOP Packages
♦ Evaluation Kit Available
______________Ord e rin g In fo rm a t io n
†
PART
TEMP. RANGE
PIN-PACKAGE
20 Plastic DIP
20 SO
MAX186_CPP
MAX186_CWP
MAX186_CAP
MAX186DC/D
MAX186_EPP
MAX186_EWP
MAX186_EAP
MAX186_MJP
0°C to +70°C
The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts
have a reference-buffer amplifier that simplifies gain
trim .
0°C to +70°C
0°C to +70°C
20 SSOP
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
20 Plastic DIP
20 SO
The MAX186/MAX188 provide a hard-wired SHDN pin
a nd two s oftwa re -s e le c ta b le p owe r-d own mod e s .
Accessing the serial interface automatically powers up
the d e vic e s , a nd the q uic k turn-on time a llows the
MAX186/MAX188 to b e s hut d own b e twe e n e ve ry
conversion. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
20 SSOP
20 CERDIP**
Ord e rin g In fo rm a t io n c o n t in u e d o n la s t p a g e .
† NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
*
Dice are specified at +25°C, DC parameters only.
The MAX186/MAX188 are available in 20-pin DIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin DIP.
For applications that call for a parallel interface, see the
MAX180/MAX181 data sheet. For anti-aliasing filters,
consult the MAX274/MAX275 data sheet.
* * Contact factory for availability and processing to MIL-STD-883.
____________________P in Co n fig u ra t io n
TOP VIEW
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
V
20
DD
________________________Ap p lic a t io n s
19 SCLK
Portable Data Logging
Data-Acquisition
CS
18
3
4
17
DIN
MAX186
MAX188
5
16 SSTRB
15 DOUT
High-Accuracy Process Control
Automatic Testing
6
DGND
AGND
7
14
13
12
11
Robotics
8
Battery-Powered Instruments
Medical Instruments
V
SS
9
REFADJ
VREF
SHDN
10
SPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.
DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
V
to AGND ............................................................+0.3V to -6V
to V ..............................................................-0.3V to +12V
SS
Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW
SO (derate 10.00mW/°C above +70°C)........................800mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
CERDIP (derate 11.11mW/°C above +70°C)................889mW
Operating Temperature Ranges:
MAX186_C/MAX188_C ........................................0°C to +70°C
MAX186_E/MAX188_E......................................-40°C to +85°C
MAX186_M/MAX188_M ..................................-55°C to +125°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
SS
V
DD
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND, DGND.............(V - 0.3V) to (V + 0.3V)
CH0–CH7 Total Input Current ..........................................±20mA
VREF to AGND ...........................................-0.3V to (V + 0.3V)
REFADJ to AGND.......................................-0.3V to (V + 0.3V)
Digital Inputs to DGND...............................-0.3V to (V + 0.3V)
SS
DD
DD
DD
DD
Digital Outputs to DGND............................-0.3V to (V + 0.3V)
DD
Digital Output Sink Current .................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
6/MAX18
(V = 5V ±5%; V = 0V or -5V; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
DD
SS
CLK
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T = T
to T , unless otherwise
MAX
A
MIN
noted.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
MAX186A/MAX188A
±0.5
±0.5
±1.0
±0.75
±1.0
±1
MAX186B/MAX188B
MAX186C
Relative Accuracy (Note 2)
LSB
MAX188C
MAX186D/MAX188D
No missing codes over temperature
MAX186A/MAX188A
MAX186B/MAX188B
MAX186C/MAX188C
MAX186D/MAX188D
MAX186 (all grades)
MAX188A
Differential Nonlinearity
Offset Error
DNL
LSB
LSB
±2.0
±3.0
±3.0
±3.0
±3.0
±1.5
±2.0
±2.0
±3.0
Gain Error (Note 3)
MAX188B
MAX188C
MAX188D
LSB
External reference
4.096V (MAX188)
Gain Temperature Coefficient
External reference, 4.096V
±0.8
±0.1
ppm/°C
LSB
Channel-to-Channel
Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096V , 133ksps, 2.0MHz external clock, bipolar input mode)
P-P
Signal-to-Noise + Distortion Ratio
SINAD
70
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-80
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
SFDR
80
dB
dB
65kHz, V = 4.096V (Note 4)
-85
IN
P-P
2
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; V = 0V or -5V; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
DD
SS
CLK
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T = T
to T , unless otherwise
MAX
A
MIN
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
-3dB rolloff
4.5
MHz
kHz
800
Internal clock
5.5
6
10
Conversion Time (Note 5)
t
µs
CONV
External clock, 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
AZ
10
Aperture Jitter
<50
1.7
ps
Internal Clock Frequency
MHz
External compensation, 4.7µF
Internal compensation (Note 6)
Used for data transfer only
0.1
0.1
2.0
0.4
External Clock Frequency Range
MHz
10
ANALOG INPUT
0 to
VREF
Unipolar, V = 0V
SS
Input Voltage Range,
Single-Ended and Differential
(Note 9)
V
Bipolar, V = -5V
SS
±VREF/2
±1
On/off leakage current, V = ±5V
Multiplexer Leakage Current
Input Capacitance
±0.01
16
µA
pF
IN
(Note 6)
INTERNAL REFERENCE (MAX186 only, reference buffer enabled)
T
A
= +25°C
VREF Output Voltage
4.076
4.096
4.116
30
V
VREF Short-Circuit Current
mA
MAX186_C
MAX186_E
MAX186_M
±30
±30
±30
±30
2.5
±50
±60
±80
MAX186A, MAX186B,
MAX186C
VREF Tempco
ppm/°C
MAX186D
Load Regulation (Note 7)
Capacitive Bypass at VREF
0mA to 0.5mA output load
Internal compensation
External compensation
Internal compensation
External compensation
mV
µF
0
4.7
0.01
0.01
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
µF
%
±1.5
EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V)
V
50mV
DD
+
2.50
12
Input Voltage Range
V
Input Current
200
20
350
µA
kΩ
µA
Input Resistance
Shutdown VREF Input Current
1.5
10
V
50mV
-
DD
Buffer Disable Threshold REFADJ
V
_______________________________________________________________________________________
3
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; V = 0V or -5V; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
DD
SS
CLK
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T = T
to T , unless otherwise
MAX
A
MIN
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode
External compensation mode
MAX186
0
Capacitive Bypass at VREF
µF
V/V
µA
4.7
1.678
1.638
Reference-Buffer Gain
MAX188
MAX186
±50
±5
REFADJ Input Current
MAX188
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
V
2.4
V
V
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
INH
6/MAX18
V
INL
0.8
V
HYST
0.15
V
I
V
= 0V or V
DD
±1
15
µA
pF
V
IN
IN
C
(Note 6)
IN
V
INH
V
- 0.5
DD
V
0.5
4.0
V
SHDN Input Low Voltage
INL
I
µA
µA
V
SHDN Input Current, High
SHDN Input Current, Low
SHDN = V
INH
DD
I
-4.0
1.5
SHDN = 0V
INL
V
V
-1.5
SHDN Input Mid Voltage
IM
DD
V
2.75
0.3
V
SHDN Voltage, Floating
SHDN = open
SHDN = open
FLT
SHDN Max Allowed Leakage,
Mid Input
-100
100
nA
V
DIGITAL OUTPUTS (DOUT, SSTRB)
I
= 5mA
0.4
SINK
Output Voltage Low
V
OL
I
= 16mA
SINK
Output Voltage High
V
OH
I
= 1mA
4
V
SOURCE
Three-State Leakage Current
I
±10
15
µA
pF
CS = 5V
L
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
C
OUT
CS = 5V (Note 6)
V
DD
5 ±5%
V
V
0 or
-5 ±5%
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
V
SS
Operating mode
1.5
30
2
2.5
70
10
50
10
mA
I
Fast power-down
DD
µA
µA
Full power-down
Operating mode and fast power-down
Full power-down
I
SS
4
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; V = 0V or -5V; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
DD
SS
CLK
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T = T
to T , unless otherwise
MAX
A
MIN
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Rejection
(Note 8)
V
= 5V ±5%; external reference, 4.096V;
DD
PSR
±0.06
±0.01
±0.5
mV
full-scale input
Negative Supply Rejection
(Note 8)
V
SS
= -5V ±5%; external reference, 4.096V;
PSR
±0.5
mV
full-scale input
Note 1: Tested at V = 5.0V; V = 0V; unipolar input mode.
DD
SS
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at V
+5% and V
-5% only.
SUPPLY
SUPPLY
Note 9: The common-mode range for the analog inputs is from V to V
.
SS
DD
TIMING CHARACTERISTICS
(V = 5V ±5%; V =0V or -5V, T = T
to T , unless otherwise noted.)
MAX
DD
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
1.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AZ
t
DS
100
t
0
DH
MAX18_ _C/E
MAX18_ _M
20
20
150
200
100
100
t
C
= 100pF
SCLK Fall to Output Data Valid
DO
LOAD
t
C
C
= 100pF
= 100pF
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
DV
LOAD
LOAD
t
TR
t
100
0
CSS
t
CSH
t
200
200
CH
t
CL
t
C
= 100pF
200
200
SSTRB
LOAD
CS Fall to SSTRB Output Enable
(Note 6)
t
External clock mode only, C
External clock mode only, C
Internal clock mode only
= 100pF
= 100pF
ns
ns
ns
SDV
LOAD
LOAD
CS Rise to SSTRB Output Disable
(Note 6)
t
200
STR
SSTRB Rise to SCLK Rise
(Note 6)
t
0
SCK
_______________________________________________________________________________________
5
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
POWER-SUPPLY REJECTION
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.30
0.16
V
= +5V ±5%
2.456
DD
0.14
0.12
0.10
0.08
0.06
0.04
0.25
0.20
V
= 0V or -5V
SS
2.455
2.454
2.453
2.452
0.15
0.10
0.05
0.00
-0.05
0.02
0
6/MAX18
-40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX186/MAX188 FFT PLOT – 133kHz
20
0
-20
-40
f = 10kHz
t
f = 133kHz
s
T = +25°C
A
-60
-80
-100
-120
-140
0
33.25kHz
66.5kHz
FREQUENCY
_____________________________________________________________P in De s c rip t io n
PIN
1-8
9
NAME
FUNCTION
CH0-CH7
Sampling Analog Inputs
V
SS
Negative Supply Voltage. Tie to -5V ±5% or AGND
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max)
supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the ref-
erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer
amplifier in external compensation mode.
10
11
SHDN
Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier
(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when
using external compensation mode. Also functions as an input when used with a precision external
reference.
VREF
6
________________________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
________________________________________________P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to
12
REFADJ
V
.
DD
13
14
15
AGND
DGND
DOUT
Analog Ground. Also IN- Input for single-ended conversions.
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external mode).
16
SSTRB
17
18
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
CS
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
19
20
SCLK
V
DD
Positive Supply Voltage, +5V ±5%
+5V
3k
18
CS
DOUT
DOUT
19
SCLK
INPUT
SHIFT
REGISTER
3k
INT
CLOCK
17
10
C
LOAD
C
DIN
LOAD
CONTROL
LOGIC
SHDN
DGND
DGND
1
CH0
15
16
OUTPUT
SHIFT
DOUT
a. High-Z to V and V to V
OH
b. High-Z to V and V to V
OL
OH
OL
OL
OH
2
3
4
CH1
CH2
CH3
REGISTER
SSTRB
Figure 1. Load Circuits for Enable Time
ANALOG
INPUT
MUX
T/H
5
6
CH4
CH5
CLOCK
IN
SAR
ADC
12-BIT
7
8
+5V
CH6
CH7
OUT
20
14
REF
13
V
DD
AGND
3k
A ≈ 1.65
DOUT
DOUT
+2.46V
REFERENCE
(MAX186)
DGND
20k
9
V
SS
12
11
REFADJ
VREF
3k
C
LOAD
C
LOAD
MAX186
MAX188
+4.096V
DGND
DGND
a V to High-Z
OH
b V to High-Z
OL
Figure 3. Block Diagram
Figure 2. Load Circuits for Disabled Time
_______________________________________________________________________________________
7
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
_______________De t a ile d De s c rip t io n
12-BIT CAPACITIVE DAC
The MAX186/MAX188 use a successive-approximation
conversion technique and input track/hold (T/H) circuit-
ry to convert an analog signal to a 12-bit digital output.
A flexible serial interface provides easy interface to
mic rop roc e s s ors . No e xte rna l hold c a p a c itors a re
required. Figure 3 shows the block diagram for the
MAX186/MAX188.
VREF
COMPARATOR
INPUT
MUX
C
HOLD
ZERO
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
16pF
10k
R
S
C
SWITCH
HOLD
P s e u d o -Diffe re n t ia l In p u t
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN– CHANNEL.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Fig ure 4). In s ing le-e nd e d mod e , IN+ is inte rna lly
switched to CH0-CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5 a nd CH6/CH7.
Configure the channels with Table 3 and Table 4.
T/H
SWITCH
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND.
DIFFERENTIAL MODE: IN+ AND IN– SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
6/MAX18
Figure 4. Equivalent Input Circuit
In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
b le within ± 0.5LSB (± 0.1LSB for b e s t re s ults ) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select-
ed analog input, respectively) to AGND.
single-ended inputs, IN- is connected to AGND, and
the converter samples the “+” input. If the converter is
set up for differential inputs, IN- connects to the “-”
input, and the difference of |IN+ - IN-| is sampled. At
the end of the conversion, the positive input connects
back to IN+, and CHOLD charges to the input signal.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by:
tAZ = 9 x (RS + RIN) x 16pF,
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply AGND. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
re ma ind e r of the c onve rs ion c yc le to re s tore nod e
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from CHOLD to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
where RIN = 5kΩ, RS = the source impedance of the
input signal, and tAZ is never less than 1.5µs. Note that
source impedances below 5kΩ do not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
In p u t Ba n d w id t h
The ADC’s inp ut tra c king c irc uitry ha s a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Tra c k /Ho ld
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
b e e n s hifte d in. If the c onve rte r is s e t up for
8
_______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
V
DD
+5V
OSCILLOSCOPE
0.1µF
DGND
AGND
SCLK
V
SS
MAX186
MAX188
SSTRB
DOUT*
0V TO
4.096V
ANALOG
INPUT
CH7
CS
SCLK
DIN
0.01µF
CH4
2MHz
OSCILLATOR
CH3
CH1
CH2
+5V
+5V
DOUT
D1
1N4148
SSTRB
REFADJ
VREF
SHDN
N.C.
C2
0.01µF
C1
4.7µF
**
+2.5V
+2.5V
REFERENCE
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**REQUIRED FOR MAX188 ONLY. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
Figure 5. Quick-Look Circuit
An a lo g In p u t Ra n g e a n d In p u t P ro t e c t io n
Table 1a. Unipolar Full Scale and Zero Scale
Zero
Internal protection diodes, which clamp the analog
input to VDD and VSS, allow the channel input pins to
swing from VSS - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV, or be
lower than VSS by 50mV.
Full Scale
Reference
Scale
Internal Reference
(MAX186 only)
0V
+4.096V
External Reference
at REFADJ
V
x A*
0V
0V
REFADJ
at VREF
VREF
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on-channel.
* A = 1.678 for the MAX186, 1.638 for the MAX188
Table 1b. Bipolar Full Scale, Zero Scale, and
Negative Full Scale
The full-scale input voltage depends on the voltage at
VREF. See Tables 1a and 1b.
Negative
Full Scale
Zero
Scale
Full Scale
Reference
Qu ic k Lo o k
Internal Reference
(MAX186 only)
-4.096V/2
0V
+4.096V/2
To e va lua te the a na log p e rforma nc e of the
MAX186/MAX188 quickly, use the circuit of Figure 5.
The MAX186/MAX188 require a control byte to be writ-
ten to DIN before each conversion. Tying DIN to +5V
fe e d s in c ontrol b yte s of $FF (HEX), whic h trig g e r
External Reference
at REFADJ
-1/2V
+1/2V
REFADJ
REFADJ
0V
0V
x A*
x A*
at VREF
-1/2 VREF
+1/2 VREF
* A = 1.678 for the MAX186, 1.638 for the MAX188
_______________________________________________________________________________________
9
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
single-ended unipolar conversions on CH7 in external
clock mode without powering down between conver-
sions. In external clock mode, the SSTRB output pulses
high for one clock period before the most significant bit
of the 12-bit conversion result comes out of DOUT.
Va rying the a na log inp ut to CH7 s hould a lte r the
sequence of bits from DOUT. A total of 15 clock cycles
is required per conversion. All transitions of the SSTRB
and DOUT outputs occur on the falling edge of SCLK.
The MAX186/MAX188 a re fully c omp a tib le with
Microwire and SPI devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. Microwire and SPI
both transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit, the simplest
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Ho w t o S t a rt a Co n ve rs io n
Example: Simple Software Interface
A conversion is started on the MAX186/MAX188 by
clocking a control byte into DIN. Each rising edge on
SCLK, with CS low, c loc ks a b it from DIN into the
MAX186/MAX188’s internal shift register. After CS falls,
the first arriving logic “1” bit defines the MSB of the
control byte. Until this first “start” bit arrives, any num-
ber of logic “0” bits can be clocked into DIN with no
effect. Table 2 shows the control-byte format.
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode, call
it TB1. TB1 should be of the format: 1XXXXX11
Binary, where the Xs denote the particular channel
and conversion-mode selected.
6/MAX18
Table 2. Control-Byte Format
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
Bit
Name
Description
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion.
See Tables 3 and 4.
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. See Tables 3 and 4.
1
PD1
PD0
Selects clock and power-down modes.
0(LSB)
PD1
PD0
Mode
0
0
Full power-down (IQ = 2µA)
0
1
Fast power-down (IQ = 30µA)
1
1
0
1
Internal clock mode
External clock mode
10 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
Table 3. Channel Selection in Single-Ended Mode (SGL/DIFF = 1)
SEL2 SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
Table 4. Channel Selection in Differential Mode (SGL/DIFF = 0)
SEL2 SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
+
–
+
–
+
–
+
2) Use a general-purpose I/O line on the CPU to pull
Figure 6 shows the timing for this sequence. Bytes RB2
a nd RB3 will c onta in the re s ult of the c onve rs ion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital Output
CS on the MAX186/MAX188 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB3.
In unipolar input mode, the output is straight binary
(s e e Fig ure 15). For b ip ola r inp uts , the outp ut is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.
6) Pull CS on the MAX186/MAX188 high.
______________________________________________________________________________________ 11
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/ SCL/
BIP DIFF
DIN
START SEL2 SEL1 SEL0
PD1 PD0
RB2
B8
RB3
SSTRB
RB1
FILLED WITH
ZEROS
B11
MSB
B0
LSB
DOUT
B10 B9
B7
B6
B5
B4
B3
B2
B1
ACQUISITION
CONVERSION
IDLE
IDLE
A/D STATE
1.5µs (CLK = 2MHz)
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
6/MAX18
• • •
CS
t
t
t
CSH
CSS
CH
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
t
t
TR
DV
DO
DOUT
• • •
Figure 7. Detailed Serial-Interface Timing
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (see Figure 6).
SSTRB and DOUT go into a high-impedance state when
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
In t e rn a l a n d Ex t e rn a l Clo c k Mo d e s
The MAX186/MAX188 may use either an external serial
c loc k or the inte rna l c loc k to p e rform the
successive-approximation conversion. In both clock
modes, the external clock shifts data in and out of the
MAX186/MAX188. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
c loc k mod e . Figure s 7 through 10 show the timing
characteristics common to both modes.
The conversion must complete in some minimum time, or
else droop on the sample -and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
12 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
CS
• • •
• • •
t
t
STR
SDV
SSTRB
• • •
• • •
t
t
SSTRB
SSTRB
SCLK
• • •
•
• • • •
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SCL/
DIP DIFF
START SEL2 SEL1 SEL0
PD1 PD0
SSTRB
t
CONV
FILLED WITH
ZEROS
B11
MSB
B0
LSB
DOUT
B10 B9
B2
B1
ACQUISITION CONVERSION
10µs MAX
IDLE
IDLE
A/D STATE
1.5µs (CLK = 2MHz)
Figure 9. Internal Clock Mode Timing
Internal Clock
will produce the MSB of the conversion at DOUT, fol-
lowed by the remaining bits in MSB-first format (see
Figure 9). CS does not need to be held low once a con-
version is started. Pulling CS high prevents data from
being clocked into the MAX186/MAX188 and three-
states DOUT, but it does not adversely effect an internal
clock-mode conversion already in progress. When inter-
nal clock mode is selected, SSTRB does not go into a
high-impedance state when CS goes high.
In internal clock mode, the MAX186/MAX188 generate
their own conversion clock internally. This frees the
microprocessor from the burden of running the SAR con-
version clock, and allows the conversion results to be
read back at the processor’s convenience, at any clock
rate from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the con-
version is complete. SSTRB will be low for a maximum of
10µs, during which time SCLK should remain low for best
noise performance. An internal register stores data when
the conversion is in progress. SCLK clocks the data out
at this register at any time after the conversion is com-
plete. After SSTRB goes high, the next falling clock edge
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in and
out of the MAX186/MAX188 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time, tAZ
,
is kept above 1.5µs.
______________________________________________________________________________________ 13
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
CS • • •
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB • • •
t
SSTRB
SCLK • • •
PD0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
6/MAX18
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Da t a Fra m in g
__________ Ap p lic a t io n s In fo rm a t io n
The falling edge of CS does not start a conversion on the
MAX186/MAX188. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as:
P o w e r-On Re s e t
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX186/MAX188 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies have
been stabilized, the internal reset time is 100µs and no
conversions should be performed during this phase.
SSTRB is high on power-up and, if CS is low, the first
logical 1 on DIN will be interpreted as a start bit. Until a
conversion takes place, DOUT will shift out zeros.
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after VCC is applied.
OR
The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto the DOUT pin.
Re fe re n c e -Bu ffe r Co m p e n s a t io n
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
If a falling edge on CS forces a start bit before bit 5
(B5) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX186/MAX188 can run is 15 clocks per
conversion. Figure 11a shows the serial-interface timing
ne c e ssa ry to p e rform a c onve rsion e ve ry 15 SCLK
cycles in external clock mode. If CS is low and SCLK is
continuous, guarantee a start bit by first clocking in 16
zeros.
To select external compensation, float SHDN. See the
Typical Operating Circuit, which uses a 4.7µF capacitor at
VREF. A value of 4.7µF or greater ensures stability and
allows operation of the converter at the full clock speed of
2MHz. External compensation increases power-up time (see
the Choosing Power-Down Mode section, and Table 5).
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
d rive the MAX186/MAX188. Fig ure 11b s hows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal com-
pensation allows for shortest power-up times, but is only
available using an external clock and reduces the maxi-
mum clock rate to 400kHz.
14 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
CS
1
8
1
8
1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
DOUT
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
using low-leakage capacitors that will not discharge
more than 1/2LSB while shut down. In shutdown, the
capacitor has to supply the current into the reference
(1.5µA typ) and the transient currents at power-up.
P o w e r-Do w n
Choosing Power-Down Mode
You c a n s a ve p owe r b y p la c ing the c onve rte r in a
low-c urre nt s hutd own s ta te b e twe e n c onve rs ions .
Select full power-down or fast power-down mode via
bits 7 and 8 of the DIN control byte with SHDN high or
floating (see Tables 2 and 6). Pull SHDN low at any time
to shut down the converter completely. SHDN overrides
bits 7 and 8 of DIN word (see Table 7).
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX186/MAX188 have already entered a
software power-down.
Full power-down mode turns off all chip functions that draw
quiescent current, reducing IDD and ISS typically to 2µA.
Fast power-down mode turns off all circuitry except the
bandgap reference. With the fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
In both software shutdown modes, the serial interface
remains operational, however, the ADC will not convert.
Table 5 illustrates how the choice of reference-buffer
c omp e ns a tion a nd p owe r-d own mod e a ffe c ts b oth
power-up delay and maximum sample rate.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX186/MAX188. Following the
start bit, the data input word or control byte also deter-
mines clock and power-down modes. For example, if
the DIN word c onta ins PD1 = 1, the n the c hip will
remain powered up. If PD1 = 0, a power-down will
resume after one conversion.
In external compensation mode, the power-up time is
20ms with a 4.7µF compensation capacitor (200ms with
a 33µF capacitor) when the capacitor is fully discharged.
In fast power-down, you can eliminate start-up time by
______________________________________________________________________________________ 15
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 1
S X X X X X 1 1
DOUT
DATA VALID
DATA VALID
VALID DATA INVALID
(12 DATA BITS)
(12 DATA BITS)
POWERED
UP
FULL
POWER
DOWN
POWERED UP
POWERED UP
POWER-DOWN
MODE
FAST
6/MAX18
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Table 5. Typical Power-Up Delay Times
Reference
Buffer
Reference-
Buffer
Compensation
Mode
VREF
Capacitor
(µF)
Power-
Down
Mode
Power-Up
Delay
(sec)
Maximum
Sampling
Rate (ksps)
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
Fast
Full
Fast
Full
Fast
Full
5µ
26
300µ
26
4.7
4.7
See Figure 14c
133
133
133
133
See Figure 14c
2µ
2µ
Table 6. Software Shutdown and Clock Mode
Table 7. Hard-Wired Shutdown and
Compensation Mode
PD1 PD0
Device Mode
SHDN
State
Device
Mode
Reference-Buffer
Compensation
1
1
0
0
1
0
1
0
External Clock Mode
Internal Clock Mode
Fast Power-Down Mode
Full Power-Down Mode
1
Floating
0
Enabled
Internal Compensation
External Compensation
N/A
Enabled
Full Power-Down
16 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
CLOCK
MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
FULL
POWER-DOWN
POWERED UP
POWERED
UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Hardware Power-Down
Lowest Power at up to 500
Conversions/Channel/Second
The SHDN p in p la c e s the c onve rte r into the full
power-down mode. Unlike with the software shut-down
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
The following examples illustrate two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX186 power consumption for
one or e ig ht c ha nne l c onve rs ions utilizing full
power-down mode and internal reference compensation.
A 0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.2ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up. Waiting
2ms in FASTPD mode instead of full power-up will reduce
the power consumption by a factor of 10 or more. This is
achieved by using the sequence shown in Figure 13.
P o w e r-Do w n S e q u e n c in g
The MAX186/MAX188 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. The following discussion illus-
trates the various power-down sequences.
COMPLETE CONVERSION SEQUENCE
2ms WAIT
0 1
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
FULLPD
2.5V
1
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
FASTPD
NOPD
REFADJ
VREF
0V
4V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 15µs
BUFFEN
Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence
______________________________________________________________________________________ 17
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
MAX186
FULL POWER-DOWN
1000
MAX186/MAX188
FAST POWER-DOWN
10,000
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
8 CHANNELS
INTERNAL COMPENSATION
8 CHANNELS
100
1000
100
1 CHANNEL
1 CHANNEL
10
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
1
10
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
0
2k 4k 6k 8k 10k 12k 14k 16k 18k
CONVERSIONS PER CHANNEL PER SECOND
6/MAX18
Figure 14a. MAX186 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
Fig ure 14b . MAX186/MAX188 Sup p ly Curre nt vs . Sa mp le
Rate/Second, FASTPD, 2MHz Clock
Lowest Power at Higher Throughputs
3.0
2.5
2.0
1.5
1.0
Fig ure 14b s hows the p owe r c ons ump tion with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF compensation requires a 50µs wait after power-up,
accomplished by 75 idle clocks after a dummy conver-
sion. This circuit combines fast multi-channel conversion
with lowe s t p owe r c ons ump tion p os s ib le . Full
power-down mode may provide increased power sav-
ings in applications where the MAX186/MAX188 are
inactive for long periods of time, but where intermittent
bursts of high-speed conversions are required.
0.5
0
Ex t e rn a l a n d In t e rn a l Re fe re n c e s
0.0001 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
The MAX186 can be used with an internal or external
reference, whereas an external reference is required for
the MAX188. Diode D1 shown in the Typical Operating
Circuit ensures correct start-up. Any standard signal
diode can be used. For both parts, an external refer-
ence can either be connected directly at the VREF ter-
minal or at the REFADJ pin.
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
External Reference
With both the MAX186 and MAX188, an external refer-
ence can be placed at either the input (REFADJ) or the
outp ut (VREF) of the inte rna l b uffe r a mp lifie r. The
REFADJ inp ut imp e d a nc e is typ ic a lly 20kΩ for the
MAX186 and higher than 100kΩ for the MAX188, where
the internal reference is omitted. At VREF, the input
imp e d a nc e is a minimum of 12kΩ for DC c urre nts .
During conversion, an external reference at VREF must
be able to deliver up to 350µA DC load current and have
an output impedance of 10Ω or less. If the reference has
higher output impedance or is noisy, bypass it close to
the VREF pin with a 4.7µF capacitor.
An internal buffer is designed to provide 4.096V at
VREF for b oth the MAX186 a nd MAX188. The
MAX186’s inte rna lly trimme d 2.46V re fe re nc e is
buffered with a gain of 1.678. The MAX188's buffer is
trimmed with a buffer gain of 1.638 to scale an external
2.5V reference at REFADJ to 4.096V at VREF.
MAX186 Internal Reference
The full-scale range of the MAX186 with internal reference
is 4.096V with unipolar inputs, and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the Reference-Adjust Circuit of Figure 17.
18 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
011 . . . 111
11 . . . 110
11 . . . 101
011 . . . 110
FS = +4.096
2
1LSB = +4.096
000 . . . 010
000 . . . 001
000 . . . 000
4096
FS = +4.096V
1LSB = FS
4096
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0V
0
1
2
3
FS
-FS
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
Fig ure 15. MAX186/MAX188 Unip ola r Tra ns fe r Func tion,
4.096V = Full Scale
Fig ure 16. MAX186/MAX188 Bip ola r Tra ns fe r Func tion,
±4.096V/2 = Full Scale
Us ing the b uffe re d REFADJ inp ut a void s e xte rna l
buffering of the reference. To use the direct VREF input,
+5V
disable the internal buffer by tying REFADJ to VDD
.
MAX186
510k
Tra n s fe r Fu n c t io n a n d Ga in Ad ju s t
100k
REFADJ
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive integer LSB values. Output
coding is binary with 1 LSB = 1.00mV (4.096V/4096) for
unipolar operation and 1 LSB = 1.00mV ((4.096V/2 -
-4.096V/2)/4096) for bipolar operation.
12
0.01µF
24k
Figure 17. MAX186 Reference-Adjust Circuit
Figure 17, the MAX186 Reference-Adjust Circuit, shows
how to adjust the ADC gain in applications that use the
inte rna l re fe re nc e . The c irc uit p rovid e s ± 1.5%
(±65LSBs) of gain adjustment range.
and DGND should be connected to this ground. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped-
ance and as short as possible for noise-free operation.
La yo u t , Gro u n d in g , Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
0.1µF a nd 4.7µF b yp a s s c a p a c itors c los e to the
MAX186/MAX188. Minimize capacitor lead lengths for
best supply-noise rejection. If the +5V power supply is
very noisy, a 10Ω resistor can be connected as a low-
pass filter, as shown in Figure 18.
Figure 18 shows the recommended system ground
c onne c tions . A s ing le -p oint a na log g round (“s ta r”
ground point) should be established at AGND, sepa-
rate from the logic ground. All other analog grounds
______________________________________________________________________________________ 19
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
Hig h -S p e e d Dig it a l In t e rfa c in g w it h QS P I
The MAX186/MAX188 can interface with QSPI at high
throughput rates using the circuit in Figure 19. This
QSPI circuit can be programmed to do a conversion on
each of the eight channels. The result is stored in mem-
ory without taxing the CPU since QSPI incorporates its
own micro-sequencer. Figure 19 depicts the MAX186,
but the same circuit could be used with the MAX188 by
adding an external reference to VREF and connecting
SUPPLIES
+5V
-5V
GND
R* = 10Ω
REFADJ to VDD
.
Fig ure 20 d e ta ils the c od e tha t s e ts up QSPI for
autonomous operation. In external clock mode, the
MAX186/MAX188 perform a single-ended, unipolar con-
version on each of their eight analog input channels.
Figure 21, QSPI Assembly-Code Timing, shows the tim-
ing associated with the assembly code of Figure 20. The
first byte clocked into the MAX186/MAX188 is the control
byte, which triggers the first conversion on CH0. The last
two bytes clocked into the MAX186/MAX188 are all zero
and clock out the results of the CH7 conversion.
V
AGND
V
SS
DGND
+5V DGND
DD
DIGITAL
CIRCUITRY
6/MAX18
MAX186/MAX188
* OPTIONAL
Figure 18. Power-Supply Grounding Connection
+5V
V
, V
, V
, V
0.1µF
4.7µF
DDI
DDE
DDSYN STBY
1
20
19
18
CH0
CH1
CH2
V
DD
2
SCLK
CS
SCK
3
4
PCS0
MOSI
MC68HC16
CH3 MAX186
ANALOG
INPUTS
DIN 17
16
5
6
CH4
CH5
CH6
CH7
SSTRB
15
MISO
DOUT
7
DGND 14
13
8
AGND
9
12
11
V
REFADJ
VREF
SS
0.01µF
10
SHDN
+
4.7µF
0.1µF
V
SSI
VSSE
* CLOCK CONNECTIONS NOT SHOWN
Figure 19. MAX186 QSPI Connection
20 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
*Title : MAX186.ASM
* Description :
*
*
*
*
This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM
is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software
provided in the Motorola 68HC16 Evaluation Kit.
* Roger J.A. Chen, Applications Engineer
* MAXIM Integrated Products
* November 20, 1992
*
******************************************************************************************************************************************************
INCLUDE
INCLUDE
INCLUDE
ORG $0200
‘EQUATES.ASM’ ;Equates for common reg addrs
‘ORG00000.ASM’ ;initialize reset vector
‘ORG00008.ASM’ ;initialize interrupt vectors
;start program after interrupt vectors
INCLUDE ‘INITSYS.ASM’
;set EK=F,XK=0,YK=0,ZK=0
;set sys clock at 16.78 MHz, COP off
INCLUDE ‘INITRAM.ASM’ ;turn on internal SRAM at $10000
;set stack (SK=1, SP=03FE)
MAIN:
JSR INITQSPI
MAINLOOP:
JSR READ186
WAIT:
LDAA SPSR
ANDA #$80
BEQ WAIT
BRA MAINLOOP
;wait for QSPI to finish
ENDPROGRAM:
INITQSPI:
;This routine sets up the QSPI microsequencer to operate on its own.
;The sequencer will read all eight channels of a MAX186/MAX188 each time
;it is triggered. The A/D converter results will be left in the
;receive data RAM. Each 16 bit receive data RAM location will
;have a leading zero, 12 bits of conversion result and three zeros.
;
;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
;A/D Result
0
MSB
LSB 0 0 0
***** Initialize the QSPI Registers ******
PSHA
PSHB
LDAA #%01111000
STAA QPDR
;idle state for PCS0-3 = high
LDAA #%01111011
STAA QPAR
LDAA #%01111110
STAA QDDR
;assign port D to be QSPI
;only MISO is an input
LDD #$8008
STD SPCR0
;master mode,16 bits/transfer,
;CPOL=CPHA=0,1MHz Ser Clock
LDD #$0000
STD SPCR1
;set delay between PCS0 and SCK,
Figure 20. MAX186/MAX188 Assembly-Code Listing
______________________________________________________________________________________ 21
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
;set delay between transfers
LDD #$0800
STD SPCR2
;set ENDQP to $8 for 9 transfers
***** Initialize QSPI Command RAM *****
LDAA #$80
STAA $FD40
LDAA #$C0
STAA $FD41
STAA $FD42
STAA $FD43
STAA $FD44
STAA $FD45
STAA $FD46
STAA $FD47
LDAA #$40
STAA $FD48
;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE
;store first byte in COMMAND RAM
;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
6/MAX18
***** Initialize QSPI Transmit RAM *****
LDD #$008F
STD $FD20
LDD #$00CF
LDD #$009F
LDD #$00DF
LDD #$00AF
LDD #$00EF
LDD #$00BF
LDD #$00FF
LDD #$0000
STD $FD22
STD $FD24
STD $FD26
STD $FD28
STD $FD2A
STD $FD2C
STD $FD2E
STD $FD30
PULB
PULA
RTS
READ186:
;This routine triggers the QSPI microsequencer to autonomously
;trigger conversions on all 8 channels of the MAX186. Each
;conversion result is stored in the receive data RAM.
PSHA
LDAA #$80
ORAA SPCR1
STAA SPCR1
PULA
;just set SPE
RTS
***** Interrupts/Exceptions *****
BDM: BGND
;exception vectors point here
Figure 20. MAX186/MAX188 Assembly-Code Listing (continued)
22 ______________________________________________________________________________________
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
6/MAX18
CS
• • • •
• • • •
SCLK
SSTRB
DIN
• • • •
• • • •
Figure 21. QSPI Assembly-Code Timing
TMS320C3x to MAX186 Interface
Figure 22 shows an application circuit to interface the
MAX186/MAX188 to the TMS320 in e xte rna l c loc k
mode. The timing diagram for this interface circuit is
shown in Figure 23.
XF
CS
CLKX
SCLK
TMS320C3x
Use the following steps to initiate a conversion in the
MAX186/MAX188 and to read the results:
MAX186
MAX188
CLKR
DX
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
CLKX and CLKR of the TMS320 are tied together with
the SCLK input of the MAX186/MAX188.
DIN
DR
DOUT
SSTRB
FSR
2) The MAX186/MAX188 CS is driven low by the XF_
I/O port of the TMS320 to enable data to be clocked
into DIN of the MAX186/MAX188.
Figure 22. MAX186/MAX188 to TMS320 Serial Interface
3) An 8-bit word (1XXXXX11) should be written to the
MAX186/MAX188 to initiate a conversion and place
the device into external clock mode. Refer to Table
2 to select the proper XXXXX bit values for your spe-
cific application.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
4) The SSTRB output of the MAX186/MAX188 is moni-
tored via the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the MAX186/MAX188.
6) Pull CS high to disable the MAX186/MAX188 until
the next conversion is initiated.
______________________________________________________________________________________ 23
Lo w -P o w e r, 8 -Ch a n n e l,
S e ria l 1 2 -Bit ADCs
CS
SCLK
DIN
START SEL2
SEL1
SEL0 UNI/BIP SGL/DIF PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB B10
B1
LSB
Figure 23. TMS320 Serial Interface Timing Diagram
X
__________Typ ic a l Op e ra t in g Circ u it
___________________Ch ip To p o g ra p h y
SCLK
V
DD
CH1 CH0
+5V
V
DD
V
CH0
CH2
CH3
DD
CS
C3
0.1µF
0V to
4.096V
ANALOG
INPUTS
DGND
AGND
DIN
C4
0.1µF
CH4
CPU
CH7
V
SS
MAX186
I/O
CS
SSTRB
DOUT
SCLK
SCK (SK)*
MOSI (SO)
MISO (SI)
0.151"
(3.84 mm)
VREF
DIN
C1
4.7µF
DOUT
CH5
CH6
SSTRB
SHDN
REFADJ
V
SS
C2
0.01µF
DGND
AGND
CH7
V
SHDN VREF REFADJ AGND
SS
_Ord e rin g In fo rm a t io n (c o n t in u e d )
0.117"
(2.97 mm)
†
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
20 Plastic DIP
20 SO
MAX188_CPP
MAX188_CWP
MAX188_CAP
MAX188DC/D
MAX188_EPP
MAX188_EWP
MAX188_EAP
MAX188_MJP
MAX186/MAX188
0°C to +70°C
0°C to +70°C
20 SSOP
TRANSISTOR COUNT: 2278;
SUBSTRATE CONNECTED TO V
DD
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
Plastic DIP
20 SO
20 SSOP
20 CERDIP**
† NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
* Dice are specified at +25°C, DC parameters only.
PART
TEMP. RANGE
BOARD TYPE
MAX186EVKIT-DIP
0°C to +70°C
Through-Hole
* * Contact factory for availability and processing to MIL-STD-883.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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