MAX1888EUA+ [MAXIM]
Analog Circuit, 1 Func, CMOS, PDSO8, MICRO MAX PACKAGE-8;
| 型号： | MAX1888EUA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO8, MICRO MAX PACKAGE-8 光电二极管 |
| 文件： | 总7页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2189; Rev 1; 2/02
Low-Cost Integrated Offset Logic
for Notebook CPU Power Supplies
General Description
Features
The MAX1888 is a three-input decoder with three open-
drain outputs. It is used with the MAX1718 or a similar
DC-to-DC controller to offset the CPU core voltage in
notebook computers. Designed to interface with low-
voltage logic, the MAX1888 can program the controller
for three independent offsets. The circuit is extremely
low cost and is available in an 8-pin µMAX package.
ꢀ Simple, Low-Cost Offset Voltage Control
for CPU Core Power Supplies
ꢀ IMVP II Logic Interface
ꢀ 3V to 5.5V Supply Voltage
ꢀ Low 30µA (max) Supply Current
ꢀ 8-Pin µMAX Package
Applications
Ordering Information
CPU Core Supplies for Intel IMVP II Notebook
Computers
PART
TEMP RANGE
PIN-PACKAGE
MAX1888EUA
-40°C to +85°C
8 µMAX
Minimal Operating Circuit
Pin Configuration
TOP VIEW
POS
INPUT
SUPPLY
V
CC
OFFSET
ADJUST
MAX1888
DPSLP
PERF
SUS
1
2
3
4
8
7
6
5
V
CC
NEG
LOW-
DPSLP
PERF
SUS
BSM
PSM
BOM
BSM
PSM
BOM
OPEN-DRAIN
DECODER
OUTPUTS
VOLTAGE
LOGIC
MAX1888
INPUTS
GND
GND
µMAX
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND..............................................................-0.3V to +6V
Extended Operating Temperature.......................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PERF, SUS, DPSLP, BOM, PSM, BSM to GND ........-0.3V to +6V
Continuous Power Dissipation
8-Pin µMAX (derate 4.5mW/°C above +70°C)...........362.0mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
= +5V, T = -40°C to +85°C, unless otherwise noted.)
A
CC
PARAMETER
POWER SUPPLY
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range (V
)
CC
3.0
5.5
V
BIAS
All inputs = 0
< 0.01
10
1
Quiescent Supply Current (V
)
CC
µA
All inputs = 1.5V
30
LOGIC AND I/Os
Logic Input High Voltage
(PERF, SUS, DPSLP),
Hysteresis = 40mV (typ)
3V < V
3V < V
< 5.5V
< 5.5V
1.2
-1
V
V
CC
CC
Logic Input Low Voltage
(PERF, SUS, DPSLP),
Hysteresis = 40mV (typ)
0.4
0.3
Logic Input Current
1
µA
I
I
= 5mA
20
50
LOAD
LOAD
Output On-Resistance
(BOM, BSM, PSM)
Ω
= 5mA, 3V < V
< 5.5V
100
CC
Output Leakage Current
(BOM, BSM, PSM)
V(pin) = 5V
< 0.01
1
µA
DYNAMICS
Falling edge, 1.5V to 0V step in 2ns
Rising edge, 0 to 1.5V step in 2ns
700
70
Propagation Delay
ns
2
_______________________________________________________________________________________
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
Typical Operating Characteristics
(Circuit of Figure 1, logic high = 1.5V, V
= 1.3V, T = +25°C, unless otherwise noted.)
OUT
A
SUPPLY CURRENT VS. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
OUTPUT R VS. SUPPLY VOLTAGE
ON
MAX1888toc01
100
16
40
35
30
25
20
15
10
T = +85°C
A
A
B
V
= 5V
10
1
CC
12
8
T = +25°C
A
T = -40°C
A
0.1
V
= 4.5V
CC
C
D
4
0.01
V
= 3.3V
CC
0.001
0
3.0
3.5
4.0
4.5
(V)
5.0
5.5
-40
-15
10
35
60
85
3.0
3.5
4.0
4.5
(V)
5.0
5.5
TEMPERATURE (°C)
V
V
CC
CC
A = ALL INPUTS = 1.5V
B = ALL INPUTS = 3.3V
C = ALL INPUTS = 5V
D = ALL INPUTS = 0.4V
SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS
(OUTPUT TRANSITIONS INTO A 10kΩ LOAD)
(OUTPUT TRANSITIONS INTO A 10kΩ LOAD)
OUTPUT R VS. TEMPERATURE
ON
MAX1888 toc05
MAX1888 toc06
40
35
30
25
20
15
10
A
V
= 3.3V
CC
A
V
= 3.3V
CC
B
V
= 5V
CC
V
= 5V
CC
B
V
= 3.3V
CC
V
= 5V
CC
20ns/div
400ns/div
-40
-15
10
35
60
85
A = V , 1V/div
A = V , 1V/div
IN
IN
TEMPERATURE (°C)
B = V , 1V/div
B = V , 1V/div
OUT
OUT
Pin Description
PIN
NAME
DPSLP
PERF
SUS
FUNCTION
1
2
3
4
5
6
Deep-Sleep Mode Control Digital Input
Performance-Mode Offset Control Digital Input
Suspend-Mode (Deeper Sleep) Control Digital Input
Ground
GND
BOM
PSM
Open-Drain Output for Battery Operating Mode (BOM)
Open-Drain Output for Performance Sleep Mode (PSM)
Open-Drain Output for Battery Sleep Mode (BSM)
Supply Voltage
7
8
BSM
V
CC
_______________________________________________________________________________________
3
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
TTable 1. Truth Table
INPUTS
OUTPUTS
MODE
Deeper Sleep
DPSLP
PERF
SUS
BSM
Hi-Z
L
PSM
Hi-Z
Hi-Z
L
BOM
Hi-Z
Hi-Z
Hi-Z
L
X
L
X
L
H
L
L
L
L
Battery Sleep
Performance Sleep
Battery Operating
Performance
L
H
L
Hi-Z
Hi-Z
Hi-Z
H
H
Hi-Z
Hi-Z
H
Hi-Z
Detailed Description
Logic Characteristics
The MAX1888 is a three-input decoder with three open-
drain outputs. It is used with the MAX1718 DC-to-DC
controller to offset the CPU core voltage in notebook
computers. The MAX1718 has two dedicated inputs
(POS and NEG) that simplify the task of offsetting its
output voltage. Specifically, the output voltage shifts by
an amount equal to the difference between POS and
NEG multiplied by a scale factor that depends on the
DAC code (refer to the MAX1718 data sheet). The volt-
age between the POS and NEG inputs can be set with
a programmable voltage-divider using the MAX1888 to
connect the bottom resistor of the divider to ground
(see Figure 1.)
The Intel mobile processor specifications require inde-
pendent offset to the CPU core voltage for battery
sleep mode (BSM), performance sleep mode (PSM)
and battery-operating mode (BOM). No offsets are
required for the deeper-sleep mode (DPSLP) and per-
formance mode (PERF). Table 1 explicitly describes
the logical operation of the decoder.
The decoder’s inputs may come from system-level
logic or directly from the CPU. To interface with low-
voltage logic, the MAX1888’s input logic thresholds are
designed with an input-logic high voltage of 1.2V (min)
and an input-logic low voltage of 0.3V (max). The logic
inputs also include 40mV (typ) hysteresis to improve
noise immunity.
The output on-resistance is guaranteed to be less than
100Ω over the entire supply voltage and temperature
range. When loaded with a total pullup resistance
greater than 10kΩ, the open-drain output resistance
causes less than 1% error in impedance. If the offset
voltage is set to 5% of the regulated output voltage,
then the effect of the impedance error on the output
voltage is approximately 0.05%, which is negligible in
most applications.
V
OUT
NEG
POS
TO
MAX1718
5V INPUT
V
CC
MAX1888
The MAX1888 has rising- and falling-edge propagation
delays of 70ns (typ) and 700ns (typ), respectively.
Since transition times for CPU core voltage are typically
much longer than these intervals, such delays are neg-
ligible. Note the time constant of the rising edge in the
output voltage is set by the capacitance of the open-
drain output transistor and the load impedance (see
the Typical Operating Characteristics).
LOW-
VOLTAGE
LOGIC
DPSLP
PERF
SUS
BSM
PSM
BOM
OPEN-DRAIN
DECODER
OUTPUTS
INPUTS
GND
Figure 1. Simplified Application Circuit; Also Used for
Obtaining Characterization Data; Offset Voltage is a
Percentage of the Output Voltage.
4
_______________________________________________________________________________________
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
R1
20Ω
5V INPUT
C8
C1
0.22µF
17
9
0.1µF
BATT 7V TO 24V
V
V
DD
CC
1
2
SKP/SDN
V+
C2, 25V, X5R
5 x 10µF
D1
10
26
CMPSH-3
SHUTDOWN
TON
BST
2x
2x
IRF7811A
Q1
25
24
V
L1
CC
28
R8
D0
D1
DH
OUTPUT
0.68µH
0.004Ω
0.6V TO 1.75V
C3
0.1µF
SUMIDA
R2
100kΩ
C4
CEP125#4712-TO11
27
16
23
LX
DL
6 x 270µF, 2V
PANASONIC SP
EEFUE0E271R
D2
D2
R3
100kΩ
FDS7764A
Q2
CENTRAL
SEMICONDUCTOR
CMSH5-40
5V INPUT
C7
MAX1718
22
21
D3
D4
8
V
CC
15
4
0.1µF
GND
FB
MAX1888
19
18
ZMODE
SUS
7
6
5
1
2
3
MUX CONTROL
BSM
PSM
BOM
DPSLP
PERF
SUS
LOGIC
INPUTS
REF
7
8
SUSPEND
INPUT
DECODER
S0
S1
5
4
NEG
POS
GND
R4
62kΩ
R10
1kΩ
R11
R12
R13
82.5kΩ
3
6
TIME
CC
26.7kΩ
15.8kΩ
C6
47pF
13
5V
C5
0.22µF
R5
100kΩ
11
12
REF
14
20
POWER-GOOD
OUTPUT
R18
24.9kΩ
VGATE
OVP
ILIM
R19
27.4kΩ
Figure 2. Typical Application Circuit
_______________________________________________________________________________________
5
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
Supply Current
V
REF
The MAX1888 needs no shutdown control. The circuit
consumes virtually no current (I(V ) < 1µA) when all
CC
NEG
POS
the logic inputs are 0V, and less than 30µA when all the
logic inputs are 1.5V. In general, the supply current
increases with supply voltage and decreases with the
logic input voltage. For a given supply voltage, the sup-
ply current decreases with temperature (see the
Typical Operating Characteristics).
TO
MAX1718
5V INPUT
V
CC
MAX1888
LOW-
VOLTAGE
LOGIC
DPSLP
PERF
SUS
BSM
PSM
BOM
Applications Information
OPEN-DRAIN
DECODER
OUTPUTS
Figure 2 shows a typical CPU core supply application
using the MAX1888 and the MAX1718. The voltage
dividers are set to obtain negative offsets of 1%, 3%,
and 5% of the output voltage for battery-operating
mode (BOM), battery sleep mode (BSM), and perfor-
mance sleep mode (PSM), respectively. The offset volt-
age is given by the following equation:
INPUTS
GND
Figure 3. Using the MAX1888 to Set the Offset Voltage
Independent of V
OUT
V
= K V
− V
(
)
OFFSET
POS NEG
The MAX1888 can be inserted in the feedback path of
any regulator to offset the output voltage. An external
reference greater than the feedback set point is need-
ed to affect negative offsets. The basic arrangement is
shown in Figure 4.
where K is the DAC code-dependent scale factor (refer
to Table 3 in the MAX1718 data sheet). The offset volt-
age in each mode is:
R10
V
= − K
= − K
= − K
V
OUT
OFFSET,BOM
R10 + R13
V
REF
V
OUT
R10
V
V
OUT
OFFSET,BSM
R10 + R11
5V INPUT
R10
V
FB
V
V
OUT
OFFSET,PSM
V
R10 + R12
CC
MAX1888
Note that divider ratio in each mode must be adjusted
for a given DAC code. The circuit in Figure 2 assumes
OUT
values for R11, R12, R13 in the divider are 26.7kΩ,
15.8kΩ, and 82.5kΩ, respectively. Please note that
these offsets are provided as an example only. Contact
Intel for specific offset requirements.
LOW-
VOLTAGE
LOGIC
DPSLP
PERF
SUS
BSM
PSM
BOM
V
= 1V with K = 0.84 and R10 = 1kΩ. The resulting
OPEN-DRAIN
DECODER
OUTPUTS
INPUTS
GND
The circuits in Figures 1 and 2 set the offset voltage as
a percentage of the output voltage. Alternatively, the
offset can be set as independent of the output voltage
by biasing the POS and NEG inputs from a fixed refer-
ence voltage (see Figure 3).
Figure 4. Inserting the MAX1888 into the Feedback Path of Any
Regulator to Shift Output Voltage
6
_______________________________________________________________________________________
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
Layout Guidelines
Chip Information
Most applications do not drive the MAX1888 with high
frequency signals with ultra-fast transition times.
Therefore, the layout requirements are minimal. Keep
the resistive voltage-divider traces away from noisy
nodes and terminate the dividers through the MAX1888
to quiet analog ground. Place a 0.1µF decoupling
capacitor close to the device.
TRANSISTOR COUNT: 170
PROCESS: CMOS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50±0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6±0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
α
S
0.6±0.1
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
α
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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