MAX189 [MAXIM]
+5V.Low-Power.12-Bit Serial ADCs ; + 5V.Low - Power.12位串行模数转换器\n
| 型号： | MAX189 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +5V.Low-Power.12-Bit Serial ADCs
|
| 文件： | 总20页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0196; Rev 0; 10/93
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
__________________Ge n e ra l De s c rip t io n
________________________________Fe a t u re s
♦ 12-Bit Resolution
The MAX187/MAX189 serial 12-bit analog-to-digital
converters (ADCs) operate from a single +5V supply
and accept a 0V to 5V analog input. Both parts feature
a n 8.5µs s uc c e s s ive -a p p roxima tion ADC, a fa s t
track/hold (1.5µs), an on-chip clock, and a high-speed
3-wire serial interface.
♦ ±1⁄
LSB Integral Nonlinearity (MAX187A/MAX189A)
2
♦ Internal Track/Hold, 75kHz Sampling Rate
♦ Single +5V Operation
7/MAX189
♦ Low Power: 2µA Shutdown Current
1.5mA Operating Current
The MAX187/MAX189 d ig itize s ig na ls a t a 75ks p s
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and micro-
c ontrolle rs . The inte rfa c e is c omp a tib le with SPI™,
QSPI™, and Microwire™.
♦ Internal 4.096V Buffered Reference (MAX187)
♦ 3-Wire Serial Interface, Compatible with SPI,
QSPI, and Microwire
♦ Small-Footprint 8-Pin DIP and 16-Pin SO
_________________Ord e rin g In fo rm a t io n
The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin DIP and
16-pin SO packages. Power consumption is 7.5mW
and reduces to only 10µW in shutdown.
ERROR
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX187ACPA
MAX187BCPA
MAX187CCPA
MAX187ACWE
MAX187BCWE
MAX187CCWE
MAX187BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
16 Wide SO
16 Wide SO
16 Wide SO
Dice*
±1⁄
±1
2
Excellent AC characteristics and very low power con-
sumption combined with ease of use and small pack-
age size make these converters ideal for remote DSP
and sensor applications, or for circuits where power
consumption and space are crucial.
±2
±1⁄
±1
±2
±1
2
___________________________Ap p lic a t io n s
Portable Data Logging
Ordering Information continued on last page.
* Dice are specified at T = +25°C, DC parameters only.
A
Remote Digital Signal Processing
Isolated Data Acquisition
** Contact factory for availability and processing to MIL-STD-883.
High-Accuracy Process Control
_________________P in Co n fig u ra t io n s
________________Fu n c t io n a l Dia g ra m
6
TOP VIEW
OUTPUT
SHIFT
REGISTER
DOUT
SCLK
8
5
GND
REF-
DAC
REF+
AV = 1.638
10k
(4.096V)
V
DD
1
2
3
4
8
7
6
5
+2.5V
BANDGAP
SCLK
CS
AIN
SHDN
REF
REFERENCE
(MAX187 ONLY)
12-BIT
SAR
MAX187
MAX189
DOUT
4
2
REF
GND
AIN
T/H
COMPARATOR
DIP
7
3
MAX187
MAX189
CS
CONTROL
AND
BUFFER ENABLE/DISABLE
1
TIMING
SHDN
V
DD
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY.
Pin Configurations continued on last page.
™ SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.
________________________________________________________________ Maxim Integrated Products
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
1
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND .............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AIN to GND................................................-0.3V to (V + 0.3V)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ..500mW
16-Pin Wide SO (derate 8.70mW/°C above +70°C) ...478mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C) ......440mW
Operating Temperature Ranges:
DD
REF to GND ...............................................-0.3V to (V + 0.3V)
DD
Digital Inputs to GND.................................-0.3V to (V + 0.3V)
DD
Digital Outputs to GND..............................-0.3V to (V + 0.3V)
DD
SHDN to GND.............................................-0.3V to (V + 0.3V)
MAX187_C_ _/MAX189_C_ _.............................0°C to +70°C
MAX187_E_ _/MAX189_E_ _ ..........................-40°C to +85°C
MAX187_MJA/MAX189_MJA .......................-55°C to +125°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
DD
REF Load Current (MAX187) .........................4.0mA Continuous
REF Short-Circuit Duration (MAX187)................................20sec
DOUT Current..................................................................±20mA
7/MAX189
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
MAX1
(V
= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
= 4.0MHz, external clock (50% duty cycle); MAX187—internal
DD
CLK
reference: V
= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V
= 4.096V applied to REF pin, 4.7µF
REF
REF
capacitor at REF pin; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
12
MAX18_A
MAX18_B
MAX18_C
±1⁄
±1
±2
±1
±11⁄
±3
2
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
MAX18_A
LSB
LSB
2
MAX18_B/C
MAX187
±3
Gain Error (Note 3)
LSB
MAX189A
±1
MAX189B/C
±3
Gain Temperature Coefficient
External reference, 4.096V
±0.8
ppm/°C
(10kHz sine wave input, 0V to 4.096Vp-p, 75ksps)
DYNAMIC SPECIFICATIONS
Signal-to-Noise plus
Distortion Ratio
SINAD
70
80
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-80
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Full-Power Bandwidth
SFDR
dB
Rolloff -3dB
4.5
0.8
MHz
MHz
2
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
= 4.0MHz, external clock (50% duty cycle); MAX187—internal
DD
CLK
reference: V
= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V
= 4.096V applied to REF pin, 4.7µF
REF
REF
capacitor at REF pin; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
CONVERSION RATE
Conversion Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
8.5
UNITS
7/MAX189
tCONV
tACQ
5.5
1.5
µs
µs
Track/Hold Acquisition Time
Throughput Rate
External clock, 4MHz, 13 clocks
75
ksps
ns
Aperture Delay
tAPR
10
Aperture Jitter
<50
ps
ANALOG INPUT
Input Voltage Range
Input Capacitance (Note 4)
0 to VREF
V
16
pF
INTERNAL REFERENCE (MAX187 only, reference buffer enabled)
TA = +25°C
4.076
4.060
4.050
4.040
4.096
4.116
4.132
4.140
4.150
30
MAX187_C
MAX187_E
MAX187_M
REF Output Voltage
VREF
V
TA = TMIN to TMAX
REF Short-Circuit Current
REF Tempco
mA
MAX187AC/BC
MAX187AE/BE
±30
±30
±30
±30
1
±50
±60
ppm/°C
MAX187AM/BM
MAX187C
±80
Load Regulation (Note 5)
0mA to 0.6mA output load
mV
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V)
Input Voltage Range
Input Current
2.50
12
VDD + 50mV
350
V
200
20
µA
kΩ
µA
Input Resistance
Shutdown REF Input Current
1.5
10
_______________________________________________________________________________________
3
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V ±5%; GND = 0V; unipolar input mode; 75ksps, f
= 4.0MHz, external clock (50% duty cycle); MAX187—internal
DD
CLK
reference: V
= 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: V
= 4.096V applied to REF pin, 4.7µF
REF
REF
capacitor at REF pin; T = T
to T ; unless otherwise noted.)
MAX
A
MIN
PARAMETER
SYMBOL
SHDN
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, CS
SCLK, CS Input High Voltage
SCLK, CS Input Low Voltage
SCLK, CS Input Hysteresis
SCLK, CS Input Leakage
SCLK, CS Input Capacitance
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
,
)
V
2.4
V
V
INH
V
0.8
INL
7/MAX189
VHYST
0.15
V
IIN
V
IN = 0V or VDD
±1
15
µA
pF
V
CIN
(Note 4)
V
VDD - 0.5
INSH
MAX1
V
0.5
±4.0
V
INSL
IINS
SHDN = VDD or 0V
µA
V
SHDN Input Mid Voltage
SHDN Voltage, Floating
V
1.5
VDD -1.5
IM
VFLT
SHDN = open
SHDN = open
2.75
V
SHDN Maximum Allowed
Leakage, Mid Input
-100
100
0.4
nA
V
DIGITAL OUTPUT (DOUT)
ISINK = 5mA
ISINK = 16mA
ISOURCE = 1mA
CS = 5V
Output Voltage Low
VOL
0.3
Output Voltage High
VOH
IL
4
V
Three-State Leakage Current
±10
15
µA
Three-State Output
Capacitance
COUT
CS = 5V (Note 4)
pF
POWER REQUIREMENTS
Supply Voltage
VDD
4.75
5.25
2.5
2.0
10
V
MAX187
MAX189
1.5
1.0
2
Operating mode
mA
IDD
Supply Current
Power-down mode
µA
V
DD = +5V, ±5%; external reference, 4.096V;
Power-Supply Rejection
PSR
±0.06
±0.5
mV
full-scale input (Note 6)
4
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
TIMING CHARACTERISTICS
(V = +5.0V ±5%, T = T
to T , unless otherwise noted.)
MAX
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
CS = high (Note 7)
MIN
TYP
MAX
UNITS
7/MAX189
Track/Hold Acquisition Time
SCLK Fall to Output Data Valid
tACQ
1.5
20
20
µs
MAX18_ _C/E
MAX18_ _M
150
200
100
100
5
tDO
CLOAD = 100pF
ns
CS Fall to Output Enable
CS Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
tDV
tTR
fSCLK
tCH
CLOAD = 100pF
CLOAD = 100pF
ns
ns
MHz
ns
100
100
tCL
ns
SCLK Low to CS Fall
tCSO
tCS
50
ns
ns
Setup Time
CS Pulse Width
500
Note 1: Tested at V = +5V.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, t
is the maximum time the device takes to acquire the signal, and is also the minimum
ACQ
time needed for the signal to be acquired.
_______________________________________________________________________________________
5
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
________________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
POWER-SUPPLY REJECTION vs.
V
REF
vs. TEMPERATURE
TEMPERATURE
4.090
4.089
0.16
0.14
4.088
4.087
0.12
0.10
7/MAX189
4.086
4.085
4.084
4.083
4.082
4.081
4.080
0.08
0.06
0.04
0.02
0
MAX1
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT vs.
TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
7
2.2
1.8
6
5
MAX187
MAX189
4
3
2
1
0
1.4
1.0
0.6
0.2
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
_______________________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
DIP
1
WIDE SO
7/MAX189
1
3
VDD
AIN
Supply voltage, +5V ±5%
2
Sampling analog input, 0V to VREF range
Three-level shutdown input. Pulling SHDN low shuts the MAX187/MAX189
down to 10µA (max) supply current. Both MAX187 and MAX189 are fully opera-
tional with either SHDN high or floating. For the MAX187, pulling SHDN high
enables the internal reference, and letting SHDN float disables the internal
reference and allows for the use of an external reference.
3
4
6
8
SHDN
Reference voltage—sets analog voltage range and functions as a 4.096V output
for the MAX187 with enabled internal reference. REF also serves as a +2.5V to
REF
VDD input for a precision reference for both MAX187 (disabled internal reference)
and MAX189. Bypass with 4.7µF if internal reference is used, and with 0.1µF if an
external reference is applied.
5
—
10
11
12
GND
AGND
DGND
DOUT
Analog and digital ground
—
—
6
Analog ground
Digital ground
Serial data output. Data changes state at SCLK’s falling edge.
Active-low chip select initiates conversions on the falling edge. When CS is high,
DOUT is high impedance.
7
15
CS
8
16
SCLK
N.C.
Serial clock input. Clocks data out with rates up to 5MHz.
—
2,4,5,7,9,13,14
Not internally connected. Connect to AGND for best noise performance.
unipolar serial format. A high bit, signaling the end of
conversion (EOC), followed by the data bits (MSB first),
make up the serial data stream.
_______________De t a ile d De s c rip t io n
Co n ve rt e r Op e ra t io n
The MAX187/MAX189 use input track/hold (T/H) and
successive approximation register (SAR) circuitry to
convert an analog input signal to a digital 12-bit output.
No e xte rna l hold c a p a c itor is ne e d e d for the T/H.
Figures 3a and 3b show the MAX187/MAX189 in their
simplest configuration. The MAX187/MAX189 convert
The MAX187 operates in one of two states: (1) internal
reference and (2) external reference. Select internal
reference operation by forcing SHDN high, and external
reference operation by floating SHDN
.
An a lo g In p u t
input signals in the 0V to V
range in 10µs, including
Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.
REF
T/H acquisition time. The MAX187’s internal reference
is trimmed to 4.096V, while the MAX189 requires an
external reference. Both devices accept external refer-
ZERO
SCALE
FULL
SCALE
ence voltages from +2.5V to V . The serial interface
DD
REFERENCE
requires only three digital lines, SCLK, CS, and DOUT,
and provides easy interface to microprocessors (µPs).
Internal Reference
(MAX187 only)
0V
0V
+4.096V
Both converters have two modes: normal and shut-
down. Pulling SHDN low shuts the device down and
reduces supply current to below 10µA, while pulling
SHDN high or leaving it floating puts the device into the
op e ra tiona l mod e . A c onve rs ion is initia te d b y CS
falling. The conversion result is available at DOUT in
External Reference
V
REF
For specified accuracy, the external reference voltage
range spans from +2.5V to V
.
DD
_______________________________________________________________________________________
7
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
+5V
3k
DOUT
DOUT
7/MAX189
3k
C
= 100pF
C
= 100pF
LOAD
LOAD
DGND
DGND
MAX1
a. High-Z to V and V to V
b. High-Z to V and V to V
OL OH OL
OH
OL OH
Figure 1. Load Circuits for DOUT Enable Time
+5V
3k
DOUT
DOUT
3k
C
= 100pF
C
= 100pF
LOAD
LOAD
DGND
DGND
a. V to High-Z
OH
b. V to High-Z
OL
Figure 2. Load Circuits for DOUT Disable Time
8
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
4.7µF
0.1µF
4.7µF
0.1µF
7/MAX189
1
2
8
7
1
2
8
7
+5V
V
SCLK
+5V
V
SCLK
DD
DD
SERIAL
INTERFACE
MAX187
ANALOG INPUT
0V TO +5V
SERIAL
INTERFACE
ANALOG INPUT
0V TO +5V
MAX189
CS
AIN
CS
AIN
3
4
6
5
SHUTDOWN
INPUT
3
4
6
5
SHUTDOWN
INPUT
SHDN
REF
DOUT
GND
SHDN
REF
DOUT
GND
ON
ON
OFF
REFERENCE
INPUT
OFF
4.7µF
0.1µF
Figure 3b. MAX189 Operational Diagram
Figure 3a. MAX187 Operational Diagram
interval. At this instant, the T/H switches the input side
of C to GND. The retained charge on C rep-
HOLD
HOLD
resents a sample of the input, unbalancing the node
ZERO at the comparator’s input.
12-BIT CAPACITIVE DAC
REF
In hold mode, the capacitive DAC adjusts during the
re ma inde r of the c onve rsion c yc le to re store nod e
ZERO to 0V within the limits of a 12-bit resolution. This
a c tion is e q uiva le nt to tra ns fe rring a c ha rg e from
COMPARATOR
C
HOLD
TRACK
AIN
INPUT
ZERO
-
+
16pF
C
to the binary-weighted capacitive DAC, which in
HOLD
HOLD
5k
turn forms a digital representation of the analog input
R
IN
C
SWITCH
signal. At the conversion’s end, the input side of C
C
HOLD
PACKAGE
HOLD
switches back to AIN, and C
signal again.
charges to the input
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. Acquisition time
is calculated by:
GND
Figure 4. Equivalent Input Circuit
t
= 9 (R + R ) 16pF,
S IN
ACQ
where R = 5kΩ, R = the source impedance of the
IN
S
Track/Hold
input signal, and t
is never less than 1.5µs. Source
ACQ
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
impedances below 5kΩ do not significantly affect the
AC performance of the ADC.
During a c q uis ition, the a na log inp ut AIN c ha rg e s
capacitor C
. Bringing CS low ends the acquisition
HOLD
_______________________________________________________________________________________
9
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
Input Bandwidth
The ADCs’ input tracking circuitry has a 4.5MHz small-
signal bandwidth, and an 8V/µs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC's
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is rec-
ommended. See the MAX274/MAX275 continuous-time
filters data sheet.
ed by the 75ksps sample rate of the MAX187/MAX189.
Therefore, the maximum sinusoidal input frequency
allowed is 37.5kHz. Higher-frequency signals cause
aliasing problems unless undersampling techniques
are used.
Re fe re n c e
The MAX187 can be used with an internal or external ref-
erence, while the MAX189 requires an external reference.
Internal Reference
The MAX187 has an on-chip reference with a buffered
te mp e ra ture -c omp e ns a te d b a nd g a p d iod e , la s e r-
trimmed to +4.096V ±0.5%. Its output is connected to
REF and also drives the internal DAC. The output can
be used as a reference voltage source for other com-
ponents and can source up to 0.6mA. Decouple REF
with a 4.7µF c a p a c itor. The inte rna l re fe re nc e is
enabled by pulling the SHDN pin high. Letting SHDN
float disables the internal reference, which allows the
us e of a n e xte rna l re fe re nc e , a s d e s c rib e d in the
External Reference section.
7/MAX189
Input Protection
Internal protection diodes that clamp the analog input
allow the input to swing from GND - 0.3V to V + 0.3V
DD
without damage. However, for accurate conversions
near full scale, the input must not exceed V by more
DD
than 50mV, or be lower than GND by 50mV.
MAX1
If the analog input exceeds the supplies by more than
50mV beyond the supplies, limit the input current to
2mA, since larger currents degrade conversion
accuracy.
Driving the Analog Input
The input lines to AIN and GND should be kept as short
as possible to minimize noise pickup. Shield longer
leads. Also see the Input Protection section.
External Reference
The MAX189 operates with an external reference at the
REF pin. To use the MAX187 with an external reference,
disable the internal reference by letting SHDN float. Stay
Because the MAX187/MAX189 incorporate a T/H, the
drive requirements of the op amp driving AIN are less
stringent than those for a successive-approximation
ADC without a T/H. The typical input capacitance is
16pF. The amplifier bandwidth should be sufficient to
handle the frequency of the input signal. The MAX400
and OP07 work well at lower frequencies. For higher-
frequency operation, the MAX427 and OP27 are practi-
cal choices. The allowed input frequency range is limit-
within the voltage range +2.5V to V to achieve speci-
DD
fied accuracy. The minimum input impedance is 12kΩ
for DC currents. During conversion, the external refer-
ence must be able to deliver up to 350µA DC load cur-
rent and have an output impedance of 10Ω or less. The
recommended minimum value for the bypass capacitor
is 0.1µF. If the reference has higher output impedance
or is noisy, bypass it close to the REF pin with a 4.7µF
capacitor.
COMPLETE CONVERSION SEQUENCE
CS
t
WAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED UP
POWERED DOWN
Figure 5. MAX187/MAX189 Shutdown Sequence
10 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
10000
1000
3.0
2.5
2.0
7/MAX189
MAX187
100
10
1
1.5
1.0
MAX189*
0.5
0
*REF CONNECTED TO V
DD
0.1
1
10
100 1000 10000 100000
0.0001 0.001
0.01
0.1
1
10
CONVERSIONS PER SECOND
TIME IN SHUTDOWN (sec)
Figure 6. Average Supply Current vs. Conversion Rate
Figure 7. t
vs. Time in Shutdown (MAX187 only)
WAKE
Ex t e rn a l Clo c k
____________________S e ria l In t e rfa c e
The actual conversion does not require the external
clock. This frees the µP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the µP’s convenience at any clock
rate from 0MHz to 5MHz. The clock duty cycle is unre-
stricted if each clock phase is at least 100ns. Do not
run the clock while a conversion is in progress.
In it ia liza t io n Aft e r P o w e r-Up a n d
S t a rt in g a Co n ve rs io n
Whe n p owe r is firs t a p p lie d , it ta ke s the fully d is -
charged 4.7µF reference bypass capacitor up to 20ms
to provide adequate charge for specified accuracy.
With SHDN not pulled low, the MAX187/MAX189 are
now ready to convert.
Tim in g a n d Co n t ro l
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline the operation of the
serial interface.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. After an internally timed 8.5µs conversion period,
the end of conversion is signaled by DOUT pulling
high. Data can then be shifted out serially with the
external clock.
A
CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to con-
vert, and DOUT changes from high impedance to logic
low. SCLK must be kept inactive during the conversion.
An internal register stores the data when the conversion
is in progress.
Us in g SHDN t o Re d u c e S u p p ly Cu rre n t
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver-
sions. This is shown in Figure 6, a plot of average sup-
ply current vs. conversion rate. Because the MAX189
uses an external reference voltage (assumed to be pre-
sent continuously), it "wakes up" from shutdown more
quickly, and therefore provides lower average supply
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge pro-
duces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing 0s at
DOUT and have no effect on converter operation.
currents. The wakeup-time, t
is the time from
WAKE,
SHDN deasserted to the time when a conversion may
be initiated. For the MAX187, this time is 2µs. For the
MAX189, this time depends on the time in shutdown
(see Figure 7) because the external 4.7µF reference
bypass capacitor loses charge slowly during shutdown
(see the specifications for shutdown, REF Input Current
= 10µA max).
______________________________________________________________________________________ 11
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
CS
1
4
8
12
SCLK
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
EOC
EOC
CONVERSION
IN PROGRESS
TRAILING
ZEROS
1
CLOCK OUTPUT DATA
TRACK
INTERFACE IDLE
IDLE
CONVERSION
0
CONV. 1
A/D
TRACK
STATE
0.5µs
(t
MAX1
12 × 0.250µs = 3.25µs
TOTAL = 12.25µs
0µs
8.5µs (t
)
0µs
CONV
)
MINIMUM
CYCLE TIME
CS
Figure 8. MAX187/MAX189 Interface Timing Sequence
t
CS
CS
…
…
t
CS0
t
CH
SCLK
t
DO
t
CL
t
TR
t
CONV
t
DV
…
…
DOUT
B2
B1
B0
t
APR
(TRACK)
(HOLD)
(TRACK)
INTERNAL
T/H
Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing
12 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
20
OUTPUT CODE
f
= 75ksps
S
0
-20
FULL-SCALE
TRANSITION
f = 10kHz
T
T = +25°C
A
7/MAX189
11…111
11…110
11…101
-40
-60
FS = +4.096V
FS
4096
1LSB =
-80
00…011
00…010
00…001
-100
-120
-140
00…000
0
1
2
3
FS
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
0
18.75
FREQUENCY (kHz)
37.5
Figure 11. MAX187/MAX189 FFT plot
Figure 10. MAX187/MAX189 Unipolar Transfer Function,
4.096V = Full Scale
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
13 clock cycles at full speed. Raise CS after the conver-
sion’s LSB has been read. After the specified minimum
input frequency. ADCs have traditionally been evaluat-
ed by specifications such as Zero and Full-Scale Error,
Integral Nonlinearity (INL), and Differential Nonlinearity
(DNL). Such parameters are widely accepted for speci-
fying performance with DC and slowly varying signals,
but are less useful in signal-processing applications,
where the ADC’s impact on the system transfer function
is the main concern. The significance of various DC
errors does not translate well to the dynamic case, so
different tests are required.
time, t
, CS can be pulled low again to initiate the
ACQ
next conversion.
Ou t p u t Co d in g a n d Tra n s fe r Fu n c t io n
The data output from the MAX187/MAX189 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive
inte g e r LSB va lue s . If VREF
1 LSB = 1.00mV or 4.096V/4096.
=
+ 4.096V, the n
S ig n a l-t o -No is e Ra t io a n d
Effe c t ive Nu m b e r o f Bit s
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS amplitude of all other ADC output signals. The
input bandwidth is limited to frequencies above DC and
below one-half the ADC sample (conversion) rate.
_____________Dyn a m ic P e rfo rm a n c e
High-speed sampling capability and a 75ksps through-
put make the MAX187/MAX189 ideal for wideband sig-
nal processing. To support these and other related
applications, Fast Fourier Transform (FFT) test tech-
niques are used to guarantee the ADC’s dynamic fre-
quency response, distortion, and noise at the rated
throughput. Specifically, this involves applying a low-
distortion sine wave to the ADC input and recording the
digital conversion results for a specified time. The data
is then analyzed using an FFT algorithm that deter-
mines its spectral content. Conversion errors are then
seen as spectral elements outside of the fundamental
The theoretical minimum ADC noise is caused by quan-
tization error and is a direct result of the ADC’s resolu-
tion: SINAD = (6.02N + 1.76)dB, where N is the number
of bits of resolution. An ideal 12-bit ADC can, therefore,
d o no b e tte r tha n 74d B. An FFT p lot of the outp ut
shows the output level in various spectral bands. Figure
11 shows the result of sampling a pure 10kHz sine
wave at a 75ksps rate with the MAX187/MAX189.
______________________________________________________________________________________ 13
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
12.2
12.0
I/O
CS
11.8
11.6
11.4
11.2
11.0
SCK
SCLK
DOUT
MISO
+5V
MAX187
MAX189
8
10.8
10.6
10.4
10.2
SS
(UNDERSAMPLED)
100 1000
a. SPI
1
10
INPUT FREQUENCY (kHz)
CS
SCK
CS
SCLK
DOUT
Figure 12. Effective Bits vs. Input Frequency
MISO
+5V
MAX187
MAX189
The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
a b ove e q ua tion a nd s ub s tituting in the me a s ure d
SINAD: N = (SINAD - 1.76)/6.02. Figure 12 shows the
effective number of bits as a function of the input fre-
quency for the MAX187/MAX189.
SS
b. QSPI
I/O
SK
SI
CS
To t a l Ha rm o n ic Dis t o rt io n
If a pure sine wave is sampled by an ADC at greater
than the Nyquist frequency, the nonlinearities in the
ADC’s transfer function create harmonics of the input
frequency present in the sampled output data.
SCLK
DOUT
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not includ-
ing the DC component) to the RMS amplitude of the
fundamental frequency. This is expressed as follows:
MAX187
MAX189
c. MICROWIRE
2
2
2
2
√ V + V + V + … V
N
2
3
4
THD = 20log
V
1
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
where V is the fundamental RMS amplitude, and V
through V are the amplitudes of the 2nd through Nth
1
2
N
ha rmonic s . The THD s p e c ific a tion in the Ele c tric a l
Cha ra c te ris tic s inc lud e s the 2nd throug h 5th
harmonics.
14 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
SCLK’s falling edge and is available in MSB-first for-
____________Ap p lic a t io n s In fo rm a t io n
mat. Observe the SCLK to DOUT valid timing charac-
teristic. Data can be clocked into the µP on SCLK’s
rising edge.
Co n n e c t io n t o S t a n d a rd In t e rfa c e s
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, a nd Mic rowire s ta nd a rd s e ria l
interfaces.
4. Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
7/MAX189
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 2.5MHz.
5. With CS = high, wait the minimum specified time, t
CS
,
before launching a new conversion by pulling CS
low. If a conversion is aborted by pulling CS high
before the conversions end, wait for the minimum
1. Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2. Wait the for the maximum conversion time specified
b e fore a c tiva ting SCLK. Alte rna tive ly, look for a
DOUT ris ing e d g e to d e te rmine the e nd of
conversion.
a c q uis ition time , t
conversion.
, b e fore s ta rting a ne w
ACQ
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of
the conversion padded with one leading 1, and trailing
0s if SCLK is still active with CS kept low.
3. Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge will produce the MSB of the
DOUT conversion. DOUT output data transitions on
1ST BYTE READ
2ND BYTE READ
SCLK
CS
t
CONV
HI-Z
HI-Z
MSB D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 LSB
DOUT
EOC
Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CS
t
CONV
HI-Z
HI-Z
DOUT
MSB D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 LSB
EOC
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
______________________________________________________________________________________ 15
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
12 bits of data with no trailing 0s (Figure 15). The maxi-
mum clock frequency to ensure compatibility with QSPI
is 2.77MHz.
S P I a n d Mic ro w ire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until
DOUT goes high or the maximum specified 8.5µs con-
ve rs ion time . Two c ons e c utive 1-b yte re a d s a re
required to get the full 12 bits from the ADC. DOUT out-
p ut d a ta tra ns itions on SCLK’s fa lling e d g e a nd is
clocked into the µP on SCLK’s rising edge.
Op t o -Is o la t e d In t e rfa c e ,
S e ria l-t o -P a ra lle l Co n ve rs io n
Many industrial applications require electrical isolation
to separate the control electronics from hazardous
electrical conditions, provide noise immunity, or pre-
vent excessive current flow where ground disparities
exist between the ADC and the rest of the system.
Isolation amplifiers typically used to accomplish these
tasks are expensive. In cases where the signal is even-
tually converted to a digital form, it is cost effective to
isolate the input using opto-couplers in a serial link.
The first byte contains a leading 1 and 7 bits of conver-
sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections
and Figure 14 for timing.
7/MAX189
QS P I
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the
ADC, QSPI allows the minimum number of clock cycles
necessary to clock in the data. The MAX187/MAX189
require 13 clock cycles from the µP to clock out the
The MAX187 is ide a l in this a pp lic a tion b e c a use it
inc lud e s b oth T/H a mp lifie r a nd volta g e re fe re nc e ,
operates from a single supply, and consumes very little
power (Figure 16).
MAX1
CS/START
+5V ON THIS SIDE OF
BARRIER MUST BE ISOLATED POWER
SCLK/INPUT CLOCK
+5V
6N136
+5V
8
1
7
QH
QG
QF
QE
QD
QC
QB
QA
200Ω
14
7
2
3
4
6
5
4
3
2
1
SER
74HC595
3k
6
11
12
10
SCK
5
10µF
D11 (MSB)
D10
D9
74HC04
74HC04
RCK
MAX187
6N136
6N136
0.1µF
1
2
4
5
3
7
8
6
8
7
6
5
1
2
3
4
15
16
V
SHDN
CS
SCLR
D8
+5V
DD
200Ω
AIN
3k
13
8
REF
GND
SCLK
DOUT
0.1µF
ANALOG
INPUT
4.7µF
470Ω
9
QH′
7
QH
QG
QF
QE
QD
QC
QB
QA
D7
D6
D5
D4
D3
D2
D1
14
1
2
3
4
8
7
6
5
6
SER
74HC595
5
8.2k
11
12
4
3
2
1
SIGNAL
GROUND
SCK
RCK
15
16
10
D0(LSB)
+5V
+5V
SCLR
13
8
0.1µF
Figure 16. 12-Bit Isolated ADC
16 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
The ADC results are transmitted across a 1500V isola-
tion barrier provided by three 6N136 opto-isolators.
Isolated power must be supplied to the converter and
the isolated side of the opto-couplers. 74HC595 three-
state shift registers are used to construct a 12-bit paral-
lel data output. The timing sequence is identical to the
timing shown in Figure 8. Conversion speed is limited
by the delay through the opto-isolators. With a 140kHz
clock, conversion time is 100µs.
7/MAX189
SUPPLIES
+5V
GND
The universal 12-bit parallel data output can also be
used without the isolation stage when a parallel inter-
face is required. Clock frequencies up to 2.9MHz are
possible without violating the 20ns shift-register setup
time. Delay or invert the clock signal to the shift regis-
ters beyond 2.9MHz.
R* = 10Ω
4.7µF
0.01µF
La yo u t , Gro u n d in g , Byp a s s in g
For best performance, use printed circuit boards. Wire-
wra p b oa rd s a re not re c omme nd e d . Boa rd la yout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
V
AGND
DGND
+5V DGND
DD
DIGITAL
CIRCUITRY
MAX187
MAX189
*OPTIONAL
Figure 17 shows the recommended system ground
c onne c tions . A s ing le -p oint a na log g round (“s ta r”
ground point) should be established at GND, separate
from the logic ground. All other analog grounds should
be connected to this ground. The 16-pin versions also
have a dedicated DGND pin available. Connect DGND
to this star ground point for further noise reduction. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped-
ance and as short as possible for noise-free operation.
Figure 17. Power-Supply Grounding Condition
High-frequency noise in the V
power supply may
DD
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 4.7µF bypass capacitors. Minimize capacitor lead
le ng ths for b e s t s up p ly-nois e re je c tion. If the +5V
power supply is very noisy, a 10Ω resistor can be con-
nected as a lowpass filter to attenuate supply noise
(Figure 17).
______________________________________________________________________________________ 17
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
__Ord e rin g In fo rm a t io n (c o n t in u e d )
____P in Co n fig u ra t io n s (c o n t in u e d )
ERROR
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX187AEPA -40°C to +85°C
MAX187BEPA -40°C to +85°C
MAX187CEPA -40°C to +85°C
MAX187AEWE -40°C to +85°C
MAX187BEWE -40°C to +85°C
MAX187CEWE -40°C to +85°C
MAX187AMJA -55°C to +125°C
MAX187BMJA -55°C to +125°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
16 Wide SO
16 Wide SO
16 Wide SO
8 CERDIP**
8 CERDIP**
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
16 Wide SO
16 Wide SO
16 Wide SO
Dice*
±1⁄
±1
2
V
SCLK
CS
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
±2
N.C.
AIN
N.C.
±1⁄
±1
±2
2
N.C.
N.C.
MAX187
MAX189
7/MAX189
N.C.
SHDN
N.C.
DOUT
DGND
AGND
N.C.
±1⁄
2
±1
MAX189ACPA
MAX189BCPA
MAX189CCPA
MAX189ACWE
MAX189BCWE
MAX189CCWE
MAX189BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
±1⁄
±1
±2
2
REF
MAX1
Wide SO
±1⁄
±1
±2
±1
2
MAX189AEPA -40°C to +85°C
MAX189BEPA -40°C to +85°C
MAX189CEPA -40°C to +85°C
MAX189AEWE -40°C to +85°C
MAX189BEWE -40°C to +85°C
MAX189CEWE -40°C to +85°C
MAX189AMJA -55°C to +125°C
MAX189BMJA -55°C to +125°C
8 Plastic DIP
8 Plastic DIP
8 Plastic DIP
16 Wide SO
16 Wide SO
16 Wide SO
8 CERDIP**
8 CERDIP**
±1⁄
±1
±2
2
±1⁄
±1
±2
2
±1⁄
2
±1
* Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
18 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
MAX1
___________________Ch ip To p o g ra p h y
MAX187/MAX189
7/MAX189
V
DD
SCLK
CS
AIN
0. 151"
(3. 84mm)
DOUT
DGND
SHDN
REF
0. 117"
AGND
AGND
(2. 97mm)
TRANSISTOR COUNT: 2278;
SUBSTRATE CONNECTED TO V
.
DD
______________________________________________________________________________________ 19
+5 V, Lo w -P o w e r, 1 2 -Bit S e ria l ADCs
________________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
E
A
–
A2
A3
E1
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.14
0.20
1.27
15.24
13.34
2.54
15.24
–
D
A
0.175
0.080
0.020
0.065
0.012
0.090
0.625
0.575
–
4.45
2.03
0.51
1.65
0.30
2.29
15.88
14.61
–
B
0.016
B1 0.045
0.008
D1 0.050
0.600
E1 0.525
0.100
eA 0.600
0°-15°
C
A1
e
C
L
E
eA
eB
B1
B
e
–
–
D1
eB
L
–
0.700
0.150
17.78
3.81
7/MAX189
0.120
3.05
P PACKAGE
PLASTIC
DUAL-IN-LINE
INCHES
MILLIMETERS
DIM
PINS
MIN
MAX MIN MAX
D
D
D
24
28
40
1.230 1.270 31.24 32.26
1.430 1.470 36.32 37.34
2.025 2.075 51.44 52.71
INCHES
MILLIMETERS
DIM
MIN
MAX
0.104
0.012
0.019
0.013
0.299
MIN
2.35
0.10
0.35
0.23
7.40
MAX
2.65
0.30
0.49
0.32
7.60
D
A
0.093
A1 0.004
0°- 8°
B
C
E
e
0.014
0.009
0.291
A
0.101mm
0.005in.
1.27
0.050
e
B
A1
H
L
0.394
0.016
0.419
0.050
10.00
0.40
10.65
1.27
C
L
INCHES
MILLIMETERS
MAX
PINS
DIM
MIN MAX MIN
E
H
W PACKAGE
SMALL
OUTLINE
0.398 0.413 10.10 10.50
0.447 0.463 11.35 11.75
0.496 0.512 12.60 13.00
0.598 0.614 15.20 15.60
0.697 0.713 17.70 18.10
21-0042A
D
D
D
D
D
16
18
20
24
28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1993 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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