MAX19516EVKIT+ [MAXIM]
On-Board Single-Ended to Differential Transformer Circuitry;
| 型号： | MAX19516EVKIT+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | On-Board Single-Ended to Differential Transformer Circuitry |
| 文件： | 总30页 (文件大小：2293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for production status of specific part numbers.
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
General Description
Features
● Single Power-Supply Operation
The
MAX19505–MAX19507/MAX19515–MAX19517
evaluation kits (EV kits) are fully assembled and tested
circuit boards that contain all the components necessary
to evaluate the performance of this family of 8-bit and
10-bit analog-to-digital converters (ADCs). The EV kits
● Low-Voltage and Low-Power Operation
● On-Board Single-Ended to Differential
Transformer Circuitry
®
● Differential or Single-Ended Clock Configuration
also include Windows 7/10-compatible software that
provides a simple graphical user interface (GUI) for
exercising the programmable features of the MAX19505/
MAX19507/MAX19515–MAX19517.
● On-Board Clock-Shaping Circuit with Adjustable Duty
Cycle
● On-Board SPI™ Interface Circuit
● User-Selectable Supply Voltages
● Lead(Pb)-Free and RoHS Compliant
● Fully Assembled and Tested
The MAX19505–MAX19507/MAX19515–MAX19517 EV
kits accept a single-ended analog input from an analog
signal source. The EV kits provide an on-board circuit that
transforms this analog single-ended signal into a differential
signal. The ADC digital output can be captured easily with
a basic logic analyzer. The EV kits can operate from a
single 3.6V nominal power supply and provide on-board
regulation for the analog, clock, digital, and logic circuitry.
Ordering Information
PART
TYPE
EV Kit
EV Kit
EV Kit
EV Kit
EV Kit
EV Kit
MAX19505EVKIT+
MAX19506EVKIT+
MAX19507EVKIT+
MAX19515EVKIT+
MAX19516EVKIT+
MAX19517EVKIT+
Part Selection Table
PART
RESOLUTION (Bits) SPEED (Msps)
MAX19505ETM+
MAX19506ETM+
MAX19507ETM+
MAX19515ETM+
MAX19516ETM+
MAX19517ETM+
8
8
65
100
130
65
8
+Denotes lead(Pb)-free and RoHS compliant.
10
10
10
100
130
Component List
REF DES
QTY
DESCRIPTION
REF DES
QTY
DESCRIPTION
4.7µF Tantalum Capacitor SMT
(3528), 16V, 20%
C6, C7, C29,
C48-C53,
C66-C73
C1, C40
2
0.1µF Ceramic Capacitor
SMT (0402), 10V; 10%; X5R
17
C2, C27,
C28, C76,
C77
10µF Ceramic Capacitor;
SMT (0805), 6.3V, 20%, X5R
5
0.1µF Ceramic Capacitor
SMT (0603), 50V, 10%, X7R
C25, C26
C30, C31
2
2
1µF Ceramic Capacitor SMT
(0402), 6.3V; TOL = 10%, X5R
100pF Ceramic Capacitor
SMT (0402), 50V, 5%, C0G
C3
1
2
8pF Ceramic Capacitor SMT (0402),
TOL = ±0.25pF
C43, C79,
C81-C89
0.1µF Ceramic Capacitor
SMT (0402), 10V, 10%, X7R
C4, C5
11
Windows 7, and Windows 10 are registered trademarks of Microsoft Corp.
SPI is a trademark of Motorola, Inc.
19-4301; Rev 2; 7/19
Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Component List (continued)
REF DES
QTY
DESCRIPTION
REF DES
R81
QTY
DESCRIPTION
1
1
1
4
1kΩ Resistor (0603), 5%, 0.10W
12kΩ Resistor (0603), 1%, 0.10W
Surface Mount Tactile Switch, SMT
0.4-800MHz Transformer, SMT
C54, C55,
C75, C78
0.01µF Ceramic Capacitor
SMT (0603), 25V, 10%
4
R82
3.3µF Ceramic Capacitor
SMT (0402), 6.3V, 20%, X5R
S1
C80
1
4
T1-T4
CLK, SYNC,
VINA, VINB
0.20MHz TO 400MHz,
Transformer, SMT
SMA Connector, 5 Pins
T5
1
Schottky Diode,
PIV = 70V, PD = 0.25W
TP1, TP2
TP3
2
1
Orange Test Point
Black Test Point
D2
1
4
2
DS1-DS4
Green LED SMT (0603)
ADC, Dual-Channel, 10-BIT,
130Msps, TQFN 48-EP
GND,
VSUPPLY
U1
U2
1
1
Banana Connector
Ultra-Low-Noise, High PSRR,
Low-Dropout, Linear Regulator
J1, J8-J10,
JU6, JU7,
JU9, JU10
8
2 Pin Header
48 Pin Header
Usb, Quad High Speed USB to
Multipurpose UART/MPSSE IC,
LQFP 64 12X12
U3
U4
U9
1
1
1
J5
J6
1
1
USB MINI B-TYPE SMT Connector,
Right Angle, 9 PINS
4-Bit Dual-Supply Bus Transceiver
With Configurable Voltage
Translation And 3-State Output,
TSSOP 16
J7
1
3
10 Pin Header
4 Pin Header
JU1-JU3
28 Ferrite-Bead Inductor SMT
(0603), 25%; 4A
L1, L2
2
4
EEPROM, 2K, 16-BIT MICROWIRE
Compatible Serial EEPROM,
NSOIC8 150MIL
5/8IN Round-Thru Hole Spacer;
No Thread; M3.5; Nylon
MH1-MH4
TINYLOGIC, ULP-AS Dual Inverter,
SC70-6
R1, R3-R12,
R45, R58-R63,
R70-R75
U10
1
2
47 Resistor SMT (0402),
5%, 0.1W
24
16-BIT Buffer/Driver with
3-State Outputs, TSSOP 48
U11, U12
R2, R43, R44
R19-R22
3
4
4
100kΩ Resistor (0603), 5%; 0.1W
75Ω Resistor (0603), 0.1%, 0.10W
121Ω Resistor (0603), 0.1%, 0.10W
LOW-NOISE LDO regulator
PIN-Selectable Output Voltage.
TDFN8 2X2
U14, U15
2
R23-R26
R27-R41,
R47-R49
18
0Ω Resistor; 0402, 0%, 0.10W
USB3V3
Y1
1
1
1
0
Red Test Point
Crystal, SMT, 18pF, 12MHz
PCB: MAX19517
R42, R54, R55
R46
3
1
3
1
49.9Ω Resistor (0603), 1%, 0.10W
10kΩ Resistor, 10%, 0.5W
PCB
J2-J4
Not Installed, 2 Pin Header
R56, R57, R65
R64
100Ω Resistor (0603), 1%, 0.10W
0Ω Resistor (0603), 5%, 0.10W
R13-R18, R50,
R52, R53
0
Not Installed, (0603) Resistor
R66-R68,
R83-R85
6
10kΩ Resistor (0603), 5%, 0.10W
Not Installed, (0402)
Non-Polar Capacitor
C32-C35
R51
0
0
2.2kΩ Resistor (0603),
2.2kΩ, 5%, 0.10W
R69
1
3
Not Installed, (0402) Resistor
R76-R78
75Ω Resistor (0603), 1%, 0.10W
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
EV Kit-Specific Component List
PART
DESIGNATION
DESCRIPTION
8-bit 65Msps dual ADC (48 TQFN)
Maxim MAX19505ETM+
MAX19505EVKIT+
8-bit 100Msps dual ADC (48 TQFN)
Maxim MAX19506ETM+
MAX19506EVKIT+
MAX19507EVKIT+
MAX19515EVKIT+
MAX19516EVKIT+
MAX19517EVKIT+
8-bit 130Msps dual ADC (48 TQFN)
Maxim MAX19507ETM+
U1
10-bit 65Msps dual ADC (48 TQFN)
Maxim MAX19515ETM+
10-bit 100Msps dual ADC (48 TQFN)
Maxim MAX19516ETM+
10-bit 130Msps dual ADC (48 TQFN)
Maxim MAX19517ETM+
Component Suppliers
SUPPLIER
Central Semiconductor Corp.
Coilcraft, Inc.
PHONE
WEBSITE
www.centralsemi.com
www.coilcraft.com
631-435-1110
847-639-6400
805-446-4800
888-522-5372
—
Diodes, Inc.
www.diodes.com
Fairchild Semiconductor
Future Technology Devices International Ltd.
IRC, Inc.
www.fairchildsemi.com
www.ftdichip.com
361-992-7900
718-934-4500
770-436-1300
800-344-2112
973-808-8990
208-328-0307
800-348-2496
847-803-6100
972-644-5580
www.irctt.com
Mini-Circuits
www.minicircuits.com
www.murata-northamerica.com
www.panasonic.com
www.linkinstruments.com
www.susumu-usa.com
www.t-yuden.com
Murata Electronics North America, Inc.
Panasonic Corp.
Link Instruments
Susumu International USA
Taiyo Yuden
TDK Corp.
www.component.tdk.com
www.ti.com
Texas Instruments Inc.
Note: Indicate that you are using the MAX19505, MAX19506, MAX19507, MAX19515, MAX19516, or MAX19517 when contacting
these component suppliers.
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
5) Verify that shunt is installed across jumper J8, and no
jumper is installed across J10 (OVDD = 1.8V).
MAX19505–MAX19507/
MAX19515–MAX19517 EV Kit Files
6) Connect the clock generator output to the clock band-
pass filter input.
FILE
DESCRIPTION
7) Connect the output of the clock bandpass filter to the
MAX195xxDualADCEVKit
SoftwareInstaller.exe
Installs the EV kit files on
your computer
CLK SMA connector.
8) Connect the output of the analog signal generator to
the input of the signal bandpass filter. Keep the cable
connection between the signal generators, filters, and
EV kit board as short as possible for optimum dynam-
ic performance.
MAX195xxGUI.exe
ftd2xx.dll
Application program
Supporting Library
MaximStyle.dll
libMPSSE.dll
Supporting Library
Supporting Library
9) Connect the output of the signal bandpass filter to the
VINA SMA connector. Note: It is recommended that a
3dB or 6dB attenuation pad be used to reduce reflec-
tions and distortion from the bandpass filter.
FTD2XX_NET.dll
unins000.exe
Supporting Library
Uninstalls the EV kit software
10) If using IO3200, apply power to the IO3232A by
connecting the USB cable from the computer’s type-
A USB port to the IO3232A module’s mini-USB port.
Quick Start
Recommended Equipment
● Single nominal 3.6V, 1A DC power supply
11) Connect the MAX195xx J5 header pins to the logic
analyzer (See Connecting the IO3232A to the EV Kit
below, if applicable).
● Signal generator with low phase noise and low jitter
for clock input (e.g., HP 8644B)
12) Connect the power supply to V
. Connect the
SUPPLY
● Signal generator for analog signal input
ground terminal of this supply to the corresponding
GND pad.
(e.g., HP 8644B)
● Logic analyzer (recommended, IO3232A)
13) Connect the USB cable from the computer’s type-A
USB port to the EV kit board’s Mini USB port.
● Analog bandpass filters (e.g., K&L Microwave) for
input and clock signal
14) Visit www.maximintegrated.com and search for
the device EV Kit to download the latest version of
the MAX195xx EV kit software and install it on your
computer by running the INSTALL.EXE program. The
program files are copied and icons are created in the
Windows Start menu.
● User-supplied Windows 7/10 PC with two spare USB
ports
Note: In the following sections, software-related items are
identified by bolding. Text in bold refers to items from the
EV kit software. Text in bold and underlined refers to
items from the Windows operating system.
15) Start the MAX195xx program by opening its icon in
the Start menu.
Procedure
16) Turn on the 5V power supply.
The MAX19505–MAX19507/MAX19515–MAX19517
EV kits are fully assembled and tested surface-mount
boards. Follow the steps below to verify board operation.
Caution: Do not turn on power supplies or enable
signal generators until all connections are completed.
17) Enable the signal generators.
18) Set the clock signal generator for an output amplitude
of 2V
or higher (recommended +16dBm to +19dBm
P-P
for optimum AC performance for input frequencies >
100MHz) and the frequency (f ) as appropriate.
CLK
1) Verify that shunts are installed across pins 1-3 of
jumpers JU1, JU2, and JU3 (SPI connected).
19) Set the analog input signal generators for an output
amplitude of less than or equal to 2V
desired frequency.
and to the
P-P
2) Verify that no shunts are installed across jumpers JU6
(device enabled) and JU7 (SPI enabled).
20) Verify that the two signal generators are phase locked
to each other. Adjust the output power level of the
signal generators to overcome cable, bandpass filter,
and attenuation pad losses at the input.
3) Verify that shunts are installed across jumpers JU9
(AVDD connected) and JU10 (OVDD connected).
4) Verify that shunt is installed across jumper J1, and no
jumper is installed across J8 (AVDD = 1.8V).
21) Collect data using the logic analyzer.
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
User-Interface Panel
Detailed Description of Software
The program’s main window contains two tabs, Input/
Output/Clock (Figure 1) and Power Management (Figure
2), that provide controls for the MAX195xx software-
configurable features. The Input/Output/Clock tab
provides controls for Output Format, Input Common
Mode, Output CMOS Termination, Output Timing
Control, and Clock Controls. The Power Management
tab provides controls for Power Management and Output
Driver Power Mgmt. Controls. Changes to the controls
result in a write operation that updates the appropriate
registers of the ADC. A status bar is also provided at the
bottom of the program’s main window and is used to verify
command module and device connectivity. For reference,
a list of registers and their content is provided in a column
on the right side of the program’s main window.
Updating Registers
To send the new register values to the device through the
SPI interface, click the Update Registers button after the
settings are changed.
Application Menu
This menu contains 3 options, File, Device and Help.
These options allow the user to Exit the program, choose
their MAX195xx device, and view the splash screen,
respectively. The user should select a device upon startup,
as this will adjust the Output Timing Controls to the
device’s default settings.
Figure 1. MAX195xx EV Kit Software (Input/Output/Clock Tab)
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Figure 2. MAX195xx EV Kit Software (Power Management Tab)
becomes active. The Test Pattern drop-down list allows
the user to choose between ramping or alternating test
pattern data.
Input/Output/Clock Tab
Output Format
The Output Format group box contains several functions
that format the output data. The option to select between
single or dual data channels or set the multiplexer
between channels A or B is available through proper
selection of the radio buttons in the Data Channel Mode
and Mux Ch. Select group boxes. The CHA Reverse
and CHB Reverse checkboxes in the Reverse Bit Order
group box allow the user to reverse the bit order of
channels A and B, respectively.
Input Common Mode
The CHA Adjust and CHB Adjust drop-down lists
set the input common-mode voltage according to the
value selected. The CHA Self-Bias and CHB Self-Bias
checkboxes apply common-mode voltages to input pins
when checked, and disable common-mode inputs when
unchecked.
Output CMOS Termination
The Format drop-down list in the Data group box config-
ures the output data to two’s complement, offset binary,
or gray code. The Test Data drop-down list in the Data
Test Pattern group box gives the user the option to
choose between normal and test data modes. When Test
Data mode is selected, the Test Pattern drop-down list
The Output CMOS Termination group box contains
independent controls to set the CMOS back termination
of CHA Data and CHB Data and CHA DCLK and CHB
DCLK. The CHA Data and CHB Data drop-down lists
set the data termination, while the CHA DCLK and CHB
DCLK drop-down lists sets the DCLK termination.
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
DOR checkbox disables DOR. Note: Disable DCLK and
disable DOR applies to CMOS modes only. The Power
Down Output State drop-down list sets the digital output
high, low, or to tri-state during power-down. For more
details on output driver power management control, refer
to the respective IC data sheet.
Output Timing Control
The Output Timing Control group box contains controls
to make adjustments to data and DCLK timing. The Data
Timing Adjust drop-down list adjusts DATA timing by the
selected value. The DCLK Timing Adjust drop-down list
adjusts DCLK timing by the selected value. By check-
ing the Delay DATA/DCLK by T/2 checkbox, DATA and
DCLK outputs are delayed by a factor of T/2. The Data
Aligner Bypass checkbox bypasses the data aligner
delay line when checked. For more details on output
timing control, refer to the respective IC data sheet.
User Log
The User Log is in each tab. The User Log keeps track
of all settings when the Update Registers button is
pressed. When the user switches tabs, the contents are
updated between both tabs. The User Log can also be
used to take notes, and hitting the Copy Log button will
copy the log to the clipboard.
Clock Controls
The Clock Controls group box contains controls for
manipulating the clock. The Divider drop-down list sets
the clock divider. The Sync Mode drop-down list sets
clock synchronization to either slip or edge mode. In slip
mode, the divided output is forced to skip a state transition
on the third rising edge of the input clock (CLK) after the
rising edge of SYNC. In edge mode, the divided output
is forced to state 0 on the third rising edge of CLK. The
100 Ohm Input Term. checkbox switches 100Ω across
differential clock inputs when checked. For more details
on clock synchronization and control, refer to the respective
IC data sheet.
Detailed Description of Hardware
The MAX19505–MAX19507/MAX19515–MAX19517
evaluation kits (EV kits) are fully assembled and tested
circuit boards that contain all the components necessary
to evaluate the performance of this family of 8-bit and
10-bit analog-to-digital converters (ADCs).
The ADCs accept differential input signals; however,
on-board transformers (T1–T4) convert a readily avail-
able single-ended source output to the required differential
signal. The input signals of the ADCs can be measured
using a differential oscilloscope probe at headers J2 and J3.
Power Management Tab
Output drivers (U11 and U12) buffer the output signals of
the data converter. The digital outputs of each EV kit are
accessible at header J5.
Power Management Controls
The Power Management group box contains two sets of
controls. The first set is used only when the SHDN pin on
the EV kit is set low; the second set is used only when
the SHDN pin on the EV kit is set high. When checked,
the CHA Active and CHB Active checkboxes activate
channel A and channel B, respectively, and power down/
standby channel A and channel B when unchecked. The
Standby checkbox toggles between standby mode when
checked and full power-down mode when unchecked,
as long as CHA Active or CHB Active checkboxes are
unchecked. The A+B Adder mode checkbox toggles
between A+B adder mode when checked and normal
dual mode when unchecked. For more details on power
management, refer to the respective IC data sheet.
Each EV kit is designed as a four-layer PCB to optimize
the performance of this family of ADCs. Separate analog,
digital, clock, and buffer power planes minimize noise
coupling between analog and digital signals. The 100Ω
differential microstrip transmission lines are used for
analog and clock inputs. The 50Ω microstrip transmission
lines are used for all digital outputs. The trace lengths of
the 100Ω differential input lines are matched to within a
few thousandths of an inch to minimize layout-dependent
input-signal skew.
Using the IO3232A with the EV Kit
The Logic Analyzer Pattern Generator (IO3200) is one
of the many instrument options to evaluate the perfor-
mance of this specific family of evaluation kits. While it is
simple enough to use, this method does require the user
to download the IO3200 software from the following link:
www.linkinstruments.com
Output Driver Power Management Controls
The Output Driver Power Mgmt. Controls group box
contains controls to disable the digital clock (DCLK) and
out-of-range indicator (DOR). The Disable DCLK check-
box disables the DCLK when checked and the Disable
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Evaluate: MAX19505–MAX19507/
MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Configuring the EV Kits for
Connecting the IO3232A to the EV Kit
Single-Ended Clock Operation
The IO3232A can be connected to the MAX195xx boards
using the following pin ordering. It is not essential to
match the pins exactly as specified below, as they are a
recommended connection sequence.
To configure the MAX195xx EV kits for single-ended clock
operation, the following modifications must be made to
the clock circuit:
1) Remove 0Ω resistors at locations R47, R48, and R49.
2) Install 0Ω resistors at locations R51 and R52.
3) Install a 49.9Ω ±1% resistor at location R50.
Power Supplies
The MAX195xx EV kits operate from a single DC power
supply (VSUPPLY) and provide on-board regulation
to power the analog, digital, and clock-shaping circuit
blocks. The nominal voltage input for the VSUPPLY is at
3.6V. The maximum voltage supported by the MAX195xx
EV kits is 5V, and the minimum voltages are represented
in Table 1 and Table 2 based on the user’s desired regu-
lated voltage. The analog and clock (AVDD) are regulated
to a desired voltage (1.8V, 2.5V, 3.0V, or 3.3V) through the
MAX8902A (U14), a pin-selectable linear regulator. The
digital output and logic circuitry (OVDD and VLOGIC) are
both regulated to a desired voltage (1.8V, 2.5V, 3.0V, or
3.3V) through the MAX8902A (U15). J1, J8, J9, and J10
are provided to select the desired output of U14 and U15.
See Table 2 and Table 3 for AVDD and OVDD/VLOGIC
supply options. Jumpers JU9 and JU10 are provided to
either disconnect or measure current through AVDD and
OVDD, respectively.
In single-ended clock configuration, potentiometer R46
can be utilized to control the duty cycle of the clock input
signal. Measure the clock input at J4 and adjust R46 until
the desired duty cycle is achieved.
Input Signal
Although this family of ADCs accepts differential analog
input signals, the EV kits only require single-ended analog
input signals. Insertion losses due to a series-connected
filter and the interconnecting cables decrease the amount
of power seen at the EV kit input. Account for these losses
when setting the signal generator amplitude. On-board
transformers (T1–T4) convert the single-ended analog input
signals and generate the recommended differential analog
signals at the ADCs’ differential input pins. The input circuit
supports input frequencies from 1MHz to 400MHz.
Clock Input
The data converter allows for either differential or single-
ended signals to drive the clock inputs. The MAX195xx
EV kits support both methods.
Table 2. MAX8902A Output Voltage for
AVDD (J1 and J9)
In single-ended operation, the clock signal is applied to
the ADC through a buffer (U10). In differential mode, an
on-board transformer converts a user-supplied single-
ended analog input and generates a differential analog
signal, which is then applied to the ADC’s input pins.
J1
J9
AVDD
1.8V*
2.5V
VSUPPLY MIN
2.1V
OPEN
INSTALL
OPEN
OPEN
2.8V
INSTALL
INSTALL
INSTALL
OPEN
3.0V
3.3V
3.3V
3.6V
Table 1. J5 Header and IO3232A Pin
Relationships
*Default
Table 3. MAX8902A Output Voltage for
OVDD and VLOGIC (J8 and J10)
J5 HEADER FROM EV KIT
IO3232A PINS
Ext. clk0 (interchangeable
with DCLKB)
DCLKA
VSUPPLY
MIN
J8
J10
OVDD/VLOGIC
DORA
PIN 10
OPEN
OPEN
INSTALL
OPEN
1.8V*
2.5V
3.0V
3.3V
2.1V
2.8V
3.3V
3.6V
D9A:D0A
D9B:D0B
DORB
PINS 9:0, respectively
PINS 25:16, respectively
PIN 26
INSTALL
INSTALL
INSTALL
OPEN
Ext. clk0 (interchangeable
with DCLKA)
DCLKB
*Default
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MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
respective IC data sheet for more information on SPEN
and parallel programming. Note that when the serial port
is enabled, jumpers JU1, JU2, and JU3 must be set to
pins 1-3 for proper operation.
Output Signal
The MAX19505, MAX19506, and MAX19507 feature
two 8-bit, parallel, CMOS-compatible digital outputs that
transmit the converted analog input signals. The higher
resolution MAX19515, MAX19516, and MAX19517 fea-
ture two 10-bit, parallel, CMOS-compatible digital outputs
that transmit the converted analog input signals. Each set
of 8-bit or 10-bit digital outputs also includes a clock bit
(DCLKA/B) and overrange bit (DORA/B) to accommodate
data synchronization and error detection. See the Output
Bit Locations section for more details on how to configure
these 8-bit and 10-bit converter outputs.
Shutdown (SHDN)
The MAX19505–MAX19507/MAX19515–MAX19517
ADCs can also be placed in a low-power shutdown
mode through jumper JU6. This pin has different effects
depending on the state of SPEN. When in SPI program-
ming mode, SHDN can select between two power-
management states. When in parallel programming mode,
SHDN can enable/disable the IC.
Output Bit Locations
When SPI programming is enabled (SPEN = 0), the SHDN
pin is a toggle switch between two power-management
states, shown in Figure 2 under the Power Management
group box of the software interface. When a shunt is
installed on JU6, SHDN is connected to AVDD and the
user can select the appropriate settings for CHA Active,
CHB Active, Standby, and A+B Adder mode under the
label **Use when SHDN = 1 (IC pin 7)**. When no shunt
is installed on JU6, SHDN is connected to GND through
R43 and the user can select the appropriate settings for
CHA Active, CHB Active, Standby, and A+B Adder
mode under the label **Use when SHDN = 0 (IC pin 7)**.
Two drivers (U11 and U12) buffer the digital outputs
of the individual ADCs. These drivers are able to drive
large capacitive loads, which may be present at the
logic analyzer connection. The outputs of the buffers are
connected to J5.
Serial Port Enable (SPEN)
The SPEN pin selects the means of programming
the internal registers of the MAX19505–MAX19507/
MAX19515–MAX19517 ADCs. SPEN is set high or low
based on the settings of jumper JU7, shown in Table 4.
When a shunt on JU7 is installed, the 3-wire serial port is
disabled and the part can be programmed through jumpers
JU1, JU2, and JU3 in parallel mode. When JU7 is left
open, SPEN is pulled to GND through R44. Refer to the
When parallel programming mode is enabled (SPEN = 1),
the SHDN pin enables/disables the IC according to the
settings in Table 5.
Table 4. Jumper JU7 Functions
SHUNT POSITION
SPEN PIN
Connected to AVDD
3-WIRE SERIAL PORT
Installed
Disabled (parallel programming mode)
Not installed*
Enabled (SPI programming)
Connected to GND though a 100kΩ pulldown resistor
*Default position.
Table 5. Jumper JU6 Functions (SPEN = AVDD)
POWER STATE
SHUNT POSITION
SHDN PIN
(SPEN = AVDD)
Installed
Connected to AVDD
Complete power-down
Not installed*
CHA + CHB active
Connected to GND through a 100kΩ pulldown resistor
*Default position.
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Jumpers JU1, JU2, JU3, and JU7 control the
feature selection when the serial port is disabled (parallel
programming is enabled). See Table 6 for functionality.
Parallel Programming
Limited feature selection is available as an alternative to
full programmability through the serial port. If the serial
port is disabled by setting the SPEN pin high, the serial
port pins (CS, SCLK, SDIN) become feature selection
pins (OUTSEL, DIV, FORMAT) that require an analog
control network.
Table 6. Parallel Programming Feature Selection
SCLK/DIV
(JU1)
SDIN/FORMAT
(JU2)
CS/OUTSEL
SPEN
DESCRIPTION
(JU3)
(JU7)
Serial port active. Features are programmed
through the serial port.
SCLK
SDIN
CS
0
X
0
X
1
1
1
1
1
1
1
1
1
Two’s complement
Offset binary
X
VDD
X
X
(Unconnected pin)
X
Gray code
0
X
X
X
X
X
X
X
Clock divide-by-1
VDD
X
Clock divide-by-2
(Unconnected pin)
X
Clock divide-by-4
X
X
X
0
CMOS (dual bus)
VDD
MUX CMOS (channel A data bus)
MUX CMOS (channel B data bus)
(Unconnected pin)
X = Don’t care.
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MAX19515–MAX19517
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MAX19505/MAX19506/MAX19507 EV Kit Schematics (Sheet 1 of 5)
I . C .
3 3
I . C .
3 2
I . C .
2 2
O V D D
O V D D
I . C .
I . C .
E P
2 5
3 6
2 1
4 9
1 8
1 7
8
A V D D
A V D D
A V D D
A V D D
G N D
G N D
1
1 2
1 3
4 8
5
3
4
2
2
1
2
1
5
5
5
5
5
3
4
2
5
3
4
2
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MAX19515–MAX19517
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MAX19515–MAX19517
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MAX19515/MAX19516/MAX19517 EV Kit Schematics (Sheet 1 of 5)
I . C .
8
O V D D
2 5
O V D D
3 6
E P
4 9
A V D D
A V D D
A V D D
A V D D
G N D
G N D
1
1 8
1 7
1 2
1 3
4 8
5
3
4
2
2
1
2
1
5
5
5
5
5
3
4
2
5
3
4
2
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MAX19515–MAX19517
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MAX19515–MAX19517
Evaluation Kits
MAX19505/MAX19506/MAX19507 EV Kit Schematics (Sheet 2 of 5)
VLOGIC
U11
SN74AUC16244DGGR
1
1OE
47
46
44
43
2
3
5
6
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
48
41
40
38
37
2OE
2A1
2A2
2A3
2A4
8
2Y1
2Y2
2Y3
2Y4
9
R4
R5
47
47
11
12
D0A
D1A
25
36
35
33
32
3OE
3A1
3A2
3A3
3A4
R6
R7
R8
R9
47
47
47
47
13
14
16
17
3Y1
3Y2
3Y3
3Y4
D2A
D3A
D4A
D5A
24
30
29
27
26
4OE
4A1
4A2
4A3
4A4
R10
R11
R12
R45
47
47
47
47
19
20
22
23
4Y1
4Y2
4Y3
4Y4
D6A
D7A
J5
PBC24DAAN
DORA
DCLKA
2
4
1
1
2
3
4
3
5
6
5
6
8
7
8
7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
VLOGIC
U12
SN74AUC16244DGGR
1
47
46
44
43
1OE
1A1
1A2
1A3
1A4
2
1Y1
3
5
6
1Y2
1Y3
1Y4
48
41
40
38
37
2OE
2A1
2A2
2A3
2A4
R58
R59
47
47
8
2Y1
2Y2
2Y3
2Y4
DORB
9
DCLKB
11
12
25
36
35
33
32
3OE
3A1
3A2
3A3
3A4
R62
R63
R70
R71
47
47
47
47
13
14
16
17
3Y1
3Y2
3Y3
3Y4
D0B
D1B
D2B
D3B
24
30
29
27
26
4OE
4A1
4A2
4A3
4A4
R72
R73
R74
R75
47
47
47
47
19
20
22
23
4Y1
4Y2
4Y3
4Y4
D4B
D5B
D6B
D7B
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19515/MAX19516/MAX19517 EV Kit Schematics (Sheet 2 of 5)
VLOGIC
U11
SN74AUC16244DGGR
1
1OE
47
46
44
43
2
3
5
6
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
48
41
40
38
37
2OE
2A1
2A2
2A3
2A4
R1
R3
R4
R5
47
47
47
47
8
2Y1
2Y2
2Y3
2Y4
D0A
D1A
D2A
D3A
9
11
12
25
36
35
33
32
3OE
3A1
3A2
3A3
3A4
R6
R7
R8
R9
47
47
47
47
13
14
16
17
3Y1
3Y2
3Y3
3Y4
D4A
D5A
D6A
D7A
24
30
29
27
26
4OE
4A1
4A2
4A3
4A4
R10
R11
R12
R45
47
47
47
47
19
20
22
23
4Y1
4Y2
4Y3
4Y4
D8A
D9A
J5
PBC24DAAN
DORA
DCLKA
2
4
1
1
2
3
4
3
5
6
5
6
8
7
8
7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
VLOGIC
U12
SN74AUC16244DGGR
1
47
46
44
43
1OE
1A1
1A2
1A3
1A4
2
1Y1
3
5
6
1Y2
1Y3
1Y4
48
41
40
38
37
2OE
2A1
2A2
2A3
2A4
R58
R59
R60
R61
47
47
47
47
8
2Y1
2Y2
2Y3
2Y4
DORB
DCLKB
D0B
9
11
12
D1B
25
36
35
33
32
3OE
3A1
3A2
3A3
3A4
R62
R63
R70
R71
47
47
47
47
13
14
16
17
3Y1
3Y2
3Y3
3Y4
D2B
D3B
D4B
D5B
24
30
29
27
26
4OE
4A1
4A2
4A3
4A4
R72
R73
R74
R75
47
47
47
47
19
20
22
23
4Y1
4Y2
4Y3
4Y4
D6B
D7B
D8B
D9B
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX19515–MAX19517 EV Kit Schematics (Sheet 3 of 5)
2
1
3
5
2
1
3
5
3
4
2
Maxim Integrated
│ 15
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX19515–MAX19517 EV Kit Schematics (Sheet 4 of 5)
1 5
1 0
1 6
1 0 K
1 0 K
1 0 K
R 8 5
R 8 4
R 8 3
4
4
4
2
2
2
4
4
4
2
2
2
V C C I O
V C C I O
V C C I O
V C C I O
5 6
4 2
3 1
2 0
G N D
G N D
G N D
G N D
G N D
G N D
G N D
5 1
4 7
3 5
2 5
1 5
1 1
V C C C O R E
6 4
3 7
1 2
V C C C O R E
V C C C O R E
5
V P L L
V P H Y
G N D
9
4
1
A G N D
1 0
+
+
7
6
5
8
6
7
8
9
6
7
8
9
Maxim Integrated
│ 16
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX19515–MAX19517 EV Kit Schematics (Sheet 5 of 5)
2
1
1
2
2
9
1
2
2
1
1
2
2
9
1
2
Maxim Integrated
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Top Silkscreen
Maxim Integrated
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Top Layer
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Internal 2
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Internal 3
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Bottom Layer
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19505/MAX19506/MAX19507 EV Kit PCB Layout—Bottom Silkscreen
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Top Silkscreen
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Top Layer
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Internal 2
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Internal 3
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Bottom Layer
Maxim Integrated
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
MAX19505–MAX19507/MAX1915–MAX19517 EV Kit PCB Layout Diagrams (cont’d)
1.0’’
MAX19515/MAX19516/MAX19517 EV Kit PCB Layout—Bottom Silkscreen
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MAX19515–MAX19517
MAX19505–MAX19507/
MAX19515–MAX19517
Evaluation Kits
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
11/08
7/09
7/19
Initial release
Corrected connector name on DCEP board
Updated to match Rev C and Rev D hardware, plus updated GUI
—
5, 10
1–30
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 30
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