MAX19541EVKIT [MAXIM]
Low-Voltage and Low-Power Operation;
| 型号： | MAX19541EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Voltage and Low-Power Operation |
| 文件： | 总14页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3535; Rev 1; 5/07
MAX19541/MAX19542 Evaluation Kits
General Description
Features
♦ Up to 170Msps Sampling Rate Using the MAX19542
♦ Up to 125Msps Sampling Rate Using the MAX19541
♦ Low-Voltage and Low-Power Operation
♦ Fully Differential Input Signal Configuration
♦ On-Board Output Buffers
The MAX19541/MAX19542 evaluation kits (EV kits) are
fully assembled and tested printed-circuit boards
(PCBs) that contain all the components necessary to
evaluate the performance of the MAX19541 (125Msps)
and MAX19541/MAX19542 (170Msps) 12-bit analog-to-
digital converters (ADCs). The MAX19541/MAX19542
accept differential analog inputs; however, the EV kits
generate this signal from a user-provided, single-ended
signal source. The digital outputs produced by the ADC
are CMOS compatible and can be easily captured with
a user-provided, high-speed logic analyzer or data-
acquisition system. The EV kits operate from 1.8V and
3.3V power supplies and include circuitry that generates
a clock signal from a user-provided AC signal.
♦ Fully Assembled and Tested
Ordering Information
PART
TEMP RANGE
0°C to +70°C*
0°C to +70°C*
IC PACKAGE
68 QFN-EP**
68 QFN-EP**
MAX19541EVKIT+
MAX19542EVKIT+
+Denotes a lead-free and RoHS-compliant EV kit.
*This limited temperature range applies to the EV kit PCB only.
The MAX19541/MAX19542 IC temperature range is -40°C to
+85°C.
**EP = Exposed paddle.
Component List
DESIGNATION
QTY
DESCRIPTION
INP, CLK,
ꢁESET
SMA PC board vertical-mount
connectors
3
0
0.1µF 10ꢀ, 10V X5ꢁ ceramic
capacitors (0402)
TDK C1005X5ꢁ1A104K
C1, C2, C3,
C5–C27
26
Not installed, vertical-mount SMA
connector
INN
J1, J2
JU1–JU6, JU8
JU7
2
7
1
Dual-row 40-pin headers
3-pin headers
Not installed, ceramic capacitor
(0402)
C4
0
3
Dual-row 8-pin header
0.22µF 10ꢀ, 6.3V X5ꢁ ceramic
capacitors (0402)
TDK C1005X5ꢁ0J224K
C28, C29, C30
ꢁ1, ꢁ2, ꢁ11,
ꢁ12, ꢁ14,
ꢁ15, ꢁ22
0
Not installed, resistors (0603)
47µF 10ꢀ, 10V tantalum
capacitors (C case)
AVX TAJC476K010
C31–C34
C35–C38
C39–C42
4
4
4
ꢁ3–ꢁ7
ꢁ8, ꢁ9
5
2
2
49.9Ω 1ꢀ resistors (0603)
510Ω 5ꢀ resistors (0603)
0Ω resistors (0603)
ꢁ10, ꢁ13
10µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitors (0805)
TDK C2012X5ꢁ0J106M
24.9Ω 0.1ꢀ resistors (0603)
IꢁC PFC-W0603ꢁLF-02-24ꢁ9-B
Panasonic EꢁA3HB24ꢁ9V
ꢁ16, ꢁ17
2
1.0µF 10ꢀ, 10V X5ꢁ ceramic
capacitors (0603)
TDK C1608X5ꢁ1A105K
ꢁ18, ꢁ19
ꢁ20
2
1
1
0
24.9Ω 1ꢀ resistors (0603)
100kΩ, 12-turn, 1/4in
potentiometer
0.01µF 20ꢀ, 25V X7ꢁ ceramic
capacitor (0402)
TDK C1005X7ꢁ1E103M
C43
1
0
ꢁ21
13kΩ 1ꢀ resistor (0603)
Not installed, shorted by PC
trace (0603)
ꢁ23–ꢁ26
Not installed, shorted by PC trace
(0603)
C44, C45
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX19541/MAX19542 Evaluation Kits
Component List (continued)
DESIGNATION
QTY
DESCRIPTION
DESIGNATION
QTY
DESCRIPTION
100Ω 5ꢀ resistor arrays (1206)
Panasonic EXB-2HV-101J
ꢁA1–ꢁA4
4
Low-voltage, 16-bit flip-flops
(48-pin TSSOP)
Pericom PI74ALVTC16374AE
U3, U4
2
22Ω 5ꢀ resistor arrays (1206)
Panasonic EXB-2HV-220J
ꢁA5–ꢁA8
4
Dual two-input exclusive-Oꢁ gate
(8-pin VSSOP)
TI SN74AUC2G86DCUꢁE4
1:1 800MHz ꢁF transformers
Mini-Circuits ADT1-1WT+
T1, T2
TP1, TP2, TP3
U1
2
3
1
U5
—
1
1
Test points (black)
PCB: MAX19541/MAX19542
Evaluation Kit+
See the EV Kit-Specific
Component List
3.3V ECL differential receiver
(8-pin SO)
ON Semiconductor
MC100LVEL16DG
EV Kit-Specific Component list
U2
1
EV KIT PART
NUMBER
REFERENCE
DESIGNATOR
DESCRIPTION
MAX19541EGK+
MAX19541EVKIT+
MAX19542EVKIT+
(68-pin QFN with EP,
10mm x 10mm x 0.9mm)
U1
MAX19542EGK+
(68-pin QFN with EP,
10mm x 10mm x 0.9mm)
Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.avxcorp.com
AVX Corp.
843-946-0238
361-992-7900
714-373-7183
847-803-6100
843-626-3123
361-992-3377
714-373-7939
847-390-4405
IꢁC, Inc.
www.irctt.com
Panasonic Corp.
TDK Corp.
www.panasonic.com
www.component.tdk.com
Note: Indicate that you are using the MAX19541/MAX19542 when contacting these component suppliers.
• Logic analyzer or data-acquisition system (e.g., HP
Quick Start
Recommended Equipment
16500C with high-speed state card such as the HP
16517A
• DC power supplies:
Analog (AVCC)
Clock (CVCC)
Buffers (BVCC)
Digital (OVCC)
• Digital voltmeter
1.8V, 1A
Procedure
The MAX19541/MAX19542 EV kits are fully assembled
and tested surface-mount boards. Follow the steps below
for board operation. Caution: Do not turn on power
supplies or enable signal generators until all connec-
tions are completed:
3.3V, 500mA
1.8V, 500mA
1.8V, 1A
• Signal generator with low phase noise for clock input
signal (e.g., HP 8662A, HP 8644B)
1) Verify that shunts are installed in the following
locations:
• Signal generator for analog input signal (e.g., HP
8662A, HP 8644B)
a) JU1 (1-2)—Divide-by-two disabled
b) JU2 (2-3)—Parallel mode selected
2
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
c) JU3 (2-3)—Demux parallel mode selected if
load signals that can be captured by a wide variety of
logic analyzers. The buffered CMOS outputs can be
accessed at headers J1 and J2.
JU2 is pulled high
d) JU4 (2-3)—Two’s-complement output selected
e) JU5 (1-2)—Noninverted DCLKP selected
f) JU6 (2-3)—Noninverted DCLKN selected
g) JU7 (3-4)—Internal reference enabled
Each EV kit is designed as a four-layer PCB to optimize
the performance of the MAX19541/MAX19542. Separate
analog, digital, clock, and buffer power planes minimize
noise coupling between analog and digital signals; 50Ω
coplanar transmission lines are used for analog and
clock inputs. The trace lengths of the 50Ω CMOS lines
are matched to within a few thousandths of an inch to
minimize layout-dependent delays.
2) Connect the clock signal generator to the SMA
connector labeled CLK.
3) Connect the analog input signal generator to the
SMA connector labeled INP.
Power Supplies
The MAX19541/MAX19542 EV kits require separate
analog, digital, clock, and buffer power supplies for
best performance. Two separated 1.8V power supplies
are used to power the analog and digital portions of the
MAX19541/MAX19542. The on-board clock circuitry is
powered by another 3.3V power supply, and a 1.8V
power supply is used to power the output buffers (U3
and U4) on the EV kits.
4) Connect the logic analyzer’s high-speed state card
probe connectors to header J1 (CMOS-compatible
signals); see Table 5 for header connections.
5) Connect a 1.8V, 1A power supply to AVCC.
Connect the ground terminal of this supply to the
GND pad closest to the AVCC pad.
6) Connect a 3.3V, 500mA power supply to CVCC.
Connect the ground terminal of this supply to the
GND pad closest to the CVCC pad.
Clock
The MAX19541/MAX19542 require a differential clock
signal. However, if only a single-ended clock signal
source is available, the EV kit’s on-board level transla-
tor helps to convert a single-ended clock to the
required differential signal. An on-board clock-shaping
circuit generates a differential clock signal from an AC-
coupled sine-wave signal applied to the clock input
SMA connector CLK. The input signal amplitude should
7) Connect a 1.8V, 500mA power supply to BVCC.
Connect the ground terminal of this supply to the
GND pad closest to the BVCC pad.
8) Connect a 1.8V, 1A power supply to OVCC.
Connect the ground terminal of this supply to the
GND pad closest to the OVCC pad.
9) Turn on all the power supplies.
10) Enable the signal generators. Set the clock signal
not exceed 2.6V . The frequency of the clock signal
P-P
generator to output a 170MHz signal, with a 2.4V
P-P
should not exceed 170MHz. The frequency of the sinu-
soidal input clock signal determines the sampling fre-
amplitude. Set the analog input signal generato to
output the desired frequency with an amplitude
quency (f
) of the ADC. A differential line receiver
CLK
≤2V . For coherent sampling, the signal genera-
P-P
(U2) processes the input signal to generate the
required clock signal.
tors should be synchronized.
11) Enable the logic analyzer.
Clock Divider
The MAX19541/MAX19542 feature an internal divide-
by-two clock divider. Use jumper JU1 to enable/disable
this feature. See Table 1 for shunt positions.
12) Collect data using the logic analyzer.
Detailed Description
The MAX19541/MAX19542 EV kits are fully assembled
and tested PCBs that contain all the components nec-
essary to evaluate the performance of the
MAX19541/MAX19542. The MAX19541/MAX19542 can
Table 1. Clock-Divider Shunt Settings
(JU1)
be evaluated with a maximum clock frequency (f
170MHz.
) of
CLK
SHUNT
POSITION
MAX19541/MAX19542
CLKDIV PIN
DESCRIPTION
The MAX19541/MAX19542 accept differential inputs.
Applications that only have a single-ended signal source
available can use the on-board transformer (T2) to con-
vert a single-ended signal to a differential signal.
Clock signal
divided by 1
1-2*
Connected to AVCC
Connected to GND
Clock signal
divided by 2
2-3
Output buffers (U3 and U4) buffer the digital output sig-
nals of the MAX19541/MAX19542 to higher capacitive
*Default position.
_______________________________________________________________________________________
3
MAX19541/MAX19542 Evaluation Kits
Input Signal
Reference Voltage
The MAX19541/MAX19542 accept differential analog
input signals. However, the EV kits only require a sin-
gle-ended analog input signal with an amplitude of less
There are two methods to set the full-scale range of the
MAX19541/MAX19542. Both EV kits can be configured
to use the MAX19541/MAX19542’s internal reference, or
a stable, low-noise, external reference can be applied to
the ꢁEFIO pad. Jumper JU7 controls which reference
source is used. See Table 2 for shunt settings.
than 2V
provided by the user. An on-board trans-
P-P
former then takes the single-ended analog input and
generates a differential analog signal, which is applied
to the ADC’s differential input pins.
Output Mode
The MAX19541/MAX19541/MAX19542 feature three
modes of operation: parallel mode, demux parallel
mode, and demux interleaved mode. In each mode of
operation, the digital data is output in a different format
and is controlled by the ADC’s DEMUX and ITL pins.
The EV kits incorporate jumpers JU2 and JU3 to control
the DEMUX and ITL pins, respectively. See Table 3 for
shunt settings.
Optional Input Transformer
The MAX19541/MAX19542 EV kits use a second trans-
former to enhance THD and SFDꢁ performance at high
input frequencies (>100MHz). This transformer helps to
reduce the increase of even-order harmonics at high
frequencies. To use only the primary transformer, follow
the directions below:
1) ꢁemove ꢁ10 and ꢁ13.
2) Install a 0.1µF capacitor on C4.
3) Install a 0Ω resistor at ꢁ22.
4) Install an SMA connector on INN.
5) Connect the analog signal source to INN instead
of INP.
Table 2. Reference Shunt Settings (JU7)
SHUNT
DESCRIPTION
POSITION
Internal ꢁeference Disabled. Apply an
1-2
external reference voltage to the ꢁEFIO pad.
Internal ꢁeference Enabled. ꢁEFIO is the
output of the internal reference.
3-4*
Increases FSꢁ through trim potentiometer
ꢁ20.
5-6
Decreases FSꢁ through trim potentiometer
ꢁ20.
7-8
*Default position.
Table 3. Output-Mode Shunt Settings (JU2 and JU3)
JU2 SHUNT
POSITION
JU3 SHUNT
POSITION
DEMUX PIN
ITL PIN
OUTPUT MODE
Parallel mode
OUTPUT PORT
Port A
2-3
1-2
Connected to GND
—
—
Connected to AV
2-3
Connected to GND
Demux parallel mode
Ports A and B
CC
Demux interleaved
mode
1-2
Connected to AV
1-2
Connected to AV
CC
Ports A and B
CC
4
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
Output Format
The digital output coding can be chosen to be either in
two’s complement or straight offset-binary format by
configuring jumper JU4. See Table 4 for shunt settings.
Output Bit Locations
The buffered digital outputs of the ADC are connected
to two 40-pin headers (J1 and J2). PCB trace lengths
are matched to minimize output skew and improve per-
formance of the device. The buffers are able to drive
large capacitive loads, which may be present at the
logic analyzer connection. See Table 5 for headers J1
and J2 bit locations.
Table 4. Output-Format Shunt Settings (JU4)
SHUNT POSITION
T/B PIN
DESCRIPTION
1-2
Connected to AV
Digital data appears in straight offset-binary code.
Digital data appears in two’s-complement code.
CC
2-3*
Connected to GND
Table 5. Output Bit Locations (J1 and J2)
PORT A
BIT
BUFFERED
OUTPUT
BUFFERED
OUTPUT
LABEL
NAME
LABEL NAME
PORT B BIT
DESCRIPTION
OꢁA
DA11
DA10
DA9
J1-35
J1-31
J1-29
J1-27
J1-25
J1-23
J1-21
J1-19
J1-17
J1-15
J1-13
J1-11
J1-9
BOꢁA
BDA11
BDA10
BDA9
BDA8
BDA7
BDA6
BDA5
BDA4
BDA3
BDA2
BDA1
BDA0
CLKA
OꢁB
DB11
DB10
DB9
J2-35
J2-31
J2-29
J2-27
J2-25
J2-23
J2-21
J2-19
J2-17
J2-15
J2-13
J2-11
J2-9
BOꢁB
BDB11
BDB10
BDB9
BDB8
BDB7
BDB6
BDB5
BDB4
BDB3
BDB2
BDB1
BDB0
CLKB
Overrange bit
Bit 11 (MSB)
DA8
DB9
DA7
DB7
DA6
DB6
Bits 10–1
DA5
DB5
DA4
DB4
DA3
DB3
DA2
DB2
DA1
DB1
DA0
DB0
Bit 0 (LSB)
DCLKP
J1-3
DCLKN
J2-3
Clock output signal
_______________________________________________________________________________________
5
MAX19541/MAX19542 Evaluation Kits
C C
O V
O V
A G N D
C C
C C
O V
O V
O V
O G N D
O G N D
O G N D
C C
C C
A G N D
A G N D
A G N D
A G N D
C C
A V
C C
A V
C C
A V
C C
A V
A G N D
A G N D
A G N D
A G N D
A G N D
C C
A V
C C
A V
C C
A V
C C
A V
C C
A V
C C
A V
C C
A V
Figure 1a. MAX19541/MAX19542 EV Kits Schematic (Sheet 1 of 3)
6
_______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
C C
O V
A G N D
C C
C C
C C
C C
O V
O V
O V
O V
O G N D
O G N D
O G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
C C
C C
C C
C C
C C
C C
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
C C
C C
C C
C C
C C
Figure 1b. MAX19541/MAX19542 EV Kits Schematic (Sheet 2 of 3)
_______________________________________________________________________________________
7
MAX19541/MAX19542 Evaluation Kits
BVCC
CLKA
48
CLKA
48
7
18
31 42
RA5
22Ω
RA1
100Ω
J1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
26
27
29
30
32
33
35
36
23
22
20
19
17
16
14
13
J1-39
J1-37
J1-40
J1-38
2D8
2Q8
2Q7
2Q6
2Q5
2Q4
2Q3
2Q2
2Q1
2D7
2D6
2D5
2D4
2D3
2D2
2D1
J1-35
J1-31
J1-29
J1-27
J1-36
J1-32
J1-30
J1-28
ORA
DA11
DA10
DA9
J1-25
J1-33
J1-26
J1-34
DA8
U3
PI74ALVC16374
RA6
RA2
22Ω
100Ω
12
11
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
37
38
40
41
43
44
46
47
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
J1-23
J1-21
J1-24
J1-22
1D8
1D7
1D6
1D5
1D4
1D3
1D2
1D1
1Q8
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q1
J1-19
J1-17
J1-15
J1-13
J1-20
J1-18
J1-16
J1-14
8
6
5
3
J1-11
J1-9
J1-7
J1-5
J1-12
J1-10
J1-8
J1-6
J1-4
J1-2
2
1
1OE
2OE
24
J1-3
J1-1
CLKA
4
10 15 21 28 34 45 39
BVCC
CLKB
CLKB
48
48
7
18
31 42
RA7
22Ω
RA3
100Ω
J2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
26
27
29
30
32
33
35
36
23
22
20
19
17
16
14
13
J2-39
J2-37
J2-40
J2-38
2D8
2D7
2D6
2D5
2D4
2D3
2D2
2D1
2Q8
2Q7
2Q6
2Q5
2Q4
2Q3
2Q2
2Q1
J2-35
J2-31
J2-29
J2-27
J2-36
J2-32
J2-30
J2-28
ORB
DB11
DB10
DB9
J2-25
J2-33
J2-26
J2-34
DB8
U4
PI74ALVC16374
RA8
RA4
22Ω
100Ω
12
11
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
37
38
40
41
43
44
46
47
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
J2-23
J2-21
J2-24
J2-22
1D8
1D7
1D6
1D5
1D4
1D3
1D2
1D1
1Q8
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q1
J2-19
J2-17
J2-15
J2-13
J2-20
J2-18
J2-16
J2-14
8
6
5
3
J2-11
J2-9
J2-7
J2-5
J2-12
J2-10
J2-8
J2-6
J2-4
J2-2
2
BVCC
1
1OE
2OE
J2-3
J2-1
CLKB
1
2
3
24
JU8
4
10 15 21 28 34 45 39
Figure 1c. MAX19541/MAX19542 EV Kits Schematic (Sheet 3 of 3)
_______________________________________________________________________________________
8
MAX19541/MAX19542 Evaluation Kits
Figure 2. MAX19541/MAX19542 EV Kits Component Placement Guide—Component Side
_______________________________________________________________________________________
9
MAX19541/MAX19542 Evaluation Kits
Figure 3. MAX19541/MAX19542 EV Kits PCB Layout—Component Side
10 ______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
Figure 4. MAX19541/MAX19542 EV Kits PCB Layout—Ground Plane (Inner Layer 2)
______________________________________________________________________________________ 11
MAX19541/MAX19542 Evaluation Kits
Figure 5. MAX19541/MAX19542 EV Kits PCB Layout—Power Planes (Inner Layer 3)
12 ______________________________________________________________________________________
MAX19541/MAX19542 Evaluation Kits
Figure 6. MAX19541/MAX19542 EV Kits PCB Layout—Solder Side
______________________________________________________________________________________ 13
MAX19541/MAX19542 Evaluation Kits
Figure 7. MAX19541/MAX19542 EV Kits Component Placement Guide—Solder Side
Revision History
Pages changed at ꢁev 1: Title Change—all pages,
1–13
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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