MAX20067 [MAXIM]
Automotive 3-Channel Display Bias IC with VCOM Buffer, Level Shifter, and I2C Interface;
| 型号： | MAX20067 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Automotive 3-Channel Display Bias IC with VCOM Buffer, Level Shifter, and I2C Interface |
| 文件： | 总39页 (文件大小：4711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with
VCOM Buffer, Level Shifter, and I C Interface
2
General Description
Benefits and Features
The MAX20067/MAX20067B are complete TFT bias solu-
tions for automotive applications. They include a current-
mode boost converter and two push-pull charge-pump dri-
vers.
● Versatile TFT Display Power Section
• Integrated Synchronous Boost Converter with
Output Voltages Up to 18V and High-power
(MAX20067) or Lower-power (MAX20067B)
Options
The ICs also include a gate-shading push-pull level shifter
that can be used to improve display uniformity (when
needed), and a DAC and VCOM buffer. All blocks on the
• Integrated Charge-Pump Drivers for the VGON
(+32V, max) and VGOFF (-24V, min) Outputs
2
ICs can be used in stand-alone mode or through the I C
● Low EMI Operation
interface.
• Programmable Switching Frequencies of 440kHz or
2.2MHz
• Programmable Spread Spectrum
Comprehensive control functions are included using the
2
built-in I C interface, as well as diagnostics and monitor-
2
ing.
● Full Sequencing Flexibility Through I C, Along with
Preset Sequences Using SEQ Pin
● Extended Diagnostics Using I C Interface
The ICs are intended to operate with 2.7V to 5.5V sup-
plies.
2
• Undervoltage/Overvoltage on HVINP, VGON, and
VGOFF
• Overcurrent on AVDD
The MAX20067/MAX20067B are available in a 32-pin
TQFN package and operate in the -40°C to +105°C tem-
perature range.
• Temperature Warning
● Built-In Gate-Shading Circuit Controlled by CTL Input
● 8-Bit DAC-Controlled VCOM Buffer
● Robust
Applications
● Infotainment Displays
● Central Information Displays
● Instrument Clusters
• -40°C to +105°C Operating Temperature Range
• Internal Temperature Shutdown
• AEC-Q100 Qualified
● Compact 32-Pin (5mm x 5mm) TQFN Package
Ordering Information appears at end of datasheet.
19-100112; Rev 2; 1/21
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Simplified Block Diagram
DGND ADD FLT ENP SEQ
CONTROL
INA
SDA
SCL
REF
BANDGAP
REFERENCE
GND
VCINH
DAC
VCOMP
VCOM
BST
MODE
DEL
BOOST
LXP
CONTROL
CTL
SRC
PGND
FBP
GATE
SHADING
GATES
DRN
1.25V
MAX20067/B
HVINP
AVDD
HVINP
POSITIVE
OSC.
SOFT-START &
DISCHARGE
PCP_ON
PGVDD
DRVP
VGOFF
FBGL
NEGATIVE CP
POSITIVE
CP
HVINP
FBGH VGON
DRVN
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Maxim Integrated | 2
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
32-Pin TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAX20067 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TFT Power Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Source-Driver Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Gate-Driver Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operation of the Positive Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operation of the Negative Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fault Protection on the TFT Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-Up/Power-Down Sequencing and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Gate-Shading Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VCOM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FLTB Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Individual Output Control Through I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Autosequencing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 1. Sample Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Maxim Integrated | 3
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
TABLE OF CONTENTS (CONTINUED)
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output-Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Boost Converter Operation at low INA and high Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Charge-Pump Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Selecting the Number of Charge-Pump Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flying Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Charge-Pump Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PCB Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Maxim Integrated | 4
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
LIST OF FIGURES
Figure 1. Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Maxim Integrated | 5
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
LIST OF TABLES
Table 1. Gate-Shading Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. VCOM DAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3. Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. FLTB Output Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
Table 5. I C Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Maxim Integrated | 6
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Absolute Maximum Ratings
INA, SDA, SCL, ENP, FLTB, CTL to GND ............... -0.3V to +6V
DEL, REF, FBP, FBGH, FBGL, SEQ, MODE, ADD to GND ...... -
0.3V to INA + 0.3V
LXP, BST to GND..................................................... -0.3V to 26V
BST to LXP............................................................... -0.3V to +6V
HVINP, VCOMP to GND ........................................ -0.3V to +26V
DRVP, DRVN to PGND ............................-0.3V to HVINP + 0.3V
GND to PGND........................................................-0.3V to +0.3V
GND to DGND .......................................................-0.3V to +0.3V
LXP Continuous Current........................................................2.4A
Continuous Power Dissipation (Multilayer Board) (T = +70°C)...
A
W to 2.758W
Package Thermal Resistance......................................... 1.7°C/W
ESDHB..................................................................... -2kV to +2kV
ESDMM................................................................-200V to +200V
Operating Temperature.........................................-40°C to 105°C
Junction Temperature.........................................-40°C to +150°C
Storage Temperature Range ..............................-65°C to +150°C
Lead Temperature Range.................................................+300°C
VCINH, VCOM to GND............................ -0.3V to V
+ 0.3V
COMP
VCINH to VCOM..................................................................... +1V
AVDD, PGVDD to HVINP......................... -0.3V to HVINP + 0.3V
VGON, SRC, DRN to GND..................................... -0.3V to +34V
DRN to GATES........................................................ -34V to +34V
GATES to GND ............................................-0.3V to SRC + 0.3V
VGOFF to GND ...................................................... -26V to +0.3V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations see www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
32-Pin TQFN
Package Code
T3255+4C
21-0140
90-0012
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
47
JA
Junction to Case (θ
)
JC
1.7
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
29
JA
Junction to Case (θ
)
JC
1.7
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INA POWER INPUT
INA Supply Voltage
Range
V
2.7
5.5
V
V
INA
INA Undervoltage-
Lockout Threshold,
Rising
UVLO
2.45
2.55
2.65
R
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Maxim Integrated | 7
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Electrical Characteristics (continued)
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INA Undervoltage-
Lockout Threshold,
Falling
UVLO
2.45
V
F
Supply Current
Shutdown Current
OSCILLATOR
I
ENP = 1 or ENP bit = 1, no switching
1.8
7
3
mA
µA
INA
ENP = 0 and ENP bit = 0, total current
INA + HVINP
I
15
SD
Boost Converter
Switching Frequency
f
SWFREQ bit = 0
1.98
2.2
2.42
MHz
SW0
SW1
Boost Converter
Switching Frequency,
Low Setting
f
SWFREQ bit = 1
SSOFF bit = 1
390
-4
440
490
+4
kHz
%
Frequency Dither
REFERENCE
REF Output Voltage
REF Load Regulation
REF Line Regulation
BOOST CONVERTER
V
REF
1.238
1.25
10
1.262
20
V
I
from 0μA to 100μA
mV
mV
REF
2.7V < V
< 5.5V, no load
5
INA
AVDD Output Voltage
Range
V
AVDD
V
+ 1
18
V
A
INA
MAX20067B, 75% duty-cycle
MAX20067, 85% duty cycle
0.75
2.1
1
1.25
2.9
LXP Current Limit
2.5
Low-Side Switch On-
Resistance
R
0.2
0.4
5
Ω
μA
Ω
LXP
LXP Leakage Current
I
V
= 18V, T = +25°C
LXP
LXP A
Synchronous Rectifier
On-Resistance
R
SYNC
0.25
140
0.5
Synchronous Rectifier
Zero-Crossing
Threshold
I
2.2MHz
mA
SYNCZ
Maximum Duty Cycle
DC
90
94
98
%
MAX
Current-Limit Ramp
Time at Startup
t
12.5
ms
RAMP
FBP Regulation Voltage
FBP Load Regulation
FBP Line Regulation
V
1.225
1.25
-1
1.275
V
%
%
FPB
1mA < I
< 200mA
AVDD
V
INA
= 2.7V to 5.5V
-0.4
75
+0.4
85
FBP Undervoltage-Fault
Threshold
V
80
%
%
FBPUV
FBP Overvoltage-Fault
Threshold
V
110
115
120
FBPOV
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Maxim Integrated | 8
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Electrical Characteristics (continued)
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FBP Input Bias Current
I
200
nA
FBP
HVINP-AVDD Switch
On-Resistance
R
0.5
1.5
1
2
Ω
HA
AVDD Discharge
Resistance
R
AVDD
1
kΩ
After soft-start
During soft-start
240
120
HVINP-AVDD Switch
Current Limit
I
mA
LIMHA
POSITIVE CHARGE-PUMP REGULATOR
PGVDD Operating
Voltage Range
V
6
18
32
V
PGVDD
VGON Output Voltage
Range
V
V
VGON
DRVP Current Limit
I
40
mA
kHz
LIM_P
Positive Charge-Pump
Switching Frequency
440
1.25
80
FBGH Regulation
Voltage
V
1.225
75
1.275
85
V
%
FBGH
FBGH Undervoltage-
Fault Threshold
V
FBGHUV
FBGHOV
FBGH Overvoltage-
Fault Threshold
V
110
115
120
60
%
DRVP On-Resistance
High
R
Ω
ONH_DRVP
DRVP On-Resistance
Low
R
30
Ω
ONL_DRVP
HVINP-PGVDD Switch
On-Resistance
R
30
12
60
Ω
HP
HVINP-PGVDD Current
Limit
40
8
mA
kΩ
VGON Discharge
Resistance
16
-4
NEGATIVE CHARGE-PUMP REGULATOR
VGOFF Output Voltage
Range
-24
15
V
DRVN Current Limit
I
mA
kHz
LIMN
Negative Charge-Pump
Switching Frequency
440
1
FBGL Regulation
Voltage
V
FBGL
V
- V
FBGL
0.98
400
1.02
500
V
REF
FBGL Undervoltage-
Fault Threshold
V
Rising
450
mV
FBGLUV
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Maxim Integrated | 9
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Electrical Characteristics (continued)
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FBGL Overvoltage-Fault
Threshold
V
Falling
20
50
100
mV
FBGLOV
DRVN On-Resistance
High
R
60
30
16
Ω
Ω
ONH_DRVN
DRVN On-Resistance
Low
VGOFF Discharge
Resistance
8
12
kΩ
GATE-SHADING CIRCUIT
SRC Input Voltage
Range
V
32
20
V
Ω
Ω
SRC
SRC-to-GATES Switch
On-Resistance
R
R
10
10
SRC_GATES
DRN_GATES
DRN-to-GATES Switch
On-Resistance
20
6
DEL Pullup Current
DEL Enable Threshold
CTL-to-GATES Delay
4
5
µA
V
1.25
150
C
= 1nF
ns
GATES
MODE Switch On-
Resistance
1250
Ω
MODE Voltage
Threshold
MODE rising
2
V
μA
V
MODE Pullup Current
80
100
1.7
120
18
MODE Current-Source
Stop Threshold
VCOM BUFFER
VCOMP Voltage Range
5
V
VCOMP Quiescent
Supply Current
I
= 0mA, V
= 12V
COMP
1.8
500
0.5
mA
kΩ
VCOMP
VCINH Input Impedance
VCINH/VCOMP Division
Ratio
V/V
VCOM Output Current
Limit
130
-8
mA
mV
V
VCOM Offset Voltage
+8
VCOM Output Voltage
Range
V
-
COMP
1.5V
1.5
VCOM DAC Step Size
19.5
mV
V
VCOM DAC Voltage
Range
V
/
COMP
2 + 2.5V
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Maxim Integrated | 10
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Electrical Characteristics (continued)
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
VCINH - VCOM, falling
MIN
TYP
MAX
UNITS
VCOM Undervoltage-
Detection Threshold
-0.55
0.04
-0.35
-0.15
V
VCOM Overvoltage-
Detection Threshold
VCINH - VCOM, rising
tfault[1:0] = 01
0.25
60
0.41
20
V
VCOM Fault Detection
Filter Time
ms
kΩ
VCOM Discharge
Resistance
6
13
TFT FAULT PROTECTION
Fault Timeout
tfault[1:0] = 01
60
2.4
1
ms
s
Fault Retry Time
FLTB Output Frequency
Stand-alone mode only
0.88
1.12
kHz
FLTB Output Duty
Cycle, VGON or VGOFF
Fault
75
%
FLTB Output Duty
Cycle, HVINP Fault
50
25
%
%
%
%
%
V
FLTB Output Duty
Cycle, AVDD Fault
AVDD Undervoltage-
Fault Threshold
Relative measurement between HVINP
and AVDD
70
30
30
0.8
75
80
50
50
0.9
FBP Short-Circuit Fault
Threshold
40
FBGH Short-Circuit
Fault Threshold
40
FBGL Short-Circuit Fault
Threshold
0.85
10
Short-Circuit and
Overload Fault Delay
µs
THERMAL PROTECTION
Thermal Shutdown
T
165
15
°C
°C
SHDN
Thermal-Shutdown
Hysteresis
T
SHDN_HYS
LOGIC INPUT AND OUTPUTS
FLTB, DEL Low Output
Voltage
V
I
= 5mA
SINK
0.4
+1
V
µA
V
OL
FLTB, DEL, SDA
Leakage Current
I
-1
ILEAK
SDA Output Voltage
Low
V
0.8
OLSDA
ENPPD
ENP Pulldown Resistor
Value
R
50
75
kΩ
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Maxim Integrated | 11
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Electrical Characteristics (continued)
(V
= 3.6V, Limits are 100% tested at T = +25°C and T = +105°C. Limits over the operating temperature range and relevant
INA
A A
supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not
production tested. T = T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C, unless otherwise noted)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENP Glitch Filter Time
t
10
μs
ENP
ENP, CTL, SCL, SDA,
ADD Input Voltage Low
V
0.8
V
V
IL
ENP, CTL, SCL, SDA,
ADD Input Voltage High
V
IH
2
I2C INTERFACE
Clock Frequency
f
400
kHz
ns
SCL
Setup Time (Repeated)
START
t
260
260
SU:STA
Hold Time (Repeated)
START
t
ns
HD:STA
SCL Low Time
SCL High Time
Data Setup Time
Data Hold Time
t
350
260
50
ns
ns
ns
ns
LOW
t
HIGH
t
SU:DAT
HD:DAT
t
t
0
Setup Time for STOP
Condition
260
ns
ns
SU:STO
Spike Suppression
50
Note 2: Note 1: Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range
A
are guaranteed by design and characterization.
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Maxim Integrated | 12
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Typical Operating Characteristics
((V
= 3.3V, f
= 2.2MHz, C
= 1μF, T = +25°C unless otherwise noted.))
VCOM A
INA
SW
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Maxim Integrated | 13
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Typical Operating Characteristics (continued)
((V
= 3.3V, f
= 2.2MHz, C
= 1μF, T = +25°C unless otherwise noted.))
VCOM A
INA
SW
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Maxim Integrated | 14
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Typical Operating Characteristics (continued)
((V
= 3.3V, f
= 2.2MHz, C
= 1μF, T = +25°C unless otherwise noted.))
VCOM A
INA
SW
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Maxim Integrated | 15
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Typical Operating Characteristics (continued)
((V
= 3.3V, f
= 2.2MHz, C
= 1μF, T = +25°C unless otherwise noted.))
VCOM A
INA
SW
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Maxim Integrated | 16
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Pin Configuration
MAX20067
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
ENP
DRN
15
14
13
12
11
10
9
GATES
SRC
DGND
ADD
SDA
SCL
FLTB
FBP
MAX20067
MAX20067B
PGND
LXP
HVINP
AVDD
BST
+
REF
1
2
3
4
5
6
7
8
TQFN
5mm x 5mm
Pin Description
REF
SUPPLY
PIN
NAME
FUNCTION
Positive Charge-Pump Feedback Connection. FBGH is regulated to 1.25V.
Connect a resistor-divider from VGON to GND with its midpoint connected to
FBGH.
1
FBGH
Negative Charge-Pump Feedback Connection. FBGL is regulated to 0.25V.
Connect a resistor-divider from REF to VGOFF with its midpoint connected to
FBGL.
2
FBGL
3
4
5
6
7
GND
VGOFF
DRVN
VGON
DRVP
Ground Connection
Output of Negative Charge-Pump Block.
Negative Charge-Pump Push-Pull Drive Output
Output of Positive Charge-Pump Block
Positive Charge-Pump Push-Pull Drive Output
Supply voltage for positive charge-pump. PGVDD is connected to HVINP by
means of an internal switch when the positive charge-pump is enabled. Bypass
PGVDD with a ceramic capacitor of at least 1μF to GND.
8
PGVDD
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Maxim Integrated | 17
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Pin Description (continued)
REF
PIN
NAME
FUNCTION
SUPPLY
Bootstrap Capacitor Connection for Synchronous Rectifier Driver. Connect a
0.1μF ceramic capacitor between BST and LXP.
9
BST
HVINP
Switched Output of Boost Converter. Connect a bypass capacitor of at least 4.7μF
from AVDD to PGND.
10
11
12
13
AVDD
HVINP
LXP
Boost Output and Input to Positive and Negative Charge Pumps. Bypass HVINP
with the boost-converter output capacitor placed close to the pin.
Switching Node of Boost Converter. Connect the boost inductor between LXP and
INA.
Ground Connection for Boost Switching Device and VCOM Buffer. Connect to
GND using a low-impedance trace.
PGND
Source of Internal High-Side Switch in Gate-Shading Circuit. SRC is usually
connected to VGON. Bypass SRC with a 0.1μF capacitor placed close to the pin.
14
15
16
SRC
GATES
DRN
Switched Output of Gate-Shading Circuit
Lower Input of Gate-Shading Circuit. Connect to an external source or GND
through a discharge resistor.
Supply Voltage for VCOM Buffer. Normally connected to AVDD. Bypass V
with a 0.1μF ceramic capacitor placed close to the pin.
COMP
17
18
VCOMP
VCOM
Output of VCOM Amplifier. Bypass VCOM to GND with a 1μF ceramic capacitor.
Noninverting Input of VCOM Amplifier. In stand-alone mode, drive VCINH to set
19
20
21
VCINH
INA
the VCOM output voltage. VCINH is prebiased to 50% of V
resistor-divider comprising two 1MΩ resistors.
with an internal
COMP
Supply Connection for Display Bias Circuitry. Bypass INA with a local 0.1μF
capacitor.
Mode Configuration Pin for Gate-Shading Level Shifter. MODE is used to adjust
the timing of the gate-shading output. MODE is high impedance when connected
to INA, and internally pulled down during UVLO or in shutdown.
MODE
Control Input for Gate-Shading Circuit. When CTL is high, the switch between
GATES and SRC is on and the switch between GATES and DRN is off. When
CTL is low, the switch between GATES and DRN is on and the switch between
22
23
24
CTL
DEL
SEQ
GATES and SRC is off. CTL is inhibited by V
1.25V.
UVLO and when DEL is less than
CC
Gate-Shading Circuit Delay Input. Connect a capacitor from DEL to GND to set
the turn-on delay.
Logic-Level Sequencing Input Pin. The voltage level on SEQ determines whether
the IC is serially controlled, or one of the predetermined sequences is used.
Connect SEQ to INA or a resistive divider between INA and GND to set one of the
preset stand-alone sequences (see Table 3). For serial control, connect SEQ to
GND.
Active-High Enable Input for Boost Converter. ENP also enables the VGON and
VGOFF regulators in the set sequence. ENP has an internal pulldown resistor.
When serial control is used, connect ENP low.
25
ENP
26
27
28
DGND
ADD
Digital Ground. Connect directly to the exposed pad of the package.
2
I C Address-Selection Pin. Connect to GND for a base address of 0x20, or to INA
for a base address of 0x28.
2
SDA
Bidirectional I C Data Pin
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Maxim Integrated | 18
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Pin Description (continued)
REF
PIN
NAME
FUNCTION
SUPPLY
29
SCL
Serial-Clock Input
Open-Drain, Active-Low Fault Output. Connect a pullup resistor from FLTB to a
logic supply ≤ 5V. In stand-alone mode, the duty cycle of the FLTB pin indicates
an error condition, if present (see Table 4). When the serial interface is used,
FLTB is either a 0 (indicating data to be read from the internal registers) or a 1. It
does not output a PWM signal.
30
FLTB
Boost Feedback Connection. FBP is regulated to 1.25V. Connect a resistor-divider
from HVINP to GND with its midpoint connected to FBP.
31
FBP
32
-
REF
EP
Internal 1.25V Reference Output. Connect a 0.22μF capacitor from REF to GND.
Exposed Pad. Connect EP to GND.
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Maxim Integrated | 19
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Functional Diagrams
Typical Application Circuit
VIN
10mF
10mH
0.1mF
10mF
MODE
ADD SEQ INA
LXP
BST HVINP
FBP
FLT
SDA
SCL
PGND
VCOM
1mF
VCOM
VCINH
VCOMP
AVDD
100pF
AVDD
4.7mF
PGVDD
DRVP
0.1mF
MAX20067/MAX20067B
1mF
SRC
GS
VGON
0.1mF
0.1mF
VGON
VGON
AVDD
DRN
CTL
From
TCON
2.2mF
FBGH
DRVN
DEL
VGOFF FBGL
REF
GND ENP DGND
22nF
0.1mF
0.1mF
0.22mF
0.1mF
2.2mF
VGOFF
www.maximintegrated.com
Maxim Integrated | 20
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Detailed Description
The MAX20067/MAX20067B are highly integrated power-supply ICs for automotive TFT-LCD applications. The ICs
integrate one boost converter, two gate-driver supplies, a high-voltage “gate-shading” level shifter, and a high-current
VCOM buffer.
The main power-supply section, comprising the boost converter and gate-driver supplies, operates from a 2.7V to 5.5V
supply. The boost converter operates at 440kHz or 2.2MHz and has built-in spread spectrum that can be disabled using
the serial interface for reducing EMI.
The boost converter provides an output voltage adjustable up to 18V, with up to 200mA output current and has two
internal MOSFET switching elements.
The ICs provide gate-driver supplies using positive and negative charge-pump regulators, with a current capability of
10mA for the positive charge pump (using a doubler charge pump) and 3mA for the negative charge pump (assuming a
2-stage charge pump). Output voltage is adjustable with a +32V (max) output on the positive charge pump and -24V on
the negative charge pump.
The startup and shutdown sequences for all power domains, controlled using one of the preset modes, are selected
using the SEQ pin. Sequencing can also be controlled through the serial interface when the SEQ pin is grounded.
TFT Power Section
Source-Driver Power Supplies
The source-driver power supply consists of a boost converter that generates +18V (max) and can deliver up to +200mA
(+100mA for MAX20067B). The source-driver power supply’s regulation voltage (HVINP) is set by a resistor-divider
on FBP. The source driver uses constant-frequency peak-current-mode control, with internal fixed-slope compensation.
Internal compensation stabilizes the control loop. At low output power, the converter enters skip mode.
The TFT boost converter has an internal error amplifier with a g of 13μS that has FBP and REF = 1.25V as inputs.
m
There is an internal compensation network at the output of the error amplifier as follows:
C
C
= 140pF, R = 500kΩ
C
For the current loop, there is internal current sensing using a transresistance of R = 0.21V/A. The current-sense voltage
T
(V
= I_inductor x R ) is added to the slope compensation. The slope-compensation signal has a slope of 1250mV per
CS
T
microsecond.The resulting V
= V
+ V
is compared to V
(output of the error amplifier) at the input of
COMP
SUM
CS
SLOPE
the PWM comparator to regulate the LXP duty cycle.
Gate-Driver Power Supplies
The positive gate-driver charge pump (VGON) generates +32V (max) and the negative gate-driver charge pump
(VGOFF) generates -24V (min). The gate-driver supplies have a current capability of 10mA for the positive charge pump
(using a doubler charge pump) and 3mA for the negative charge pump (assuming a 2-stage charge pump). The VGON
and VGOFF regulation voltages are both set using the external resistor networks, as shown in the Typical Application
Circuit. Both charge-pump regulators use a 440kHz switching frequency. The charge pumps regulate the output voltages
by controlling the current that flows into the flying capacitors.
Operation of the Positive Charge Pump
The positive charge-pump regulator is typically used to generate the positive supply rail for the TFT-LCD gate-driver ICs.
The output voltage is set with an external resistive voltage-divider from its output to GND, with the midpoint connected to
FBGH. The number of charge-pump stages and the setting of the feedback-divider determine the output voltage of the
positive charge-pump regulator. The charge pump push-pull output consists of a high-side p-channel MOSFET (P1) and
a low-side n-channel MOSFET (N1) to control the power transfer.
The positive charge pump uses a simple skipping control scheme. The feedback signal (FBGH) is compared with a 1.25V
internal reference. The result of this comparison is sampled on every clock cycle. If the feedback signal is below 1.25V,
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Maxim Integrated | 21
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
a DRVP cycle is initiated. In the first half period, the rising edge of the clock turns on N1 and turns off P1, allowing the
flying capacitors to charge, while during the second half period, the falling edge of the clock turns off N1 allowing charge
transfer to the output. During both phases, N1 and P1 act as current-limited switches with a current limit of at least 40mA.
Alternatively, if the feedback signal is above 1.25V at the clock rising edge, the regulator ignores the clock period and N1
and P1 remain off.
The charge-pump regulator also includes a discharge switch from VGON to ground, turned off to discharge the output
2
capacitors during the sequential turn-off of the output voltages, as programmed by the SEQ pin or through I C. The
PGVDD node is internally connected through a switch to the HVINP voltage. See Table 3 for stand-alone sequencing
options.
Operation of the Negative Charge Pump
The negative charge-pump regulator is typically used to generate the negative supply rail for the TFT-LCD gate-driver
ICs. The output voltage is set with an external resistive voltage-divider from its output to REF, with the midpoint connected
to FBGL. The number of charge-pump stages and the setting of the feedback-divider determine the output of the negative
charge-pump regulator. The charge-pump controller includes a high-side p-channel MOSFET (P1) and a low-side n-
channel MOSFET (N1) to control the power transfer.
The feedback signal (FBGL) is compared with a 0.25V internal reference obtained by partitioning the main 1.25V
reference. The result of this comparison is sampled on every clock cycle. If (REF - FBGL) is less than 1.25V - 0.25V or
1V, a DRVN cycle is initiated. In the first half period, the rising edge of the clock turns on P1 and turns off N1, allowing
the flying capacitors to charge, while during the second half period, the falling edge of the clock turns on N1 and turns off
P1 allowing charge transfer to the output. During both phases, N1 and P1 act as current-limited switches with a current
limit of at least 15mA.
Alternatively, if (REF - FBGL) is less than 1V at the clock rising edge, the regulator ignores the clock period and N1 and
P1 remain off.
For sequencing of the output voltages at turn-off, a discharge switch is connected from VGOFF to ground. The desired
2
sequence is programmable using the SEQ pin or through I C. See Table 3 for the stand-alone sequencing options.
Fault Protection on the TFT Section
The ICs have robust fault and overload protection. If any of the source-driver or gate-driver supplies fall below 80% (typ)
or above 115% of the programmed regulation voltage for more than 60ms (typ, default), all the outputs turn off and a
fault condition is set. If a short condition occurs on any of the source-driver supplies for more than 10μs, all the outputs
turn off and a fault condition is set. A short condition is detected when the output voltage falls below 40% of the intended
regulation voltage. The output with the fault turns off immediately, while the other outputs follow the turn-off sequence
2
programmed by the SEQ pin or through I C. The fault condition is cleared when the ENP pin or INA supply is cycled
or after the retry timer (2.4s typ, default) times out, if enabled. If needed, the retry time can be adjusted or this function
disabled using the serial interface. In the case of a thermal fault, the ICs turn off immediately and remain off until the chip
temperature drops by 15°C (typ).
Output Control
The sequencing of the source-driver and gate-driver outputs (AVDD, VGON, and VGOFF) is determined by the setting of
2
the SEQ pin or through I C. All outputs are brought up with soft-start control to limit the inrush current. Table 3 lists the
sequencing options using the SEQ pin.
The outputs are also turned off in sequence, with the boost converter the last block to be disabled. Active pulldowns are
provided on all outputs to facilitate a controlled discharge. The pulldowns remain active for 512ms after the boost has
been disabled, at which point the ICs enter shutdown mode, if applicable.
Power-Up/Power-Down Sequencing and Timing
The ICs allow for flexible power-up/power-down sequencing and timing of the source-driver and gate-driver power
supplies (AVDD, VGON, and VGOFF). Toggling the ENP pin from low to high initiates an adjustable preset power-up
2
sequence. Alternatively, power-up sequencing can be controlled through I C. Toggling the ENP pin from high to low
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Maxim Integrated | 22
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
initiates the power-down sequence. The ENP pin has an internal deglitching filter of 10μs (typ). Note: A glitch in the ENP
signal with a period less than 10μs is ignored by the internal enable circuitry.
Gate-Shading Level Shifter
The gate-shading level shifter is enabled when the soft-start of all regulators is completed and the DEL pin exceeds its
enable threshold. A capacitor on the DEL pin can be used to adjust the startup-delay time together with the internal 5μA
current source. The delay can be calculated using the following equation:
1.25V × C
(
)
DEL
Delay =
5μA
When the ICs are disabled, GATES is discharged to GND. After the ICs are enabled, the GATES switches are off and
GATES is high impedance until the complete power sequence is finished (without a fault occurring) and DEL exceeds
1.25V. When DEL exceeds 1.25V, the level shifter is activated and its state controlled by the CTL and MODE inputs
according to Table 1. An external resistor and capacitor are used to produce the desired waveform where the rise of the
output signal is fast, but the fall is an exponential decay controlled by the external values of the resistor and capacitor. In
addition, a capacitor on the MODE pin can be used to delay the fall of the GATES output.
Connect MODE to INA when the V
according to the following equation:
delay is not needed. Connect a capacitor from MODE to GND to set the delay
GGS
100μA × t
(
)
DMODE
C
=
MODE
1.75V
where t
is the desired delay if the level shifter is not used to connect CTL to GND.
DMODE
Table 1
Table 1. Gate-Shading Operating Modes
CTL
Low
High
Low
High
MODE
High
High
Low
GATES OUTPUT
GATES shorted to DRN using internal device
GATES shorted to SRC using internal device
GATES shorted to DRN using internal device
GATES shorted to SRC using internal device
C
MODE
DISCHARGE
—
—
Off
On
Low
VCOM Buffer
The VCOM buffer is enabled when AVDD crosses its power-good threshold. The VCOM positive supply is V
, which
COMP
is normally externally connected to the AVDD output, while its negative supply is ground. The output voltage is set by
default to half of V through two 1000kΩ internal resistors. The VCOM buffer can be controlled either by driving
COMP
the VCINH pin or using the internal DAC that is written to through the serial interface. When driving the VCINH pin, the
source impedance or the resistance of the external resistor-divider should be much lower than 500kΩ. In DAC mode,
2
an 8-bit value is written through I C, which sets the VCOM output voltage in a nominal range of ±2.5V around AVDD/
2. Table 2 shows the correspondence between the DAC value written and the VCOM output voltage. The VCOM output
can source or sink a current up to a peak of 130mA. The LCD backplane consists of a distributed series capacitance and
resistance, a load that can be easily driven by the buffer. In a short-circuit condition, the power dissipation of the VCOM
buffer can lead to complete thermal shutdown of the ICs.
The VCOM buffer should be used with an external 1μF ceramic capacitor connected from its output to GND.
A VCOM buffer fault is detected if the voltage difference between VCINH and the VCOM output pin is greater than
250mV. The VCOM fault detection is filtered internally and a VCOM buffer fault is latched. To clear a fault, write a 0 to the
corresponding fault bit. In stand-alone mode, toggle the ENP pin or power down the device and then power it on again.
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Maxim Integrated | 23
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Table 2
Table 2. VCOM DAC Values
DAC VALUE
0xFF
0xFE
...
NOMINAL VCOM OUTPUT VOLTAGE WITH V
= 12V
AVDD
8.5V
8.5V
...
0x80
0x7F
0x7E
...
6.02V
6V
5.98V
...
0x01
0x00
3.52V
3.5V
FLTB Output
The FLTB output pin is an active-low, open-drain output that can be used to signal various device faults (for operation in
2
stand-alone mode, see the Stand-Alone Mode section). When the I C interface is used, the FLTB output can flag any or
all of the following conditions:
● Overtemperature fault
● Overcurrent on AVDD
● Undervoltage on HVINP, VGON, or VGOFF
● Overvoltage on HVINP, VGON, or VGOFF
● VCOM overvoltage or undervoltage
Some of the above conditions can be masked from causing FLTB to go low by using the corresponding mask bit in the
Fault Mask 1 (0x08) and Fault Mask 2 (0x09) registers.
Stand-Alone Mode
2
The ICs can be used either in stand-alone mode (when there is no local microcontroller), or in I C mode. In stand-alone
mode, the SEQ pin sets the sequence according to Table 3.
The ENP pin (active high) is used to turn on or off the complete device. In stand-alone mode, the open-drain FLTB output
is high when there is no detected fault. When a fault is detected, the FLTB pin outputs a signal with a duty cycle that
indicates what type of fault has been detected. This is summarized in Table 4.
Table 3
Table 3. Output Sequencing
POWER-ON SEQUENCING
POWER-OFF SEQUENCING
NOMINAL SEQ PIN VOLTAGE
1st
2nd
3rd
1st
2nd
3rd
2
GND
INA/2
INA
I C CONTROL
AVDD
AVDD
VGOFF
VGON
VGON
VGOFF
VGON
VGOFF
VGON
AVDD
AVDD
VGOFF
Table 4
Table 4. FLTB Output Duty Cycle
FLTB DUTY CYCLE
Continuously high
75%
ERROR CONDITION
No error
VGON or VGOFF fault
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Maxim Integrated | 24
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Table 4. FLTB Output Duty Cycle (continued)
50%
25%
1.5%
HVINP fault
AVDD fault
Thermal shutdown
I2C Serial Interface
2
2
The ICs contain an I C serial interface and act as slave devices. The basic unit of data transfer is 8 bits. To select I C
mode, connect the SEQ pin to GND. The state of the SEQ pin is sampled when the INA voltage exceeds approximately
2V and the status is latched.
2
Control of the power-up sequence through I C can be performed in two ways, manual or automatic. In manual mode, the
2
I C host enables the outputs individually using the bits in the Regulator Control register (0x02). If a fault is detected in
manual mode, the faulty output is disabled after the corresponding deglitch time and no other action is performed. Retry
is disabled in manual mode.
The bits in Fault registers 0x0A and 0x0B can be cleared by writing a 0 to the corresponding position in the register. If
the values of the other bits are retained, a 1 should be written to them. (e.g., if the vgon_ov bit is cleared in register 0x0A,
0x77 should be written to the register). In this manner, only bit 3 is cleared, and the other bits are left unchanged.
In automatic mode, the sequence is preset using the autoseq_row1–autoseq_row3 and textd_dly1, textd_dly2 bits, and
executed using the autoseq_ctrl bit. See the Automatic Sequencing Mode section for further details.
I2C Protocol
2
The I C address is chosen by connecting the ADD pin to either GND or INA (see Table 5). A master device
communicates with the IC by transmitting the correct Slave ID followed by the register address and data word. Each
transmit sequence is framed by a START (S) or Repeated START (Sr) condition and a STOP (P) condition. Each word
transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.
The SDA line operates as both an input and an open-drain output. A pullup resistor greater than 500Ω is required on
the SDA bus, or the resistor has to be selected as a function of bus capacitance, such that the rise time on the bus is
2
not greater than 120ns per the I C bus specification. The SCL line operates as an input only. A pullup resistor greater
than 500Ω is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an
open-drain SCL output. In general, for the SCL line resistor selection, the same recommendations as the SDA line apply.
Series resistors in line with SDA and SCL are optional. The SCL and SDA inputs suppress noise spikes to ensure proper
device operation even on a noisy bus.
Table 5
2
Table 5. I C Slave Addresses
DEVICE ADDRESS
WRITE
ADDRESS
READ
ADDRESS
ADD PIN CONNECTION
A6
0
A5
1
A4
0
A3
0
A2
0
A1
0
A0
0
GND
INA
0x40
0x50
0x41
0x51
0
1
0
1
0
0
0
Individual Output Control Through I2C
Using the bits in the Regulator Control register (0x02), all outputs can be controlled individually by the local host
microcontroller. When using this mode of operation, a fault on any output is signaled by the FLTB output pin (if not
masked) and the fault bits. The output with the fault remains active until the microcontroller intervenes.
When using the individual control bits, the boost converter must always be enabled first and disabled last in the sequence.
Autosequencing Mode
In autosequencing mode, a complete sequence is configured using the autoseq_row1-3[2:0] and textd_dly1-2 bits and
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Maxim Integrated | 25
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
then executed by setting the autoseq_ctrl bit.
To use autosequencing, set the en_autoseq bit in the Configurations register (0x01) to 1 and then configure the desired
sequence using the autoseq_row1–autoseq_row3 bits in the Auto Sequencing ctrl1 (0x04) and Auto Sequencing ctrl2
(0x05) registers. The 3 bits of autoseq_row1 correspond to the AVDD output and each bit represents one of three time
slots. To enable AVDD during the first time slot, set autoseq_row1 to 100. To enable AVDD during the second time slot,
set autoseq_row1 to 010, etc. In an analogous fashion, autoseq_row2 sets the VGON time slot and autoseq_row3 sets
the VGOFF time slot.
The delays between each of the time slots are configured using the textd_dly1 and textd_dly2 settings.
When the complete configuration is set, the sequence is executed automatically by setting autoseq_ctrl in the Regulator
Control register (0x02) to 1. The corresponding power-off sequence can be performed by setting autoseq_ctrl to 0. If a
fault occurs in automatic mode, the faulty output is turned off and the other outputs are turned off in the set order. If retry
is enabled, a retry is attempted after the appropriate delay.
Note: If the manual control bits have been used to enable one or more of the outputs, automatic sequencing behaves
differently: it starts immediately when the en_autoseq bit is set.
Figure 1. Sample Sequence
VGON
AVDD
0V
textd_dly1
textd_dly2
VGOFF
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Maxim Integrated | 26
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Register Map
Register Map
ADDRESS
bank 0
0x00
NAME
MSB
LSB
Device Id[7:0]
rev_id[3:0]
fault_latc en_autos
dev_id[3:0]
dis_ss
0x01
0x02
0x03
0x04
Configurations[7:0]
tretry[1:0]
tfault[1:0]
swfrq
en_bst
bst_on
h_dis
eq
autoseq_ dis_vco
Regulator control[7:0]
–
dis_gs
gs_on
en_vgoff en_vgon en_avdd
vgoff_on vgon_on avdd_on
ctrl
–
m
Regulator power
status[7:0]
–
–
–
vcom_on
Auto sequencing
ctrl1[7:0]
–
autoseq_row2[2:0]
textd_dly1[1:0]
vcom_dac[7:0]
autoseq_row1[2:0]
Auto sequencing
ctrl2[7:0]
0x05
0x06
0x07
textd_dly2[1:0]
autoseq_row3[2:0]
– –
VCOM voltage[7:0]
UNUSED - do not write
to this register[7:0]
–
–
–
–
–
–
–
–
vgoff_uv vgoff_ov vgon_uv vgon_ov avdd_ovl hvinp_uv hvinp_ov
0x08
0x09
Fault mask 1[7:0]
Fault mask 2[7:0]
_mask
_mask
_mask
vcom_uv vcom_ov
_mask _mask
_mask
d_mask
_mask
_mask
–
–
–
–
–
avdd_ovl
d
0x0A
0x0B
Fault register 1[7:0]
Fault register 2[7:0]
–
–
vgoff_uv vgoff_ov vgon_uv vgon_ov
vcom_uv vcom_ov
hvinp_uv hvinp_ov
–
–
–
th_shdn
hw_rst
Register Details
Device Id (0x00)
Register to identify the device type and the revision number
BIT
7
6
5
4
3
2
1
0
Field
rev_id[3:0]
0x0
dev_id[3:0]
0x9
Reset
Access
Type
Read Only
Read Only
BITFIELD
BITS
7:4
DESCRIPTION
rev_id
dev_id
Revision ID. 0 = revision 1, etc.
Device ID. Reads 0x9.
3:0
Configurations (0x01)
Miscellaneous configurations needed for part operations
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Maxim Integrated | 27
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BIT
Field
7
6
5
4
3
2
1
0
fault_latch_
dis
en_autoseq
0x0
tretry[1:0]
0x2
tfault[1:0]
0x1
dis_ss
0x0
swfrq
0x0
Reset
0x0
Access
Type
Write, Read Write, Read
Write, Read
Write, Read
Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Fault register bits are latched fault flags
0x1: Fault register bits are fault status bits (no
latching)
fault_latch_di
s
Fault register control. When set to 0, the fault
register bits are latched.
7
6
When set to 1, this bit enables the automatic
sequencing feature.
0x0: Automatic sequencing is disabled
0x1: Automatic sequencing is enabled
en_autoseq
tretry
If retry is enabled (set to any value other than 0x0: Retry is disabled
0x0), then this is the time that elapses before 0x1: Retry to power on regulator after 0.95s
5:4
3:2
a new power-on is attempted after turn-off
due to a regulator fault.
0x2: Retry to power on regulator after 1.9s
0x3: Retry to power on regulator after 3.8s
0x0: 30ms
0x1: 60ms
0x2: 120ms
0x3: 250ms
Fault-deglitch duration. This is the time that a
regulator fault must be continuously present
before the fault is considered valid.
tfault
0x0: Boost spread spectrum enabled
0x1: Boost spread spectrum disabled
dis_ss
swfrq
1
0
Boost spread-spectrum-disable control bit.
Boost converter switching-frequency
selection.
0x0: 2.2MHz boost switching frequency
0x1: 440kHz boost switching frequency
Regulator control (0x02)
Direct control of regulators enable. This register can be used on I2C variant when "en_autoseq = 0" to control the
manual sequencing of regulators, i.e. regulators sequencing is completely controlled by host software. Note that some
controls are implemented in this registers. As an example the enable of any regulator is not allowed unless "en_bst" has
been enabled and ready (bst_on = 1).
BIT
7
–
–
6
5
4
3
2
1
0
Field
autoseq_ctrl
0x0
dis_vcom
0x0
dis_gs
0x0
en_vgoff
0x0
en_vgon
0x0
en_avdd
0x0
en_bst
0x0
Reset
Access
Type
–
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Controls the automatic sequencer. If the
automatic sequencer is enabled, setting this
bit to 1 starts the power-on sequence as
programmed. Deasserting this bit to 0 starts
the power-down sequence. Note that the
sequence programming cannot be altered
while the sequence is ongoing. Once the
current sequence is completed, sequence
programming is again enabled. If the
en_autoseq bit is set to 0, this bit has no
effect.
0x0: If regulators are off, keep them as they are. If
regulators are on, start the power off sequence and
keep them off
0x1: If regulators are off start the power on
sequence and keep them on. Else keep them as
they are.
autoseq_ctrl
6
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Maxim Integrated | 28
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BITFIELD
BITS
DESCRIPTION
DECODE
VCOM buffer disable. By default, the VCOM
buffer is enabled when the AVDD crosses its
power-good threshold.
0x0: VCOM buffer is enabled
0x1: VCOM buffer has been disabled
dis_vcom
5
Gate-shading disable. By default, the gate-
shading block is enabled when soft-start for
all regulators is completed and when the DEL 0x1: Gate shading has been disabled
pin exceeds its enable threshold.
0x0: Gate shading is enabled
dis_gs
4
0x0: Negative charge pump is disabled
Negative charge-pump enable.
en_vgoff
en_vgon
3
2
0x1: Negative charge pump has been enabled
0x0: Positive charge pump is disabled
Positive charge-pump enable.
0x1: Positive charge pump has been enabled
Control bit for the switch between HVINP and
0x0: Switch beween HVINP and AVDD is open
AVDD. Note that any attempt to set this bit to
0x1: Switch beween HVINP and AVDD is closed
1 fails if the field "bst_ok" is 0.
en_avdd
en_bst
1
0
0x0: Buck is disabled
Boost converter enable.
0x1: Buck is enabled
Regulator power status (0x03)
Status of the regulators. Each bit set to 1 means that related regulator is powered on (i.e. it has been enabled, the
transient has completed and it's active ready)
BIT
7
–
–
6
–
–
5
4
3
2
1
0
Field
vcom_on
0x0
gs_on
0x0
vgoff_on
0x0
vgon_on
0x0
avdd_on
0x0
bst_on
0x0
Reset
Access
Type
–
–
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: The VCOM buffer is off
0x1: The VCOM buffer is on
vcom_on
5
This bit shows the status of the VCOM buffer.
This bit shows the status of the gate-shading
block.
0x0: The gate shading is off
0x1: The gate shading is on
gs_on
4
3
2
1
This bit shows the status of the negative
charge pump.
0x0: The charge pump is off
0x1: The charge pump is on
vgoff_on
vgon_on
avdd_on
This bit shows the status of the positive
charge pump.
0x0: The charge pump is off
0x1: The charge pump is on
This bit shows the status of the switch
between HVINP and AVDD.
0x0: The switch is open
0x1: The switch is closed
When this bit is set to 1, the boost converter
0x0: Boost has not been activated
bst_on
0
has been activated and its output voltage is in 0x1: Boost has been activated and power on
range. transient completed
Auto sequencing ctrl1 (0x04)
Programming for the control of the automatic sequncing
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Maxim Integrated | 29
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BIT
Field
7
–
–
6
–
–
5
4
autoseq_row2[2:0]
0x0
3
2
1
autoseq_row1[2:0]
0x0
0
Reset
Access
Type
–
–
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
Autosequencing matrix row 2, corresponding to VGON. A 1 in this bit
corresponds to start the regulator in slot 1, 2, or 3 depending on the position
of the 1. If more than a 1 is present in the field, only the first one is considered
valid.
autoseq_row2
autoseq_row1
5:3
2:0
Autosequencing matrix row 1, corresponding to AVDD. A 1 in this bit
corresponds to start the regulator in slot 1, 2, or 3 depending on the position
of the 1. If more than a 1 is present in the field, only the first one is considered
valid.
Auto sequencing ctrl2 (0x05)
Programming for the control of the automatic sequncing
BIT
7
–
–
6
5
4
3
2
1
autoseq_row3[2:0]
0x0
0
Field
textd_dly2[1:0]
textd_dly1[1:0]
Reset
0x0
0x0
Access
Type
–
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No delay after power OK of preceeding
regulators
0x1: Additional 10% delay after power OK of
preceeding regulators
0x2: Additional 20% delay after power OK of
preceeding regulators
0x3: Additional 30% delay after power OK of
preceeding regulators
Delay extension as a percentage of the time
that elapses between the power-on command
for regulators in slot 2 and the assertion of
the feedback signal that notifies they
completed ramp up. If we name Tok such
time the delay between slot 2 and slot 3 will
be Tok x (1 + textd_dly2).
textd_dly2
6:5
0x0: No delay after power OK of preceeding
regulators
0x1: Additional 10% delay after power OK of
preceeding regulators
0x2: Additional 20% delay after power OK of
preceeding regulators
0x3: Additional 30% delay after power OK of
preceeding regulators
Delay extension as a percentage of the time
that elapses between the power-on command
for regulators in slot 1 and the assertion of
the feedback signal that notifies they
completed ramp up. If we name Tok such
time the delay between slot 1 and slot 2 will
be Tok x (1 + textd_dly1).
textd_dly1
4:3
2:0
Autosequencing matrix row 3, corresponding
to VGOFF. A 1 in this bit corresponds to start
the regulator in slot 1, 2, or 3 depending on
the position of the 1. If more than a 1 is
present in the field, only the first one is
considered valid.
autoseq_row
3
VCOM voltage (0x06)
This byte controls the setting of the DAC controlling the VCOM output voltage
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Maxim Integrated | 30
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BIT
Field
7
6
5
4
3
2
1
0
vcom_dac[7:0]
Reset
0x7F
Access
Type
Write, Read
BITFIELD
vcom_dac
BITS
DESCRIPTION
This byte controls the DAC that sets the VCOM output voltage. The output
step is 20mV/LSB. The mid-point is 0x7F = AVDD/2.
7:0
Fault mask 1 (0x08)
Fault mask register. Each bit in this register is able to mask the fault of the related bit. A 1 in a position enables the
contribution of the fault flag to the FLTB assertion.
BIT
7
–
–
–
6
5
4
3
2
1
0
vgoff_uv_m vgoff_ov_m vgon_uv_m vgon_ov_m avdd_ovld_ hvinp_uv_m hvinp_ov_m
Field
ask
ask
ask
ask
mask
ask
ask
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
Type
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
Mask for VGOFF undervoltage fault. If this bit is set to 1, an undervoltage fault
on VGOFF does not cause FLTB to go low.
vgoff_uv_mask
vgoff_ov_mask
vgon_uv_mask
vgon_ov_mask
avdd_ovld_mask
hvinp_uv_mask
hvinp_ov_mask
6
Mask for VGOFF overvoltage fault. If this bit is set to 1, an overvoltage fault
on VGOFF does not cause FLTB to go low.
5
4
3
2
1
0
Mask for VGON undervoltage fault. If this bit is set to 1, an undervoltage fault
on VGON does not cause FLTB to go low.
Mask for VGON overvoltage fault. If this bit is set to 1, an overvoltage fault on
VGON does not cause FLTB to go low.
Mask for AVDD overcurrent fault. If this bit is set to 1, an overcurrent fault on
AVDD does not cause FLTB to go low.
Mask for HVINP underervoltage fault. If this bit is set to 1, an undervoltage
fault on HVINP does not cause FLTB to go low.
Mask for HVINP overvoltage fault. If this bit is set to 1, an overvoltage fault on
HVINP does not cause FLTB to go low.
Fault mask 2 (0x09)
Fault mask register. Each bit in this register is able to mask the fault of the related bit. A 1 in a position enables the
contribution of the fault flag to the FLTB assertion.
BIT
7
–
–
–
6
–
–
–
5
–
–
–
4
3
2
–
–
–
1
–
–
–
0
–
–
–
vcom_uv_m vcom_ov_m
Field
ask
ask
Reset
0x0
0x0
Access
Type
Write, Read Write, Read
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Maxim Integrated | 31
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BITFIELD
BITS
DESCRIPTION
Mask for VCOM undervoltage fault. If this bit is set to 1, an undervoltage fault
on VCOM does not cause FLTB to go low.
vcom_uv_mask
4
3
Mask for VCOM overvoltage fault. If this bit is set to 1, an overvoltage fault on
VCOM does not cause FLTB to go low.
vcom_ov_mask
Fault register 1 (0x0A)
Fault register 1. Each bit of this register can be a status bit (reflecting current status of the fault) or a flag bit (latched
version of a status bit).
BIT
7
–
–
6
5
4
3
2
1
0
Field
vgoff_uv
0x0
vgoff_ov
0x0
vgon_uv
0x0
vgon_ov
0x0
avdd_ovld
0x0
hvinp_uv
0x0
hvinp_ov
0x0
Reset
Access
Type
Write 0 to
Write 0 to
Write 0 to
Write 0 to
Write 0 to
Write 0 to
Write 0 to
–
Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read Clear, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present else this bit is 0.
VGOFF undervoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
vgoff_uv
6
5
4
3
2
1
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
VGOFF overvoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
vgoff_ov
vgon_uv
vgon_ov
avdd_ovld
hvinp_uv
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
VGON undervoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
VGON overvoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
AVDD overcurrent fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
HVINP undervoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
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Maxim Integrated | 32
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
HVINP overvoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
hvinp_ov
0
Fault register 2 (0x0B)
Fault register 2. Each bit of this register is a flag bit (latched fault).
BIT
7
–
–
6
–
–
5
–
–
4
3
2
–
–
1
0
Field
vcom_uv
0x0
vcom_ov
0x0
th_shdn
0x0
hw_rst
0x1
Reset
Access
Type
Write 0 to
Clear, Read Clear, Read
Write 0 to
Write 0 to
Clear, Read
–
–
–
–
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
VCOM buffer undervoltage fault. Depending
on programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
vcom_uv
4
3
0x0: No fault is present or has happened
0x1: If "fault_latch_dis" = 0 then a fault has
happened or is still present. In this case the bit is
CoR, but reasserts if fault is still present.
If "fault_latch_dis" = 1 then a fault is currently
present, else this bit is 0.
VCOM buffer overvoltage fault. Depending on
programing of "fault_latch_dis," this is a
status bit or a clear-on-read flag bit.
vcom_ov
Thermal-shutdown event was detected. If the 0x0: no thermal shutdown since last read
event is still on, the flag reasserts upon CoR. 0x1: Device is in thermal shutdown
th_shdn
hw_rst
1
0
0x0: no POR since last read
Hardware reset event was detected
0x1: this is the first read from the device after a
POR
www.maximintegrated.com
Maxim Integrated | 33
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Applications Information
Boost Converter
Inductor Selection
The value of the boost inductor is determined as follows:
V
× D
(
)
INA
L =
LIR × I
× f
(
)
INA SW
where V
is the boost input voltage, D is the duty cycle, LIR is the current ripple factor in the inductor (choose a value
INA
between 0.5 and 1), I
is the boost converter input current, and f
is either 2.2MHz or 440kHz.
SW
INA
Calculate the duty-cycle using:
1 − η × V
(
)
INA
D =
V
OUT
where η is the converter efficiency (assume 0.85) and V
is the boost output voltage.
OUT
I
, the average input current, can be estimated as follows:
INA
V
× I
(
)
OUT OUT
I
=
INA
η × V
(
)
INA
where I
is the boost output current.
OUT
Capacitor Selection
The input and output filter capacitors should be a low-ESR type (e.g., tantalum, ceramic, or low-ESR electrolytic) and
should have RMS current ratings greater than:
LIR × I
(
)
INA
I
=
RMS
12
√
for the input capacitor, and:
2
LIR
12
D +
(
)
I
= I
×
RMS
OUT
√
1 − D
(
)
for the output capacitor. The output voltage contains a ripple component whose peak-to-peak value depends on the value
of the ESR and capacitance of the output capacitor and is approximately the sum of two contributions:
ΔV
= ΔV
+ ΔV
RIPPLE
ESR
CAP
where:
LIR
2
ΔV
= I
× 1 +
(
× R
ESR
ESR
INA
)
and
I
× D
(
C
)
)
OUT
ΔV
=
CAP
× f
(
OUT SW
where R
is the ESR of the chosen output capacitor.
ESR
www.maximintegrated.com
Maxim Integrated | 34
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Output-Voltage Selection
The output voltage of the boost converter can be adjusted using a resistive voltage-divider formed by R
and
TOP
R
. Connect R
between HVINP and FBP, and connect R
between FBP and GND. Select R
BOTTOM BOTTOM
BOTTOM
TOP
in the 10kΩ to 50kΩ range. Calculate R
with the following equation:
TOP
V
OUT
R
= R
×
− 1
TOP
BOTTOM
1.25
(
(
)
)
Place the resistors close to the device and connect R
to the analog ground plane.
BOTTOM
Boost Converter Operation at low INA and high Output Power
At high boost output power and low input voltages, the input current becomes high and and the boost converter's
efficiency is lower. Under these conditions, it may be preferable to use the 440kHz low-frequency setting. A further boost
in efficiency at low input voltages can be obtained by adding a Schottky diode from LXP to HVINP. See all the relevant
curve in the Typical Operating Characteristics section
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest number of charge-pump stages that meet the output voltage
requirement. The number of positive charge-pump stages is given by:
VGON + V
− V
DROPOUT
AVDD
nPOS =
V
− 2 × V
SUP
D
where nPOS is the number of positive charge-pump stages, VGON is the output of the positive charge-pump regulator,
is the supply voltage of the charge-pump regulators (HVINP), V is the forward voltage drop of the charge-pump
V
SUP
D
diodes, and V
is the dropout margin for the regulator. Use V
= 600mV.
DROPOUT
DROPOUT
The number of negative charge-pump stages is given by:
− VGOFF + V
DROPOUT
nNEG =
V
− 2 × V
SUP
D
where nNEG is the number of negative charge-pump stages and VGOFF is the output of the negative charge-pump
regulator.
Flying Capacitors
Increasing the flying capacitor (connected to DRVN and DRVP) value lowers the effective source impedance and
increases the output current capability. Increasing the capacitance indefinitely, however, has a negligible effect on output-
current capability because the internal switch resistance and the diode impedance place a lower limit on the source
impedance. A 0.1μF ceramic capacitor works well in most applications. The flying capacitor’s voltage rating must exceed
the following:
VCX > n × V
HVINP
where n is the stage number in which the flying capacitor appears.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-to-peak
transient voltage. With ceramic capacitors, the output-voltage ripple is dominated by the capacitance value. Use the
following equation to approximate the required capacitor value:
I
LOAD_CP
C
>
2xf
OUT_CP
× V
SW
RIPPLE_CP
where C
is the output capacitor of the charge pump, I
is the desired peak-to-peak value of the output ripple, and f
is the load current of the charge pump,
is the switching frequency, which is 440kHz.
OUT_CP
LOAD_CP
V
RIPPLE_CP
SW
www.maximintegrated.com
Maxim Integrated | 35
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Power Dissipation
The total internal power dissipation comprises five terms:
1. Boost converter power dissipation
2. Positive charge-pump dissipation
3. Negative charge-pump dissipation
4. Gate-shading power dissipation
5. VCOM buffer power dissipation
Items 2–4 are negligible, while the other terms can be estimated using:
2
INA
2
P
= I
× R × D + I
× R × 1 − D + 0.5 × I
INA
× V
× t × f
(
)
BOOST
L
H
INA
HVINP RF SW
where R is the low-side LXP switch resistance, R is the high-side LX switch resistance, and t
is the LXP rise/fall
L
H
RF
time that can be approximated by 5ns:
P
= V
(
− V
* I
)
VCOM
AVDD
VCOM VCOM
where I
is the RMS VCOM buffer output current.
VCOM
PCB Layout Example
Figure 2 shows an example for the layout of the power components around the MAX20067/MAX20067B. This layout
minimizes the area of the LXP node and the area of the switching current loop. Follow these guidelines for the rest of the
layout:
1. Separate power and analog grounds on the board and connect them together at a single point.
2. Connect all feedback resistor-dividers to the analog or "quiet" ground, along with the REF and INA capacitors.
Feedback resistors should be placed close to their associated pins to avoid noise pickup.
3. Place decoupling capacitors as close as possible to their respective pins.
4. Keep high-current paths as short and wide as possible.
5. Route high-speed switching nodes (i.e., LXP, DRVN, and DRVP) away from sensitive analog nodes (i.e., FBP, FBGH,
FBGL, and REF).
www.maximintegrated.com
Maxim Integrated | 36
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Layout Example
24
23
22
21
20
19
18
17
DRN
25
26
27
16
15
14
GATES
SRC
Vias to
PGND plane
BOOST
INDUCTOR
28
29
30
31
13
12
PGND
LXP
MAX20067
INPUT VOLTAGE
HVINP 11
10
9
AVDD
BST
32
CBST
COUT
1
3
4
5
6
7
8
2
PGND
Vias to
COUT
PGND plane
Figure 1. Layout Example
www.maximintegrated.com
Maxim Integrated | 37
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Ordering Information
PART
TEMP RANGE
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
32 TQFN
PKG CODE
T3255+4C
T3255+4C
MAX20067GTJ/V+
MAX20067BGTJ/V+
32 TQFN
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
www.maximintegrated.com
Maxim Integrated | 38
MAX20067/MAX20067B
Automotive 3-Channel Display Bias IC with VCOM
2
Buffer, Level Shifter, and I C Interface
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
7/17
Initial release
—
Added MAX20067B variant, adjusted VGON, SRC and DRN absolute maximum
ratings and operating voltage ranges.
1
2
9/20
1/21
1, 3, 4, 5, 6, 16
1, 3, 4, 5, 6, 16
Changed maximum value of VGOFF Output Voltage Range to -4V, adjusted VGON,
SRC and DRN absolute maximum ratings and operating voltage ranges.
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2021 Maxim Integrated Products, Inc.
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