MAX20310DEWE [MAXIM]
Ultra-Low Quiescent Current PMIC with SIMO Buck-Boost for Wearable Applications;
| 型号： | MAX20310DEWE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Quiescent Current PMIC with SIMO Buck-Boost for Wearable Applications 集成电源管理电路 |
| 文件： | 总30页 (文件大小：849K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
General Description
Benefits and Features
The MAX20310 is a compact power management
integrated circuit (PMIC) for space-constrained, battery-
powered applications where size and efficiency are critical.
The device combines two single inductor, multiple output
(SIMO) buck-boosted outputs with two LDOs and other sys-
tem power management features like a push-button monitor
and sequencing controller.
● Extend System Battery Use Time
• Single Inductor, Multiple Output (SIMO) Ultra-Low
I
Buck-Boost Regulator
Q
• Battery Input Voltage from 0.7V to 2.0V
• Output Voltage Programmable From 0.9V
to 4.05V
• 250mW Maximum Total Input Power
• Incremental CAP Quiescent Current 1μA per
channel
The device includes a SIMO buck-boost switching regula-
tor that provides two programmable voltage rails using
a single inductor, minimizing solution footprint. The
MAX20310 operates with battery voltages down to 0.7V
for use with Zinc Air, Silver Oxide, or Alkaline batteries.
The architecture allows for output voltages above or
below the battery voltage.
• 84% Efficiency for 1.8V, 10mA Output
• Input Current Limited
• Dual Ultra-Low I 50mA LDO
Q
• Inputs Supplied by Dual Buck-Boost Outputs
• Output Programmable from 0.5V to 3.65V
• Quiescent Current 1.1µA per LDO / 600nA per
Load Switch
Additionally, the MAX20310 has two programmable low-
dropout (LDO) linear regulators. The linear regulators can
also operate as power switches that can disconnect the
quiescent load of system peripherals.
• Configurable as Load Switch
● Extend Product Shelf-Life
• Battery Seal Mode
The MAX20310 includes
a programmable power
• 10nA Battery Current (typ)
controller that allows the device to be configured for
use in applications that require a true off state or for
always-on applications. This controller provides a delayed
reset signal, voltage sequencing, and customized button
timing for on/off control and recovery hard reset.
● Minimize Board Area
• 1.63mm x 1.63mm WLP
● Easy-to-Implement System Control
• Voltage Monitor Multiplexer
• 1% Accurate Battery Inverter (±10mV at 1.0V)
• Power Button Monitor
The device also features a multiplexer for monitoring the
power inputs and outputs of each function. The MAX20310
is available in a 16-bump 0.4mm pitch 1.63mm x 1.63mm
wafer-level package (WLP) and operates over the -40°C
to +85°C extended temperature range.
• Buffered Output
• Power Sequencing
• Reset Output
2
• I C Control Interface
Typical Operating Circuit
Applications
● Wearable Medical Devices
● Wearable Fitness Devices
● Portable Medical Devices
+1.8V +1.5V +1.2V +1.2V
VIO VAN VDD VSW
MAX20310
CAP
LX
BB1OUT
L1OUT
LDO
SIMO
BUCK-
BOOST
GND
BB2OUT
L2OUT
LDO
BATN
Ordering Information appears at end of data sheet.
KIN
KOUT
MPO
MON
RST
MPC
SCL
SDA
CONTROL
19-8611; Rev 2; 3/18
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Absolute Maximum Ratings
(Voltages reference to GND unless otherwise noted)
Continuous Current into any other terminal ...................±100mA
CAP, BB1OUT, BB2OUT, L1OUT, L2OUT
Continuous Power Dissipation (T = +70°C):
A
MPC, SDA, SCL, RST, KOUT to GND, BATN....-0.3V to +6V
KIN............................................ (BATN – 0.3V) to (GND + 0.3V)
LX to BATN..............................................................-0.3V to +6V
MPO, MON to BATIN ..............................................-0.3V to +6V
GND to BATN.......................................................-0.3V to +2.2V
Continuous Current into LX, BATN ....................................+0.5A
16-bump WLP 1.65mm x 1.65mm 0.4mm Pitch
(derate 17.4mW/°C above +70°C) ..............................957mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
PACKAGE TYPE: 16 WLP
Package Code
W161F1+1
Outline Number
21-0491
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
58°C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 2
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics
(V
= +1.2V, V
= +1.8V, V
= +1.2V, V
= +1.5V, V
= +1.0V, I
= I
= I
= I
= 0A,
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB1OUT
BB2OUT
L1OUT
L2OUT
T
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T = +25°C) (Note 1) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY CURRENT
Seal mode, all functions disabled,
Seal Input Current
I
0.01
465
0.2
µA
SEAL
T
= +25°C
A
KIN Pullup Resistor to
GND
KIN
kΩ
PULLUP
Buck-boost 1 enabled
4
5
µA
µA
µA
µA
Buck-boost 1 and 2 enabled
CAP Quiescent Current
I
Q_CAP
Buck-boost 1 and 2 and LDO 1 enabled
Buck-boost 1 and 2 and LDO 1 and 2 enabled
5.25
5.5
POWER SEQUENCE
Reset Time Accuracy
t
-10
+10
%
V
RST
BUCK-BOOST REGULATOR
Operating
0.7
0.8
0.9
2
2
Input Voltage
V
BAT
Startup
Output Voltage Range
V
50mV steps, (Note 3)
4.05
V
OUT
Quiescent Supply
Current From CAP
Burst mode, no switching, V
= +1.8V
1
µA
IQ_BB
BB_OUT
T
T
T
= +25°C
-1
-1.8
-3
1
A
A
A
Output Accuracy
V
= 0°C to +85°C
= -40°C to +85°C
+1.8
+3
%
OUT_ACC_BB_OUT
PSRR
Power Supply Rejection
Ratio
C
= 10µF
40
dB
BB_OUT
Maximum Input Power
P
(Note 5)
250
mW
IN
V
V
= +1.8V
= +3.3V
200
244
BB_OUT
BB_OUT
Maximum Input Current
I
mA
IN
Short-Circuit Current
Limit
I
Maximum programmable current setting
0.6
10
A
LIM
Passive Discharge
Resistance
R
kΩ
PAS_BB_OUT
LDO
LDO UVLO enabled
1.1
0.4
2
Quiescent Supply
Current
I
µA
µA
Q_LDO
Switch mode, V
= +1.8V
– 0.1V
BB_OUT
Quiescent supply
Current in Dropout
I
V
= V
1.7
3.5
Q_LDO_D
BB_OUT
LDO_SET
Maximum Output
Current
I
(Note 4)
50mV steps
50
mA
V
MAX_LDO
Output Voltage
V
0.5
3.65
OUT_LDO
Maxim Integrated
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics (continued)
(V
= +1.2V, V
= +1.8V, V
= +1.2V, V
= +1.5V, V
= +1.0V, I
= I
= I
= I
= 0A,
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB1OUT
BB2OUT
L1OUT
L2OUT
T
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T = +25°C) (Note 1) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(V
=
BB_OUT
T
T
= 0°C to +85°C
-3
3
A
A
+
LDO_SET
Output Accuracy
Dropout Voltage
V
%
OUT_ACC_LDO
0.5V) or higher,
= -40°C to +85°C
-3.5
-1
+3.5
100
1
I
= 1mA
LOAD
V
= V
= 50mA
= +1.8V,
BB_OUT
LDO_SET
V
mV
DROP_LDO
I
LOAD
V
= (V
+ 0.5V) to
BB_OUT
LDO_SET
Line Regulation
Load Regulation
LINEREG
%/V
%/mA
kΩ
LDO
+4.05V
LOADREG
I
= 50µA to 50mA
0.003
10
LDO
PAS_LDO
LOAD
Passive Discharge
Resistance
R
Power Switch Mode
Resistance
R
V
= +1.2V
= 0mA
1
Ω
ON_LS
BB_OUT
I
I
0.7
2.8
LDO_OUT
LDO_OUT
Turn-On Time
t
V/µs
ON_SLOPE
= 0mA. Switch mode.
Thermal Shutdown
Threshold
T
T rising
150
21
°C
°C
SD
J
Thermal Shutdown
Hysteresis
T
HYS
MONITOR MULTIPLEXER
MON Impedance
R
Sense pin voltage > +0.5V
500
10
Ω
MON
Battery Voltage Buffer
Precision
V
-10
1.4
mV
BAT_OFF
DIGITAL SIGNALS
SDA, SCL, MPC Input
Logic-High
V
V
V
V
IH
SDA, SCL, MPC Input
Logic-Low
V
0.5
0.4
IL
SDA, RST, KOUT
Output Logic-Low
V
I
= 4mA
OL
OL
I
I
= 4mA to GND
= 4mA to BATN
0.4
0.4
OL
OL
MPO Output Logic-Low
SCL Clock Frequency
V
V
OL_MPO
f
(Note 5)
0
400
kHz
SCL
Bus Free Time Between
a STOP and START
Condition
t
1.3
µs
BUF
Maxim Integrated
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Electrical Characteristics (continued)
(V
= +1.2V, V
= +1.8V, V
= +1.2V, V
= +1.5V, V
= +1.0V, I
= I
= I
= I
= 0A,
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB1OUT
BB2OUT
L1OUT
L2OUT
T
= -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at T = +25°C) (Note 1) (Note 2)
A
A
PARAMETER
SYMBOL
t
CONDITIONS
MIN
TYP
MAX
UNITS
START Condition
(Repeated) Hold Time
(Note 6)
0.6
µs
HD:STA
Low Period of SCL
Clock
t
1.3
0.6
µs
µs
LOW
High Period of SCL
Clock
t
HIGH
Setup Time for a
Repeated START
Condition
µs
µs
t
0.6
SU:STA
Data Hold Time
Data Setup Time
t
(Notes 7, 8)
(Note 7)
0
µs
ns
HD:DAT
t
100
SU:DAT
Setup Time for STOP
Condition
t
0.6
µs
SU:STO
Note 1: All devices are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
Note 2: V
refers to the voltage across the battery terminals; V
= V
– V
.
BAT
BAT
GND
BATN
Note 3: Output voltage must not exceed V
- V
= 5.0V.
BB_OUT
BATN
Note 4: Actual value may be limited by the lower of the capability of the source (battery) or the maximum input power of the MAX20310.
Note 5: Timing must be fast enough to prevent the device from entering sleep mode due to bus low for period > t
.
SLEEP
Note 6: f
must meet the minimum clock low time plus the rise/fall times.
SCL
Note 7: The maximum t
has to be met only if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 8: The device internally provides a hold time of at least 100ns for the SDA signal (referred to the V
of the SCL signal) to
IH_MIN
bridge the undefined region of the falling edge of SCL.
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Typical Operating Characteristics
(V
= 1.2V, V
= 1.8V, V
= 1.2V, V
= 1.5V, V
= 1.0V, L = 1.5µH, C
= 10µF (effective), C
= 1µF
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB_OUT
CAP
(effective), C
= 2.2µF (effective) no load on any rail, T = +25°C, unless otherwise noted.)
A
LDO
SEAL MODE INPUT CURRENT vs. VBAT
QUIESCENT CURRENT vs. VBAT
ALL OUTPUTS
QUIESCENT CURRENT vs. TEMPERATURE
toc01
toc02
toc03
18
16
14
12
10
8
40
35
30
25
20
15
10
5
30
25
20
15
10
5
BB1OUT,
ALL
BB2OUT,
REGULATORS
L1OUT ON
ON
BB1OUT,
BB2OUT,
L1OUT ON
ON
BB1OUT,
BB2OUT ON
+25°C
-40°C
6
4
BB1OUT,
ALL
ALL OUTPUTS
OFF
BB2OUT ON
BB1OUT ON
2
REGULATORS
BB1OUT ON
1.74
OFF
0
0
0
0.7
0.96
1.22
1.48
1.74
2
0.7
0.96
1.22
1.48
2
-40
-15
10
35
60
85
VBAT (V)
TEMPERATURE (°C)
VBAT (V)
BB1OUT EFFICIENCY vs. LOAD CURRENT
BB1OUT LOAD REGULATION ERROR
toc04
toc05
90
2
1.8
1.6
1.4
1.2
1
ISET = 00
80
70
60
50
40
30
20
10
0
ISET = 11
ISET = 10
ISET = 11
ISET = 01
0.8
0.6
0.4
0.2
0
ISET = 00
ISET = 10
120
ISET = 01
L = 2.2µH
BBst2En = 0
L = 2.2µH
30
0.001
0.01
0.1
1
10
100
0
60
90
150
IBB1OUT (mA)
IBB1OUT (mA)
BB2OUT EFFICIENCY vs. LOAD CURRENT
BB2OUT LOAD REGULATION ERROR
toc07
toc06
90
80
70
60
50
40
30
20
10
0
1.4
1.2
1
ISET = 00
ISET = 11
ISET = 10
ISET = 01
ISET = 11
0.8
0.6
0.4
0.2
0
ISET = 00
ISET = 01
ISET = 10
L = 2.2µH
BBst1En = 0
L = 2.2µH
30
0.001
0.01
0.1
1
10
100
0
60
90
120
150
IBB2OUT (mA)
IBB2OUT (mA)
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Typical Operating Characteristics (continued)
(V
= 1.2V, V
= 1.8V, V
= 1.2V, V
= 1.5V, V
= 1.0V, L = 1.5µH, C
= 10µF (effective), C = 1µF
CAP
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB_OUT
(effective), C
= 2.2µF (effective) no load on any rail, T = +25°C, unless otherwise noted.)
A
LDO
BB2OUT LINE REGULATION
NO LOAD
BB1OUT LINE REGULATION
LDO LOAD REGULATION ERROR
L1OUT
toc09
toc10
toc08
1.813
1.8125
1.812
1.2112
1.211
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
NO LOAD
1.2108
1.2106
1.2104
1.2102
1.21
IBB2OUT = 10mA
1.8115
1.811
IBB1OUT = 10mA
L2OUT
1.2098
1.2096
1.2094
1.8105
1.81
0.7
0
0.96
1.22
1.48
1.74
2
0.7
0.96
1.22
1.48
1.74
2
0.001
0.01
0.1
1
10
100
VBAT (V)
VBAT (V)
LOAD CURRENT (mA)
LDO2 LINE REGULATION
LDO1 LINE REGULATION
toc12
toc11
1.509
1.002
1.001
1
1.508
1.507
1.506
1.505
1.504
1.503
1.502
1.501
1.5
NO LOAD
0.999
0.998
0.997
0.996
0.995
NO LOAD
IL1OUT = 10mA
IL2OUT = 10mA
3.44 4
1.7
2.16
2.62
3.08
3.54
4
1.2
1.76
2.32
2.88
VBB1OUT (V)
VBB2OUT (V)
L1OUT LOAD TRANSIENT RESPONSE
L1OUT LOAD TRANSIENT RESPONSE
10μA TO 10mA
50μA TO 50mA
toc13
toc14
50mV/div
(AC-
COUPLED)
50mV/div
(AC-
COUPLED)
VL1OUT
VL1OUT
IL1OUT
IL1OUT
10mA/div
50mA/div
10ms/div
10ms/div
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Typical Operating Characteristics (continued)
(V
= 1.2V, V
= 1.8V, V
= 1.2V, V
= 1.5V, V
= 1.0V, L = 1.5µH, C
= 10µF (effective), C = 1µF
CAP
BAT
BB1OUT
BB2OUT
L1OUT
L2OUT
BB_OUT
(effective), C
= 2.2µF (effective) no load on any rail, T = +25°C, unless otherwise noted.)
A
LDO
L2OUT LOAD TRANSIENT RESPONSE
L2OUT LOAD TRANSIENT RESPONSE
BB1OUT LOAD TRANSIENT RESPONSE
50μA TO 50mA
10μA TO 10mA
50μA TO 50mA
toc15
toc16
toc17
ILimSet = 600mA
50mV/div
(AC-
COUPLED)
50mV/div
VBB1OUT
(AC-
COUPLE
50mV/div
(AC-
COUPLED)
VL2OUT
VL2OUT
IL2OUT
IL2OUT
IBB1OUT
10mA/div
50mA/div
50mA/div
10ms/div
10ms/div
10ms/div
BB_OUT RIPPLE AND INDUCTOR CURRENT
BB1OUT LINE TRANSIENT RESPONSE
toc19
toc18
L = 2.2µH
VBATN = -1.8 to -1.2V
IBB1OUT = 10mA
10mV/div
(AC-
COUPLED)
VBB1OUT
10mV/div
VBB1OUT
(AC-
COUPLED)
10mV/div
(AC-
COUPLED)
VBB2OUT
VBATN
IL
500mA/div
500mV/div
20μs/div
10ms/div
BB_OUT RIPPLE AND INDUCTOR CURRENT
BB_OUT RIPPLE AND INDUCTOR CURRENT
toc20
toc21
L = 2.2µH
L = 2.2µH
10mV/div
(AC-
COUPLED)
10mV/div
(AC-
COUPLED)
VBB1OUT
VBB1OUT
10mV/div
(AC-
COUPLED)
10mV/div
(AC-
COUPLED)
VBB2OUT
VBB2OUT
IL
IL
500mA/div
500mA/div
10μs/div
4μs/div
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN )
MAX20310
1
2
3
4
+
GND
MPC
L2OUT
L1OUT
A
B
C
D
CAP
BB1
OUT
SDA
MON
BB2
OUT
KIN
SCL
MPO
KOUT
RST
BATN
LX
16 WLP 0.4mm pitch
1.63mm x 1.63mm
Bump Description
BUMP
A1
NAME
GND
FUNCTION
Ground/Battery Positive Terminal
LDO/Switch 2 Output
A2
L2OUT
L1OUT
CAP
A3
LDO/Switch 1 Output
A4
Internal Supply Decoupling. Connect a minimum 1µF of capacitance to GND.
Multipurpose Control Input
B1
MPC
2
B2
SDA
I C Serial Data
B3
MON
Monitor Multiplexer Output
B4
BB1OUT
KIN
Buck-Boost 1 Output
C1
C2
Key Input, Internally Pulled to GND. To signal active, short KIN to BATN.
2
SCL
I C Serial Clock
Multipurpose Output. Level shifted digital output for controlling devices referenced to the
negative battery terminal.
C3
MPO
C4
D1
D2
D3
D4
BB2OUT
KOUT
RST
Buck-Boost 2 Output
Key Output. Active-low, level-shifted button status output.
Reset Output. Active-low, open-drain output indicates completion of sequencer.
Battery Negative Terminal
BATN
LX
Inductor Switch Connection
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Functional Block Diagram
MAX20310
CAP
LX
BB1OUT
L1OUT
LDO
LDO
SIMO
BUCK-
BOOST
GND
BATN
BB2OUT
L2OUT
KIN
KOUT
MPO
MON
RST
MPC
SCL
SDA
CONTROL
supplied by the buck-boost outputs. As such, an LDO
cannot be enabled unless its corresponding switching
regulator output is active. The LDOs can be used as
switches to disconnect the quiescent loads of peripheral
systems, increasing battery life. The LDO outputs are
configurable from 0.5 to 3.65V in 50mV increments.
Detailed Description
Power Regulation
The MAX20310 features an ultra-low I SIMO buck-boost
switching regulator that provides two programmable volt-
Q
agle rails and two low-I LDOs. The regulators minimize
Q
quiescent current and operate on low input voltages. This
makes the MAX20310 ideal for applications powered by
singe-cell Alkaline, Zinc Air, or Silver Oxide batteries. All
regulator outputs are capable of being discharged through
a resistive load (passive discharge) when turned off. The
discharge mode is set by the PDsc bits in each regulator’s
configuration register.
Voltage Monitor Multiplexer
In addition to the four regulator outputs, the MAX20310
2
includes a voltage monitor multiplexer. The I C controlled
multiplexer connects the MON pin to any one of the
regulator outputs or to BATN. This provides access to the
different voltage rails in the device for ADC measurements.
An inverting amplifier buffers the BATN channel in order
to allow a positive, single-ended ADC to measure the
voltage.
Switching Regulator
In order to maximize efficiency, the switching regulator
is implemented with an inverting buck-boost topology.
Referencing the battery’s positive terminal to ground
configures the battery as a negative supply and the
switching regulator output is positive. The switching
regulator operates at supplies from -2.0V down to -0.7V,
but requires -0.8V to start up. The outputs are independently
configurable in 50mV increments.
Multipurpose Control Input
The MAX20310 includes a multipurpose control (MPC)
pin that can control various functions inside the part
based on the buck-boost and LDO configuration and
sequence register settings. For devices with at least one
BBst_Seq[2:0] or LDO_Seq[2:0] field set by the factory
to 101 (enabled by MPC, active-low) or 110 (enabled
by MPC, active-high) according to Table 19, the MPC
pin can be configured to control the multipurpose output
(MPO) pin for level-shifting to the battery voltage. See the
Multipurpose Output section below for details. If the MPC
pin is unused, it must be tied to GND.
LDO
For applications that require lower noise supplies, or
simply need additional regulated voltages, the MAX20310
includes two LDO regulators. In normal operation, each
LDO can source up to 50mA. The LDO inputs are
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the MPC pin, regardless of polarity. Table 1 below shows
the truth table associated with such devices. Devices with
none of the one BBst_Seq[2:0] or LDO_Seq[2:0] fields
set by the factory to 101 (enabled by MPC, active-low)
or 110 (enabled by MPC, active-high) allow the MPO
Multipurpose Output
In addition to the MPC pin, the MAX20310 also features
a multipurpose output (MPO). The MPO pin can be
configured to pull down to BATN, to pull up to GND, to
pullup/down (push/pull), or be disabled (no pull). On
devices with at least one BBst_Seq[2:0] or LDO_Seq[2:0]
field set by the factory to 101 (enabled by MPC, active-
low) or 110 (enabled by MPC, active-high), as detailed
in table 19, the MPOCfg register allows the state of the
2
output to be controlled by I C command only. Table 2
below shows the truth table associated with such devices.
An example implementation is included in Figure 1 to
show how to use this pin to control an external regulator
powered directly from the battery.
2
MPO pin to be controlled either by I C command or by
Table 1. MPO Truth Table for Devices with One or More BBst_Seq[2:0]/LDO_Seq[2:0]
Field Set to 101 or 110 by the Factory
MPOPull[1:0]
MPOEn[1:0]
MPC
X
X
X
0
OUTPUT STATE
High-Impedance
High-Impedance
Pulled to BATN
Pulled to BATN
High-Impedance
High-Impedance
Pulled to BATN
Pulled to GND
High-Impedance
High-Impedance
Pulled to GND
Pulled to GND
High-Impedance
Pulled to GND
Pulled to BATN
Pulled to BATN
Pulled to GND
Pulled to GND
Pulled to BATN
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
X
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
1
0
1
X
X
0
1
0
1
X
X
0
1
0
1
Table 2. MPO Truth Table for Devices with None of the BBst_Seq[2:0]/LDO_Seq[2:0]
Fields Set to 101 or 110 by the Factory
MPOPull[1:0]
MPOEn[1:0]
MPC
OUTPUT STATE
High-Impedance
High-Impedance
Pulled to BATN
Pulled to GND
High-Impedance
Pulled to GND
Pulled to BATN
0
0
0
1
1
1
1
0
1
1
0
0
1
1
X
0
0
0
0
0
0
X
0
1
0
1
0
1
X
X
X
X
X
X
X
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Ultra-Low Quiescent Current PMIC with
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The list of settings and corresponding actions is shown
in Table 18. A button press always wakes up the device,
and the factory configuration determines other behavior.
Power On/Off and Reset Control
The MAX20310 is intended for use in small battery-
powered applications. It includes an off mode to minimize
drain on the battery. In the off mode, all outputs are
disabled and the part waits until the KIN input goes active
to wake the device. The KIN input is internally pulled
to GND and needs to be shorted to BATN to wake the
device. An open-drain buffered copy of the state of KIN
is available at KOUT allowing the system to monitor the
status of the button. When the device is powered on, each
function can be automatically enabled by a sequencing
Reverse Battery Protection
Some applications use batteries like AAA’s that do not
have mechanical reverse installation protection. In such
applications, an optional external nMOSFET and resistor
connected as shown in Figure 2 provide reverse battery
protection for the system. In normal operation, the 100Ω
resistor slows the charging of C at startup until V
-
IN
CAP
V
exceeds the threshold of the external MOSFET.
BATN
2
controller or remain off until an I C command enables
Thereafter, the circuit functions nominally. In the case of
battery reversal, the 100Ω resistor limits the current from
the battery and protects the downstream system.
it. This behavior is determined by the factory settings. A
button monitor is present on the MAX20310 and can
produce different actions for long or short button presses.
+1.8V +1.5V +1.2V +1.2V
VAN
VDD VSW
V
IO
MAX20310
CAP
LX
BB1OUT
L1OUT
1µF
LDO
LDO
SIMO
BUCK-
BOOST
GND
BB2OUT
L2OUT
+1.2V
BATN
10µF 2.2µF 10µF 2.2µF
10µH
KIN
KOUT
MPO
MON
RST
MPC
SCL
SDA
MAX1724
BATT
SHDN
LX
CONTROL
VOUT
GND
+5V
+3.8V
Figure 1. Controlling an External Regulator with MPO
L
MAX20310
LX
BB1OUT
L1OUT
GND
BB2OUT
100Ω
L2OUT
CAP
BATN
Figure 2. Reverse Battery Protection Using an External MOSFET
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Power Sequencing
Additional Voltage Regulators
The sequencing of the voltage regulators during power-on
is configurable. Regulators can be configured to turn on
at one of four points during the power on process. The
four points are: 100ms after the power-on event, after
the RST signal is released, or at two points in between.
The two points are fixed proportionally to the duration
of the Power-On Reset (POR) process, but the overall
time of the reset delay is configurable (refer to PwrCfg
register). The timing relationship is presented graphically
in Figure 3. Additionally, the regulators are controllable by
In applications with additional voltage regulators operat-
ing directly from the battery, careful consideration must
be given to battery and system power domains. Due to
the negative battery implementation of the MAX20310,
the common node for the system power domain (GND) is
connected to the positive terminal of the battery.
Regulators using the battery as a positive supply should
connect BATN as the local ground and GND as the input
supply. However, the output must always be referenced
to the positive terminal of the battery (GND). This causes
the output voltage of the regulator, referenced to GND, to
2
the sequencer, an input pin, or I C command after reset
is released. Note that the LDOs will not turn on until the
associated switching output is also enabled.
equal V
– V . As the battery discharges, this volt-
BAT
OUT
age might change over time.
2
I C Interface
For example, in Figure 1, the external MAX1724 step-
up converter produces 5V with respect to the regulator
ground (BATN). Because the battery voltage is 1.2V, the
output voltage in the system power domain is 3.8V. Due
to the relative flatness of the discharge curves for Silver-
Oxide, Zinc-Air, and other common coin cell batteries, the
challenges associated with a changing reference node
are reduced. However, designs should account for some
variation of the BATN node.
2
The MAX20310 uses the two-wire I C interface to
communicate with a host microcontroller. The configuration
settings and status information provided through this
interface are detailed in the register descriptions. The
slave address is 0x50 for writes and 0x51 for reads.
Applications Information
Always-On Devices
2
I C Interface
The MAX20310 contains an I C-compatible interface
Due to its low power consumption, the MAX20310 is
ideal for always-on applications. Products targeting these
always-on, buttonless applications should select a ver-
sion of the MAX20310 with PwrCfgMd[1:0] = 00 and con-
nect the KIN input to BATN as shown in Figure 4. This
PwrCfgMd setting configures a KIN press to only turn on
the device. When a fresh battery is inserted, or when a
battery tab used during product shelf life is removed, KIN
is pulled to BATN and the device turns on.
2
for data communication with a host controller (SCL and
SDA). The interface supports a clock frequency of up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Start, Stop, and Repeated Start Conditions
2
When writing to the MAX20310 using I C, the master
sends a START condition (S) followed by the MAX20310
MAX20310
GND
BATN
KIN
Figure 4. KIN Connected to BATN for Always-On Applications
Figure 3. Reset Sequence Programming
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2
I C address. After the address, the master sends the
STOP condition (P) to relinquish control of the bus, or
a REPEATED START condition (Sr) to communicate to
another I C slave. See Figure 5.
register address of the register that is to be programmed.
The master then ends communication by issuing a
2
Slave Address
Set the Read/Write bit high to configure the MAX20310
to read mode. Set the Read/Write bit low to configure the
MAX20310 to write mode. The address is the first byte
of information sent to the MAX20310 after the START
condition.
S
Sr
P
SCL
SDA
Bit Transfer
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered control
signals (see the START, STOP and REPEATED START
Conditions section). Both SDA and SCL remain high when
the bus is not active.
2
Figure 5. I C START, STOP and REPEATED START
Conditions
WRITE SINGLE BYTE
DEVICE SLAVE ADDRESS-W
S
A
A
REGISTER ADDRESS
A
P
8 data bits
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 6. Write Byte Sequence
BURST WRITE
DEVICE SLAVE ADDRESS-W
S
A
A
A
A
A
REGISTER ADDRESS
8 DATA BITS - 2
8 DATA BITS - 1
………………
P
8 DATA BITS - N
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 7. Burst Write Sequence
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The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
Single-Byte Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 6). The following
procedure describes the single byte write operation:
The master sends 8 data bits
The slave asserts an ACK on the data line
Repeat 6 and 7 N-1 times
The master sends a START condition
The master sends the 7-bit slave address plus a write bit
(low)
The master generates a STOP condition
Single-Byte Read
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 8). The following procedure describes the
single byte read operation:
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
The master sends 8 data bits
The master sends a START condition
The slave asserts an ACK on the data line
The master generates a STOP condition
The master sends the 7-bit slave address plus a write bit
(low)
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
Burst Write
In this operation, the master sends an address and mul-
tiple data bytes to the slave device (Figure 7). The slave
device automatically increments the register address after
each data byte is sent, unless the register being accessed
is 0x00, in which case the register address remains the
same. The following procedure describes the burst write
operation:
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
The master sends a REPEATED START condition
The master sends the 7-bit slave address plus a read bit
(high)
The addressed slave asserts an ACK on the data line
The slave sends 8 data bits
The master sends a START condition
The master sends the 7-bit slave address plus a write bit
(low)
The master asserts a NACK on the data line
The master generates a STOP condition
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
READ SINGLE BYTE
S
REGISTER ADDRESS
8 DATA BITS
A
DEVICE SLAVE ADDRESS-W
A
A
DEVICE SLAVE ADDRESS-R
P
Sr
NA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 8. Read Byte Sequence
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BURST READ
A
S
DEVICE SLAVE ADDRESS-W
REGISTER ADDRESS
8 DATA BITS - 1
A
A
Sr
DEVICE SLAVE ADDRESS-R
8 DATA BITS - 2
A
A
A
8 DATA BITS - 3
8 DATA BITS - N
………………
P
NA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 9. Burst Read Sequence
Burst Read
S
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (Figure 9). The following procedure describes the
burst byte read operation:
SCL
SDA
1
2
8
9
NOT ACKNOWLEDGE
The master sends a START condition
The master sends the 7-bit slave address plus a write bit
(low)
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
ACKNOWLEDGE
Figure 10. Acknowledge
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
Acknowledge Bits
The master sends a REPEATED START condition
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX20310 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see Figure 10). To generate a NACK,
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
The master sends the 7-bit slave address plus a read bit
(high)
The slave asserts an ACK on the data line
The slave sends 8 data bits
The master asserts an ACK on the data line
Repeat 9 and 10 N-2 times
The slave sends the last 8 data bits
The master asserts a NACK on the data line
The master generates a STOP condition
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2
I C Register Descriptions
Table 3. ChipId Register (0x00)
ADDRESS
0x00 (Read-Only)
BIT
7
6
5
4
3
2
2
2
1
1
1
0
0
0
NAME
ChipId[7:0]
ChipId[7:0] bits show information about the version of the MAX20310
ChipId[7:0]
Table 4. ChipRev Register (0x01)
ADDRESS
0x01 (Read-Only)
BIT
7
6
5
4
3
NAME
ChipRev[7:0]
ChipRev shows information about the revision of the MAX20310 silicon
ChipRev[7:0]
Table 5. BBstCfg Register (0x02)
ADDRESS
0x02 (Read, Write)
BIT
7
6
-
5
-
4
-
3
NAME
BBstDmpEn
ILimSet[1:0]
FetScale[1:0]
Buck-Boost Dump Enable
This enables a dump switch to reduce LX oscillations
0: Switch disabled
BBstDmpEn
1: Switch enabled
Buck-Boost Peak Current Limit Setting
Sets the peak current supplied by the buck-boost regulator
00: 300mA
01: 400mA
10: 500mA
11: 600mA
ILimSet[1:0]
FetScale
Scales the switching FETs to optimize efficiency at a given load
00: 28%
01: 60%
10: 80%
11: 100%
FetScale[1:0]
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Table 6. BBst1VSet Register (0x04)
ADDRESS
0x04 (Read, Write)
BIT
7
-
6
-
5
4
3
2
1
0
NAME
BBst1VSet[5:0]
Buck-Boost 1 Output Voltage Setting
0.90V to 4.05V, linear scale, 50mV increments
000000 = 0.90V
000001 = 0.95V
…
BBst1VSet[5:0]
111110 = 4.00V
111111 = 4.05V
Table 7. BBst1Cfg Register (0x05)
ADDRESS
0x05 (Read, Write)
BIT
7
6
5
4
3
BBst1RmpDis
2
1
0
NAME
BBst1En[1:0]
BBst1PDsc
—
—
—
—
Buck-Boost 1 Enable
00: Disabled
BBst1En[1:0]
01: Enabled
10: Controlled by MPC (active low)
11: Controlled by MPC (active high)
Buck-Boost 1 Passive Discharge
0: Disabled
BBst1PDsc
1: Enabled when output is off
Disable the ramped output of Buck-Boost output 1. If disabled, the BBst1VSet value is immediately
applied to the output.
1: Immediate transition to set value
0: Ramp to set value mode
BBst1RmpDis
Table 8. BBst2VSet Register (0x06)
ADDRESS
0x06 (Read, Write)
BIT
7
-
6
-
5
4
3
2
1
0
NAME
BBst2VSet[5:0]
Buck-Boost 2 Output Voltage Setting
0.90V to 4.05V, linear scale, 50mV increments
000000 = 0.90V
000001 = 0.95V
…
BBst2VSet[5:0]
111110 = 4.00V
111111 = 4.05V
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Table 9. BBst2Cfg Register (0x07)
ADDRESS
0x07 (Read, Write)
BIT
7
6
5
4
-
3
2
-
1
-
0
-
NAME
BBst2En[1:0]
BBst2PDsc
BBst2RmpDis
Buck-Boost 2 Output Enable
00: Disabled
BBst2En[1:0]
01: Enabled
10: Controlled by MPC (active-low)
11: Controlled by MPC (active-high)
Buck-Boost 2 Passive Discharge
0: Disabled
BBst2PDsc
1: Enabled when output is off
Disable the ramped output of Buck-Boost output 2. If disabled, the BBst2VSet value is immediately applied to
the output.
1: Immediate transition to set value
0: Ramp to set value mode
BBst2RmpDis
Table 10. LDO1VSet Register (0x08)
ADDRESS
0x08 (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
—
—
LDO1VSet[5:0]
LDO 1 Output Voltage Setting
0.50V to 3.65V, 50mV increments
000000 = 0.50V
000001 = 0.55V
…
LDO1VSet[5:0]
111110 = 3.60V
111111 = 3.65V
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Table 11. LDO1Cfg Register (0x09)
ADDRESS
0x09 (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
LDO1En[1:0]
LDO1PDsc
LDO1ADsc
—
—
—
LDO1Mode
LDO 1 Output Enable
00: Disabled
LDO1En[1:0]
01: Enabled
10: Controlled by MPC (active-low)
11: Controlled by MPC (active-high)
LDO 1 Passive Discharge
0: Disabled
1: Enabled when output is off
LDO1PDsc
LDO1Mode
LDO 1 Mode
Configure LDO1 as an LDO or a load switch
0: LDO
1: Load Switch
Table 12. LDO2VSet Register (0x0A)
ADDRESS
0x0A (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
—
—
LDO2VSet[5:0]
LDO 2 Output Voltage Setting
0.50V to 3.65V, 50mV increments
000000 = 0.50V
000001 = 0.55V
…
LDO2VSet[5:0]
111110 = 3.60V
111111 = 3.65V
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Table 13. LDO2Cfg Register (0x0B)
ADDRESS
0x0B (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
LDO2En[1:0]
LDO2PDsc
—
—
—
—
LDO2Mode
LDO 2 Output Enable
00: Disabled
LDO2En[1:0]
01: Enabled
10: Controlled by MPC (active-low)
11: Controlled by MPC (active-high)
LDO 2 Passive Discharge
0: Disabled
1: Enabled when output is off
LDO2PDsc
LDO2Mode
LDO 2 Mode
Configure LDO2 as an LDO or a load switch
0: LDO
1: Load Switch
Table 14. MonCfg Register (0x0C)
ADDRESS
0x0C (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
—
—
—
—
MonHiZ
MonSel[2:0]
Monitor Off Mode Condition
MonHiZ
0: 100kΩ pulldown when disabled
1: High impedance when disabled
Monitor Pin Source Selection
000: Disabled
001: BB1OUT selected
010: BB2OUT selected
011: L1OUT selected
100: L2OUT selected
101: BATIN selected
110: CAP selected
MonSel[2:0]
111: Reserved
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Table 15. MPOCfg Register (0x0D)
ADDRESS
0x0D (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
MPOEn[1:0]
—
—
—
—
MPOPull[1:0]
Multipurpose Output Enable
00: Pull up (to GND)
MPOEn[1:0]
MPOPull[1:0]
01: Pull down (to BATN)
10: Pull up when MPC high, pull down when MPC low
11: Pull up when MPC low, pull down when MPC high
Multipurpose Output Pull Mode
00: Disabled
01: Pull down (to BATN)
10: Pull up (to GND)
11: Pull up/down (Push/Pull)
Table 16. PwrCmd Register (0x0E)
ADDRESS
0x0E (Read, Write)
BIT
7
6
5
4
3
2
1
0
NAME
PwrCmd[7:0]
Power Command Register
10110010: Power Off - Turn off and stay off
11000011: Hard Reset - Turn off and return back on
PwrCmd[7:0]
11010100: Soft Reset - Pulse RST low
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Table 17. Status Register (0x0F)
ADDRESS
0x0F (Read-Only)
BIT
7
6
5
4
3
2
1
0
NAME
LDO2UVLO
LDO1UVLO
LDO2Thm
LDO1Thm
LDO2CrMd
LDO1CrMd
KINSts MPCSts
LDO 2 Undervoltage Lockout Status
0: Normal
LDO2UVLO
1: Undervoltage
LDO 1 Undervoltage Lockout Status
0: Normal
1: Undervoltage
LDO1UVLO
LDO2Thm
LDO1Thm
LDO2CrMd
LDO1CrMd
KINSts
LDO 2 Thermal Limit Status
0: Normal
1: Thermal shutdown
LDO 1 Thermal Limit Status
0: Normal
1: Thermal shutdown
LDO 2 Current Mode
0: LDO
1: Switch
LDO 1 Current Mode
0: LDO
1: Switch
KIN Status
0: Low
1: High
Multi-Purpose Control Status
MPCSts
0: Low
1: High
Maxim Integrated
│ 24
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Table 18. PwrCfg Register (0x10)
ADDRESS
0x10 (Read-Only)
BIT
7
6
5
4
3
2
1
0
NAME
PwrCfgMd[1:0]
GPasDsc
—
—
—
BootDly[1:0]
Power Configuration Mode
A short button press will always wake the device from the off state.
2
00: Button only wakes device (can be turned off by I C command)
PwrCfgMd[1:0]
01: Long button press generates reset pulse
10: Long button press power cycles and reboots device
11: Long button press turns device off
Global Passive Discharge
GPasDsc
0: Passive discharge disabled in off state
1: Passive discharged enabled in off state
Boot Sequence Delay (t
00: 80ms
)
RST
BootDly[1:0]
01: 120ms
10: 160ms
11: 200ms
Table 19. BBstSeq Register (0x11)
ADDRESS
0x11 (Read-Only)
BIT
7
6
5
4
3
2
1
BBst1Seq[2:0]
0
NAME
—
BBst2Seq[2:0]
—
Buck-Boost 2 Sequencing Configuration
000: Disabled
001: Reserved
010: Enabled at 0% of power on delay
011: Enabled at 25% of power on delay
100: Enabled at 50% of power on delay
101: Enabled by MPC (active low)
110: Enabled by MPC (active high)
BBst2Seq[2:0]
111: Controlled by BBst2En[1:0] after 100% of power on delay
Buck-Boost 2 Sequencing Configuration
000: Disabled
001: Reserved
010: Enabled at 0% of power on delay
011: Enabled at 25% of power on delay
100: Enabled at 50% of power on delay
101: Enabled by MPC (active low)
110: Enabled by MPC (active high)
111: Controlled by BBst1En[1:0] after 100% of power on delay
BBst1Seq[2:0]
Maxim Integrated
│ 25
www.maximintegrated.com
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Table 20. LDOSeq Register (0x12)
ADDRESS
0x12 (Read-Only)
BIT
7
6
5
4
3
2
1
0
NAME
—
LDO2Seq[2:0]
—
LDO1Seq[2:0]
LDO 2 Sequencing Configuration
000: Disabled
001: Reserved
010: Enabled at 0% of power on delay
011: Enabled at 25% of power on delay
100: Enabled at 50% of power on delay
101: Enabled by MPC (active low)
110: Enabled by MPC (active high)
LDO2Seq[2:0]
111: Controlled by LDO2En[1:0] after 100% of power on delay
LDO 1 Sequencing Configuration
000: Disabled
001: Reserved
010: Enabled at 0% of power on delay
011: Enabled at 25% of power on delay
100: Enabled at 50% of power on delay
101: Enabled by MPC (active low)
110: Enabled by MPC (active high)
111: Controlled by LDO1En[1:0] after 100% of power on delay
LDO1Seq[2:0]
Maxim Integrated
│ 26
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Table 21. Register Bit Default Values
REGISTER BITS
MAX20310A
MAX20310B
MAX20310C
MAX20310D
MAX20310E
ILimSet[1:0]
FetScale[1:0]
LDO1En[1:0]
LDO1VSet[5:0]
LDO2En[1:0]
LDO2VSet[5:0]
BBst1En[1:0]
BBst1VSet[5:0]
BBst2En[1:0]
BBst2VSet[5:0]
BBstDmpEn
LDO2Mode
400mA
100%
600mA
100%
300mA
80%
300mA
80%
300mA
80%
Disabled
1.5V
Disabled
0.5V
Disabled
1.5V
Disabled
3.0V
Disabled
1.2V
Disabled
1.0V
Disabled
1.8V
Disabled
1.0V
Disabled
1.2V
Disabled
1.0V
Disabled
1.8V
Disabled
3.0V
Enabled
2.5V
Enabled
3.3V
Enabled
1.8V
Disabled
1.2V
Disabled
2.1V
Disabled
1.2V
Disabled
1.5V
Disabled
1.2V
Disabled
Switch
LDO
Disabled
LDO
Disabled
LDO
Disabled
LDO
Disabled
LDO
LDO1Mode
Switch
GND
LDO
LDO
LDO
MPOEn[1:0]
PullMode[1:0]
PwrCfgMd[1:0]
GPasDsc
GND
GND
GND
GND
Disabled
ON/off
Disabled
120ms
Disabled
ON
Disabled
Hard Reset
Enabled
200ms
Disabled
Soft Reset
Enabled
160ms
Disabled
On/Off
Enabled
80ms
Disabled
80ms
BootDly[1:0]
2
2
2
I C after 100%
boot
I C after 100%
boot
I C after 100%
boot
BBst2Seq[2:0]
BBst1Seq[2:0]
LDO2Seq[2:0]
LDO1Seq[2:0]
0% boot
0% boot
25% boot
0% boot
2
2
2
I C after 100%
I C after 100%
I C after 100%
boot
boot
boot
2
2
2
2
I C after 100%
boot
I C after 100%
I C after 100%
I C after 100%
50% boot
boot
boot
boot
2
2
2
2
2
I C after 100%
I C after 100%
boot
I C after 100%
I C after 100%
I C after 100%
boot
boot
boot
boot
Maxim Integrated
│ 27
www.maximintegrated.com
MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Table 22. Register Default Values
DEFAULT VALUES
REGISTER
ADDRESS
REGISTER
NAME
MAX20310A
0x00
MAX20310B
0x00
MAX20310C
0x00
MAX20310D
0x00
MAX20310E
0x00
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0D
0x10
0x11
0x12
ChipId
ChipRev
BBstCfg
0x00
0x00
0x00
0x00
0x00
0x07
0x0F
0x2A
0x10
0x02
0x02
0x02
BBst1VSet
BBst1VCfg
BBst2VSet
BBst2VCfg
LDO1Vset
LDO1Cfg
LDO2Vset
LDO2Cfg
MPOCfg
PwrCfg
0x12
0x20
0x30
0x12
0x10
0x60
0x60
0x60
0x06
0x18
0x06
0x0C
0x20
0x06
0x10
0x10
0x20
0x20
0x14
0x00
0x14
0x32
0x0E
0x20
0x10
0x11
0x20
0x20
0x0A
0x11
0x1A
0x10
0x0A
0x20
0x0E
0x20
0x0A
0x20
0x00
0x00
0x00
0x00
0x00
0xD1
0x22
0x10
0xA3
0x77
0x62
0xE0
0x77
BBstSeq
LDOSeq
0x32
0x77
0x77
0x47
0x77
0x77
0x77
Maxim Integrated
│ 28
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Typical Application Circuit
+1.8V
+3.3V
+1.2V
ANALOG
I/O
MAX20310
LX
L1OUT
B1OUT
B2OUT
L2OUT
V
V
V
DD18
DDA
RTC
LDO/SW
BUCK-BOOST
LDO/SW
2.2µF
LED
10µF
GND
CORE
10µF
V
DD12
+0.7V
TO
+2.0V
LOAD
SWITCH
BLE
BATN
2.2µF
MAX32620
KIN
MON
SCL
SDA
CAP
ADC
SCL
SDA
MPO
MPC
RST
CONTROL
1µF
RST
GPO
GPI
Note: The capacitor values shown reflect an effective capacitance. Derate capacitors appropriately according to specific
application requirements.
Ordering Information
Chip Information
PROCESS: BiCMOS
PIN-
TOP
PART
TEMP RANGE
PACKAGE MARK
MAX20310AEWE+
-40°C to +85°C
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
16 WLP
AAK
AAK
AAK
AAK
AAK
AAK
AAK
AAK
AAK
AAK
MAX20310AEWE+T -40°C to +85°C
MAX20310BEWE+ -40°C to +85°C
MAX20310BEWE+T -40°C to +85°C
MAX20310CEWE+ -40°C to +85°C
MAX20310CEWE+T -40°C to +85°C
MAX20310DEWE+ -40°C to +85°C
MAX20310DEWE+T -40°C to +85°C
MAX20310EEWE+
-40°C to +85°C
MAX20310EEWE+T -40°C to +85°C
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Maxim Integrated
│ 29
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MAX20310
Ultra-Low Quiescent Current PMIC with
SIMO Buck-Boost for Wearable Applications
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
9/16
Initial release
—
Added future products. Updated Typical Operating Characteristics, General
Description, Benefits and Features, Power Regulation, Power Sequencing
sections, and Typical Application Circuit. Added Always-On Devices and
Additional Voltage Regulators sections. Replaced Figure 1, added new Figure 4
and renumbered Figures 5-10. Updated Table 5 and replaced Tables 21-22.
1, 6–8
10, 12–16
18, 26–28
1
2
5/17
3/18
2
Updated the Detailed Description section, I C Register Map, and Register
10, 17,
27, 29
Bit Default Values table. Replaced Typical Application Circuit figure. Updated
Ordering Information to show that the MAX20310A-E are released products.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 30
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