MAX20335DEWX [MAXIM]
PMIC with Ultra-Low IQ Voltage Regulators and Battery Chargers for Small Lithium Ion Systems;
| 型号： | MAX20335DEWX |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PMIC with Ultra-Low IQ Voltage Regulators and Battery Chargers for Small Lithium Ion Systems 电池 集成电源管理电路 |
| 文件： | 总67页 (文件大小：1615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for production status of specific part numbers.
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
General Description
Benefits and Features
● Extend System Use Time Between Battery Charging
The MAX20335 is a battery-charge-management solution
ideal for low-power wearable applications. The device
includes a linear battery charger with a smart power
selector and several power-optimized peripherals. The
MAX20335 features two ultra-low quiescent current buck
regulators and three ultra-low quiescent current low-dropout
(LDO) linear regulators, providing up to five regulated
voltages, each with an ultra-low quiescent current, allows
designers to minimize power consumption and extend
battery life in 24/7 operation devices, such as those in the
wearable market.
• Dual Ultra-Low-I 200mA Buck Regulators
Q
• Output Programmable from 0.7V to 2.275V and
0.7V to 3.85V
• 0.9μA (typ) Quiescent Current (Buck 1)
• Optional Fixed Peak-Current Mode to Optimize
Ripple Frequency in Noise-Sensitive Applications
• Three Ultra-Low-I 100mA LDOs
Q
• LDO1
• Output Programmable from 0.8V to 3.6V
• 0.6μA (typ) Quiescent Current
• 2.7V to 5.5V Input with Dedicated Pin
• LDO2/3
The battery charger features a smart power selector that
allows operation on a dead battery when connected to a
power source. To avoid overloading a power adapter, the
input current to the smart power selector is limited based
• Output Programmable from 0.9V to 4V
• 1μA (typ) Quiescent Current
• 1.71V to 5.5V Input with Dedicated Pin
● Easy-to-Implement Li+ Battery Charging
• Smart Power Selector
• 28V/-5.5V Tolerant Input
• Thermistor Monitor
● Minimize Solution Footprint Through High Integration
• Provides Five Regulated Voltage Rails
• Switch Mode Option on Each LDO
● Optimize System Control
2
on an I C register setting. If the charger power source
is unable to supply the entire system load, the smart
power control circuit supplements the system load with
current from the battery. The charger also supports
temperature dependent charge currents.
The two synchronous, high-efficiency step-down buck
regulators feature a variable frequency mode for increased
efficiency during light-load operation. The output voltage
2
of these regulators can be programmed through I C
• Monitors Pushbutton for Ultra-Low Power Mode
• Power-On Reset Delay and Voltage Sequencing
• On-Chip Voltage Monitor Multiplexer
with the default preconfigured. The buck regulators can
support dynamic voltage scaling to further improve
system power consumption.
Applications
● Wearable Electronics
● Fitness Monitors
● Rechargeable IoT devices
The three configurable LDOs each have a dedicated
input pin. Each LDO regulator output voltage can be
2
programmed through I C with the default preconfigured.
The linear regulators can also be configured to operate
as power switches that may be used to disconnect the
quiescent load of the system peripherals.
The MAX20335 features a programmable power controller
that allows the device to be configured for applications
that require the device be in a true-off, or always-on,
state. The controller also provides a delayed reset signal
and voltage sequencing.
Ordering Information appears at end of data sheet.
The MAX20335 is available in a 36-bump, 0.4mm pitch,
2.72mm x 2.47mm wafer-level package (WLP).
19-100288; Rev 6 6/21
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power On/Off and Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Smart Power Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal Current Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
System Load Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Fast-Charge Current Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Thermistor Monitoring with Charger Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2
I C Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Thermistor Monitoring with Charger Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2
I C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Start, Stop, And Repeated Start Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Single-Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Acknowledge Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2
I C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2
I C Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Maxim Integrated
│ 2
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
TABLE OF CONTENTS (continued)
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
PCB Layout and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LIST OF FIGURES
Figure 1. Power Function Input Control Modes Flow Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2a. Power-On Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2b. Power-On Sequencing Without Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 3. Smart Power Selector Current/Voltage Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4a. Charging Behavior Using Thermistor Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4b. Charging Behavior Using JEITA Monitoring 1 and 2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 5a. Charger State Diagram (Thermistor Monitoring with Charger Shutdown) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5b. Battery Charger State Diagram (JEITA Monitoring with Charger Shutdown). . . . . . . . . . . . . . . . . . . . . . . 37
2
Figure 6. I C START, STOP and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. Write Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 8. Burst Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 9. Read Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Burst Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LIST OF TABLES
Table 1. Power Function Input Control Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 2. Thermistor Monitoring/JEITA Monitoring Enable Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
Table 3. I C Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4. ChipId Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5. ChipRev Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 6. StatusA Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7. StatusB Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maxim Integrated
│ 3
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
LIST OF TABLES (continued)
Table 8. StatusC Register (0x04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9. IntA Register (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. IntB Register (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11. IntMaskA Register (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 12. IntMaskB Register (0x08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 13. ILimCntl Register (0x09). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14. ChgCntlA Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 15. ChgCntlB Register (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 16. ChTmr Register (0x0C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 17. Buck1Cfg Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 18. Buck1VSet Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 19. Buck2Cfg Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 20. Buck2VSet Register (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 21. Buck1/2ISet Register (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 22. LDO1Cfg Register (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23. LDO1VSet Register (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 24. LDO2Cfg Register (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 25. LDO2VSet Register (0x15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 26. LDO3Cfg Register (0x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 27. LDO3VSet Register (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 28. ThrmCfg Register (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 29. ThrmCfg Register (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 30. MONCfg Register (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 31. BootCfg Register (0x1B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. PinStat Register (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 33. Buck1/2Extra Control Register (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 34. PwrCfg Register (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 35. PwrCmd Register (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 36. Suggested Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 37. Output Capacitor Values* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 38. Register Bit Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 39. Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Maxim Integrated
│ 4
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Typical Application Circuit
MAX20335
CAP
SET
Li+ BATTERY
THM
CHARGER WITH
SMART POWER
SELECTOR
CHGIN
GND
BAT
EXT
1µF
1µF
1µF
VIO
VSYS
10µF
10µF
(*)
SYS
SCL
SDA
INT
VB1
SCL
SDA
B1OUT
B1LX
2.2µH
BUCK 1
INT
VB2
MPC0
MPC0
B2OUT
B2LX
CONTROL
MPC1
PFN2
RST
BUCK 2
10µF
1µF
2.2µH
VSYS
MPC1
PFN2
RST
L1IN
LDO/
PFN1
VL1
SWITCH 1
L1OUT
VSYS
LED
VSYS
VSYS
L2IN
LDO/
VL2
VL3
1µF
1µF
SWITCH 2
L2OUT
MON
MUX/
DIVIDER
MON
L3IN
LDO/
SWITCH 3
L3OUT
* OPTIONAL EXTERNAL FET
Maxim Integrated
│ 5
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Absolute Maximum Ratings
(Voltages referenced to GND.)
SDA, SCL, THM, RST, SYS, PFN1, PFN2,
MPC0, MPC1, INT, MON, BAT, LED,
L1IN, L2IN, L3IN.............................................. -0.3V to +6.0V
Continuous Current into CHGIN, BAT, SYS ................±1000mA
Continuous Current into any other terminal ..................±100mA
Continuous Power Dissipation (multilayer board at +70°C):
6 x 6 Array 36-Bump 2.72mm x 2.47mm
B1LX, B2LX, B1OUT, B2OUT, EXT ...... -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
0.4mm Pitch WLP (derate 21.70mW/°C).......................1.74W
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
SYS
L1IN
L2IN
L3IN
L1OUT................................................... -0.3V to (V
L2OUT................................................... -0.3V to (V
L3OUT................................................... -0.3V to (V
CHGIN .................................................................... -6V to +30V
CAP ................................... -0.3V to min (|V | + 0.3V, +6V)
CHGIN
SET .......................................................... -0.3V to V
+ 0.3V
BAT
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
PACKAGE TYPE: 36 WLP
Package Code
W362D2+1
Outline Number
21-0897
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
46°C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 6
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL SUPPLY CURRENT (L_IN Connected to SYS)
All functions disabled
Power on, V = 5V
0.26
CHGIN
Charger Input Current
I
mA
SYS switch closed, buck regulators
CHG
1.5
1.7
4.3
enabled, LDO1 enabled, I = 0A,
SYS
I
= 0A, I
= 0A
B_OUT
L_OUT
Power off, V
= 0V,
CHGIN
0.96
2.8
SYS switch open
Power on, V
= 0V
CHGIN
SYS switch closed, 2x buck
regulators enabled, LDOs disabled.
I
= 0A, I
= 0A
SYS
B_OUT
Power on, V
= 0V SYS switch
CHGIN
BAT Input Current
I
µA
closed, 2x buck regulators enabled,
BAT
3.5
5.2
7
LDO1 enabled, I = 0A, I
=
B_OUT
SYS
0A, I
= 0A
L_OUT
Power on, V
= 0V
CHGIN
SYS switch closed, 2x buck
regulators enabled, 3x LDOs
enabled, I = 0A, I = 0A,
SYS
B_OUT
I
= 0A
L_OUT
BUCK REGULATOR 1
(V
= +3.7V, L = 2.2µH, C = 2.2µF, V
= 1.2V)
SYS
B1OUT
Input Voltage
V
Input voltage = V
2.7
0.7
5.5
V
V
IN_BUCK1
SYS
Output Voltage
V
25mV step resolution
2.275
OUT_BUCK1
Note: For V < UVLO ZC is
OUT
Output UVLO Voltage
V
imposed. Falling edge (75mV typ
0.35
0.55
V
UVLO_BUCK1
hysteresis)
Buck enabled, I
= 0mA,
= 1.2V
B1OUT
Quiescent Supply
Current
I
V
= 3.7V, V
0.9
1.1
60
1.3
µA
mA
µA
Q_BUCK1
SYS
B1OUT
(Note 2)
Dropout Quiescent
Supply Current
I
= 0mA, (V
– V
)
B1OUT
SYS
OUT
I
QDO_BUCK1
≤ 0.1V
Shutdown Supply
Current with Active
Discharge Enabled
Buck1 disabled. Falling edge (75mV typ
hysterisis)
I
SD_BUCK1
Output Accuracy
ACC
I
= 1mA
B1OUT
-2.5
50
+2.5
375
%
BUCK1
Buck1ISet = 100mA, C
I
= 2.2µF,
OUT
Peak-to-Peak Ripple
V
10
mV
PPRIPPLE1
= 1mA
B1OUT
25mA step resolution set by
Buck1ISet[3:0].
I
Set Range
I
mA
PEAK
PEAK_BUCK1
Maxim Integrated
│ 7
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
Buck1ISet = 150mA,
Buck1IAdptEnb = 0,
MIN
TYP
MAX
UNITS
Load Regulation Error
Line Regulation Error
V
-3
%
LOADR_BUCK1
I
= 300mA
B1OUT
V
= 1.2V; V
from 2.7V
B1OUT
SYS
V
3
mV
mA
LINER_BUCK1
to 5.5V
V
= 3.7V, Buck1VSet = 1.2V,
SYS
Maximum Operating
Output Current
I
Buck1ISet = 200mA, Buck1IAdptEnb
= 0, load regulation error = -5%
200
500
OUT_BUCK1
LEAK_B1OUT
B1OUT Pulldown
Current
I
Buck1 enabled
110
12
nA
B1OUT Pulldown
Resistance
R
Buck1 disabled, V
= 1.2V
B1OUT
MΩ
PD_B1OUT
Buck1FFET = 0
Buck1FFET = 1
Buck1FFET = 0
Buck1FFET = 1
0.27
0.55
0.24
0.43
0.5
1
Ω
Ω
Ω
Ω
pMOS On-Resistance
nMOS On-Resistance
R
ONP_BUCK1
0.45
0.9
R
ONN_BUCK1
Freewheeling
On-Resistance
R
V
= 3.7V, V = 1.2V
B1OUT
7.3
13
Ω
ONFW_BUCK1
SYS
Minimum T
T
40
98
3
80
ns
%
ON
ON_MIN
Maximum Duty Cycle
Switching Frequency
D
Buck1IAdptEnb = 0
MAX_BUCK1
f
Load regulation error = -3%
MHz
SW_BUCK1
Average Current During
Short-Circuit to GND
Buck1ISet = 150mA,
Buck1IAdptEnb = 0, V
I
100
0.005
17
mA
µA
SHRT_BUCK1
= 0V
B1OUT
BLX Leakage Current
I
1
BLX_BUCK1
Active Discharge Current
I
V
V
= 1.2V
= 1.2V
mA
PD_BUCK1
B1OUT
Passive Discharge
Resistance
R
9
kΩ
PD_BUCK1
ON_BUCK1
B1OUT
Time from enable to full current
capability, Buck1Fst = 0
Full Turn-On Time
t
58
ms
I
= 10mA, Buck1ISet = 150mA,
LOAD
Efficiency
Eff
Inductor = BOURNS SRP2010-
87
%
BUCK1
2R2M, V = 1.2V
B1OUT
Buck1LowEMI = 0
Buck1LowEMI = 1
2
BLX Rising/Falling Slew
Rate
SR
V/ns
BLX_BUCK1
0.5
Thermal-Shutdown
Temperature
T
140
10
°C
°C
SHDN_BUCK1
Thermal-Shutdown
Temperature Hysteresis
T
SHDN_HYST_BUCK1
Maxim Integrated
│ 8
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUCK REGULATOR 2
(V = +3.7V, L = 2.2µH, C = 2.2µF, V
= 1.2V)
B2OUT
SYS
Input Voltage
V
Input voltage = V
2.7
0.7
5.5
V
V
IN_BUCK2
SYS
Output Voltage
V
50mV step resolution
Note: For V < UVLO ZC is
3.85
OUT_BUCK2
OUT
Output UVLO Voltage
V
imposed. Falling edge (75mV typ
0.35
0.55
V
UVLO_BUCK2
hysteresis)
Buck enabled, I
= 0mA,
= 1.2V
B2OUT
Quiescent Supply
Current
I
V
= 3.7V, V
1
1.4
µA
mA
µA
Q_BUCK2
SYS
B2OUT
(Note 2)
Dropout Quiescent
Supply Current
I
= 0mA, V – V
SYS B2OUT
B2OUT
I
1.1
60
QDO_BUCK2
≤ 0.1V
Shutdown Supply
Current with Active
Discharge Enabled
I
Buck1 disabled, Buck2ActDSC = 1.
SD_BUCK2
Output Accuracy
ACC
I
= 1mA, V < 3.4V
B2OUT
-2.5
50
+2.5
375
%
BUCK2
B2OUT
Buck2ISet = 100mA, C
I
= 2.2µF,
OUT
Peak-to-Peak Ripple
V
10
mV
PPRIPPLE2
= 1mA
B2OUT
25mA step resolution set by
Buck2ISet[3:0].
I
Set Range
I
mA
%
PEAK
PEAK_BUCK2
Buck2ISet = 150mA,
Buck2IAdptEnb = 0, I
300mA
Load Regulation Error
Line Regulation Error
V
=
B2OUT
-3
3
LOADR_BUCK2
V
= 1.2V; V
from 2.7V
B2OUT
SYS
V
mV
mA
LINER_BUCK2
to 5.5V
V
= 3.7V, Buck2VSet = 1.2V,
SYS
Maximum Operating
Output Current
I
Buck2ISet = 200mA, Buck2IAdptEnb
= 0, load regulation = -5%
200
500
OUT_BUCK2
LEAK_B2OUT
B2OUT Pulldown
Current
I
Buck2 enabled
220
6
nA
B2OUT Pulldown
Resistance
R
Buck2 disabled, V
= 1.2V
B2OUT
MΩ
PD_B2OUT
Buck2FFET = 0
Buck2FFET = 1
Buck2FFET = 0
Buck2FFET = 1
0.27
0.55
0.24
0.43
0.5
1
Ω
Ω
Ω
Ω
pMOS On-Resistance
nMOS On-Resistance
R
ONP_BUCK2
0.45
0.9
R
ONN_BUCK2
Freewheeling
On-Resistance
R
V
= 3.7V, V = 1.2V
B2OUT
7.3
13
Ω
ONFW_BUCK2
SYS
Maxim Integrated
│ 9
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
40
98
3
MAX
UNITS
ns
Minimum T
T
80
ON
ON_MIN
Maximum Duty Cycle
Switching Frequency
D
f
Buck2IAdptEnb = 0
%
MAX_BUCK2
SW_BUCK2
Load regulation error = -3%
MHz
Average Current During
Short-Circuit to GND
Buck2ISet = 150mA,
Buck2IAdptEnb = 0, V
I
100
0.005
17
mA
µA
SHRT_BUCK2
= 0V
B2OUT
BLX Leakage Current
I
1
BLX_BUCK2
Active Discharge Current
I
V
V
= 1.2V
= 1.2V
mA
PD_BUCK2
B2OUT
Passive Discharge
Resistance
R
9
kΩ
PD_BUCK2
ON_BUCK2
B2OUT
Time from enable to full current
capability, Buck2Fst = 0
Full Turn-On Time
T
58
ms
I
= 10mA, Buck2ISet = 150mA,
LOAD
Efficiency
Eff
Inductor = BOURNS SRP2010-
87
%
BUCK2
2R2M, V = 1.2V
B2OUT
Buck2LowEMI = 0
2
BLX Rising/Falling Slew
Rate
SR
V/ns
BLX_BUCK2
Buck2LowEMI = 1
0.5
Thermal-Shutdown
Temperature
T
140
10
°C
°C
SHDN_BUCK2
Thermal-Shutdown
Temperature Hysteresis
T
SHDN_HYST_BUCK2
LDO1
(C = 1μF, unless otherwise noted. Typical values are at V
= 3.7V, with I
= 10mA, V
= 3V.)
L1IN
L1OUT
L1OUT
LDO mode
2.7
5.5
5.5
4
V
V
Input Voltage
V
INLDO1
Switch mode
1.2
LDO enabled, I
= 0µA
0.55
0.45
L1OUT
L1OUT
Quiescent Supply
Current
I
µA
µA
LDO enabled, I
Switch mode
= 0µA,
Q_LDO1
Shutdown Supply
Current with Active
Discharge Enabled
I
LDO1 disabled. LDO1ActDSC=1.
55
SD_LDO1
Maximum Output
Current
I
100
0.8
mA
V
L1OUT_MAX
Output Voltage
V
3.6
L1OUT
V
= (V
= 100µA
+ 0.5V) or higher,
L1IN
L1OUT
Output Accuracy
ACC
-2.7
+2.7
%
LDO1
I
L1OUT
Maxim Integrated
│ 10
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= 3V, I = 100mA,
MIN
TYP
MAX
UNITS
V
L1IN
L1OUT_
Dropout Voltage
V
102
mV
DROP_LDO1
LDO1VSet = 3V
Line Regulation Error
Load Regulation Error
V
V
= (V + 0.5V) to 5.5V
L1OUT
-0.12
0.022
0.002
±36
+0.12
%/V
%/mA
mV
LINEREG_LDO1
L1IN
V
I
= 100µA to 100mA
0.005
LOADREG_LDO1
L1OUT
V
= 4V to 5V, 200ns rise time
= 4V to 5V, 1µs rise time
L1IN
L1IN
Line Transient
V
LINETRAN_LDO1
V
±28
mV
I
= 0mA to 10mA, 200ns
L1OUT
145
290
10
mV
mV
KΩ
mA
rise time
Load Transient
V
LOADTRAN_LDO1
I
= 0mA to 100mA, 200ns
L1OUT
rise time
Passive Discharge
Resistance
R
5
7
16
PD_LDO1
Active Discharge Current
I
V
= 3.7V
20
37
ADL_LDO1
L1IN
V
V
V
= 2.7V, I
= 1.8V, I
= 1.2V, I
= 100mA
= 100mA
= 5mA
0.5
0.76
1.7
0.85
1.3
L1IN
L1OUT
L1OUT
L1OUT
Switch Mode Resistance
R
Ω
ON_LDO1
L1IN
2.8
L1IN
I
= 0mA, time from 10% to
L1OUT
1.6
3.7
90% of final value
Turn-On Time
t
ms
ON_LDO1
I
= 0mA, time from 10% to
L1OUT
0.25
345
335
0.65
550
550
90% of final value, Switch mode
V
V
= 2.7V, V
= GND
= GND,
150
150
mA
mA
L1IN
L1OUT
Short-Circuit Current
Limit
I
= 2.7V , V
SHRT_LDO1
L1IN
L1OUT
Switch mode
Thermal-Shutdown
Temperature
T
150
16
°C
°C
SHDN_LDO1
Thermal-Shutdown
Temperature Hysteresis
T
SHDN_HYST_LDO1
10Hz to 100kHz, V
= 5V,
= 5V,
= 5V,
= 5V,
L1IN
L1IN
L1IN
L1IN
110
95
V
= 3.3V
L1OUT
10Hz to 100kHz, V
= 2.5V
V
L1OUT
Output Noise
OUT
µVrms
NOISE
10Hz to 100kHz, V
= 1.2V
60
V
L1OUT
10Hz to 100kHz, V
= 0.8V
60
V
L1OUT
Maxim Integrated
│ 11
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= 3.7V, with I
MIN
TYP
= 3V.)
MAX
UNITS
LDO2
(C = 1μF, unless otherwise noted. Typical values are at V
= 10mA, V
L2IN
L2OUT
L2OUT
LDO mode
Switch mode
1.71
5.5
5.5
5.1
V
V
Input Voltage
V
INLDO2
1.2
I
I
I
= 0µA
1
Quiescent Supply
Current
L2OUT
L2OUT
L2OUT
I
µA
µA
Q_LDO2
= 0µA, Switch mode
0.5
Quiescent Supply
Current in Dropout
= 0µA, V = 2.9V,
L2IN
I
1.8
QDO_LDO2
LDO2VSet = 3V.
Shutdown Supply
Current with Active
Discharge Enabled
I
LDO2 disabled. LDO2ActDSC=1.
54
µA
SD_LDO2
V
V
≥ 2.7V
100
50
mA
mA
V
Maximum Output
Current
L2IN
I
L2OUT_MAX
= 1.8V or lower
L2IN
Output Voltage
V
0.9
4
L2OUT
V
= (V
= 100µA
+ 0.5V) or higher,
L2IN
L2OUT
Output Accuracy
ACC
-2.7
+2.7
%
LDO2
I
L2OUT
V
= 3V, I
= 100mA,
L2IN
L2OUT_
Dropout Voltage
V
100
mV
DROP_LDO2
LDO2VSet = 3V
Line Regulation Error
Load Regulation Error
V
V
= (V + 0.5V) to 5.5V
L2OUT
-0.4
+0.05
0.001
±35
+0.4
%/V
%/mA
mV
LINEREG_LDO2
L2IN
V
I
= 100µA to 100mA
0.005
LOADREG_LDO2
L2OUT
V
= 4V to 5V, 200ns rise time
= 4V to 5V, 1µs rise time
L2IN
L2IN
Line Transient
V
LINETRAN_LDO2
V
±25
mV
I
= 0mA to 10mA, 200ns
L2OUT
100
200
10
mV
mV
KΩ
mA
rise time
Load Transient
V
LOADTRAN_LDO2
I
= 0mA to 100mA, 200ns
L2OUT
rise time
Passive Discharge
Resistance
R
5
7
16
PD_LDO2
Active Discharge Current
I
V
= 3.7V
20
37
ADL_LDO2
L2IN
V
V
V
= 2.7V, I
= 1.8V, I
= 1.2V, I
= 100mA
= 50mA
= 5mA
0.46
0.7
0.76
1.15
2.6
L2IN
L2OUT
L2OUT
L2OUT
Switch Mode
Resistance
R
Ω
ON_LDO2
L2IN
1.7
L2IN
I
= 0mA, time from 10% to
L2OUT
1.5
3.7
90% of final value
Turn-On Time
t
ms
ON_LDO2
I
= 0mA, time from 10% to
L2OUT
0.25
0.65
90% of final value, Switch mode
Maxim Integrated
│ 12
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= 2.7V, V = GND
MIN
TYP
MAX
UNITS
V
V
140
340
600
mA
L2IN
L2OUT
Short-Circuit Current
Limit
I
= 2.7V , V
= GND,
SHRT_LDO2
L2IN
L2OUT
140
330
150
21
600
mA
°C
Switch mode
Thermal-Shutdown
Temperature
T
SHDN_LDO2
Thermal-Shutdown
Temperature Hysteresis
T
°C
SHDN_HYST_LDO2
10Hz to 100kHz, V
= 5V,
= 5V,
= 5V,
= 5V,
L2IN
L2IN
L2IN
L2IN
150
125
90
V
= 3.3V
L2OUT
10Hz to 100kHz, V
= 2.5V
V
L2OUT
Output Noise
OUT
µVrms
NOISE
10Hz to 100kHz, V
= 1.2V
V
L2OUT
10Hz to 100kHz, V
80
V
V
V
= 0.9V
L2OUT
Falling
1.14
1.38
1.4
L2IN
L2IN
L2IN UVLO
V
V
UVLO_LDO2
Rising
1.64
LDO3
(C = 1μF, unless otherwise noted. Typical values are at V
= 3.7V, with I
= 10mA, V
= 3V.)
L3IN
L3OUT
L3OUT
LDO mode
Switch mode
1.71
5.5
5.5
5.1
V
V
Input Voltage
V
INLDO3
1.2
I
I
I
= 0µA
1
Quiescent Supply
Current
L3OUT
L3OUT
L3OUT
I
µA
µA
Q_LDO3
= 0µA, Switch mode
0.5
Quiescent Supply
Current in Dropout
= 0µA, V = 2.9V,
L3IN
I
1.8
QDO_LDO3
LDO3VSet = 3V.
Shutdown Supply
Current with Active
Discharge Enabled
I
LDO3 disabled. LDO3ActDSC=1.
54
µA
SD_LDO3
V
V
≥ 2.7V
100
50
mA
mA
V
Maximum Output
Current
L3IN
I
L3OUT_MAX
= 1.8V or lower
L3IN
Output Voltage
V
0.9
4
L3OUT
V
= (V
= 100µA
+ 0.5V) or higher,
L3IN
L3OUT
Output Accuracy
ACC
-2.7
+2.7
%
LDO3
I
L3OUT
V
= 3V, I
= 100mA,
L3IN
L3OUT_
Dropout Voltage
V
100
mV
DROP_LDO3
LDO3VSet = 3V
Maxim Integrated
│ 13
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= (V + 0.5V) to 5.5V
L3OUT
MIN
TYP
+0.05
0.001
±35
MAX
+0.4
UNITS
%/V
Line Regulation Error
Load Regulation Error
V
V
-0.4
LINEREG_LDO3
L3IN
V
I
= 100µA to 100mA
0.005
%/mA
mV
LOADREG_LDO3
L3OUT
V
= 4V to 5V, 200ns rise time
= 4V to 5V, 1µs rise time
L3IN
L3IN
Line Transient
V
LINETRAN_LDO3
V
±25
mV
I
= 0mA to 10mA, 200ns
L3OUT
100
200
10
mV
mV
KΩ
mA
rise time
Load Transient
V
LOADTRAN_LDO3
I
= 0mA to 100mA, 200ns
L3OUT
rise time
Passive Discharge
Resistance
R
5
7
16
PD_LDO3
Active Discharge Current
I
V
= 3.7V
20
37
ADL_LDO3
L3IN
V
V
V
= 2.7V, I
= 1.8V, I
= 1.2V, I
= 100mA
= 100mA
= 5mA
0.46
0.7
0.76
1.15
2.6
L3IN
L3OUT
L3OUT
L3OUT
Switch Mode Resistance
R
Ω
ON_LDO3
L3IN
1.7
L3IN
I
= 0mA, time from 10% to
L3OUT
1.5
3.7
90% of final value
Turn-On Time
t
ms
ON_LDO3
I
= 0mA, time from 10% to
L3OUT
0.25
340
330
0.65
600
600
90% of final value, Switch mode
V
= 2.7V, V
= GND
= GND,
140
140
mA
mA
L3IN
L3IN
L3OUT
Short-Circuit Current
Limit
I
V
= 2.7V , V
SHRT_LDO3
L3OUT
Switch mode
Thermal-Shutdown
Temperature
T
150
21
°C
°C
SHDN_LDO3
Thermal-Shutdown
Temperature Hysteresis
T
SHDN_HYST_LDO3
10Hz to 100kHz, V
= 5V,
= 5V,
= 5V,
= 5V,
L3IN
L3IN
L3IN
L3IN
150
125
80
V
= 3.3V
L3OUT
10Hz to 100kHz, V
= 2.5V
V
L3OUT
Output Noise
L3IN UVLO
OUT
µVrms
NOISE
10Hz to 100kHz, V
= 1.2V
V
L3OUT
10Hz to 100kHz, V
60
V
V
V
= 0.9V
L3OUT
Falling
1.14
1.38
1.4
L3IN
L3IN
V
V
UVLO_LDO3
Rising
1.64
Maxim Integrated
│ 14
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHGIN TO SYS PATH
(V = 5.0V, V
= V
SYS_REG
)
CHGIN
SYS
Allowed CHGIN Input
Voltage Range
V
-5.5
28
V
V
CHGIN_RNG
Rising
Falling
3.8
3.0
3.9
4.1
V
Detect
CHGIN
V
CHGIN_DET
Threshold
3.1
3.2
V
Overvoltage
CHGIN
V
Rising
7.2
7.5
200
7.8
V
CHGIN_OV
Threshold
V
Overvoltage
CHGIN
V
mV
mV
mV
CHGIN_OV_HYS
Threshold Hysteresis
V
V
– V
, Rising,
CHGIN
SYS
V
Valid Trip Point
V
+30
+145
275
+290
CHGIN
CHGIN
CHGIN-SYS_TP
= 4V
BAT
V
Valid Trip Point
V
CHGIN-SYS_TP_HYS
Hysteresis
ILimCntl[1:0] = 00
ILimCntl[1:0] = 01
ILimCntl[1:0] = 10
ILimCntl[1:0] = 11
0
90
100
Input Limiter Current
Internal CAP Regulator
I
mA
LIM
450
1000
4.2
550
V
V
= 5V
3.9
4.7
V
CAP
CHGIN
CHGIN
CHGIN-SYS Regulation
Voltage
V
R
V
= 4V, I
= 1mA
40
370
+150
30
mV
CHGIN-SYS
SYS
CHGIN to SYS
On-Resistance
V
= 4.4V, I
= 500mA
SYS
660
mΩ
oC
oC
ms
V
CHGIN-SYS
CHGIN
Thermal-Shutdown
Temperature
T
(Note 3)
CHGIN_SHDN
Thermal-Shutdown
Temperature Hysteresis
T
CHGIN_SHDN_HYS
Input Current Soft-Start
Time
t
1
SFST_LIM
Internal Supply
Switchover Threshold
V
V
= V
rising, V = 4.2V
BAT
2.5
2.8
3.0
CCINT_TH
CHGIN
CAP
Maxim Integrated
│ 15
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYS, BATTERY, AND VCCINT UVLOs
V
Rising
Falling
3
3.06
3.04
SYSUVLO_R
SYS UVLO Threshold
V
V
2.92
2.98
SYSUVLO_F
SYS UVLO Threshold
Hysteresis
V
Hysteresis
26
20
mV
µs
SYSUVLO_HYS
SYS UVLO Falling
Debounce Time
t
SYS Falling
SYSUVLO_FDEB
V
UVLO Threshold
CCINT
V
V
Rising
0.8
1.82
140
2.6
2.2
V
UVLO
CCINT
(POR)
V
UVLO Threshold
CCINT
V
mV
UVLO_HYS
Hysteresis
Rising (Valid only when CHGIN is
present. When V < V
the BAT-SYS switch opens and
BAT is connected to SYS through a
diode.)
,
BAT_UVLO
BAT
BAT UVLO Threshold
V
1.9
2.05
50
V
BAT_UVLO
BAT UVLO Threshold
Hysteresis
V
Hysteresis
mV
BAT_UVLO_HYS
BATTERY CHARGER (See Figure 5a and Figure 5b)
(V
= 4.2V. Typical values are at V
= 5.0V, V
= V
SYS_REG
)
BAT
CHGIN
SYS
Allowed BAT Voltage
Range
V
0
5.5
V
BAT_RNG
BAT to SYS
On-Resistance
R
V
= 4.2V, I = 300mA
BAT
80
120
22
140
mΩ
BAT-SYS
BAT
Current Reduce Thermal
Threshold Temperature
T
(Note 4)
oC
CHG_LIM
BAT-to-SYS Switch-On
Threshold
V
SYS falling
SYS rising
10
35
mV
mV
V
BAT-SYS-ON
BAT-to-SYS Switch-Off
Threshold
V
-3
-1.5
0
BAT-SYS-OFF
SYS-BAT Regulation
Voltage
V
V
V
BatReg
BatReg
BatReg
V
V
= 5V, I
= 1mA
SYS
SYS_REG
CHGIN
+ 140mV + 200mV + 260mV
Maxim Integrated
│ 16
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
SysMin = 000,
> 3.6V
MIN
TYP
MAX
UNITS
V
+
BAT
V
0.1
BAT
SysMin = 000,
< 3.4V
3.6
3.7
3.8
3.9
4
V
BAT
SysMin = 001,
< 3.4V
V
BAT
SysMin = 010,
< 3.4V
V
BAT
SYS Threshold Voltage
Charger Limiting Current
(Note 5)
SysMin = 011,
< 3.4V
V
V
SYS_LIM
V
BAT
SysMin = 100,
< 3.4V
3.86
4.14
V
BAT
SysMin = 101,
< 3.4V
4.1
4.2
4.3
1
V
BAT
SysMin = 110,
< 3.4V
V
BAT
SysMin = 111,
< 3.4V
V
BAT
Charger Current Soft-
Start Time
t
ms
CHG_SOFT
PRECHARGE
IPChg = 00
5
IPChg = 01
9
10
11
Precharge Current
I
%I
FChg
PCHG
IPChg = 10
20
IPChg = 11
30
VPChg = 000
VPChg = 001
VPChg = 010
VPChg = 011
VPChg = 100
VPChg = 101
VPChg = 110
VPChg = 111
2.1
2.15
2.25
2.40
2.55
2.7
2.35
Prequalification
Threshold
V
V
BAT_PChg
2.85
3.0
3.15
Prequalification
Threshold Hysteresis
V
90
mV
BAT_PChg_HYS
Maxim Integrated
│ 17
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAST CHARGE
SET Current Gain Factor
SET Regulation Voltage
K
V
2000
1
A/A
V
SET
SET
R
R
R
= 400kΩ
5
SET
SET
SET
Fast-Charge Current
I
= 40kΩ
45
50
55
mA
%
FChg
= 4kΩ
450
500
550
Fast-Charge Current
Accuracy (Note 6)
I
R
Range = 4kΩ to 40kΩ
-10
+10
FChg_ACC
SET
MAINTAIN CHARGE
ChgDone = 00
ChgDone = 01
ChgDone = 10
ChgDone = 11
BatReg = 0000
BatReg = 0001
BatReg = 0010
5
8.5
10
11.5
Charge Done
Qualification
I
%IFChg
Chg_DONE
20
30
4.05
4.10
4.15
4.2
T
= +25°C
4.179
4.221
BatReg =
A
A
0011
T
= 0 to +45C
4.168
4.2
4.232
BatReg = 0100
BatReg = 0101
BatReg = 0110
BatReg = 0111
BatReg = 1000
BatReg = 1001
BatReg = 1010
BatReg = 1011
BatReChg = 00
BatReChg = 01
BatReChg = 10
BatReChg = 11
4.25
4.3
BAT Regulation Voltage
(Note 7)
V
V
BatReg
4.35
4.4
4.45
4.5
4.55
4.6
V
- 70
BatReg
V
- 120
-170
-220
BAT Recharge
Threshold
BatReg
V
mV
BatReChg
V
BatReg
BatReg
V
Maxim Integrated
│ 18
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGER TIMER
PChgTmr = 00
30
60
PChgTmr = 01
PChgTmr = 10
PChgTmr = 11
FChgTmr = 00
FChgTmr = 01
FChgTmr = 10
FChgTmr = 11
TOChgTmr = 00
TOChgTmr = 01
TOChgTmr = 10
TOChgTmr = 11
Maximum
Prequalification Time
t
min
PChg
120
240
75
150
300
600
0
Maximum Fast-Charge
Time
t
min
FChg
15
Maintain-Charge Time
t
min
%
TOChg
30
60
Timer Accuracy
t
-10
+10
CHG_ACC
If charge current is reduced due to
ILIM or TDIE this is the percentage
of charge current below which timer
clock operates at half speed
Timer Extend Threshold
TIM
50
20
%I
%I
EXD_THRES
SUS_THRES
FChg
FChg
If charge current is reduced due to
ILIM or TDIE this is the percentage
of charge current below which timer
clock pauses
Timer Suspend
Threshold
TIM
THERMISTOR MONITOR AND NTC DETECTION
V
V
V
V
V
V
V
falling
falling
falling
falling
rising
rising
rising
30.9
21.3
48
32.9
23.3
50
34.9
25.3
52
THM
THM
THM
THM
THM
THM
THM
THM Hot Threshold
T
T
4
THM Warm Threshold
3
30.9
62.5
71.9
91
32.9
64.5
73.9
93
34.9
66.5
75.9
95
%CAP
THM Cool Threshold
THM Cold Threshold
THM Disable Threshold
T
T
2
1
THM
DIS
THM Threshold
Hysteresis
THM
60
mV
µA
HYS
THM Input Leakage
I
-1
1
LKG_THM
Maxim Integrated
│ 19
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
START UP TIMING (See Figure 2)
Boot Delay
BootDly = 00
80
BootDly = 01
BootDly = 10
BootDly = 11
120
220
420
t
ms
%
RST
Boot Delay Timer
Accuracy
t
-10
1.4
10
RST_ACC
DIGITAL SIGNALS
Input Logic-High (SDA,
SCL, MPC0, MPC1,
PFN1, PFN2)
V
IH
V
Input Logic-Low (SDA,
SCL, MPC0, MPC1,
PFN1, PFN2)
V
0.5
0.4
IL
V
V
Output Logic-Low (SDA,
V
I
I
= 4mA
OL
OL
RST
, INT, LED, PFN2)
High Level Leakage
Current (SDA, RST
,
INT
,
1
µA
kHz
µs
LK
LED, PFN2)
SCL Clock Frequency
Bus Free Time Between
f
400
SCL
BUF
a
STOP and START
t
1.3
Condition
START Condition
(Repeated) Hold Time
t
(Note 8)
0.6
1.3
0.6
µs
µs
µs
HD:STA
Low Period of SCL
Clock
t
LOW
High Period of SCL
Clock
t
HIGH
Setup Time for a
Repeated START
Condition
t
0.6
µs
SU:STA
Data Hold Time
Data Setup Time
t
(Note 9)
(Note 9)
0
0.9
µs
ns
HD:DAT
t
100
SU:DAT
Setup Time for STOP
Condition
t
0.6
µs
SU:STO
Spike Pulse Widths
Suppressed by Input
Filter
t
(Note 10)
50
ns
SP
Maxim Integrated
│ 20
www.maximintegrated.com
MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Electrical Characteristics (continued)
(V
= 5.0V, V
= 3.7V, T = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical values are at
CHGIN
BAT A
T
= +25°C.) (Note 1)
A
Note 1:
All devices are 100% production tested at T = +25°C. Limits over the operating temperature range guaranteed by
A
design.
Note 2:
Note 3:
Note 4:
Note 5:
This value is included in the I
When the die temperature exceeds T
When the die temperature exceeds T
This is the threshold at which the charger starts to limit the current due to SYS dropping; if VSYS drops below this value
the charger will not move to maintain charge.
quiescent current values for the ON states.
BAT
, the CHGIN to SYS path opens, and the charger is turned off.
CHGIN_SHDN
, the charger current starts to decrease.
CHG_LIM
Note 6:
Note 7:
Note 8:
Note 9:
Fast charge current accuracy tested only at 50mA and 500mA, all other values guaranteed by design.
Values over temperature are not production tested and guaranteed by characterization.
f
must meet the minimum clock low time plus the rise/fall times.
SCL
The maximum t
has to be met only if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 10: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Maxim Integrated
│ 21
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Typical Operating Characteristics
(V
= 3.7V, V
= 0V, registers in their default state, T = +25°C, unless otherwise noted.)
BAT
CHGIN A
IBAT vs. VBAT
IFCHG vs. TEMPERATURE
VCHGIN = 5V
RSET = 40kΩ
IPChg[1:0] = 01
IBAT vs. TEMPERATURE
VBAT = 3.7V
toc02
toc01
toc03
10
8
10
8
100
80
60
40
20
0
BUCKS ON, ALL LDOS ON
BUCKS ON, LDO1 ON
BUCKS ON, ALL LDOS ON
BUCKS ON, LDO1 ON
BUCKS ON
6
6
BUCKS ON
4
4
VBAT = 3.7V
VBAT = 2V
2
2
POWER OFF
POWER OFF
10
0
0
-40
-15
35
60
85
2.7
3.0
3.3
VBAT (V)
3.6
3.9
4.2
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
VSYS vs. VCHGIN
VBAT_REG vs. TEMPERATURE
VCHGIN = 5V
BatReg[2:0] = 011
RSET = 40kΩ
IBAT/ VBAT vs. TIME
toc04
toc05
toc06
4.22
200
160
120
80
6
5
4
3
2
1
0
6
5
4
3
2
1
0
150mAhr BATTERY
IChgDone[1:0]= 01
IPChg[1:0=01
VPChg[2:0]=110
RSET = 40kΩ
VBAT = 2.8V
RSYS = 50Ω
4.21 4.2kΩ at BAT
VBAT
4.20
4.19
4.18
IBAT
40
0
-40
-15
10
35
60
85
0
40
80
120 160 200 240 280
TIME (minutes)
3
4
5
6
7
8
VCHGIN (V)
TEMPERATURE (°C)
ICHGIN vs. TEMPERATURE
VBAT = 3.7V
VCHGIN = 5V
ISYS = 600mA
VL1OUT vs. LOAD
VL2OUT vs. LOAD
VL2OUT = 3.0V
toc09
toc08
toc07
800
600
400
200
0
3.10
3.05
3.00
2.95
2.90
3.10
3.05
3.00
2.95
2.90
VL1OUT = 3.0V
VBAT = 3.3V, 3.7V, 4.2V
VBAT = 3.3V, 3.7V, 4.2V
ILimCntl[1:0] = 0x02
ILimCntl[1:0] = 0x01
-40
-15
10
35
60
85
0
20
40
60
80
100
0
20
40
60
80
100
TEMPERATURE (°C)
IL1OUT (mA)
IL2OUT (mA)
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Typical Operating Characteristics (continued)
(V
= 3.7V, V
= 0V, registers in their default state, T = +25°C, unless otherwise noted.)
BAT
CHGIN A
V
L3OUT vs. LOAD
VL3OUT = 3.0V
LDO1 TRANSIENT RESPONSE
LDO1 TRANSIENT RESPONSE
toc10
toc11
toc12
3.10
3.05
3.00
2.95
2.90
VL1OUT = 3.0V
VL1OUT = 3.0V
VBAT = 3.3V, 3.7V, 4.2V
200mV/div
50mA/div
200mV/div
50mA/div
VOUT
VOUT
IOUT
IOUT
100ms/div
40µs/div
0
20
40
60
80
100
IL3OUT (mA)
LDO2 TRANSIENT RESPONSE
LDO2 TRANSIENT RESPONSE
LDO3 TRANSIENT RESPONSE
toc13
toc15
toc14
VL3OUT = 3.0V
VL2OUT = 3.0V
VL2OUT = 3.0V
VOUT
VOUT
VOUT
200mV/div
50mA/div
200mV/div
50mA/div
200mV/div
50mA/div
IOUT
IOUT
IOUT
100ms/div
100ms/div
40µs/div
LDO3 TRANSIENT RESPONSE
BUCK2 EFFICIENCY vs. LOAD
BUCK2 EFFICIENCY vs. LOAD
toc16
toc17
toc18
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VL3OUT = 3.0V
VBAT = 4.2V
VBAT = 4.2V
VBAT = 3.7V
V
BAT = 3.7V
VOUT
200mV/div
50mA/div
VBAT = 3.3V
VBAT = 3.3V
VB2OUT = 1.8V
INDUCTOR = TOKO
DFE201610E0-2R2M
IOUT
VB2OUT = 0.7V
INDUCTOR = TOKO
DFE201610E0-2R2M
40µs/div
0.001
0.1
10
1000
0.001
0.1
10
1000
IB2OUT (mA)
IB2OUT (mA)
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Typical Operating Characteristics (continued)
(V
= 3.7V, V
= 0V, registers in their default state, T = +25°C, unless otherwise noted.)
BAT
CHGIN A
BUCK1 EFFICIENCY vs. LOAD
VB2OUT vs. LOAD
VB2OUT = 1.8V
VB2OUT vs. LOAD
VB2OUT = 0.7V
toc19
toc20
toc21
100
90
80
70
60
50
40
30
20
10
0
1.90
1.86
1.82
1.78
1.74
1.70
0.80
0.76
0.72
0.68
0.64
0.60
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V, 3.7V, 4.2V
VBAT = 3.3V
VBAT = 3.3V, 3.7V, 4.2V
VB1OUT = 1.2V
INDUCTOR = TOKO
DFE201610E0-2R2M
0
100
200
300
400
0
100
200
300
400
0.001
0.1
10
1000
IB1OUT (mA)
IB2OUT (mA)
IB2OUT (mA)
VB1OUT vs. LOAD
VB1OUT vs. LOAD
VB1OUT = 0.7V
BUCK1 EFFICIENCY vs. LOAD
toc22
toc23
toc24
100
90
80
70
60
50
40
30
20
10
0
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.80
0.75
0.70
0.65
0.60
VB1OUT = 1.2V
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
VBAT = 3.3V, 3.7V, 4.2V
VBAT = 3.3V, 3.7V, 4.2V
VB1OUT = 0.7V
INDUCTOR = TOKO
DFE201610E0-2R2M
0
100
200
300
400
0
100
200
300
400
0.001
0.1
10
1000
IB1OUT (mA)
IB1OUT (mA)
IB1OUT (mA)
BUCK1 TRANSIENT RESPONSE
BUCK2 TRANSIENT RESPONSE
toc25
toc26
VB1OUT = 1.2V
VB2OUT = 1.8V
VB1OUT
20mV/div
50mA/div
VB2OUT
20mV/div
50mA/div
IB1OUT
IB2OUT
20µs/div
20µs/div
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX20335
1
2
3
4
5
6
+
L1OUT
L2OUT
L1IN
CAP
GND
B2OUT
B2LX
A
B
C
D
L2IN
INT
MON
BAT
BAT
L3OUT
LED
L3IN
GND
GND
GND
GND
SET
EXT
SYS
SYS
PFN2
E
RST
MPC0
SCL
MPC1
THM
PFN1
GND
CHGIIN
B1OUT
CHGIN
B1LX
SDA
F
WLP
(2.72mm x 2.47mm)
Bump Description
BUMP
A1
NAME
L1OUT
L1IN
FUNCTION
LDO1 Output. Bypass with a minimum 1µF capacitor to GND.
LDO1 Input
A2
A3
CAP
Bypass for Internal LDO. Bypass with a 1µF capacitor to GND.
A4, C3, C4
D3, D4, F4
GND
Ground
A5
A6
B1
B2
B3
B4
B2OUT
B2LX
L2OUT
L2IN
0.7V to 3.85V Buck Regulator Output Feedback. Bypass with a 10µF capacitor to GND.
0.7V to 3.85V Buck Regulator Switch. Connect 2.2µH inductor to B2OUT.
LDO2 Output. Bypass with a minimum 1µF capacitor to GND.
LDO2 Input
INT
Open-Drain, Active-Low Interrupt Output.
MON
Voltage Monitor Pin
Battery Connection. Connect BAT to a positive battery terminal, bypass BAT with a minimum 1µF
capacitor to GND.
B5,B6
BAT
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PMIC with Ultra-Low I Voltage Regulators and
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Bump Description (continued)
PIN
C1
NAME
L3OUT
L3IN
FUNCTION
LDO3 Output. Bypass with a minimum 1µF capacitor to GND.
C2
LDO3 Input
External Resistor For Battery Charge Current Level Setting. Do not connect any external capacitance
C5
SET
SYS
on this pin; maximum allowed capacitance (C
< 5µs/R
) pF.
SET
SET
System Load Connection. Connect SYS to the system load. Bypass SYS with a minimum 10µF low-
ESR ceramic capacitor to GND.
C6, D6
D1
LED
LED Open-Drain Pulldown Current. Add an external current limiting pullup resistor.
D2
PFN2
Power Function Control Input/Output. Programmable functionality via PwrFnMode. See Table 1.
Push-Pull Gate Drive for Optional External pFET from BAT-to-SYS. Output is pulled to GND when
charger is disconnected and internal BAT-SYS FET is switched on. Otherwise, this output is pulled
high to the SYS voltage.
D5
EXT
E1
E2
RST
MPC0
MPC1
PFN1
CHGIN
SDA
Power-On Reset Output. Active-low, open-drain.
Multipurpose Configuration Input 0
E3
Multipurpose Configuration Input 1
E4
Power Function Control Input. Programmable functionality via PwrFnMode. See Table 1.
-5.5V/+28V Protected Charger Input. Bypass CHGIN with 1µF capacitor to GND.
E5, E6
F1
2
Open-Drain, I C Serial Data Input/Output.
2
F2
SCL
I C Serial Clock Input
Battery Temperature Thermistor Measurement Connection. Connect a 10kΩ resistor from THM to
CAP and a 10kΩ, 3380β NTC thermistor from THM to GND.
F3
THM
F5
F6
B1OUT
B1LX
0.7V to 2.275V Buck Regulator Output Feedback. Bypass B1OUT with a 10µF capacitor to GND.
0.7V to 2.275V Buck Regulator Switch Terminal. Connect B1LX to B1OUT with a 2.2µH inductor.
Note: All capacitance values listed in this document refer to effective capacitance. Be sure to specify capacitors that will meet these
requirements under typical system operating conditions taking into consideration the effects of voltage and temperature.
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Block Diagram
MAX20335
LINEAR
Li+ BATTERY CHARGER
WITH POWER SELECTOR
28V/-5.5V INPUT
PROTECTION
POWER
POWER
SEQUENCER
BUCK 1
MONITOR
CONTROL
BUCK 2
LDO/SWITCH 1
LDO/SWITCH 2
DATA
SYS
LDO/SWITCH 3
Power On/Off and Reset Control
Detailed Description
The behavior of power function control pins (PFN1 and
PFN2) is preconfigured to support one of the multiple
types of wearable application cases. Table 1 describes
the behavior of the PFN1 and PFN2 pins based on
the PwrRstCfg[3:0] bits and Figure 1 shows basic flow
diagrams associated with each mode.
Power Regulation
The MAX20335 family includes two high-efficiency, low
quiescent current buck regulators, and three low quiescent
current linear regulators that are also configurable as
power switches. Excellent light-load efficiency allows
the switching regulators to run continuously without
significant energy cost.
A Soft-Reset generates a 10ms logic low pulse at RST
and resets all registers to their default values. A Hard-
Reset initiates a complete Power-On Reset sequence and
generates a 50ms logic-low pulse at RST.
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PMIC with Ultra-Low I Voltage Regulators and
Q
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Table 1. Power Function Input Control Modes
Available PwrCmd
OFF HARD SOFT
NO NO YES
PFN1 PU/PD
PFNxResEna = 1
PFN2 PU/PD
PFNxResEna = 1
PwrRstCfg[3:0]**
PFN1**
PFN2**
ENABLE
PULLDOWN
Manual Reset
PULLUP*
On/Off
On/Off Mode with 10ms debounce. PFN1 is the active-high on/off control input. PFN2 is the active-low soft-
reset input.
DISABLE
PULLUP*
Manual Reset
PULLUP*
NO
NO
YES
On/Off
On/Off Mode with 10ms debounce. PFN1 is the active-low on/off control. PFN2 is the active-low soft-reset
input.
Hard-Reset on PFN1
Soft-Reset on
PFN2 Rising
PULLDOWN
PULLDOWN
YES
YES
YES
Rising
AON
Always-On Mode. A rising edge on PFN1 generates a hard reset after a 200ms delay. A rising edge on PFN2
generates a soft-reset after a 200ms delay. In this mode, the device can only enter the off state by writing to
the PwrCmd register.
Hard-Reset on PFN1
Soft-Reset on
PFN2 Falling
PULLUP*
PULLUP*
YES
YES
YES
Falling
AON
Always-On Mode. A falling edge on PFN1 generates a hard-reset after a 200ms delay. A falling edge on PFN2
generates a soft-reset after a 200ms delay. In this mode, the device can only enter the off state by writing to
the PwrCmd register.
Hard-Reset on CHGIN
insertion When PFN1
High
Soft-Reset CHGIN
Insertion When
PFN2 High
PULLDOWN
PULLDOWN
YES
YES
YES
CR High
Charger Reset High Mode. When PFN1 is high, a CHGIN insertion generates a hard-reset after a 200ms
delay. When PFN2 is high, a CHGIN insertion generates a soft-reset after a 200ms delay. In this mode, the
device can only enter the off state by writing to the PwrCmd register.
Hard-Reset on CHGIN
Insertion
Soft-Reset on
CHGIN Insertion
When PFN2 Low
PULLUP*
PULLUP*
YES
YES
YES
When PFN1 low
CR Low
Charger Reset Low Mode. When PFN1 is low, a CHGIN insertion generates a Hard-Reset after a 200ms
delay. When PFN2 is low, a CHGIN insertion generates a Soft-Reset after a 200ms delay. In this mode, the
device can only enter the off state by writing to the PwrCmd register.
KIN
PULLUP*
KOUT
NONE
YES
YES
YES
Custom Button Mode. PFN1 is the active-low KIN button input. PFN2 is the open-drain KOUT output, which
buffers the KIN input. The device can enter the off state by either a KIN press (>12s) or by writing to the
PwrCmd register. A CHGIN insertion or a KIN press (>400ms) can exit the off state.
KIN
KIN
PULLUP*
KOUT
NONE
YES
NO
NO
Custom Soft Reset 1. PFN1 is the active-low KIN button input. PFN2 is the open-drain KOUT output, which
buffers the KIN input. A KIN press (>12s) generates a soft-reset. The device can only enters the off state
through the PwrCmd register. A CHGIN insertion or a KIN press (>3s) can exit the off state.
CSR1
CSR2
KIN
PULLUP*
Manual Reset
NONE
YES
YES
YES
Custom Soft-Reset 2. PFN1 is the active-low KIN button input. PFN2 is the active-low soft-reset input. A PFN2
press (>12s) generates a soft-reset. In this mode, the device can only enter the off state by writing to the
PwrCmd register.
* Pullup is connected to an internal supply, V
. (V
= V
if V
> V
, or V
2
= V
if V
< V
).
CCINT
CCINT
CAP
CAP
CCINT_TH
CCINT
BAT
CAP
CCINT_TH
** PwrRstCfg[3:0] is read-only; the functions of PFN1 and PFN2 cannot be changed through I C
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Figure 1. Power Function Input Control Modes Flow Diagrams
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MAX20335
PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
In general, if an undervoltage condition is detected on
SYS the device goes into the off state. However if there
Power Sequencing
There are multiple configuration options for the sequenc-
ing of the buck regulators and LDOs during power-on. See
Table 1 for details. Regulators can be configured to turn
on at one of the four points during the power-on process:
is a valid voltage on CHGIN the behavior is determined
by the ChgAlwTry setting. If ChgAlwTry = 0, and an
undervoltage condition is detected on SYS during the
sequencing process the device turns SYS and all other
external resources off and waits for CHGIN removal. On
CHGIN removal the device enters the off state to avoid
draining the battery. If ChgAlwTry = 1, the process will
continually recheck the SYS undervoltage condition every
500ms until it is no longer vaild before continuing with the
sequencing process.
0% t
delay t
, 25% t
, 50% t
, and 100% t
. The reset
can be set to 80ms, 120ms, 220ms, or 420ms
RST
RST
RST
RST
RST
by BootDly[1:0] in the BootCfg register. The power-on
sequencing is depicted in Figure 2a and Figure 2b.
Additionally, the regulators can be selected to default off
2
and can be turned on with an I C command after RST is
released. Each LDO regulator can be configured to be
always-on as long as SYS or BAT is present.
t
RST
POR
15ms
CHGIN INSERTION
OR KIN PRESS*
SYS
ENABLE VIA
CHGIN INSERTION
30ms
30ms
15ms
5ms
2
I C/MPC
KIN PRESS
ENABLE VIA
LDO_En
BUCK_En**
RST
2
I C/MPC
BUCK
CANNOT BE
ALWAYS ON
011
100
111
010
0%
_Seq
001
ALWAYS-ON
25%
50%
100%
% OF t
RST
*KIN PRESS TURN-ON ENABLED VIA SPECIFIC PwrRstCfg ONLY
**AFTER BEING ENABLED, THE BUCK CONVERTERS HAVE AN 8ms (TYP) BLANKING TIME BEFORE THE OUTPUT VOLTAGE STARTS TO RISE.
Figure 2a. Power-On Sequencing
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PMIC with Ultra-Low I Voltage Regulators and
Q
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t
RST
POR
CHGIN
SYS
30ms
15ms
ENABLE VIA
2
I C/MPC
ENABLE VIA
I C/MPC
LDO_En
15ms
2
BUCK CANNOT
BE ALWAYS ON
Buck_En*
RST
011
100
111
010
0%
_Seq
001
ALWAYS-ON
50%
100%
25%
% of t
RST
*After being enabled, the buck converters have an 8ms (typ) blanking time before the output voltage starts to rise.
Figure 2b. Power-On Sequencing Without Battery
● When the battery is connected and there is no
external power input, the system is powered from the
battery.
Smart Power Selector
The smart power selector seamlessly distributes power
from the external CHGIN input to the battery (BAT) and
the system (SYS). With both an external adapter and
battery connected, the smart power selector basic
functions are:
Thermal Current Regulation
In case the die temperature exceeds the normal limit, the
MAX20335 will attempt to limit the temperature increase
by reducing the input current from CHGIN. In this condi-
tion, the system load has priority over charger current, so
the input current is first reduced by lowering the charge
current. If the junction temperature continues to rise and
reaches the maximum operating limit, no input current
is drawn from CHGIN and the battery powers the entire
system load.
● When the system load requirements are less than the
input current limit, the battery is charged with residual
power from the input.
● When the system load requirements exceed the
input current limit, the battery supplies supplemental
current to the load.
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Note: The body diode of an external pMOS connected
between BAT and SYS remains present when the device
is in off mode.
System Load Switch
An internal 80mΩ (typ) MOSFET connects SYS to BAT
when no voltage source is available on CHGIN. When an
external source is detected at CHGIN, this switch opens
and SYS is powered from the input source through the
input current limiter. The SYS-to-BAT switch also prevents
Input Limiter
The input limiter distributes power from the external
adapter to the system load and battery charger. In
addition to the input limiter’s primary function of passing
power to the system load and charger, it performs several
additional functions to optimize use of available power:
V
SYS
from falling below V
when the system load
BAT
exceeds the input current limit. If V
drops to V
due
BAT
SYS
to the current limit, the load switch turns on so the load is
supported by the battery. If the system load continuously
exceeds the input current limit the battery is not charged.
This is useful for handling loads that are nominally below
the input current limit but have high current peaks exceeding
the input current limit. During these peaks, battery energy
is used, but at all other times the battery charges. See
Figure 3.
Invalid CHGIN Voltage Protection: If CHGIN is above
the overvoltage threshold, the MAX20335 enters
overvoltage lockout (OVL). OVL protects the MAX20335
and downstream circuitry from high-voltage stress up to
28V and down to -5.5V. During OVL, the internal circuit
remains powered and an interrupt is sent to the host.
During OVL, the charger turns off and the system load
switch closes, allowing the battery to power SYS. CHGIN
The pin EXT can drive the gate of an external pMOS
connected between SYS (source, bulk) and BAT (drain) in
parallel to the internal one.
is also invalid if it is less than V
, or less than the USB
BAT
undervoltage threshold. With an invalid input voltage, the
SYS-to-BAT load switch closes and allows the battery to
power SYS.
When V
< V
the EXT voltage is the buffered
CHGIN
BDET
version of the internal gate command that controls the
internal 80mΩ (typ) MOSFET.
VCHG
VSYS
VBAT
CLOSED
SYS SWITCH
CLOSE
OPEN
OPEN
ILIM
ICHG
IBAT
ISYS
0mA
CONSTANT BAT CHARGE
SMART POWER SELECTOR
OPERATION WITH LIMITED VB
CURRENT
VOLTAGE
DONE
Figure 3. Smart Power Selector Current/Voltage Behavior
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
CHGIN Adaptive Input Current Limit: The CHGIN input
Thermistor Monitoring with Charger Shutdown
current is limited to prevent input overload. The input
The MAX20335 features three modes for controlling
charger behavior based on battery-pack temperature:
Thermistor Monitoring, JEITA Monitoring 1, and JEITA
Monitoring 2. The divider formed by a pull-up resistor
(RPU) to CAP, optional parallel resistor (RPA) from THM
to ground, and NTC thermistor (RTHM) from THM to
ground, provides a voltage at THM that is proportional to
temperature as a fraction of the CAP voltage. Two sets
of preconfigured default thresholds (0°C/10°C/45°C/60°C
or 0°C/10°C/25°C/45°C as a %CAP) optimized for beta
3380 thermistors are available (see Table 38). The four
default thresholds create five temperature zones, and the
fractional CAP voltage measured at the THM pin is
compared to the thresholds to determine the active
temperature zone during operation.
2
current limit is controlled by I C. However, if the voltage
at CHGIN collapses because the source is not able to
2
supply either the current programmed in I C, or the total
current required by the battery charger and system load,
the input current limit will be adaptively reduced.
Thermal Limiting: In case the die temperature exceeds
the normal limit (T
), the MAX20335 attempts to
CHG_LIM
limit temperature increase by reducing the input current
from CHGIN. In this condition, the system load has prior-
ity over the charger current, so the input current is first
reduced by lowering the charge current. If the junction
temperature continues to rise and reaches the maximum
operating limit (T
), no input current is drawn
CHGIN_SHDN
from CHGIN and the battery powers the entire system
load.
The behavior in each temperature zone is determined by
2
the configuration of bits in the I C registers. The active
Adaptive Battery Charging: While the system is powered
from CHGIN, the charger draws power from SYS to charge
the battery. If the total load exceeds the input current limit,
an adaptive charger control loop reduces charge current to
monitoring mode is selected by ThermEn[1:0] in the
ThrmCfrg register. In all modes, the T2IFchg[2:0] and
T2T3IFchg[2:0], and T3T4IFchg[2:0] fields in the ThrmCfg
registers set the fast charge current in three tempera-
ture zones, T1_T2, T2_T3, and T3_T4. In Thermistor
Monitoring mode, charging is enabled only in T1_T2
and T2_T3 and the battery termination voltage is equal
prevent V
from collapsing.
SYS
When the charge current is reduced below 50% due to
or T , the timer clock operates at half speed. When
I
LIM
DIE
the charge current is reduced below 20% due to I
or
LIM
to V , as shown in Figure 4a. In both JEITA
BATREG
T
, the timer clock is paused.
DIE
Monitoring 1 and JEITA Monitoring 2 the charger is
active in the T1_T2, T2_T3, and T3_T4 zones. However,
JEITA Monitoring 1 sets the battery termination voltage to
Fast-Charge Current Setting
The MAX20335 uses an external resistor connected from
SET to GND to set the fast-charge current. The pre-charge
and charge-termination currents are programmed as a
V
for all zones, while JEITA Monitoring 2 sets the
BATREG
battery termination voltage to V
- 150mV for zones
BATREG
2
T1_2 and T3_T4, as shown in Figure 4b. The behavior of
all three modes is summarized in Table 2.
percentage of this value through I C registers. The fast-
charge current resistor can be calculated as:
R
= K
x V /I
SET FChg
SET
SET
where K
has a typical value of 2000A/A and V
has
SET
SET
a typical value of 1V. The range of acceptable resistors for
is 4kΩ to 400kΩ
R
SET
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PMIC with Ultra-Low I Voltage Regulators and
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Battery Chargers for Small Lithium Ion Systems
PREQUAL:
FAST CHARGE CONSTANT CURRENT:
V
<V
V
< V < V
BAT BAT_REG
BAT BAT_PCHG
BAT_PCHG
I
FCHG_T1-T2
I
FCHG_T2-T3
I
PCHG
NO CHARGING
NO CHARGING
CHARGING
NO CHARGING
CHARGING
NO CHARGING
T
T
4
T
2
T
T
1
T
4
1
T
2
T
3
3
TEMPERATURE (°C)
TEMPERATURE (°C)
REGULATED VOLTAGE
CAP
V
BATREG
R
PU
NO CHARGING
CHARGING
NO CHARGING
R
R
THM
PA
T
T
4
T
2
T
3
1
TEMPERATURE (°C)
Figure 4a. Charging Behavior Using Thermistor Monitoring Mode
PREQUAL:
FAST-CHARGE CONSTANT-CURRENT:
< V < V
V
<V
BAT BAT_PCHG
V
BAT_PCHG
BAT
BAT_REG
(BOTH MODES)
(BOTH MODES)
I
FCHG_T1-T2
NO
I
FCHG_T3-T4
I
FCHG_T2-T3
I
PCHG
NO
CHARGING
NO
CHARGING
NO
CHARGING
CHARGING
CHARGING
CHARGING
T1
T4
T
1
T
4
T2
T3
T
T
3
2
TEMPERATURE (°C)
TEMPERATURE (°C)
REGULATED VOLTAGE
(JEITA MONITORING 1)
REGULATED VOLTAGE
(JEITA MONITORING 2)
V
V
BATREG
BATREG
-150mV
-150mV
NO
CHARGING
NO
CHARGING
NO
CHARGING
NO
CHARGING
CHARGING
CHARGING
T
T
4
T
T
4
T
2
T
T
T
3
1
1
3
2
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4b. Charging Behavior Using JEITA Monitoring 1 and 2 Modes
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Table 2. Thermistor Monitoring/JEITA Monitoring Enable Control
CHARGER MODE
ThermEn[1:0] DESCRIPTION
T < T1
T1 < T < T2
T2 < T < T3
T3 < T < T4
T >T4
Thermistor/
JEITA
2
00
As per I C settings
Monitoring OFF
I
= IPChg,
I
= IPChg,
PCHG
PCHG
Thermistor
Monitoring ON
I
= T1T2IFchg,
I
= T2T3IFchg,
FChg
FChg
01
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Regulated Voltage =
Regulated Voltage =
V
V
BATREG
BATREG
I
= IPChg,
I
= IPChg,
I
= IPChg,
PCHG
= T3T4IFchg
Regulated Voltage =
PCHG
PCHG
JEITA
Monitoring 1 ON
I
= T1T2IFchg,
I
= T2T3IFchg
I
FChg
FChg
FChg
10
11
Regulated Voltage =
Regulated Voltage =
V
V
V
BATREG
BATREG
BATREG
I
= IPChg,
I
= IPChg,
I
= IPChg,
PCHG
PCHG
PCHG
JEITA
Monitoring 2 ON
I
= T1T2IFchg,
I
= T2T3IFchg,
I
= T3T4IFchg,
FChg
FChg
FChg
Regulated Voltage =
V
Regulated Voltage =
Regulated Voltage =
- 150mV
- 150mV
V
V
BATREG
BATREG
BATREG
2
I C Interface
2
The device uses the two-wire I C interface to communicate
with the host microcontroller. The configuration settings
and status information provided through this interface are
detailed in the register descriptions.
2
I C Addresses
The registers of the MAX20335 are accessed through
the slave address of 0101000 (0x50 for writes/0x51 for
reads).
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Thermistor Monitoring with Charger Shutdown
FROM ANY STATE
T
< T
DIE
BUS_LIM
SYS
OR V > V
BAT
OR ChgEn = 0
RESET CHARGE TIMER
T1 < T < T3
CHARGER OFF
FAULT
ChgStat = 111
LED = 0.15s PERIOD
ChgStat = 000
LED = OFF
CHARGE SUSPEND
I = 0
CHG
I
= 0
CHG
RECOVER FROM FAULT
RESET CHARGE TIMER
ChgStat = 001
LED = 1.5s PERIOD
I
= 0
CHG
ChgEn = 1,
> V
V
RISE
SYS_LIM
SYS
V
< V
– V
BATRECHG
BAT
AND ChgAutoReSta = 1
AND V > V RISE
BATREG
PAUSE
CHARGE
TIMER
SYS
SYS_LIM
MAINTAIN
PREQUAL
RESET CHARGE TIMER
CHARGE DONE
PREQUAL SUSPEND
T < T1 or T > T3
T1 < T < T3
ChgStat = 010
LED = ON
ChgStat = 110
LED = OFF
ChgStat = 001
LED = 1.5s PERIOD
T < T1 or T > T3
I
= I
CHG PCHG
I
= 0
CHG
I
= 0
CHG
t
> t
CHG_TIMER PCHG
V
< V
V
> V
BAT BAT_PChg
BAT
BAT_PChg
RESET CHARGE TIMER
RESET CHARGE TIMER
PAUSE
CHARGE
TIMER
FAST
CHARGE
CC SUSPEND
FAST
CHARGE
(CONSTANT CURRENT)
T<T1 or T>T3
T1<T<T3
ChgStat = 001
LED = 1.5s PERIOD
ChgStat = 011
LED = ON
t
> t
CHG_TIMER MTCHG
I
= 0
CHG
I
= I
**
CHG FCHG
AND
ChgAutoStp = 1
(VOLTAGE MODE = 0*
AND V > V RISE)
tCHG_TIMER> tFCHG
SYS
OR V
SYS_LIM
< V
VOLTAGE MODE = 1* AND
BAT
BAT_PChg
V
> V
RISE
SYS_LIM
SYS
PAUSE
CHARGE
TIMER
I
> I
CHG CHG_DONE
FAST
CHARGE
CV SUSPEND
ChgAutoStp = 0"
MAINTAIN
CHARGE
FAST
CHARGE
(CONSTANT VOLTAGE)
RESET CHARGE TIMER
T<T1 or T>T3
T1<T<T3
ChgStat = 101
LED = ON
ChgStat = 001
LED = 1.5s PERIOD
T < T1 or T > T3
ChgStat = 100
LED = ON
I
< I
CHG CHG_DONE
I
< I
AND
CHG CHG_DONE
I
= 0
CHG
I
= I
CHG FCHG
V
> V
RISE
SYS
SYS_LIM
AND
T
< T
CHG_LIM
DIE
t
MTCHG
RESET CHARGE TIMER
NOTES:
* VOLTAGE MODE IS AN INTERNAL SIGNAL
** CHARGE TIMER IS SLOWED BY 50% IF I
< I
CHG FCHG
/ 2 AND PAUSED IF I
< I /5 ONLY IN FAST CHARGE CONSTANT CURRENT STATE
CHG FCHG
Figure 5a. Charger State Diagram (Thermistor Monitoring with Charger Shutdown)
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Battery Chargers for Small Lithium Ion Systems
FROM ANY STATE
T
DIE<TBUS_LIM
or VBAT>VSYS
or ChgEn =0
RESET CHARGE TIMER
T1<T<T4
1s
V
<V
–V
BAT BATREG BATRECHG
FRESH BATTERY
INSERTION
CHARGE SUSPEND
CHARGER OFF
FAULT
ChgStat =001
LED=1.5s period
ChgStat =111
LED=0.15s PERIOD
ChgStat =000
LED=OFF
ChgStat =110
LED=1s pulse
I
=0
I
=0
CHG
T<T1 or T>T4
CHG
ChgEn =1,
I
=0
CHG
RECOVER FROM FAULT
RESET CHARGE TIMER
I
=0
CHG
V
>V
–V
BAT BATREG BATRECHG
Freshbat _dis=0
ChgEn =1,
ChgEn =1
AND
V
> V
– V
BATREG BATRECHG
BAT
V
>V RISE
SYS SYS_LIM
V
<V
–V
BAT BATREG BATRECHG
PAUSE
CHARGE
TIMER
and ChgAutoReSta =1
And V
>V
RISE
MAINTAIN
CHARGE DONE
SYS SYS_LIM
RESET CHARGE TIMER
PREQUAL
PREQUAL SUSPEND
T<T1 or T>T4
T1<T<T4
ChgStat =110
LED=OFF
ChgStat =010
LED=ON
ChgStat =001
LED=1.5s PERIOD
T<T1 or T>T4
I
=0
CHG
I
=I
I
=0
CHG
CHG PCHG
t
>t
CHG_TIMER PCHG
V
<V
BAT BAT_PChg
V
>V
BAT BAT_PChg
RESET CHARGE TIMER
RESET CHARGE TIMER
PAUSE
CHARGE
TIMER
FAST
CHARGE
(CONSTANT CURRENT
FAST
CHARGE
CC SUSPEND
T<T1 or T>T4
T1<T<T4
)
ChgStat =011
LED=ON
ChgStat =001
LED=1.5s PERIOD
t
>t
CHG_TIMER MTCHG
I
=I
**
CHG FCHG
I
=0
CHG
AND
ChgAutoStp =1
(VOLTAGE MODE =0*
AND V >V RISE )
T<T2 or T>T3
VOLTAGE MODE =1*
AND
SYS SYS_LIM
<V
t
>t
CHG_TIMER FCHG
OR
V
BAT BAT_PChg
V
>V
RISE
SYS SYS_LIM
PAUSE
CHARGE
TIMER
I
>I
CHG CHG_DONE
FAST
CHARGE
(CONSTANT VOLTAGE
FAST
CHARGE
CV SUSPEND
MAINTAIN
CHARGE
ChgAutoStp =0"
T<T1 or T>T4
T1<T<T4
RESET CHARGE TIMER
)
ChgStat =101
LED=ON
ChgStat =100
LED=ON
ChgStat =001
LED=1.5s PERIOD
T<T1 or T>T4
I
<I
I
<I
CHG CHG_DONE
CHG CHG_DONE
I
=I
CHG FCHG
I
=0
CHG
AND
V
>V
RISE
SYS SYS_LIM
AND
T
<T
DIE CHG_LIM
t
MTCHG
RESET CHARGE TIMER
NOTES :
* VOLTAGE MODE IS AN INTERNAL SIGNAL
** CHARGE TIMER IS SLOWED BY 50% IF I
< I
CHG FCHG
/2 AND PAUSED IF I
< I /5 ONLY IN FAST CHARGE CONSTANT
CHG FCHG
CURRENT STATE WHERE I
IS THE EFFECTIVE FAST CHARGE CURRENT INCLUDING JEITA CURRENT LIMITATION
FCHG
Figure 5b. Battery Charger State Diagram (JEITA Monitoring with Charger Shutdown)
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2
Slave Address
I C Interface
The MAX20335 contain an I2C-compatible interface for
data communication with a host controller (SCL and
SDA). The interface supports a clock frequency of up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Set the Read/Write bit high to configure the MAX20335
to read mode (Table 3). Set the Read/Write bit low to
configure the MAX20335 to write mode. The address is
the first byte of information sent to the MAX20335 after
the START condition.
Bit Transfer
Start, Stop, And Repeated Start Conditions
2
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered control
signals (see theStart, Stop,And Repeated Start Conditions
section). Both SDA and SCL remain high when the bus
is not active.
When writing to the MAX20335 using I C, the master
sends a START condition (S) followed by the MAX20335
I C address. After the address, the master sends the
register address of the register that is to be programmed.
The master then ends communication by issuing a
STOP condition (P) to relinquish control of the bus, or
a REPEATED START condition (Sr) to communicate to
2
2
another I C slave. See Figure 6.
Single-Byte Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 7). The following
procedure describes the single byte write operation:
2
Table 3. I C Slave Addresses
1) The master sends a START condition
ADDRESS FORMAT
7-Bit Slave ID
HEX
0x28
0x50
0x51
BINARY
0101000
01010000
01010001
2) The master sends the 7-bit slave address plus a
write bit (low)
Write Address
Read Address
3) The addressed slave asserts an ACK on the data line
4) The master sends the 8-bit register address
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
S
Sr
P
6) The master sends 8 data bits
7) The slave asserts an ACK on the data line
8) The master generates a STOP condition
SCL
SDA
2
Figure 6. I C START, STOP and REPEATED START Conditions
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
A
8 DATA BITS
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 7. Write Byte Sequence
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Burst Write
Single Byte Read
In this operation, the master sends an address and
multiple data bytes to the slave device (Figure 8).
The slave device automatically increments the
register address after each data byte is sent. The following
procedure describes the burst write operation:
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 9). The following procedure describes the
single byte read operation:
1) The master sends a START condition
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a
write bit (low)
2) The master sends the 7-bit slave address plus a
write bit (low)
3) The addressed slave asserts an ACK on the data
line
3) The addressed slave asserts an ACK on the data
line
4) The master sends the 8-bit register address
4) The master sends the 8-bit register address
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
6) The master sends a REPEATED START condition
6) The master sends eight data bits
7) The slave asserts an ACK on the data line
8) Repeat 6 and 7 N-1 times
7) The master sends the 7-bit slave address plus a
read bit (high)
8) The addressed slave asserts an ACK on the data line
9) The slave sends eight data bits
9) The master generates a STOP condition
10) The master asserts a NACK on the data line
11) The master generates a STOP condition
BURST WRITE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
8 DATA BITS - 2
A
A
A
8 DATA BITS - 1
8 DATA BITS - N
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 8. Burst Write Sequence
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
A
REGISTER ADDRESS
8 DATA BITS
A
Sr
DEVICE SLAVE ADDRESS - R
NA
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 9. Read Byte Sequence
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9) The slave sends eight data bits
Burst Read
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (Figure 10). The following procedure describes the
burst byte read operation:
10) The master asserts an ACK on the data line
11) Repeat 9 and 10 N-2 times
12) The slave sends the last eight data bits
13) The master asserts a NACK on the data line
14) The master generates a STOP condition
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a
write bit (low)
Acknowledge Bits
3) The addressed slave asserts an ACK on the data
line
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX20335 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see Figure 11). To generate a NACK,
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
4) The master sends the 8-bit register address
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
6) The master sends a REPEATED START condition
7) The master sends the 7-bit slave address plus a
read bit (high)
8) The slave asserts an ACK on the data line
BURST READ
S
DEVICE SLAVE ADDRESS - W
DEVICE SLAVE ADDRESS - R
8 DATA BITS - 2
A
A
A
REGISTER ADDRESS
8 DATA BITS - 1
A
A
Sr
8 DATA BITS - 3
A
8 DATA BITS - N
NA
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 10. Burst Read Sequence
S
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 11. Acknowledge
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2
I C Register Descriptions
Table 4. ChipId Register (0x00)
ADDRESS:
MODE:
0x00
Read-Only
BIT
7
6
5
4
3
2
1
0
0
0
NAME
Chip_Id[7:0]
Chip_Id[7:0] bits show information about the version of the MAX20335.
Chip_Id[7:0]
Table 5. ChipRev Register (0x01)
ADDRESS:
MODE:
0x01
Read-Only
BIT
7
6
5
4
3
2
1
NAME
Chip_Rev[7:0]
Chip_Rev[7:0] bits show information about the revision of the MAX20335 silicon.
Chip_Rev[7:0]
Table 6. StatusA Register (0x02)
ADDRESS:
MODE:
BIT
0x02
Read-Only
7
6
5
4
3
2
1
NAME
—
—
ThermStat[2:0]
ChgStat[2:0]
Status of Thermistor Monitoring
000 = T < T1
001 = T1 < T < T2
010 = T2 < T < T3
011 = T3 < T < T4
100 = T > T4
ThermStat[2:0]
101 = No thermistor detected (THM high due to external pullup). Note that if a parallel resistor is used for
thermistor monitoring, this mode may not function properly.
110 = NTC input disabled through ThermEn[1:0]
111 = Detection disabled due to CHGIN not present.
Status of Charger Mode
000 = Charger off
001 = Charging suspended due to temperature (see Figure 5a and Figure 5b)
010 = Pre-charge in progress
011, 100 = Fast charge in progress
ChgStat[2:0]
101 = Maintain charge in progress
110 = Maintain charger timer done
111 = Charger fault condition (see Figure 5a and Figure 5b)
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Table 7. StatusB Register (0x03)
ADDRESS:
MODE:
BIT
0x03
Read-Only
7
6
5
4
3
2
1
0
Chg
ThrmSd
Chg
ThrmReg
NAME
UVLOLDO2 UVLOLDO3
ILim
UsbOVP
UsbOk
ChgTmo
Status of LDO2 UVLO
UVLOLDO2
0 = LDO2 in normal operating mode
1 = Undervoltage-lockout on LDO2
Status of LDO2 UVLO
UVLOLDO3
ILim
0 = LDO3 in normal operating mode
1 = Undervoltage-lockout on LDO3
CHGIN Input Current Limit
0 = CHGIN input current is within limit.
1 = CHGIN input is in current limit.
Status of CHGIN OVP
UsbOVP
UsbOk
0 = CHGIN OVP is not active.
1 = CHGIN OVP is active.
Status of CHGIN Input
0 = CHGIN Input is not present or outside of valid range.
1 = CHGIN Input is present and valid.
Status of Thermal Shutdown
ChgThrmSd
0 = Charger and input current limiter is in normal operating mode.
1 = Charger and input current limiter is in thermal shutdown.
Status of Thermal Regulation
0 = Charger is functioning normally, or disabled.
1 = Charger is running in thermal regulation mode and charging current is being actively reduced to prevent
device overheating.
ChgThrmReg
ChgTmo
Status of Time-Out Condition
0 = Charger is running normally, or disabled.
1 = Charger has reached a time-out condition. ChgStat =1 11 in this condition (see Figure 5).
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Table 8. StatusC Register (0x04)
ADDRESS:
MODE:
BIT
0x04
Read-Only
7
6
5
4
3
2
1
0
NAME
—
SysBLim
VLim
ThrmBuck1 ThrmBuck2 ThrmLDO1
ThrmLDO2
ThrmLDO3
Status of Minimum SYS-BAT Voltage Limit. While the system is powered from VBUS, the charger draws power
from SYS to charge the battery. If the total load exceeds the input current limit, an adaptive charger control loop
reduces charge current to prevent VSYS from collapsing. The regulation of the charge current starts when either
SysBLim
one of the following two conditions is true: 1. V
- V
= 100mV (typ) OR 2. V
= V (falling)
SYS
BAT
SYS
SYS_LIM
0 = Charge Current is normal.
1 = Charge Current is being actively reduced to prevent SYS collapse.
Status of CHGIN-SYS Voltage Limit. This bit indicates if the input current limit is being actively reduced to
maintain a 40mV drop between CHGIN-SYS. This adaptive input current limit prevents adapter collapse in the
case that a power adapter with insufficient load capability, or a high resistance charging cable is used.
0 = CHGIN input current limit is functioning normally.
VLim
1 = CHGIN input current limit is being actively reduced to maintain 40mV drop between CHGIN-SYS.
0 = Buck1 NOT in Thermal Off mode
1 = Buck1 in Thermal Off Mode
ThrmBuck1
ThrmBuck2
ThrmLDO1
ThrmLDO2
ThrmLDO3
0 = Buck2 NOT in Thermal Off mode
1 = Buck2 in Thermal Off Mode
0 = LDO1 NOT in Thermal Off mode
1 = LDO1 in Thermal Off Mode
0 = LDO2 NOT in Thermal Off mode
1 = LDO2 in Thermal Off Mode
0 = LDO3 NOT in Thermal Off mode
1 = LDO3 in Thermal Off Mode
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Battery Chargers for Small Lithium Ion Systems
Table 9. IntA Register (0x05)
ADDRESS:
MODE:
BIT
0x05
Clear On Read
7
6
5
4
3
2
1
0
Therm
StatInt
Chg
ThrmSdInt
Therm
RegInt
Chg
TmoInt
NAME
ChgStatInt
ILimInt
UsbOVPInt
UsbOk
ThermStatInt
ChgStatInt
ILimInt
Change in ThermStat caused interrupt.
Change in ChgStat caused interrupt, or first detection complete after POR.
Input current limit triggered caused interrupt.
Change in UsbOVP caused interrupt.
UsbOVPInt
UsbOk
Change in UsbOk caused interrupt.
ChgThrmSdInt Change in ChgThrmSd caused interrupt.
ThermRegInt
ChgTmoInt
Change in ChgThrmReg caused interrupt.
Change in ChgTmo caused interrupt.
Table 10. IntB Register (0x06)
ADDRESS:
MODE:
BIT
0x06
Clear On Read
7
6
5
4
3
2
1
0
Thrm
Buck1Int
Thrm
Buck2Int
Thrm
LDO1Int
Thrm
LDO2Int
Thrm
LDO3Int
NAME
—
SysBLimInt
VLimInt
SysBLimInt
VLimInt
Minimum SYS-BAT voltage limit caused interrupt
Input Voltage Limit caused interrupt
ThrmBuck1Int
ThrmBuck2Int
ThrmLDO1Int
ThrmLDO2Int
ThrmLDO3Int
Change in ThrmBuck1 caused interrupt.
Change in ThrmBuck2 caused interrupt.
Change in ThrmLDO1 caused interrupt.
Change in ThrmLDO2 caused interrupt.
Change in ThrmLDO3 caused interrupt.
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PMIC with Ultra-Low I Voltage Regulators and
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Battery Chargers for Small Lithium Ion Systems
Table 11. IntMaskA Register (0x07)
ADDRESS:
MODE:
BIT
0x07
Read/Write
7
6
5
4
3
2
1
0
Therm
StatIntM
Chg
StatIntM
Usb
OVPIntM
ChgThrm
SdIntM
Therm
RegIntM
Chg
TmoIntM
NAME
ILimIntM
UsbOkM
ThermStatIntM masks the ThermStatInt interrupt in the IntA register (0x05).
ThermStatIntM 0 = Mask
1 = Not masked
ChgStatIntM masks the ChgStatInt interrupt in the IntA register (0x05).
ChgStatIntM
ILimIntM
0 = Mask
1 = Not masked
ILimIntM masks the ILimInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
UsbOVPIntM masks the UsbOVPInt interrupt in the IntA register (0x05).
UsbOVPIntM
UsbOkM
0 = Mask
1 = Not masked
UsbOkM masks the UsbOk interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
ChgThrmSdIntM masks the ChgThrmSdInt interrupt in the IntB register (0x06).
0 = Mask
1 = Not masked
ChgThrm
SdIntM
ThermRegIntM masks the ThermRegInt interrupt in the IntA register (0x05).
ThermRegIntM 0 = Mask
1 = Not masked
ChgTmoIntM masks the ChgTmoInt interrupt in the IntA register (0x05).
ChgTmoIntM
0 = Mask
1 = Not masked
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PMIC with Ultra-Low I Voltage Regulators and
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Battery Chargers for Small Lithium Ion Systems
Table 12. IntMaskB Register (0x08)
ADDRESS:
MODE:
BIT
0x08
Read/Write
7
6
5
4
3
2
1
0
SysB
LimIntM
Thrm
Buck1IntM
Thrm
Buck2IntM
Thrm
LDO1IntM
Thrm
LDO2IntM
Thrm
LDO3IntM
NAME
—
VLimIntM
SysBLimIntM masks the SysBLimInt interrupt in the IntB register (0x06).
SysBLimIntM
0 = Mask
1 = Not masked
VLimIntM masks the VLimInt interrupt in the IntB register (0x06).
VLimIntM
0 = Mask
1 = Not masked
0 = Mask
ThrmBuck1
IntM
1 = Not masked
0 = Mask
ThrmBuck2
IntM
1 = Not masked
0 = Mask
ThrmLDO1
IntM
1 = Not masked
0 = Mask
ThrmLDO2
IntM
1 = Not masked
0 = Mask
ThrmLDO3
IntM
1 = Not masked
Table 13. ILimCntl Register (0x09)
ADDRESS:
MODE:
BIT
0x09
Read/Write* or Read-Only if Write-Protect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
SysMin[2:0]
—
—
—
ILimCntl [1:0]
SysMin sets System Voltage Minimum Threshold. When SYS drops to this level, the charger current is reduced.
000 = 3.6V
001 = 3.7V
010 = 3.8V
011 = 3.9V
100 = 4.0V
101 = 4.1V
110 = 4.2V
111 = 4.3V
SysMin[2:0]
CHGIN Custom Input Current Limit
(see Electrical Characteristics table for details)
00 = 0mA
ILimCntl[1:0]
01 = 100mA
10 = 500mA
11 = 1000mA
*Register is reset to default value upon CHGIN rising edge.
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Battery Chargers for Small Lithium Ion Systems
Table 14. ChgCntlA Register (0x0A)
ADDRESS:
MODE:
BIT
0x0A
Read/Write* or Ready-Only if Write-Protect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
BatReChg[1:0]
BatReg[3:0]
ChgEn
Recharge Threshold in Relation to BatReg
00 = BatReg - 70mV
01 = BatReg - 120mV
BatReChg[1:0]
10 = BatReg - 170mV
11 = BatReg - 220mV
Setting the Battery Regulation Threshold
0000 = 4.05V
0001 = 4.10V
0010 = 4.15V
0011 = 4.20V
0100 = 4.25V
0101 = 4.30V
0110 = 4.35V
BatReg[3:0]
0111 = 4.4V
1000 = 4.45V
1001 = 4.5V
1010 = 4.55V
1011 = 4.6V
1100…1111 = Reserved
On/Off Control for Charger (does not affect SYS node).
0 = Charger disabled.
ChgEn
1 = Charger enabled.
*Register is reset to default value upon CHGIN rising edge.
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Table 15. ChgCntlB Register (0x0B)
ADDRESS:
MODE:
BIT
0x0B
Read/Write* or Ready-Only if Write-Protect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
-
VPChg[2:0]
IPChg[1:0]
ChgDone[1:0]
Pre-charge voltage threshold setting
000 = 2.10V
001 = 2.25V
010 = 2.40V
VPChg[2:0]
111 = 2.55V
100 = 2.70V
101 = 2.85V
110 = 3.00V
111 = 3.15V
Pre-charge current setting
00 = 0.05 x I
FChg
FCHG
FChg
IPChg[1:0]
01 = 0.1 x I
10 = 0.2 x I
11 = 0.3 x I
FChg
Charge Done Threshold Setting
00 = 0.05 x I
FChg
ChgDone[1:0]
01 = 0.1 x I
10 = 0.2 x I
11 = 0.3 x I
FChg
FChg
FChg
*Register is reset to default value upon CHGIN rising edge.
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PMIC with Ultra-Low I Voltage Regulators and
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Table 16. ChTmr Register (0x0C)
ADDRESS:
MODE:
BIT
0x0C
Read/Write* or Ready-Only if Write-Protect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
ChgAutoStp
ChpAutoReSta
MtChgTmr[1:0]
FChgTmr[1:0]
PChgTmr[1:0]
Charger Auto-Stop. Controls the transition from Maintain Charger to Maintain Charger Done.
ChgAutoStp
0 = Auto-stop disabled.
1 = Auto-stop enabled.
Charger Auto-Restart Control
0 = Charger remains in maintain charge done even when VBAT is less than charge restart threshold (see
Charger state diagram)
ChgAutoReSta
1 = Charger automatically restarts when VBAT drops below charge restart threshold
Maintain Charge Timer Setting
00 = 0min
01 = 15min
MtChgTmr
[1:0]
10 = 30min
11 = 60min
Fast-Charge Timer Setting
00 = 75min
FChgTmr[1:0]
PChgTmr[1:0]
01 = 150min
10 = 300min
11 = 600min
Precharge Timer Setting
00 = 30min
01 = 60min
10 = 120min
11 = 240min
*Register is reset to default value upon CHGIN rising edge.
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Table 17. Buck1Cfg Register (0x0D)
ADDRESS:
MODE:
BIT
0x0D
Read/Write
7
6
5
4
3
2
1
0
Buck1PFWDis
Reserved
NAME
Buck1Seq[2:0] (Read-only)
Buck1En[1:0]
Buck1 Enable Configuration (Read-Only)
000 = Disabled
001 = Reserved
010 = Enabled at 0% of Boot/POR Process Delay Control
Buck1Seq[2:0] 011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Reserved
110 = Reserved
111 = Controlled by Buck1En[1:0] after 100% of Boot/POR Process Delay Control
Buck1 Enable Configuration (effective only when Buck1Seq = 111)
00 = Disabled (Buck1 OUT not actively discharged unless in Hard Reset/ShutDown/Off Mode)
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
Buck1En[1:0]
Buck1PFWDis
Buck1 Freewheeling Behavior
0 = Freewheeling FET turn-on at inductor current zero-crossing.
1 = Freewheeling FET turn-on after the inductor current zero-crossing and LX node high.
For voltage settings > 1.5V, this setting can improve efficiency
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Table 18. Buck1VSet Register (0x0E)
ADDRESS:
MODE:
BIT
0x0E
Read/Write
7
6
5
4
3
2
1
0
NAME
Buck1LowEMI
—
Buck1VSet[5:0]
Buck1 BLX Rising/Falling Slopes Setting
Buck1LowEMI
0 = Normal rising/falling slopes on BLX
1 = Reduce the rising/falling slopes on BLX by a factor of three.
Buck1 Output Voltage Setting
Linear Scale from 0.7V to 2.275V in 25mV increments
Buck1VSet
[5:0]
000000 = 0.7V
000001 = 0.725V
…
111111 = 2.275V
Changes in output voltages are digitally ramped in 25mV increments every 80µs giving a maximum slew rates of 312.5V/s.
Table 19. Buck2Cfg Register (0x0F)
ADDRESS:
MODE:
BIT
0x0F
Read/Write or Read-Only if Write-Protect Enabled (See Table 38)
7
6
5
4
3
2
1
0
NAME
Buck2Seq[2:0] (Read-only)
Buck2En[1:0]
Buck2PFWDis
Reserved
Buck2 Enable Configuration (Read-only)
000 = Disabled
001 = Reserved
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Reserved
Buck2Seq[2:0]
110 = Reserved
111 = Controlled by Buck2En [1:0] after 100% of Boot/POR Process Delay Control
Buck2 Enable Configuration (effective only when Buck2Seq = 111)
00 = Disabled (Buck2 OUT not actively discharged unless in Hard Reset/ShutDown/Off Mode)
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
Buck2En[1:0]
Buck2PFWDis
Buck2 Freewheeling Behavior
0 = Freewheeling FET turn-on at inductor current zero-crossing.
1 = Freewheeling FET turn-on after the inductor current zero-crossing and LX node high.
For voltage settings > 1.5V, this setting can improve efficiency
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Table 20. Buck2VSet Register (0x10)
ADDRESS:
MODE:
BIT
0x10
Read/Write or Read-Only if WriteProtect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
Buck2LowEMI
—
Buck2VSet[5:0]
Buck1 BLX Rising/Falling Slopes Setting
Buck2LowEMI
0 = Normal rising/falling slopes on BLX
1 = Reduce the rising/falling slopes on BLX by a factor of three.
Buck2 Output Voltage Setting
Linear Scale from 0.7V to 3.85V in 50mV increments
000000 = 0.7V
000001 = 0.75V
...
Buck2VSet
[5:0]
111111 = 3.85V
Changes in output voltages are digitally ramped in 50mV increments every 40µs giving a maximum slew rates of 1250V/s.
Table 21. Buck1/2ISet Register (0x11)
ADDRESS:
MODE:
BIT
0x11
Read/Write
7
6
5
4
3
2
1
0
NAME
Buck2ISet[3:0]
Buck1ISet[3:0]
Buck2 Inductor Peak current setting. 25mA step
0000 = Reserved
0001 = Reserved
0010 = 50mA
...
Buck2ISet[3:0]
1111 = 375mA
Buck1 Inductor Peak Current Setting. 25mA step
0000 = Reserved
0001 = Reserved
0010 = 50mA
...
Buck1ISet[3:0]
1111 = 375mA
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Table 22. LDO1Cfg Register (0x12)
ADDRESS:
MODE:
BIT
0x12
Read/Write
7
6
5
4
3
2
1
0
LDO1Act
DSC
NAME
LDO1Seq[2:0] (Read Only)
—
LDO1En[1:0]
LDO1Mode
LDO1 Enable Configuration (Read-only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
LDO1Seq[2:0]
110 = Disabled
111 = Controlled by LDO1En[1:0] after 100% of Boot/POR Process Delay Control
LDO1 Active Discharge Control
0: LDO1 output will be actively discharged only in HardReset mode
LDO1ActDSC
1: LDO1 output will be actively discharged in HardReset mode and also when its Enable goes Low. The active
discharge circuit will continue to draw additional quiescent current as long at this bit is set to 1, even when the
LDO is disabled. (See EC table.)
LDO1 Enable Configuration (effective only when LDO1Seq = 111)
00 = Disabled
LDO1En[1:0]
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO1 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO1En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
LDO1Mode
Table 23. LDO1VSet Register (0x13)
ADDRESS:
MODE:
BIT
0x13
Read/Write or Read-Only if WriteProtect Enabled (see Table 38)
7
-
6
5
-
4
3
2
1
0
NAME
-
LDO1Vset[4:0]
LDO1 Output Voltage Setting
Linear Scale from 0.8V to 3.6V in 100mV increments
00000 = 0.8V
LDO1VSet[4:0] 00001 = 0.9V
…
11100 = 3.6V
>11101 = N/A
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Table 24. LDO2Cfg Register (0x14)
ADDRESS:
MODE:
BIT
0x14
Read/Write or Read-Only if Write-Protect Enabled (See Table 38)
7
6
5
4
3
2
1
0
LDO2Act
DSC
LDO2
Mode
NAME
LDO2Seq[2:0] (Read Only)
—
LDO2En[1:0]
LDO2 Enable Configuration (Read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
LDO2Seq[2:0]
110 = Disabled
111 = Controlled by LDO2En[1:0] after 100% of Boot/POR Process Delay Control
LDO2 Active Discharge Control
0 = LDO2 output will be actively discharged only in HardReset mode
LDO2ActDSC
1 = LDO2 output will be actively discharged in HardReset mode and also when its Enable goes Low. The active
discharge circuit will continue to draw additional quiescent current as long at this bit is set to 1, even when the
LDO is disabled. (See Electrical Characteristics table.)
LDO2 Enable Configuration (effective only when LDO2Seq = 111)
00 = Disabled – LDO’s OUT not actively discharged unless HardReset/ShutDown/Off Mode
01 = Enabled
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO2En[1:0]
LDO2Mode
LDO2 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO2En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
Table 25. LDO2VSet Register (0x15)
ADDRESS:
MODE:
BIT
0x15
Read/Write or Read-Only if WriteProtect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
—
—
—
LDO2Vset[4:0]
LDO2 Output Voltage Setting
Linear Scale from 0.9V to 4.0V in 100mV increments
00000 = 0.9V
00001 = 1.0V
...
LDO2VSet[4:0]
11111 = 4.0V
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Table 26. LDO3Cfg Register (0x16)
ADDRESS:
MODE:
BIT
0x16
Read/Write
7
6
5
4
3
2
1
0
LDO3Act
DSC
LDO3
Mode
NAME
LDO3Seq[2:0] (Read-Only)
—
LDO3En[1:0]
LDO3 Enable Configuration (Read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = Disabled
LDO3Seq[2:0]
110 = Disabled
111 = Controlled by LDO3En[1:0] after 100% of Boot/POR Process Delay Control
LDO3 Active Discharge Control
0 = LDO3 output will be actively discharged only in HardReset mode
LDO3ActDSC
1 = LDO3 output will be actively discharged in HardReset modes and also when its Enable goes Low. The active
discharge circuit will continue to draw additional quiescent current as long at this bit is set to 1, even when the
LDO is disabled. (See EC table.)
LDO3 Enable Configuration (effective only when LDO3Seq == 111)
00 = Disabled. LDO’s OUT not actively discharged unless in HardReset/ShutDown/Off Mode
01 = Enabled
LDO3En[1:0]
10 = Enabled when MPC0 is high (regardless of MPC1)
11 = Enabled when MPC1 is high (regardless of MPC0)
LDO3 Mode Control
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully ON or OFF depending on state of LDO3En. When FET is ON, the
output is unregulated. This setting is internally latched and can change only when the LDO is disabled.
LDO3Mode
Table 27. LDO3VSet Register (0x17)
ADDRESS:
MODE:
BIT
0x17
Read/Write or Read-Only if WriteProtect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
—
—
—
LDO3Vset[4:0]
LDO3 Output Voltage Setting
Linear Scale from 0.9V to 4.0V in 100mV increments
00000 = 0.9V
00001 = 1.0V
…
LDO3VSet[4:0]
11111 = 4.0V
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Battery Chargers for Small Lithium Ion Systems
Table 28. ThrmCfg Register (0x18)
ADDRESS:
MODE:
BIT
0x18
Read/Write* or Read-Only if WriteProtect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
T1T2IFchg[2:0]
T2T3IFchg[2:0]
ThermEn[1:0]
Fast Charge Current for T1-T2 Temperature Zone
000 = 0.2 x I
001 = 0.3 x I
010 = 0.4 x I
011 = 0.5 x I
100 = 0.6 x I
101 = 0.7 x I
110 = 0.8 x I
FChg
FChg
FChg
FChg
FChg
FChg
FChg
T1T2IFchg[2:0]
111 = 1 x I
FChg
Fast Charge Current for T2-T3 Temperature Zone
000 = 0.2 x I
001 = 0.3 x I
010 = 0.4 x I
011 = 0.5 x I
100 = 0.6 x I
101 = 0.7 x I
110 = 0.8 x I
FChg
FChg
FChg
FChg
FChg
FChg
FChg
T2T3IFchg[2:0]
111 = 1 x I
FChg
Thermistor Monitoring Mode
00 = Thermistor Monitoring Disabled
01 = Charging enabled between T1 and T3
10 = Charging enabled between T1 and T4
ThermEn[1:0]
11 = Charging enabled between T1 and T4, Voltage reduced below T2 and above T3
*Register is reset to default value upon CHGIN rising edge.
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Table 29. ThrmCfg Register (0x19)
ADDRESS:
MODE:
BIT
0x19
Read/Write* or Read-Only if WriteProtect Enabled (see Table 38)
7
6
5
4
3
2
1
0
NAME
—
—
—
—
—
T3T4IFchg[2:0]
Fast Charge Current for T3-T4 Temperature Zone
000 = 0.2 x I
001 = 0.3 x I
010 = 0.4 x I
011 = 0.5 x I
100 = 0.6 x I
101 = 0.7 x I
110 = 0.8 x I
FChg
FChg
FChg
FChg
FChg
FChg
FChg
T3T4IFchg[2:0]
111 = 1 x I
FChg
*Register is reset to default value upon CHGIN rising edge.
Table 30. MONCfg Register (0x1A)
ADDRESS:
MODE:
BIT
0x1A
Read/Write
7
6
5
4
3
2
1
0
NAME
—
—
MONRatioCfg[1:0]
MONHiZ
MONCtr[2:0]
MON Resistive Partition Selector
00 = 4:1
01 = 3:1
10 = 2:1
11 = 1:1
MONRatioCfg
MONHiZ
MON OFF MODE condition
0 = Pulled LOW by 100k pull-down resistor
1 = Hi-Z
MON Pin Source selection (40µs BBM after any change of MONCtr)
000 = MON is not connected to any internal node and its state depends on MONHiZ
001 = MON connected to a resistive partition of BATT
010 = MON connected to a resistive partition of SYS
MONCtr[2:0]
011 = MON connected to a resistive partition of BUCK1 OUT
100 = MON connected to a resistive partition of BUCK2 OUT
101 = MON connected to a resistive partition of LDO1 OUT
110 = MON connected to a resistive partition of LDO2 OUT
111 = MON connected to a resistive partition of LDO3 OUT
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Table 31. BootCfg Register (0x1B)
ADDRESS:
MODE:
BIT
0x1B
Read-Only
7
6
5
4
3
2
1
0
NAME
PwrRstCfg[3:0]
SftRstCfg
BootDly[1:0]
ChgAlwTry
PwrRstCfg
[3:0]
See Table 1
Soft Reset Register Default
SftRstCfg
0 = Registers do not reset to default values on soft reset
1 = Registers reset to default values on soft reset
Reset Delay Control (see Figure 2a, 2b)
00 = 80ms
01 = 120ms
10 = 220ms
11 = 420ms
BootDly[1:0]
UVLO Automatic Retry
If SYS UVLO condition occurs during boot process:
0 = Part latches off until CHGIN is removed and replaced
1 = Part retries after delay
ChgAlwTry
Table 32. PinStat Register (0x1C)
ADDRESS:
MODE:
BIT
0x1C
Read Only
7
6
5
4
3
2
PFN2
1
0
NAME
ILim_T[2:0]
-
PFN1
MPC1
MPC0
Monitor of The Input limiter Current Setting
000 = Input Limiter Off
001 = 100mA
ILim_T[2:0]
010 = 500mA
100 =1A
PFN1 Input State
0 = pin low
1 = pin high
PFN1
PFN2
MPC1
MPC0
PFN2 In/Out State
0 = pin low
1 = pin high
MPC1 Input State
0 = pin low
1 = pin high
MPC0 Input State
0 = pin low
1 = pin high
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PMIC with Ultra-Low I Voltage Regulators and
Q
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Table 33. Buck1/2Extra Control Register (0x1D)
ADDRESS:
MODE:
BIT
0x1D
Read/Write
7
6
5
4
3
2
1
0
Buck2
Buck2
FFET
Buck1
Buck1
NAME
Buck2IAdptEnb
Buck2Fst
Buck1IAdptEnb Buck1Fst
ActDSC
ActDSC
FFET
Buck 2 Peak Current
Buck2IAdptEnb 0 = Enable adaptive peak current
1 = Peak current set by Buck2ISet[3:0]
Buck2 Fast Start
Buck2Fst
0 = Normal startup current limit
1 = Double the startup current to reduce the startup time by half
Buck2 Active Discharge Control
0 = Buck2 output will be actively discharged only in HardReset mode
Buck2ActDSC
Buck2FFET
1 = Buck2 output will be actively discharged in HardReset mode and also when its Enable goes Low. Note, when
BuckActDSC=1, the active discharge circuit will remain active and draw additional quiescent current even when
Buck2 is disabled.
Buck2 Force FET scaling (reduces active FET size by 50% and increases efficiency for loads <100mA.)
0 = FET Scaling disabled
1 = FET Scaling enabled
Buck 1 Peak Current
Buck1IAdptEnb 0 = Enable adaptive peak current
1 = Peak current set by Buck1ISet[3:0]
Buck1 Fast Start
Buck1Fst
0 = Normal startup current limit
1 = Double the startup current to reduce the startup time by half
Buck1 Active Discharge Control
0 = Buck1 output will be actively discharged only in HardReset mode
1 = Buck1 output will be actively discharged in HardReset mode and also when its Enable goes Low. Note, when
BuckActDSC=1, the active discharge circuit will remain active and draw additional quiescent current even when
Buck2 is disabled.
Buck1ActDSC
Buck1FFET
Buck1 Force FET Scaling (reduces active FET size by 50% and increases efficiency for loads <100mA.)
0 = FET Scaling only enabled during the Buck1 Turn-On Sequence
1 = FET Scaling enabled during the Buck1 Turn-On Sequence and also in the Buck1 Steady ON state
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Table 34. PwrCfg Register (0x1E)
ADDRESS:
MODE:
BIT
0x1E
Read/Write
7
6
5
4
3
2
1
0
PFNx
ResEna
NAME
–
–
–
–
–
–
StayOn
PFN_ PFNx Automatic Internal Pull-Up/Pull-Down Enable
0 = No internal pullup/pulldown
PFNxResEna
1 = Automatic internal pullup/pulldown as per Table 1
This bit is used to ensure that the processor booted correctly. This bit must be set within 5s of power-on to
prevent the part from shutting down and returning to the power-off condition. This bit has no effect after being
StayOn
set.
0 = Shut down 5s after power-on
1 = Stay on
Table 35. PwrCmd Register (0x1F)
ADDRESS:
MODE:
BIT
0x1F
Read/Write
7
6
5
4
3
2
1
0
NAME
PWR_CMD[7:0]
Power Command Register
Writing the following values issues the command listed:
0xB2 = places the part in off mode
0xC3 = issues a hard reset (power cycle)
0xD4 = issues a soft reset (reset pulse only)
PWR_CMD
[7:0]
After the written value has been validated by the internal logic, this register is cleared automatically. Any other
commands will be ignored. See Table 1 for the available PwrCmd for each PwrRstCfg value.
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Input Capacitor Selection
Applications Information
The input capacitors of the buck converters reduce the
current peaks drawn from the battery or input power
source and reduces switching noise in the IC. The impedance
of the input capacitors at the switching frequency should
be kept very low. Ceramic capacitors are recommended
due to their small size and low ESR. Make sure the
capacitor maintains its capacitance over temperature and
DC bias. Capacitors with X5R or X7R temperature
characteristics perform well in most applications.
The buck converters of the MAX20335 are optimized for
use with a tiny inductor and small ceramic capacitors. The
correct selection of external components ensures high
efficiency, low output ripple, and fast transient response.
Inductor Selection
A 2.2µH inductor is recommended for use with the
MAX20335 buck converters. Table 36 lists recommended
inductors for use depending on whether a given application
requires highest efficiency, or a compromise between
high efficiency and small size.
PCB Layout and Routing
High switching frequencies and large peak currents make
PCB layout a very important part of design. Good design
minimizes excessive EMI on the feedback paths and
voltage gradients in the ground plane, both of which can
result in instability or regulation errors. Connect the inductor,
input capacitor, and output capacitor as close together as
possible, and keep their traces short, direct, and wide.
Connect the two GND pins under the IC and directly to the
grounds of the input and output capacitors. Keep noisy
traces, such as the LX node, as short as possible.
Output Capacitor Selection
The output capacitors of the MAX20335 buck converters
are required to keep the output voltage ripple small and
to ensure regulation loop stability. A 10µF output capacitor
with Buck_ISet[3:0] = 150mA and Buck_IAdptEnb = 0 is
suggested to cover all the possible output voltage/load
current cases. If a lower output cap are needed, please
refer to Table 37 for the minimum allowed capacitor size).
Ceramic capacitors are recommended due to their small
size and low ESR and care should be taken to ensure
that the selected capacitor maintains its capacitance
over temperature and voltage bias. Capacitors with X5R
or X7R temperature characteristics perform well in most
applications.
Table 36. Suggested Inductors
INDUCTANCE
(µH)
DC RESISTANCE
CURRENT
RATING (mA)
DIMENSIONS
L x W x H (mm)
MANUFACTURER
SERIES
NOTES
(mΩ)
Optimized for
highest efficiency
BOURNS
SRP2010
2.2
2.2
168
2200
2.0 x 1.6 x 1.0
1.6 x 0.8 x 1.0
Optimized for
smallest size
MURATA
MFD160810
310
1400
Table 37. Output Capacitor Values*
OUTPUT VOLTAGE
(V)
OUTPUT CAPACITOR MINIMUM VALUES
(µF)
BUCK_ISET[3:0]
<150mA
<200mA
<175mA
>1.4V
>1.2V
>0.8
2.2
4.7
10
*Minimum Output Capacitor Values are given for L = 2.2µH
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Table 38. Register Bit Default Values
REGISTER BITS
Buck1IZCSet[1:0]
Buck1VSet[5:0]
Buck1ISet[3:0]
Buck1En[1:0]
Buck1Seq[2:0]
Buck2IZCSet[1:0]
Buck2VSet[5:0]
Buck2ISet[3:0]
Buck2En[1:0]
Buck2Seq[2:0]
LDO1Mode
EVKIT
MAX20335A
MAX20335B
MAX20335D
10mA
MAX20335F
20mA
REGISTER BITS
Buck1IZCSet[1:0]
Buck1VSet[5:0]
Buck1ISet[3:0]
Buck1En[1:0]
Buck1Seq[2:0]
Buck2IZCSet[1:0]
Buck2VSet[5:0]
Buck2ISet[3:0]
Buck2En[1:0]
Buck2Seq[2:0]
LDO1Mode
MAX20335G
20mA
MAX20335J
20mA
20mA
10mA
20mA
1.2V
0.7V
1.8V
0.7V
1.8V
1.8V
1.9V
150mA
Disabled
Buck1En
20mA
150mA
Enabled
Buck1En
20mA
150mA
Enabled
Buck1En
20mA
150mA
Disabled
Buck1En
20mA
150mA
Disabled
0% Boot
40mA
150mA
Disabled
Disabled
30mA
150mA
Enabled
Buck1En
20mA
1.8V
1.8V
1.2V
1.8V
3.3V
3V
3.3V
150mA
Disabled
Buck2En
LDO
150mA
Enabled
0% Boot
LDO
150mA
Enabled
Buck2En
LDO
150mA
Enabled
0% Boot
LDO
150mA
Disabled
Buck2En
LDO
200mA
Enabled
0% Boot
Switch
150mA
Disabled
Buck2En
LDO
LDO1VSet[4:0]
LDO1En[1:0]
LDO1Seq[2:0]
LDO2Mode
0.8V
3V
3.6V
3.3V
1.8V
LDO1VSet[4:0]
LDO1En[1:0]
LDO1Seq[2:0]
LDO2Mode
3V
3.3V
Disabled
LDO1En
LDO
Disabled
LDO1En
Switch
Enabled
LDO1En
Switch
Disabled
LDO1En
LDO
Disabled
LDO1En
LDO
Disabled
LDO1En
LDO
Disabled
LDO1En
LDO
LDO2VSet[4:0]
LDO2En[1:0]
LDO2Seq[2:0]
LDO3Mode
0.9V
3.5V
1.8V
3V
1.8V
LDO2VSet[4:0]
LDO2En[1:0]
LDO2Seq[2:0]
LDO3Mode
1.8V
3.4V
Disabled
LDO2En
LDO
Disabled
LDO2En
Switch
Enabled
LDO2En
LDO
Disabled
LDO2En
LDO
Disabled
LDO2En
LDO
Enabled
25% Boot
LDO
Disabled
LDO2En
LDO
LDO3VSet[4:0]
LDO3En[1:0]
LDO3Seq[2:0]
VPchg[2:0]
0.9V
3.5V
1.3V
3V
1.8V
LDO3VSet[4:0]
LDO3En[1:0]
LDO3Seq[2:0]
VPchg[2:0]
1.8V
3.3V
Disabled
LDO3En
3.00V
Disabled
LDO3En
2.85V
Enabled
LDO3En
3.00V
Disabled
LDO3En
3.00V
Disabled
LDO3En
3.00V
Enabled
50% Boot
3.00V
Disabled
LDO3En
3.00V
IPChg[1:0]
0.10 x IFChg
30min
0.10 x IFChg
30min
0.05 x IFChg
30min
0.20 x IFChg
30min
0.10 x IFChg
30min
IPChg[1:0]
0.10 x IFChg
30min
0.05 x IFChg
30min
PChgTmr[1:0]
FChgTmr[1:0]
MtChgTmr[1:0]
BatReg[3:0]
PChgTmr[1:0]
FChgTmr[1:0]
MtChgTmr[1:0]
BatReg[3:0]
150min
0min
300min
60min
300min
0min
300min
30min
150min
0min
150min
0min
300min
0min
4.20V
4.20V
4.20V
4.35V
4.20V
4.20V
4.20V
BatReChg[1:0]
ChgEn
-220mV
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
Thermistor
1.0 x IFChg
1.0 x IFChg
1.0 x IFChg
Retry
-120mV
Enabled
0.05 x IFChg
Enabled
Enabled
Done
-120mV
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
JEITA 1
0.5 x IFChg
1.0 x IFChg
1.0 x IFChg
Retry
-120mV
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
JEITA 1
0.2 x IFChg
1.0 x IFChg
0.2 x IFChg
Latch Off
-70mV
BatReChg[1:0]
ChgEn
-220mV
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
JEITA 2
0.2 x IFChg
1.0 x IFChg
1.0 x IFChg
Latch Off
-120mV
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
Off
Enabled
0.10 x IFChg
Enabled
Enabled
Charge
JEITA 1
1.0 x IFChg
1.0 x IFChg
1.0 x IFChg
Latch Off
ChgDone[1:0]
ChgAutoStp
ChgDone[1:0]
ChgAutoStp
ChgAutoSta
ChgAutoSta
FrshBatDis
FrshBatDis
ThermEn[1:0]
T1_T2_IFchg[2:0]
T2_T3_IFchg[2:0]
T3_T4_IFchg[2:0]
ChgAlwTry
JEITA 1
1.0 x IFChg
1.0 x IFChg
1.0 x IFChg
Retry
ThermEn[1:0]
T1_T2_IFchg[2:0]
T2_T3_IFchg[2:0]
T3_T4_IFchg[2:0]
ChgAlwTry
0.5 x IFChg
1.0 x IFChg
1.0 x IFChg
Retry
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Table 38. Register Bit Default Values (continued)
REGISTER BITS
ILimCntl[1:0]
PwrRstCfg[3:0]
PFNxResEna
BootDly[1:0]
SftRstCfg
EVKIT
MAX20335A
MAX20335B
MAX20335D
MAX20335F
REGISTER BITS
ILimCntl[1:0]
PwrRstCfg[3:0]
PFNxResEna
BootDly[1:0]
SftRstCfg
MAX20335G
MAX20335J
500mA
500mA
500mA
500mA
500mA
500mA
500mA
On/Off (0000)
Disabled
(80 + 34)ms
Reset
KIN(0110)
Enabled
(120 + 34)ms
Hold
CR Low(0101) Custom1(0111) Rst Fall(0011)
Rst Rise(0010) CR Low(0101)
Disabled
(80 + 34)ms
Reset
Enabled
(80 + 34)ms
Reset
Enabled
(80 + 34)ms
Reset
Disabled
(80 + 34)ms
Reset
Disabled
(80 + 34)ms
Reset
SysMin[2:0]
Write-Protect
StayOn
3.6V
3.6V
3.6V
3.6V
3.6V
SysMin[2:0]
Write-Protect
StayOn
3.6V
3.6V
Writable
Stay On
Writable
Stay On
Writable
Stay On
Writable
Stay On
Writable
Writable
Writable
Stay On
Stay On
Stay On
T1,T2,T3,T4
0,10,45,60 °C 0,10,25,45 °C 0,10,25,45 °C 0,10,45,60 °C
0,10,45,60 °C
T1,T2,T3,T4
0,10,25,45 °C
0,10,45,60 °C
Table 39. Register Default Values
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
ADDRESS
REGISTER
NAME
EVKIT
MAX20335A MAX20335B
MAX20335D
MAX20335F
MAX20335G
MAX20335J
0x00
0x01
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1D
0x1E
0x1F
ChipId
ChipRev
0x04
0x00
0x00
0x00
0x02
0x67
0x65
0xC4
0xE1
0x14
0xE1
0x16
0x66
0xE0
0x00
0xE0
0x00
0xE0
0x00
0xFD
0x07
0x00
0x09
0x00
0x01
0x00
0x04
0x00
0x00
0x00
0x02
0x27
0x54
0xF8
0xE8
0x00
0x49
0x16
0x66
0xE0
0x16
0xE1
0x1A
0xE1
0x1A
0xFE
0x07
0x00
0x63
0x00
0x81
0x00
0x04
0x00
0x00
0x00
0x02
0x27
0x61
0xC8
0xE9
0x2C
0xE9
0x0A
0x66
0xE2
0x1C
0xE3
0x09
0xE2
0x04
0x7E
0x07
0x00
0x59
0x00
0x01
0x00
0x04
0x00
0x00
0x00
0x02
0x2D
0x69
0xE8
0xE0
0x00
0x49
0x16
0x66
0xE0
0x19
0xE0
0x15
0xE0
0x15
0x1E
0x00
0x00
0x78
0x00
0x81
0x00
0x04
0x00
0x00
0x00
0x02
0x07
0x65
0xC4
0x41
0x2C
0xE3
0x34
0x66
0xE0
0x0A
0xE0
0x09
0xE0
0x09
0xFE
0x07
0x00
0x38
0x00
0x81
0x00
0x00
0x01
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1D
0x1E
0x1F
ChipId
ChipRev
0x04
0x00
0x00
0x00
0x02
0x67
0x65
0xC4
0x01
0x2C
0x4A
0x2E
0x86
0xE1
0x16
0x62
0x09
0x82
0x09
0x1F
0x07
0x00
0x28
0x00
0x01
0x00
0x04
0x00
0x00
0x00
0x02
0x27
0x61
0xC8
0xE9
0x30
0xE1
0x34
0x66
0xE0
0x19
0xE0
0x19
0xE0
0x18
0x7C
0x07
0x00
0x59
0x00
0x01
0x00
IntMaskA
IntMaskB
ILimCntl
IntMaskA
IntMaskB
ILimCntl
ChgCntlA
ChgCntlB
ChTmr
ChgCntlA
ChgCntlB
ChTmr
Buck1Cfg
Buck1VSet
Buck2Cfg
Buck2Vset
BuckISet
LDO1Cfg
LDO1VSet
LDO2Cfg
LDO2VSet
LDO3Cfg
LDO3VSet
THRMCFA
THRMCFB
MONCFG
BOOTCFG
Buck1/2Extra
PwrCfg
Buck1Cfg
Buck1VSet
Buck2Cfg
Buck2Vset
BuckISet
LDO1Cfg
LDO1VSet
LDO2Cfg
LDO2VSet
LDO3Cfg
LDO3VSet
THRMCFA
THRMCFB
MONCFG
BOOTCFG
Buck1/2Extra
PwrCfg
PwrCmd
PwrCmd
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PMIC with Ultra-Low I Voltage Regulators and
Q
Battery Chargers for Small Lithium Ion Systems
Chip Information
PROCESS: BiCMOS
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX20335AEWX+
MAX20335AEWX+T
MAX20335BEWX+
MAX20335BEWX+T
MAX20335DEWX+
MAX20335DEWX+T
MAX20335FEWX+
MAX20335FEWX+T
MAX20335GEWX+
MAX20335GEWX+T
MAX20335JEWX+
MAX20335JEWX+T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
36 WLP
+Denotes a lead(Pb)-free package/RoHS-compliant package.
T = Tape and reel.
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Q
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Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/18
Initial release
—
Updated the Electrical Characteristics table, Table 38, Table 39, and added
MAX20335BEWX+ to the Ordering Information table
1
2
3
4
10/18
3/19
7/19
9/19
16, 64–66
26, 64–66
64–66
Updated the Bump Description, Table 38, Table 39, and added MAX20335BEWX+T,
MAX20335DEWX+ and MAX20335DEWX+T to the Ordering Information table
Updated Table 38, Table 39, and added MAX20335FEWX+ and MAX20335FEWX+T
to the Ordering Information table
Removed future product designation from the MAX20335FEWX+ and
MAX20335FEWX+T to the Ordering Information table
66
Updated Tables 38 and 39 and added MAX20335GEWX+ and MAX20335GEWX+T
to the Ordering Information table
64–66
5
6
1/20
6/21
Updated Tables 38 and 39 and added MAX20335JEWX+ and MAX20335JEWX+T to
the Ordering Information table
64–66
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
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are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2021 Maxim Integrated Products, Inc.
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