MAX20743EPL+T [MAXIM]
Integrated, Step-Down Switching Regulator with PMBus;
| 型号： | MAX20743EPL+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Integrated, Step-Down Switching Regulator with PMBus |
| 文件： | 总31页 (文件大小：1029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
General Description
Benefits and Features
● High-Power Density and Low Component Count
The MAX20743 is a fully integrated, highly efficient
switching regulator with PMBus™ for applications
operating from 4.5V to 16V and requiring up to 35A
maximum load. This single-chip regulator provides
extremely compact, high-efficiency power delivery
solutions with high-precision output voltages and excellent
transient response for networking, datacom and telecom
equipment.
2
• Overall Solution Size 509mm Including Inductor
and Output Capacitors
• 90.8% Peak Efficiency with V
= 12V and
DDH
V
= 1V
OUT
• Fast Transient Response: Supports Up to 300A/μs
Load-Step Transients
● Optimized Component Performance and Efficiency
with Reduced Design-In Time
The IC offers a broad range of programmable features
through either the PMBus or through a capacitor and
resistor connected to a dedicated programming pin.
Using this feature, the operation can be optimized for a
specific application, reducing the component count and/
or setting appropriate trade-offs between the regulator’s
performance and system cost. Ease of programming
enables using the same design for multiple applications.
• PMBus-Compliant Interface for Telemetry and
Power Management
• Voltage, Current and Temperature Reporting
through Digital Bus
● Increased Power-Supply Reliability with System and
IC Self-Protection Features
• Differential Remote Sense with Open-Circuit
Detection
• Hiccup Overcurrent Protection
• Programmable Thermal Shutdown
The IC includes protection and telemetry features. Positive
and negative cycle-by-cycle overcurrent protection and
overtemperature protection ensure a rugged design. Input
undervoltage lockout shuts down the device to prevent
operation when the input voltage is out of specification.
A status pin provides an output signal to show that the
output voltage is within range and the system is regulating.
Typical System Efficiency vs.
Load Current (V
= 12V)
DDH
100
95
90
85
80
75
70
65
60
55
50
Applications
● Communication Equipment
● Networking Equipment
● Servers and Storage Equipment
● Point-of-Load Voltage Regulators
● μP Chipset
● Memory V
VOUT= 5V
= 3.3V
= 1.8V
VOUT
VOUT = 1.2V
VOUT = 1V
DDQ
V
OUT
● I/O
CURRENT
RATING* VOLTAGE
INPUT
OUTPUT
VOLTAGE
VOUT = 0.8V
VOUT = 0.65V
DESCRIPTION
Electrical Rating
Thermal Rating
35A
34A
4.5V to 16V 0.6V to 5.5V
0
5
10
15
20
25
30
35
IOUT (A)
12V
12V
1V
1V
T
= 55°C, 200LFM
A
Ordering Information appears at end of data sheet.
Thermal Rating
= 85°C, 0LFM
22A
T
A
*For specific operating conditions, refer to the SOA curves in
PMBus is a trademark of SMIF, Inc.
the Typical Operating Characteristics section.
19-8582; Rev 1; 10/16
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Absolute Maximum Ratings
Input Pin Voltage (V
) (Note 1) ........................-0.3V to +18V
Switching Node Voltage (VX) DC..........................-0.3V to +18V
Switching Node Voltage (VX) 25ns (Note 2)..........-10V to +23V
(BST - VX) Pin Differential ...................................-0.3V to +2.5V
DDH
V
..........................................................................-0.3V to +2V
CC
STAT, OE, CLK, DATA, and
SMALERT Pin Voltages.......................................-0.3V to +4V
Junction Temperature (T )...............................................+150°C
J
PGMA, PGMB, V
and
Storage Temperature Range............................ -65°C to +150°C
Peak Reflow Temperature Lead-Free .............................+260°C
SENSE+
V
Pin Voltages .........................................-0.3V to +2V
SENSE-
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Operating Ratings
Input Voltage (V
)................................................4.5V to 16V
Maximum Average Input Current (I
) (Note 3).................6A
DDH
VDDH
Junction Temperature (T )................................ -40°C to +125°C
Maximum Average Output Current (I
) ............................35A
J
OUT
Peak Output Current (I ).....................................................60A
PK
Package Information
PACKAGE CODE
P154A8F+1
Outline Number
21-100031
Land Pattern Number
90-100022
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
13°C/W
JA
Junction to Case (θ
(Still Air, No Heatsink; Note 4)
)
JC
0.47°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Note 1: As measured at the V
pin referenced to the GND pin immediatly adjacent using a high-frequency scope probe with I
LOAD
DDH
at I
. A high-frequency input bypass capacitor must be located less than 60 mils from the V
pin per our design guide-
MAX
DDH
lines.
Note 2: The 25ns rating is the allowable voltage on the VX node in excess of the -0.3V to +18V DC ratings. The VX voltage can exceed
the DC rating in either the positive or negative direction for up to 25ns per cycle.
Note 3: See the Average Input Current Limit section.
Note 4: Data taken using the MAX20743 evaluation kit (MAX20743EVKIT#). The PCB has 4 layers of 2oz copper.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics
(Circuit of Figure 6, V
= 4.5V to 16V, T = +32°C, unless otherwise noted. Typical values are at T = +32°C. All devices 100%
DDH
A
A
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER
SUPPLY VOLTAGE
SYMBOL
CONDITIONS
MIN
4.5
TYP
MAX
16
UNITS
V
Supply Voltage Range
OUTPUT VOLTAGE (Note 5)
Output-Voltage Range
V
T = -40°C to +125°C
DDH
OUT
J
V
(Note 6)
0.6
5.5
V
1
2
4
Default is 1mV/μs; other values are set
Slew Rate when V
Changed through PMBus
is
OUT
through PMBus; measured at V
pins
mV/μs
SENSE+/-
V
REF
0.6484
0.8984
1.0
V
Values
Selected by C_SELA (Note 7)
V
BOOT
0.6484V V
0.8984V V
-1.2
-1.0
-1.0
+1.2
+1.0
+1.0
REF
REF
Referred to
pins
(Notes 6, 8)
V
REF
V
Tolerance
V
%
V
REF
SENSE+/-
1V V
REF
Values Available through PMBus
Command
See Table 8 for accuracy vs. V
(Note 7)
REF
0.6016
1.0
FEEDBACK LOOP
Integrator Recovery Time
Constant
t
20
μs
REC
0.72
1.4
0.9
1.8
3.6
1.1
2.2
4.4
Gain (see the Control Loop
section for details)
Selected by R_SELB or PMBus
(Notes 6, 7, 8, 9)
R
mV/A
GAIN
2.9
SWITCHING FREQUENCY
400
500
600
700
800
900
400kHz/600kHz/800kHz selected by C_
SELB; other values are set through PMBus
(Note 7)
Switching Frequency
kHz
%
f
SW
Switching Frequency Accuracy
(Notes 6, 8, 9)
(Note 6)
-15
+15
INPUT PROTECTION
V
V
UVLO Threshold (Rising)
UVLO Threshold (Falling)
4.25
3.9
4.47
DDH
V
V
3.75
DDH
DDH_UVLO
Hysteresis
350
mV
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, V
= 4.5V to 16V, T = +32°C, unless otherwise noted. Typical values are at T = +32°C. All devices 100%
A A
DDH
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT-VOLTAGE PROTECTION (OVP)
Overvoltage-Protection Threshold
(Rising)
Relative to programmed V
Relative to programmed V
10
13
8
16
%
µs
%
OUT
OUT
OVP
OVP Deglitch Filter Time
Power-Good Protection Threshold
(Falling)
6
3
9
12
9
PWRGD
Power-Good Protection Threshold
(Rising)
6
8
%
Power-Good Deglitch Filter Time
µs
OVERCURRENT PROTECTION (OCP)
OCP Setting 0
OCP Setting 1
OCP Setting 2
11.8
16.0
19.8
18.9
24.1
29.2
26.0
32.2
38.6
Positive OCP Inception
Threshold (Inductor Valley
Current)
Selected by R_SELB
or PMBus
(Notes 6, 7, 8, 9)
A
OCP Setting 3
24.5
34.1
43.8
OCP
OCP Setting 0
OCP Setting 1
-26.4
-31.3
Negative OCP Inception
Threshold (Inductor Valley
Current)
Selected by R_SELB
or PMBus
A
OCP Setting 2
OCP Setting 3
-36.0
-40.8
20
Hysteresis
Hysteresis applies only to positive OCP
%
OVERTEMPERATURE PROTECTION (OTP)
120
140
130
150
10
140
160
Default is 150°C; 130°C is set through
PMBus (Notes 7, 8, 9)
OTP Inception Threshold
OTP
°C
Hysteresis
OE MAXIMUM VOLTAGE
OE Maximum Voltage
3.6
Full V
supply range; measured at the
CC
Rising Threshold
OE pin; keep OE ≤ V
– 2.5V and ≤
0.83
0.9
0.97
V
DDH
3.6V (Note 6)
OE
Hysteresis
0.2
OE Pin Input Resistance
OE Deglitch Filter Time
200
0.9
275
350
2.2
kΩ
(Note 9)
µs
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, V
= 4.5V to 16V, T = +32°C, unless otherwise noted. Typical values are at T = +32°C. All devices 100%
A A
DDH
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER SYMBOL CONDITIONS
STARTUP TIMING
MIN
TYP
MAX
UNITS
Enable Time from OE Rise to
Start of BST Charge
t
After t
16
µs
OE
INIT
0.75
1.5
3
3ms or 1.5ms can be bet by R_SELA; any
value can be set by PMBus (Note 7)
Soft-Start Ramp Time
t
ms
SS
6
BST Charging Time
STAT PIN
t
8
µs
V
BST
Pullup Voltage
VOH
3.6
0.4
STAT
I
I
= 2.5mA
STAT
STAT
= 0.2mA, 0V < V
< UVLO and
CC
0.65
0.75
7
0V < V
< UVLO (Note 6)
Status Output Low
VOL
V
DDH
STAT
I
= 1.3mA, 0V < V
< UVLO and
STAT
CC
0V < V
< UVLO (Note 6)
DDH
Status Output High Leakage
Current
STAT pulled up to 3.3V through 20kΩ
(Note 6)
I
t
µA
µs
STAT
125
Time from V
Ramp
STAT output low to high, default is 125;
2000 can be set through PMBus (Note 7)
OUT
STAT
Completion to STAT Pin Released
2000
PGMA AND PGMB PINS (see Tables 2–5)
Allowable R_SEL Resistor Range
12 resistor values detected
1.78
0
162
kΩ
R_SEL Resistor Required
Accuracy
EIA standard resistor values only
±1
%
Allowable C_SEL Capacitor
Range
3 options (0pF, 220pF, or 1000pF)
Use X7R or better
1000
pF
%
C_SEL Capacitor Required
Accuracy
±20
Load and stray capacitance in addition to
C_SELA/B
Allowable External Capacitance
20
16
pF
PMBus TELEMETRY
Reading Range
4.5
-3
V
Reading Update Interval
5
1
ms
ms
%
V
DDH
Reading Averaging Interval
Reading Error
Readback
T
= -40°C to T = 125°C (Notes 8, 9, 10)
+3
A
J
Reading Resolution
28
mV
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, V
= 4.5V to 16V, T = +32°C, unless otherwise noted. Typical values are at T = +32°C. All devices 100%
A A
DDH
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER SYMBOL CONDITIONS
Reading Range
MIN
TYP
MAX
UNITS
V
0
1.25
Reading Update Interval
5
1
ms
Reading Averaging Interval
ms
V
SENSE
Reading Error Referred to SENSE
Readback
Pins (V
can be scaled by
mV
OUT
divider in feedback)
T
T
= -40°C to T = +125°C (Notes 8, 9, 10)
-25
0
+25
35
A
J
Reading Resolution
Reading Range
1.95
mV
A
Reading Update Interval
Reading Averaging Interval
Reading Error
5
1
ms
ms
A
I
OUT
Readback
= -40°C to T = +125°C (Notes 8, 9, 10)
±3
0.07
A
J
Reading Resolution
Reading Range
A
-40
+125
°C
ms
ms
°C
°C
Reading Update Interval
Reading Averaging Interval
Reading Error
5
1
Temperature
Readback
(Notes 6, 8, 9)
±8
0.52
Reading Resolution
PMBus PINS (CLK, DATA, SMALERT)
Input Rising Threshold
Input Falling Threshold
Hysteresis
V
0.83
0.62
0.9
0.7
0.2
0.97
0.79
V
V
T_RISE
T_FALL
V
V
V
HYS
Output Low Voltage
PMBus Clock Frequency
V
Sinking 4mA
0.4
V
OL
PM_CLK
f
400
kHz
SYSTEM SPECIFICATIONS (Note 11)
Line Regulation
±0.2
±0.7
90.8
84
V
%
%
OUT
Load Regulation (Static)
I
= 0 - I
OUT MAX
Peak
Full load (35A)
> (V + 2V). If V
Efficiency (V = 12V,
DDH
η
V
= 1V)
OUT
Note 5: For proper regulation, it is required that V
is set > (UVLO - 2V), the IC can come out of UVLO,
DDH
OUT
OUT
but regulation is not guaranteed while V
is below (V
+ 2V). To avoid this condition, OE can be held low until V
>
DDH
OUT
DDH
(V
+ 2V).
OUT
Note 6: Denotes specifications that apply over the temperature range of T = -40°C to +125°C.
J
Note 7: Denotes parameters that are programmable.
Note 8: Min/max limits are ≥ 4σ about the mean.
Note 9: Guaranteed by design; not production tested.
Note 10:A -40°C test condition is specified at a T test condition, instead of T to allow for self heating.
A
J,
Note 11:These specifications refer to the operation of the system and are based on the circuit shown in the reference schematic.
Tolerance of external components can affect these parameters. System performance numbers are measured using the
Maxim evaluation board for this product with BOM as shown in the MAX20743 EV kit data sheet. If a different PCB layout
and different external components are used, these values can change.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, V
= 12V, V
= 1V,
OUT
DDH
f
= 400kHz, T = +25°C, Still Air, and No Heatsink.)
A
SW
STARTUP RESPONSE
TRANSIENT RESPONSE
toc01
toc02
IOUT (10A/div)
VX (20V/div)
STAT(2V/div)
VOUT (20mV/div)
VX (10V/div)
OE (2V/div)
VOUT (200mV/div)
TIME: 100µs/div
CONDITIONS: IOUT = 20A to 30A STEP at 1A/µs
TIME: 500µs/div
TYPICAL VOUT RIPPLE
toc03
VOUT (20mV/div)
VX (10V/div)
TIME: 2µs/div
CONDITIONS: IOUT = 35A
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, V
= 12V, V
= 1V,
OUT
DDH
f
= 400kHz, T = +25°C, Still Air, and No Heatsink.)
A
SW
LOAD REGULATION
SYSTEM EFFICIENCY vs. OUTPUT LOAD
toc05
toc04
100
0.4
0.3
V
OUT = 5.5V
OUT = 3.3V
OUT = 1.8V
OUT = 1V
95
90
85
80
75
V
V
0.2
V
VOUT = 0.65V
0.1
0.0
VVOUT= 5V
70
-0.1
-0.2
-0.3
-0.4
VVOUT
=
3.3V
1.8V
VVOUT
=
65
60
55
50
V
VOUT = 1.2V
V
VOUT = 1V
V
VOUT = 0.8V
V
VOUT = 0.65V
0
5
10
15
20
25
30
35
0
5
10
15
IOUT (A)
20
25
30
35
IOUT (A)
JUNCTION TEMPERATURE
vs. SYSTEM POWER DISSIPATION
SYSTEM POWER DISSIPATION
toc06
toc07
120
100
80
60
40
20
0
9
8
7
6
5
4
3
2
1
0
VOUT= 5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1V
VOUT = 0.8V
VOUT = 0.65V
SLOPE = 13°C/W
0
1
2
3
4
5
6
0
5
10
15
20
25
30
35
SYSTEM POWER DISSIPATION (W)
IOUT (A)
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, V
= 12V, V
= 1V,
OUT
DDH
f
= 400kHz, T = +25°C, Still Air, and No Heatsink.)
A
SW
SAFE OPERATING AREA (SOA)
SAFE OPERATING AREA (SOA)
toc08
toc09
40
40
35
30
25
20
15
10
5
35
30
25
20
15
VOUT = 0.8V
VOUT = 0.8V
10
VOUT = 1.2V
VOUT = 3.3V
VOUT = 1.2V
V
= 3.3V
5
0
OUT
V
= 5.0V
OUT
V
= 5.0V
OUT
0
30
40
50
60
TA (°C)
70
80
90
100
30
40
50
60
TA (°C)
70
80
90
100
CONDITIONS: 200LFM
CONDITIONS: 400LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
,
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
,
WHICHEVER HAPPENS FIRST
WHICHEVER HAPPENS FIRST
SYSTEM EFFICIENCY
vs. OUTPUT LOAD (VDDH = 5V)
SAFE OPERATING AREA (SOA)
toc10
toc11
40
35
30
25
20
15
10
5
100
95
90
85
80
75
70
65
60
55
50
VOUT = 1.8V
VOUT = 0.8V
VOUT = 1.2V
VOUT= 1V
VOUT = 0.8V
VOUT = 0.65V
VOUT = 1.2V
VOUT = 3.3V
VOUT = 5.0V
0
30
40
50
60
TA (°C)
70
80
90
100
0
5
10
15
20
25
30
35
CONDITIONS: STILL AIR / NO HEATSINK
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
WHICHEVER HAPPENS FIRST
IOUT (A)
,
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, V
= 12V, V
= 1V,
OUT
DDH
f
= 400kHz, T = +25°C, Still Air, and No Heatsink.)
A
SW
SAFE OPERATING AREA (SOA) (VDDH = 5V)
SYSTEM POWER DISSIPATION (VDDH = 5V)
toc12
toc13
40
35
30
25
20
15
10
5
7
6
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1V
VOUT=0.8V
VOUT=0.65V
5
4
3
2
1
0
VOUT = 0.8V
VOUT = 1.0V
VOUT= 1.2V
0
30
40
50
60
TA (°C)
70
80
90
100
CONDITIONS: 400LFM
0
5
10
15
20
25
30
35
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
,
IOUT (A)
WHICHEVER HAPPENS FIRST
SAFE OPERATING AREA (SOA) (VDDH = 5V)
SAFE OPERATING AREA (SOA) (VDDH = 5V)
toc14
toc15
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VOUT = 0.8V
VOUT = 0.8V
VOUT = 1.0V
VOUT= 1.2V
VOUT = 1.0V
V= 1.2V
OUT
0
0
30
40
50
60
TA (°C)
70
80
90
100
30
40
50
60
TA (°C)
70
80
90
100
CONDITIONS: STILL AIR / NO HEATSINK
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
WHICHEVER HAPPENS FIRST
CONDITIONS: 200LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX
WHICHEVER HAPPENS FIRST
,
,
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Pin Configuration
15
14
13
VSENSE+
12
CLK
1
VSENSE-
SMALERT
PGMA
11
10
9
AGND
VCC
2
3
4
5
OE
VDDH
8
BST
7
VX
6
GND
(TOP VIEW)
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Pin Description
PIN
NAME
FUNCTION
Remote-Sense Positive Node. Connect this node to V
at the load. A resistive voltage divider can
OUT
1
V
SENSE+
be used to regulate the output above the reference voltage.
2
3
4
V
Remote-Sense Negative Node. Connect this node to ground at the load using a Kelvin connection.
SMALERT Pin
SENSE-
SMALERT
PGMA
Program Node. Connect this node to ground through a programming resistor and capacitor.
Power Input Voltage. The high-side MOSFET switch is connected to this node. See the Input
Capacitor section for decoupling requirements.
5
V
DDH
6
7
8
GND
VX
Power Ground Node. The low-side MOSFET switch is connected to this node.
Power Switching Node. Connect this node to the inductor.
BST
Bootstrap for High-Side Switch. Connect a 0.22μF ceramic capacitor between BST and VX.
Output-Enable Node. This node is used to enable the regulator and has a precise threshold to allow
sequencing of multiple regulators. There is an internal 275kΩ (typ) pulldown on this pin.
9
OE
Analog/Gate-Drive Supply for the IC from Internal 1.85V (typ) LDO. This node must be connected
to three 10µF X5R or better decoupling capacitors with a very short, wide trace. V
connected to 20kΩ pullups for STAT and OE as shown in Figure 6. Do not connect V
can be
CC
10
V
CC
to other
CC
external loads. Do not overdrive V
from an external source.
CC
11
12
13
14
15
AGND
CLK
Analog/Signal Ground. See the PCB Layout section for layout information.
PMBus Clock
STAT
DATA
PGMB
Open-Drain Power-Good/Fault-Status Indication. Connect a pullup resistor to 1.8V or 3.3V.
PMBus Data
Program Node. Connect this node to ground through a programming resistor and capacitor.
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│ 12
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Block Diagram
V
CC
LDO
t
ON
TIMER
V
DDH
STAT
BST
R
POWER
SWITCHING
Q
VX
S
OE
DIGITAL
CONTROL
PGMA
PGMB
CURRENT
SENSE
OCP
GND
CLK
DATA
PMBus
INTERFACE
PWM
V
SENSE+
ERROR
AMP
SMALERT
V
CC
V
CC
TELEMETRY
CURRENT DAC
V
CC
V
SENSE-
AGND
REFERENCE VOLTAGE AND SOFT-START
The switching frequency can be set to 400kHz, 600kHz,
or 800kHz through C_SELB and can be overridden
through PMBus to 400kHz, 500kHz, 600kHz, 700kHz,
800kHz, or 900kHz.
Operation
Control Architecture
The MAX20743 provides an extremely compact, high-
efficiency regulator solution with minimal external
components and circuit design required. The monolithic
solution includes the top and bottom power switches, gate
drives, precision DAC reference, PWM controller, fault
protections, and PMBus interface (see the Block Diagram).
Voltage regulation is achieved by modulating the low-side
on-time, comparing the difference between the feedback
and reference voltages with the low-side current-sense
signal using Maxim’s proprietary integrated current-sense
technology. Once the PWM modulator forces a low-to-
high transition, the high-side switch is enabled for a fixed
time, after which the low-side switch is turned on again.
An error amplifier with an integrator is used to maintain
zero-droop operation. The integrator has a transient
recovery time constant of 20µs (typ).
An external bootstrap capacitor is used to provide the drive
voltage for the top switch. Other external components
include the input and output filter capacitors, buck
inductor, and a few resistors and capacitors to set the
operating mode.
The IC implements an advanced valley currentmode
During regulation, the differential voltage between the
control
algorithm
that
supports
all
multi-layer
V
and V
pins tracks the reference voltage,
SENSE+
SENSE-
ceramic chip (MLCC) output capacitors and fast
transient response. In steady-state, it operates
at a fixed switching frequency. When a positive load step is
applied to the output, the switching frequency speeds up to
minimizetheoutputvoltageundershoot.Similarly,whenthe
loadstepisremoved,theswitchingfrequencyslowsdownto
minimize the output voltage overshoot.
which is set by the DAC and can be set from 0.6016V
to 1V. The sense pins can be connected to the output
voltage through a voltage-divider, so V
than 1V.
can be higher
OUT
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
The switching frequency is determined by the high-side
on-time, as shown in Equation 1.
Voltage-Regulator Enable and
Turn-On Sequencing
The startup timing is shown in Figure 1. After V
applied, the IC goes through an initialization time (t
that takes up to 308μs. After initialization, OE is read.
Once OE is high for more than the 16μs OE filter time
is
)
Equation 1:
DDH
V
V
1
OUT
DDH
INIT
f
=
x
SW
t
H_ON
where:
(t ), BST charging starts and is performed for 8μs (t
OE
),
BST
after which the soft-start ramp begins. The soft-start ramp
time (t ) can be 0.75ms, 1.5ms, 3ms, or 6ms depending
f
t
= Switching frequency (MHz)
SW
SS
= On-period for high-side switch (μs)
= Output voltage (V)
H_ON
on the user’s programmed value. V
ramps up linearly
OUT
V
OUT
DDH
during the soft-start ramp time. If there are no faults, the
STAT pin can transition high after the completion of the
V
= Input voltage (V).
soft-start ramp time, plus the STAT blanking time (t
).
STAT
The t
high-side on-time is controlled by the IC to
H_ON
t
is programmable with options of 125µs and 2ms. If
STAT
be proportional to the duty cycle so that the resulting
switching frequency is independent of supply voltage and
output voltage.
OE is pulled low, the IC shuts down.
Alternatively, the IC can be enabled by sending a PMBus
Operate command. This raises the internal Operate signal
that is OR’d with the OE pin to create an internal OE
signal. Therefore, when either the OE pin or the internal
Operate signal goes high, startup is initiated, but it takes
both to be low to shut the part down.
Equation 2:
V
V
OUT
DDH
t
∝
H_ON
The t
pulse width is clamped to a minimum of
H_ON
50ns (after t ) and a maximum of 2µs to prevent any
SS
unexpected operation during extreme V
conditions.
OUT
t
INIT
V
CC
SHUTDOWN
t
OE
OE or OPERATE
t
BST
V
OUT
t
SS
t
STAT
STAT
t
: Initialization, 308µs
INIT
OE
t
t
t
t
: OE enable filter time, 16µs. If OE enabled earlier than t
: BST charging time, 8µs
completion, it is ignored until t
completes.
INIT
INIT
BST
SS
: Soft-start time per user selectuion, 0.75ms – 6ms
: STAT blanking time, 2ms or 125µs through user selection
STAT
Figure 1. Startup Timing
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Soft-Start Control
The initial output voltage behavior is determined by a
linear ramp of the internal reference voltage from zero to
Protection and Status Operation
Output-Voltage Protection
The feedback voltage is continuously monitored for both
undervoltage and overvoltage conditions. The typical
fault-detection threshold is 13% above and 9% below
the reference voltage (see the Electrical Characteristics
table). If the output voltage falls below the power-good
protection (PWRGD) threshold beyond the filter time,
the STAT output goes low but the system continues to
operate, attempting to maintain regulation.
the final value (t
programmable from 0.75ms to 6ms.
in Figure 1). The ramp time (t ) is
SS
SS
If the regulator is enabled when the output voltage has
a residual voltage, the system does not regulate until
the reference voltage ramps above this residual value.
In this case, the t
(OE valid to onset of regulation)
OE
specification is extended by the time required for the
desired voltage startup ramp to reach the actual residual
output voltage, but the time to reach the steady-state
output voltage is unchanged.
If the output voltage rises above the overvoltage-
protection (OVP) threshold beyond the filter time, the
STAT pin is lowered and the system shuts down until the
output voltage falls within the valid range.
If the residual voltage is higher than the set output
voltage, neither the high-side or low-side switch is turned
Current-Limiting and Short-Circuit Protection
on by the end of t . Under these conditions, switching
SS
begins after t
.
The regulator’s valley current-mode control architecture
provides inherent current limiting and short-circuit
protection. The bottom switch’s instantaneous current
is monitored using integrated current sensing and is
controlled on a cycle-by-cycle basis within the control
block.
SS
The MAX20743 exhibits a 400mV (typ) non-linearity
during startup when R is set to 1.8mV/A or 3.6mV/A.
This behavior is normal and does not have an adverse
effect on system operation. For best startup linearity,
GAIN
an R
of 0.9mV/A is recommended. See Startup
GAIN
Response in Typical Operating Characteristics.
Current clamping occurs when the minimum instantaneous
(“valley”) low-side switch current level exceeds the
OCP threshold current, as shown in Figure 2. In this
situation, turn-on of the high-side switch is prevented
until the current falls below the threshold level. Since
the inductor valley current is the controlled parameter,
the average current delivered during positive current
clamping remains a function of several system-level
Remote Output-Voltage Sensing
To ensure accurate sensing of the output
voltage, a differential voltage-sense topology is used,
with a negative remote-sense pin provided. Point-of-load
(PoL) sensing compensates for voltage drops between
the output of the regulator and its load and provides the
highest regulation accuracy. The voltage-sensing circuit
features excellent common-mode rejection to further
improve load voltage regulation.
parameters. Note that I
has hysteresis and the value
OCP
drops down to I
once it has been triggered, as
OCP2
shown in Figure 2.
I
t
OCP(AVG)
I
OCP
I
OCP2
1
H_ON
+
(V
V
) x
I
=
I
DDH OUT
OCP(AVG)
OCP2
2
L
OUT
I
where:
I
= I
- Hysteresis
OCP2 OCP
Figure 2. Inductor Current During Current Limiting
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Undervoltage Lockout (UVLO)
Regulator Status (STAT)
The regulator internally monitors V
with a UVLO
The STAT signal provides an open-drain output,
consistent with CMOS logic levels, which indicates
whether the regulator is functioning properly. An external
DDH
circuit. When the input supply voltage is below the UVLO
threshold, the regulator stops switching, and the STAT
pin is driven low. For UVLO levels, see the Electrical
Characteristics table.
pullup resistor is required for connecting STAT to V
another 1.8V or 3.3V supply.
or
CC
The STAT pin is low while the regulator is disabled and
goes high after the startup ramp is completed, plus the
Overtemperature Protection (OTP)
The OTP-level default is 150°C and can be set to 130°C
over PMBus. If the die temperature reaches the OTP level
during operation, the regulator is disabled and the STAT pin
is driven low. Overtemperature is a nonlatching fault, with
the hysteresis shown in the Electrical Characteristics table.
programmed t
blanking interval if the output voltage
STAT
is within the PWRGD/OVP regulation window. The STAT
pin is an open-drain output and is 3.3V tolerant. The pin
remains low when V
is not present.
DDH
Table 3. PGMA Pin C_SELA Capacitor
Values
Table 1. Summary of Fault Actions
FAULT
ACTION
NO.
1
C (pF) ±20%
Open
V
(V)
BOOT
Power good
(output undervoltage)
STAT low
STAT low,
0.6484
0.8984
1
2
220
Output OVP
shut down and restart
3
1000
STAT low,
shut down and restart
Overtemperature
Supply fault
STAT low,
Table 4. PGMB Pin R_SELB Values
(V
; V
)
shut down and restart
DDH_UVLO CC_UVLO
NO.
1
R (kΩ) ±1%
1.78
2.67
4.02
6.04
9.09
13.3
20
R
(mΩ)
OCP (A)
20
GAIN
STAT low,
shut down and restart
BST fault
3.6
2
3.6
3.6
3.6
1.8
1.8
1.8
1.8
0.9
0.9
0.9
0.9
25
3
30
Table 2. PGMA Pin R_SELA Values
4
35
5
20
R (kΩ)
±1%
SOFT-START
TIME (mS)
PMBus SLAVE
ADDRESS (1010_xxx)
NO.
6
25
1
2
1.78
2.67
4.02
6.04
9.09
13.3
20
3
3
1010 000b
1010 001b
1010 010b
1010 011b
1010 100b
1010 101b
1010 110b
1010 111b
1010 000b
1010 001b
1010 010b
1010 011b
7
30
8
30.9
46.4
71.5
107
35
3
3
9
20
4
3
10
11
12
25
5
3
30
6
3
162
35
7
3
8
30.9
46.4
71.5
107
162
3
Table 5. PGMB Pin C_SELB Capacitor
Values
9
1.5
1.5
1.5
1.5
10
11
12
NO.
1
C (pF) ±20%
Open
f
FREQUENCY (kHz)
SW
400
600
800
2
220
3
1000
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
The STAT pin is driven low when one or more of the
following conditions exists:
resistor and capacitor are connected to the PGMA/B pins
and their values are read during power-up initialization.
Power must be cycled to re-read the values.
●
●
●
PWRGD fault (see the Output-Voltage Protection section).
pin is left unconnected or shorted to V
V
.
DDH
PMBus Commands
SENSE-
Die temperature exceeds the temperature shutdown
A summary of PMBus commands is shown in Table 6. For
more information, refer to AN6042: MAX20743 PMBus
Application Note.
threshold shown in the Electrical Characteristics table.
●
OVP circuit detects that the output voltage is above
the tolerance limit.
PMBus Telemetry
The IC provides input voltage, output voltage, output
current, and junction temperature telemetry. Output
●
●
Supply voltage drops below the UVLO threshold.
Fault is detected on the BST node, such as a
shorted or open bootstrap capacitor.
voltage is measured at the V
pins; therefore,
SENSE+/-
The ensuing startup follows the same timing shown in
Figure 1.
if there is a divider in the feedback, the measurement
is scaled by the divide ratio. For range and accuracy
specifications, see the Electrical Characteristics table.
For data format, refer to AN6042: MAX20743 PMBus
Application Note.
PGMA and PGMB Pin Functionality
The PGMA and PGMB pins are used to set up some of
the key programmable features of the regulator IC. A
Table 6. PMBus Command List
NO. OF
DATA
BYTES
NO. OF
DATA
BYTES
COMMAND
COMMAND
COMMAND NAME
TYPE
COMMAND NAME
TYPE
CODE
CODE
01h
02h
03h
10h
1Bh
20h
21h
24h
78h
79h
7Ah
7Bh
7Ch
OPERATION
ON_OFF_CONFIG
CLEAR_FAULTS
WRITE_PROTECT
PMBALERT_MASK
VOUT_MODE
RW
RO
WO
RW
RW
RO
RW
RW
RO
RO
RO
RO
RO
1
1
0
1
2
1
2
2
1
2
1
1
1
7Dh
7Eh
80h
88h
8Bh
8Ch
8Dh
99h
9Bh
D1h
D2h
D3h
STATUS_TEMPERATURE
STATUS_CML
RO
RO
RO
RO
RO
RO
1
1
1
2
2
2
2
4
1
2
2
2
STATUS_MFR_SPECIFIC
READ_VIN
READ_VOUT
READ_IOUT
VOUT_COMMAND
VOUT_MAX
READ_TEMPERATURE_1 RO
MFR_ID
BLK
BLK
RW
RW
RW
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
MFR_REVISION
MFR_VOUT_MIN
MFR_DEVSET1
MFR_DEVSET2
STATUS_INPUT
Note: RW = Read/Write, WO = Write Only, RO = Read Only,
and BLK = Block.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Equation 3:
Reference Design
V
×I
OUT OUT
V
A typical application schematic is shown in Figure 3, while
Table 7 shows optimum component values for common
output voltages.
I
=
VDDH
× η
DDH
where:
Average Input Current Limit
V
= Output Voltage
= Output Current
OUT
The input current of V
is given by Equation 3. V
,
OUT
DDH
I
OUT
I
, and V
should be properly chosen so that the
OUT
DDH
V
= Input Voltage
DDH
average input current does not exceed 6A (I
).
VDDH_MAX
η =Efficiency(refertotheTypicalOperatingCharacteristics
section.)
V
DDH
C
C
VCC
IN
V
V
DDH
CC
U1
MAX20743
C
1.8V or 3.3V
BST
R
STAT
BST
VX
L
OUT
STAT
OE
STAT
OE
V
OUT
1.8V or 3.3V
COMPLIANT I/O
CLK
DATA
CLK
DATA
R
SMALERT
SMALERT
FB1
V
SENSE+
V
SENSE-
PGMA
PGMB
GND
AGND
C
R
OUT
FB2
C_SELB
C_SELA
R_SELB
R_SELA
Figure 3: Typical Application Circuit
Table 7. Reference Design Component Values
V
(V)
R
(kΩ)
R
(kΩ)
R_SELA C_SELA R_SELB C_SELB
R
(mΩ)
V
(V)
f
L
OUT
OUT
FB1
FB2
GAIN
REF
SW
C
OUT
(kΩ)
(pF)
(kΩ)
(pF)
(kHz) (nH)
0.6484
0.8
1
1
Open
5.9
1.78
1.78
1.78
1.78
1.78
1.78
1.78
Open
Open
Open
Open
Open
Open
Open
162
162
162
162
162
71.5
71.5
Open
Open
Open
Open
220
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.6484
0.6484
0.6484
0.6484
0.6484
0.6484
0.6484
400
400
400
400
600
600
600
170
170
170
170
170
210
210
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
6 x 100μF + 2 x 470μF
1.37
1.87
1.74
3.09
5.62
7.15
3.48
2.05
1.74
1.37
1.07
1.2
1.8
3.3
5.0
220
220
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Equation 4:
Output-Voltage Setting
R
R
FB1
If an output voltage not listed in Table 7 is required,
V
= V
x 1+
OUT
REF
calculate new values for R
and R
(as discussed
FB2
FB1
FB2
below) and use the other circuit values of the closest
output voltage in Table 7, or calculate them as shown
below.
where V
= 0.6016V to 1V (set by DAC).
REF
The divider resistors are then given by Equation 5.
Equation 5:
The output voltage is set by the V
DAC and divider
REF
ratio of resistors R
IC regulates the V
and R
per Equation 4. The
FB1
FB2
R
V
PAR
pin to the reference voltage
R
= V
x
OUT
SENSE+
FB1
REF
(V ), which is set by the DAC. Upon power-up, the DAC
REF
voltage initializes to one of the user-selectable V
BOOT
R
PAR
R
= R
x
FB1
voltages. Using PMBus, the DAC can also be set to any
voltage from 0.6016V to 1V with 3.9mV resolution, as
shown in Table 8. The divider resistors are chosen to give
the correct output voltage and to have an approximate
FB2
R
−R
FB1
PAR
where:
R
FB1
R
FB2
R
PAR
OUT
REF
= Top divider resistor
parallel resistance of R
= 1kΩ for best common-
PAR
mode rejection of the error amplifier. In applications
requiring less than 10mV peak-to-peak output voltage
ripple, setting a lower DAC reference voltage such as
0.6484V or less is recommended because the part will
have less DAC voltage noise.
= Bottom divider resistor
= Desired parallel resistance of R
= Output voltage
and R
FB2
FB1
V
V
= Reference voltage = 0.6016V to 1V (set by DAC).
Table 8. Voltage vs. PMBus VOUT_COMMAND
VOUT
VOUT
COMMAND VOLTAGE ACCURACY
VOUT
COMMAND VOLTAGE ACCURACY
COMMAND VOLTAGE ACCURACY
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
(decimal)
(decimal)
(decimal)
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
0.6016
0.6016
0.6055
0.6055
0.6094
0.6094
0.6133
0.6133
0.6172
0.6172
0.6211
0.6211
0.6250
0.6250
0.6289
0.6289
0.6328
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.3%
1.2%
1.2%
1.2%
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
0.6328
0.6367
0.6367
0.6406
0.6406
0.6445
0.6445
0.6484
0.6484
0.6523
0.6523
0.6563
0.6563
0.6602
0.6602
0.6641
0.6641
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
0.6680
0.6680
0.6719
0.6719
0.6758
0.6758
0.6797
0.6797
0.6836
0.6836
0.6875
0.6875
0.6914
0.6914
0.6953
0.6953
0.6992
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.2%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 8. Voltage vs. PMBus VOUT_COMMAND (continued)
VOUT
VOUT
VOUT
COMMAND VOLTAGE ACCURACY
COMMAND VOLTAGE ACCURACY
COMMAND VOLTAGE ACCURACY
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
(decimal)
(decimal)
(decimal)
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
0.6992
0.7031
0.7031
0.7070
0.7070
0.7109
0.7109
0.7148
0.7148
0.7188
0.7188
0.7227
0.7227
0.7266
0.7266
0.7305
0.7305
0.7344
0.7344
0.7383
0.7383
0.7422
0.7422
0.7461
0.7461
0.7500
0.7500
0.7539
0.7539
0.7578
0.7578
0.7617
0.7617
0.7656
0.7656
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.1%
1.0%
1.0%
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
0.7695
0.7695
0.7734
0.7734
0.7773
0.7773
0.7813
0.7813
0.7852
0.7852
0.7891
0.7891
0.7930
0.7930
0.7969
0.7969
0.8008
0.8008
0.8047
0.8047
0.8086
0.8086
0.8125
0.8125
0.8164
0.8164
0.8203
0.8203
0.8242
0.8242
0.8281
0.8281
0.8320
0.8320
0.8359
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
0.8359
0.8398
0.8398
0.8438
0.8438
0.8477
0.8477
0.8516
0.8516
0.8555
0.8555
0.8594
0.8594
0.8633
0.8633
0.8672
0.8672
0.8711
0.8711
0.8750
0.8750
0.8789
0.8789
0.8828
0.8828
0.8867
0.8867
0.8906
0.8906
0.8945
0.8945
0.8984
0.8984
0.9023
0.9023
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
Maxim Integrated
│ 20
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 8. Voltage vs. PMBus VOUT_COMMAND (continued)
VOUT
VOUT
VOUT
COMMAND VOLTAGE ACCURACY
COMMAND VOLTAGE ACCURACY
COMMAND VOLTAGE ACCURACY
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
[9:0]
(V)
(+/-)
(decimal)
(decimal)
(decimal)
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
0.9063
0.9063
0.9102
0.9102
0.9141
0.9141
0.9180
0.9180
0.9219
0.9219
0.9258
0.9258
0.9297
0.9297
0.9336
0.9336
0.9375
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
0.9375
0.9414
0.9414
0.9453
0.9453
0.9492
0.9492
0.9531
0.9531
0.9570
0.9570
0.9609
0.9609
0.9648
0.9648
0.9688
0.9688
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
—
0.9727
0.9727
0.9766
0.9766
0.9805
0.9805
0.9844
0.9844
0.9883
0.9883
0.9922
0.9922
0.9961
0.9961
1.0000
1.0000
—
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
1.0%
—
Note: The repeated voltage values in the table are due to ignoring the LSB in hardware. The available V
values are highlighted
BOOT
in gray. Voltages shown are referenced to the sense pins. Actual V
can be scaled by a voltage-divider in the feedback.
OUT
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
significantly affect the loop BW calculation. The purpose
of the integrator is to improve load regulation. The
Control-Loop Stability
The IC uses valley current-mode control which is stabilized
by selecting appropriate values of C
integrator adds a factor of (1/t
+ s)/s to the loop gain.
REC
and R
. No
GAIN
OUT
compensation network is required. For stability, the loop
bandwidth (BW) should be 100kHz or less. Consider the
case of using MLCC output capacitors that have nearly
ideal impedance characteristics in the frequency range of
interest with negligible ESR and ESL. The loop bandwidth
can be approximated by breaking the loop into gain terms
as outlined below.
Step Response
R
is important since it determines the small-
GAIN_EFF
signal transient response of the regulator. When a
load step is applied that does not exceed the slew-rate
capability of the inductor current, the regulator responds
linearly and V
temporarily changes by the amount of
OUT
V
(Equation 7).
OUT_ERROR
The voltage-loop gain consists of the following terms:
1) The IC’s valley current-mode control scheme has an
Equation 7:
V
= I
x R
STEP GAIN_EFF
OUT_ERROR
effective transconductance gain of 1/R
.
GAIN
2) For MLCC capacitors, the output capacitors contribute
The integrator causes V
value with a time constant of t
to recover to the nominal
an impedance gain of 1/(2 x π x C x f).
OUT
OUT
= 20μs. The regulator
3) The feedback-divider contributes an attenuation of
REC
can be modeled to a first-order by the averaged small-
K
= R /(R + R ).
DIV
FB2 FB1
FB2
signal equivalent circuit shown in Figure 4. Here, V
is
4) An inherent high-frequency pole located at 150kHz
EQ
an ideal voltage source, R
is an equivalent lossless
independent of switching frequency.
EQ
resistance created by the control-loop action, and L
an equivalent inductance. Note that L
is
EQ
When the BW is 100kHz or less, the high-frequency pole
can be ignored and the approximate loop gain and BW are
given by Equation 6.
is not the same
EQ
as the actual L
inductor that has been absorbed into
OUT
the model. C
is the actual output capacitance.
OUT
Equation 6:
Output-Capacitor ESR
K
DIV
x C
LOOP_GAIN(f) =
BW =
The preceding control-loop discussion considered
the use of MLCC output capacitors. Another
application worth mentioning is the use of output
2 x π x R
2 x π x R
x f
OUT
GAIN
K
DIV
x C
GAIN
OUT
t
R
GAIN_EFF
REC
OR
1
BW =
L
EQ
2 x π x R
x C
GAIN_EFF
OUT
where:
R
GAIN_EFF
R
= R
/K
.
GAIN_EFF
GAIN DIV
V
OUT
For stability, R
BW < 100kHz.
and C
should be chosen so that
GAIN
OUT
R
EQ
The available R
settings are shown in Table 4. When
C
GAIN
OUT
choosing which R
that while higher R
setting to use, one should consider
GAIN
V
V
OUT
allows the loop to be stabilized
GAIN
EQ
with less C
; less C
generally results in higher
OUT
OUT
ripple and larger transient overshoot and undershoot, so
there needs to be a balance.
GND
Figure 4. Averaged Small-Signal Equivalent Circuit of Regulator
Integrator
Note: The large-signal transient response is approximately the
The IC has an integrator included in its error amplifier that
was ignored in the above equations for simplicity. The
integrator only adds gain at low frequencies, so it does not
larger between the V
(see Equation 16).
and the Unloading Transient
OUT_ERROR
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
capacitors with more significant ESR. This can be
considered as long as the capacitors are rated to handle
the inductor current ripple and expected surge currents.
The capacitor’s ESR also introduces a zero into the loop
gain.Theinherenthigh-frequencypolehelpstocompensate
this zero. For a more in-depth view of the effect of
circuit values on regulator performance, the Maxim
Simplis model and the MAX20743 evaluation kit can
be used. It is recommended to simulate and/or test
regulator performance when using values other than the
recommended component values.
Thus far, it has been assumed that C
is comprised
OUT
of MLCCs and the net ESR is negligible compared to
/K . If the net ESR of the C bank is not
R
GAIN DIV
OUT
negligible compared to R /K , the inductor current
GAIN DIV
ripple is effectively sensed by the ESR and adds to the
, as shown in Equation 8.
R
GAIN_EFF
The performance data shown in the Typical Operating
Characteristics section was taken using the MAX20743
evaluation kit and component values in Table 7. For most
applications, these are the optimum values to use. Table 9,
Table 10, and Table 11 show suitable part numbers for
input and output capacitors and the inductor.
Equation 8:
R
GAIN
R
=
+ ESR
GAIN_EFF
K
DIV
Table 9. Recommended Inductors
VALUE
(nH)
I
R
FOOTPRINT
HEIGHT
(mm)
SAT
(A)
DC
COMPANY
PART NUMBER
WEBSITE
(mΩ)
0.29
0.32
0.32
0.32
0.32
(mm)
Cooper
Pulse
Pulse
Pulse
Pulse
170
210
260
320
440
60
64
55
45
30
10.4 x 8.0
13.5 x 13.0
13.5 x 13.0
13.5 x 13.0
13.5 x 13.0
7.5
8.0
8.0
8.0
8.0
FP1007R3-R17-R
PA0513.211NLT
PA0513.261NLT
PA0513.321NLT
PA0513.441NLT
www.cooperindustries.com
www.pulseelectronics.com
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www.pulseelectronics.com
Table 10. MLCC Input Capacitors
VALUE
(µF)
TEMPERATURE
RATING
VOLTAGE
RATING
Τ (Note 1)
(mm)
CASE SIZE
COMPANY
PART NUMBER
X7S
X7R
0.8
(Note 2)
Murata
TDK
GRM188C71C105KA12D
C1608X7R1C105K
0603
1
16V
25V
16V
16V
1.25
1.25
1.25
Murata
TDK
AVX
GRM21BR71E225KA73L
C2012X7R1C225M
0805YC225MAT
0805
2.2
X7R
0805
1206
4.7
4.7
X7R
X7R
16V
1.25
Murata
GRM21BR71C475K
AVX
Murata
1206YC475MAT
GRM31CR71C475KA01L
16V
1.65
Murata
TDK
AVX
GRM31CR71C106KAC7L
C3216X7R1C106M
1206YC106MAT
1206
1210
1210
10
10
22
X7R
X7R
X7R
16V
1.65
16V
25V
2.0
2.5
Murata
TDK
GRM32DR71C106KA01L
C3225X7R1E106M
2.45
2.5
2.5
AVX
Murata
TDK
1210YC226MAT
GRM32ER71A476K
C3225X7R1C226M
16V
Note 1: Τ indicates nominal thickness.
Note 2: Indicates capacitors with nominal thickness smaller than the minimum FCQFN package thickness.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 11. Recommended Output Capacitors
VALUE
(ΜF)
TEMP.
RATING RATING SIZE
VOLT. CASE Τ (NOTE 1)
WEBSITE
COMPANY
PART NUMBER
(mm)
22
22
08054D226MAT2A
12066D226MAT2A
X5R
X5R
4V
6.3V
0805
1206
1.3
1.65
AVX
www.avxcorp.com
www.murata.co.jp
22
22
22
GRM21BR60J226ME39L
GRM31CR60J226KE19L
GRM32DR60J226KA01L
X5R
X5R
X5R
6.3V
6.3V
6.3V
0805
1206
1210
1.25
1.6
2.0
Murata
22
22
22
ECJ3YB0J226M
ECJHVB0J226M
ECJ3Y70J226M
X5R
X5R
X7R
6.3V
6.3V
6.3V
1206
1206
1206
1.6
0.85
1.65
Panasonic
Taiyo Yuden
www.panasonic.com
www.taiyo-yuden.com
22
22
22
X5R
X5R
X5R
4V
6.3V
6.3V
0805
1206
1210
1.25
1.6
1.9
AMK212BJ226MG JMK316BJ226ML
JMK325BJ226MY
22
22
22
22
C2012X5R0J226M
C3216X5R0J226M
C3225X5R0J226M
C3216X6S0J226M
X5R
X5R
X5R
X6S
6.3V
6.3V
6.3V
6.3V
0805
1206
1210
1206
1.25
1.6
1.6
1.6
TDK
www.component.tdk.com
Note 1: Τ indicates nominal thickness.
sufficient charge to maintain regulation while the inductor
current ramps up to supply the load.
Inductor Selection
The output inductor has an important influence on
the overall size, cost, and efficiency of the voltage
regulator. Since the inductor is typically one of the larger
components in the system, a minimum inductor value is
particularly important in space-constrained applications.
Smaller inductor values also permit faster transient
response, reducing the amount of output cap needed to
maintain transient tolerances.
In contrast, smaller inductor values increase the
regulator’s maximum achievable slew rate and decrease
the necessary capacitance, at the expense of higher
ripple current. The peak-to-peak ripple current is given by
Equation 10.
Equation 10:
t
x V − V
(
)
H_ON
IN
OUT
For any buck regulator, the maximum current slew rate
through the output inductor is given by Equation 9.
I
=
OUTRIPPLE
L
OUT
Equation 9:
where:
dI
V
L
L
OUT
L
SlewRate =
=
t
= High-side switch on-time (based on nominal
) (see Equation 1)
H_ON
dt
V
OUT
where:
I = Inductor current
L
= Output inductance
= Input voltage
OUT
L
V
V
DDH
OUT
L
= Output inductance
OUT
= Output voltage.
V = V
- V
during high-side FET conduction and
L
DDH
OUT
From Equation 10, for the same switching frequency,
ripple current increases as L decreases. This increased
ripple current results in increased AC losses, larger peak
current, and for the same output capacitance, results in
increased output voltage ripple.
-V
during low-side FET conduction.
OUT
Equation 9 shows that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to step-load transients. Consequently,
more output capacitors are required to supply (or store)
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
I
should be set to 25% to 50% of the IC’s
Also, note that during a hard V
short circuit,
OUT
OUTRIPPLE
rated output current. A suitable inductor value can then
be found by solving Equation 10 for inductance as in
Equation 11 and Equation 12.
I
increases due to V
going to zero in
OUTRIPPLE
OUT
Equation 10.
Finally, the power dissipation of the inductor influences
the regulation efficiency. Losses in the inductor include
core loss, DC resistance loss, and AC resistance loss.
For the best efficiency, use inductors with core material
exhibiting low loss in the range of 0.5MHz to 2MHz and
low-winding resistance.
Equation 11:
V
× V
−V
OUT
(
)
OUT
DDH
L
=
OUT
V
×I
×f
DDH OUTRIPPLE SW
And assuming I
= 0.25 x I
for a typical
OUTRIPPLE
OUT
Table 9 provides a summary of recommended inductor
suppliers and part numbers.
inductor value (Equation 12).
Equation 12:
Output Capacitor Selection
V
x V
− V
(
)
OUT
DDH OUT
L
=
Theminimumrecommendedoutputcapacitanceforstability
is described in the Control-Loop Stability section and is
normallyimplementedusingseveral100μF1206(orsimilar)
OUT
V
x 0.25 x I
x f
(
)
DDH
OUT
SW
So, for a 35A regulator running at 400kHz with V
=
DDH
MLCCs. For low slew-rate transient loads, R
GAIN_EFF
12V and V
= 1V, Equation 13 shows the target value
OUT
determines the V
for a given load step per
OUT_ERROR
for the inductor.
the small-signal model, as discussed above. In this case,
has no effect on the V
Equation 13:
C
.
OUT_ERROR
OUT
1 x 12 −1
However, in the event that the slew rate of the load transient
greatly exceeds the slew rate of the inductor current, the
(
)
L
=
OUT
12 x 0.25 x 35 x 400000
transient V
can be larger than predicted by
OUT_ERROR
= 262nH
the small-signal model. In this case, the V
loading
OUT
and unloading transients can be approximated by taking
the larger result between Equation 7 and Equation 16.
The saturation current rating of the inductor is another
important consideration. At current limit, the peak inductor
current is given Equation 14
Equation 16:
Equation 14:
2
I
OUTRIPPLE
I
= I
+I
OCP OUTRIPPLE
LOUT × I
STEP
+
PK
2
VSAG
=
where:
= Overcurrent-protection trip point (see the Electrical
2×COUT × VDDH -VOUT
(
)
I
OCP
Characteristics table and the Current-Limiting and Short-
Circuit Protection section).
2
I
OUTRIPPLE
LOUT × I
STEP
+
tH_ON
I
= Peak-to-peak inductor current ripple,
2
OUTRIPPLE
VSOAR
where:
=
+ ISTEP ×
defined above
For proper OCP operation of the regulator, it is important
that I never exceeds the saturation current rating of
2×COUT × VOUT
COUT
PK
the inductor (I
). It is recommended that a margin of at
SAT
least 20% is included between I and I
Equation 15.
, as shown in
SAT
V
V
= Loading transient
PK
SAG
= Unloading transient.
SOAR
Equation 15:
In order to meet an aggressive transient specification,
may have to be increased and/or L decreased.
I
> 1.2 x I
PK
SAT
C
OUT
OUT
However, note that decreasing L
results in larger
OUT
inductor ripple current; thus, decreased efficiency and
increased output voltage ripple.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Output voltage ripple is another important consideration
in the selection of output capacitors. For a buck regulator
operating in CCM, the total voltage ripple across the
output capacitor bank can be approximated as the sum
of three voltage waveforms: 1) the triangle wave that
results from multiplying the AC ripple current by the ESR,
2) the square wave that results from multiplying the ripple
current slew rate by the ESL, and 3) the piecewise
quadratic waveform that results from charging and
discharging the output capacitor. In a typical MAX20743
application with a bank of 0805 X5R, 6.3V, 22µF output
capacitors, these three voltage waveform components
are roughly equal. Although the phasing of these three
components impacts the total output voltage ripple, a
common approximation is to ignore the phasing and to find
the upper bound of the peak-to-peak ripple by summing all
three components, as shown in Equation 17.
For the triangular AC ripple current at the output, the total
RMS current and power is given by Equation 18 and
Equation 19.
Equation 18:
I
OUTRIPPLE
I
=
RMS _ COUT
12
where:
I
= Peak-to peak ripple current value.
OUTRIPPLE
Equation 19:
2
P
=I
×ESR
COUT RMS _ COUT
where:
ESR = Equivalent series resistance of the entire output
capacitor bank.
Input Capacitor Selection
Equation 17:
The selection and placement of input capacitors are
important considerations. High-frequency input capacitors
serve to control switching noise. Bulk input capacitors are
designed to filter the pulsed DC current that is drawn by
the regulator. For the best performance, lowest cost and
smallest size of the MAX20743 systems, MLCC capacitors
with 1210 or smaller case sizes, capacitance values of
47µF or smaller, 16V or 25V voltage ratings, and X5R or
better temperature characteristics are recommended as
bulk. The minimum recommended value of capacitance
is 2 x 47µF (bulk) and 1.0µF + 0.1µF (high frequency).
Smaller values of bulk capacitance can be used in direct
proportion to the maximum load current.
V
L
DDH
V
= ESR(I
) + ESL
OUTRIPPLE
PP
OUT
I
OUTRIPPLE
8 x f x C
+
SW
OUT
where:
ESR = Equivalent series resistance at the output
= Peak-to-peak inductor current ripple
I
OUTRIPPLE
ESL = High-frequency equivalent series inductance at
output
V
= Input voltage
DDH
It is recommended to choose the main MLCC input
capacitance to control the peak-to-peak input voltage
ripple to 2% to 3% of its DC value in accordance with
Equation 20.
L
= Output inductance
OUT
f
= Switching frequency
SW
C
= Output capacitance.
OUT
Equation 20:
The ESLeffect of an output capacitor on output voltage ripple
cannot be easily estimated from the resonant frequency;
the high-frequency (10MHz or above) impedance of that
capacitor should be used instead. PCB traces and vias in the
I
x V
SW
x V
− V
(
)
MAX
(f
OUT
x V
DDH
OUT
)
C
=
IN
2
x V
DDH
INPP
V /GND loop contribute additional parasitic inductance.
OUT
where:
The final considerations in the selection of output capacitors
are ripple-current rating and power dissipation. Using
a conservative design approach, the output capacitors
should be designed to handle the maximum peak-to-
peak AC ripple current experienced in the worst-case
scenario. Because the recommended output capacitors
have extremely low ESR values, they are typically rated
well above the current and power stresses seen here.
C
= Input capacitance (MLCC)
IN
I
= Maximum load current
= DC input voltage
MAX
V
V
DDH
OUT
= DC output voltage
f
= Switching frequency (CCM)
SW
V
= Target peak-to-peak input-voltage ripple.
DDHPP
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Because the bulk input capacitors must source the pulsed
DC input current of the regulator, the power dissipation,
and ripple-current rating for these capacitors are far more
important than that for the output capacitors. The RMS
current that the input capacitor must withstand can be
approximated using Equation 21.
accuracy of the set output voltage. Due to the form of
Equation 4, the effect is higher at higher output voltages.
Figure
5
shows the effect of 0.1% tolerance
resistors over a range of output voltages. For different
tolerance resistors, multiply the output voltage error by the
resistors’ tolerances divided by 0.1%. For example, for
0.5% tolerance resistors, multiply the output error shown
by 5. To obtain accuracy over temperature, for a worst-case
scenario, the temperature coefficients multiplied by the
temperature range should be added to the tolerance (i.e.,
for 25ppm/°C resistors over a 50°C excursion, add 0.125%
to the 25°C tolerance).
Equation 21:
I
V
x V
− V
(
)
LOAD
OUT
DDH OUT
I
=
RMS_CIN
V
DDH
where:
The error due to the voltage-feedback resistors’ tolerance
I
= Output DC load current.
LOAD
(R
FB1
and R ) should be added to the output voltage
FB2
With an equivalent series resistance of the bulk input
capacitor bank (ESR ), the total power dissipation in
tolerance due to the IC’s feedback-voltage accuracy
shown in the Electrical Characteristics table.
CIN
the input capacitors is given by Equation 22.
Voltage Margining
Voltage margining can be achieved by changing the
Equation 22:
2
V
setting through PMBus. V
changes occur with
OUT
OUT
P
= I
× ESR
CIN RMS _ CIN
CIN
a default linear slew rate of 1V/ms. The slew rate can be
set to 1, 2, or 4mV/μs using the V bits. See AN6042:
MAX20743 PMBus Application Note for details. If a
voltage-divider is present in the feedback loop, the V
slew rate is scaled accordingly.
RATE
Resistor Selection and its Effect on DC
Output-Voltage Accuracy
OUT
R
FB1
and R
set the output voltage, as described in
FB2
Equation 4. The tolerance of these resistors affects the
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Figure 5. DC Accuracy Impact Showing Effect of 0.1% Tolerance for R
and R
FB2
FB1
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
For remote-sense applications where the load and
regulator IC are separated by a significant distance
or impedance, it is important to place the majority of
the output capacitors directly at the load. Ideally, for
system stability, all of the output capacitors should be
placed as close as possible to the load. In remote-sense
applications, common-mode filtering is necessary to filter
high-frequency noise in the sense lines.
PCB Layout
PCB layout can dramatically affect the performance of the
regulator. A poorly designed board can degrade efficiency,
noise performance, and even control-loop stability. At higher
switching frequencies, layout issues are especially critical.
As a general guideline, the input capacitors and the
output inductor should be placed in close proximity to
the regulator IC, while the output capacitors should
be lumped together as close as possible to the load.
Traces to these components should be kept as short and
wide as possible to minimize parasitic inductance and
resistance. Traces connecting the input capacitors and
The following layout recommendations should be used for
optimal performance:
● It is essential to have a low-impedance and
uninterrupted ground plane under the IC and extended
out underneath the inductor and output capacitor bank.
V
DDH
(power input node) on the IC require particular
attention since they carry currents with the largest
RMS values and fastest slew rates. According to best
practice, the input capacitors should be placed as close as
possible to the input supply pins, with the smallest
package high-frequency capacitor being the closest to the
IC and no more than 60 mils from the IC pins. Preferably,
there should be an uninterrupted ground plane located
immediately underneath these high-frequency current
paths, with the ground plane located no more than 8
mils below the top layer. By keeping the flow of this high-
frequency AC current localized to a tight loop at the
regulator, electromagnetic interference (EMI) can be
minimized.
● Multiple vias are recommended for all paths that carry
high currents (i.e., GND, V
, VX). Vias should be
DDH
placed close to the chip to create the shortest possible
current loops. Via placement must not obstruct the
flow of currents or mirror currents in the ground plane.
● A single via in close proximity to the chip should be
used to tie the top layer A
trace to the second
GND
layer ground plane, it must not be connected to the top
power ground area.
● The feedback-divider and compensation network
should be close to the IC to minimize the noise on the
IC side of the divider.
Gerber files with layout information and complete
reference designs can be obtained by contacting a Maxim
account representative.
Voltage-sense lines should be routed differentially directly
from the load points. The ground plane can be used as a
shield for these or other sensitive signals to protect them from
capacitive or magnetic coupling of high-frequency noise.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
G N D
H D D V
V D D H
V C C
A G N D
V C C
Figure 6. MAX20743 Reference Schematic (V
= 1V, V
= 4.5V to 16V)
OUT
DDH
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
15 FCQFN
MAX20743EPL+
MAX20743EPL+T
-40°C to +125°C
-40°C to +125°C
15 FCQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/16
Initial release
—
1–7,
9–10, 18–19,
22–27
Updated the Typical Operating Characteristics, and Absolute Maximum Ratings
sections; Added the Input Current Limit section and updated numbering for Equations
3-22.
1
10/16
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 31
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