MAX20808AFH+ [MAXIM]
Dual-Output 4A, 3MHz, 2.7Vâ16V Step-Down Switching Regulator;
| 型号： | MAX20808AFH+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Output 4A, 3MHz, 2.7Vâ16V Step-Down Switching Regulator |
| 文件： | 总27页 (文件大小：1723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for production status of specific part numbers.
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
General Description
Benefits and Features
The MAX20808/MAX20808T is a dual-output, fully
integrated, highly efficient, step-down DC-DC switching
regulator. The regulator is able to operate from 2.7V to
16V input supplies, and each output can be regulated
from 0.5V to 5.8V, delivering up to 4A of load current per
output. With the MAX20808, the two outputs can be
connected in parallel as a single-output, dual-phase
regulator that supports up to 8A load current.
•
High-Power Density with Low Component Count
• Dual-Output or Dual-Phase Operation
• Single-Supply Operation with Integrated LDO for
Bias Generation
• Optional 2.5V to 5.5V External Bias for Higher
Efficiency
• Compact 3.5mm x 4.6mm, 21-Pin, FC2QFN
Package
• Internal Compensation
Wide Operating Range
The switching frequency of the device can be configured
from 500kHz to 3MHz and provides the capability of
optimizing the design in terms of solution size and
performance.
•
• 2.7V to 16V Input Voltage Range
• 0.5V to 5.8V Output Voltage Range
• 500kHz to 3MHz Configurable Switching
Frequency
• -40°C to +125°C Junction Temperature Range
• Three Pin-Strap Programming Pins to Select
Different Configurations
• Independent Enable and Power Good for Each
Output
Optimized Performance and Efficiency
The MAX20808/MAX20808T utilizes fixed-frequency,
current-mode control with internal compensation. The
dual-switching regulators operate 180° out-of-phase.
The MAX20808/MAX20808T features a selectable
advanced modulation scheme (AMS) to provide
improved dynamic load transient performance. The
device also features selectable discontinuous current
mode (DCM) operation to improve light load efficiency.
Operation settings and configurable features can be
selected by connecting pin-strap resistors from the
PGM_ pins to ground.
•
• 92.5% Peak Efficiency with VDDH = 12V, VOUT
1.8V, and fSW = 1MHz
• Interleaved 180° Out-of-Phase Operation
• Selectable AMS to Improve Load Transient
=
The MAX20808/MAX20808T has an internal 1.8V low-
• Selectable DCM to Improve Light Load Efficiency
• Active Current Balancing for Dual-Phase
Operation (MAX20808 only)
dropout (LDO) output to power the gate drives (V ) and
CC
internal circuitry (AVDD). The device also has an
optional LDO input pin (LDOIN), allowing connection
from a 2.5V to 5.5V bias input supply for optimized
efficiency.
Electrical and Thermal Ratings
The MAX20808/MAX20808T integrates multiple
protections including positive and negative overcurrent
protection, output overvoltage protection, and
overtemperature protection to ensure a robust design.
DESCRIPTION
CURRENT
RATING*
(DUAL-
PHASE)
(A)
INPUT
VOLTAGE VOLTAGE
OUTPUT
(V)
(V)
The MAX20808/MAX20808T is available in a compact
3.5mm x 4.6mm FC2QFN package that supports -40°C
to +125°C junction temperature operation. The
MAX20808 package has an open top, and MAX20808T
package has a closed top.
Electrical Rating
Thermal Rating
TA = 85°C, no air
flow
Thermal Rating
TA = 55°C,
8
2.7 to 16
12
0.5 to 5.8
5.0
8
8
Applications
12
5.0
200LFM
•
•
•
•
•
•
Communications Equipment
Networking Equipment
Servers and Storage Equipment
Point-of-Load Voltage Regulators
μP Chipsets
*Maximum TJ = 125°C. For specific operating conditions, see
the Safe Operating Area (SOA) curves in the Typical
Operating Characteristics section.
Memory V
DDQ
•
I/O Pins of an FPGA/DSP/MCU
19-101082; Rev 0; 5/21
Click here for production status of specific part numbers.
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
SIMPLIFIED APPLICATION CIRCUIT
MAX20808/MAX20808T DUAL-OUTPUT APPLICATION CIRCUIT
2.7V TO 16V INPUT
MAX20808/
MAX20808T
VDDH1
BST2
VDDH2
LDOIN
VCC
LX2
OUTPUT2: 0.5V TO 5.8V, 4A
OPTIONAL 2.5V TO 5.5V
SNSP2
BST1
AVDD
PGOOD1
PGOOD2
EN1
LX1
OUTPUT1: 0.5V TO 5.8V, 4A
SNSP1
EN2
PGM0
PGM1
PGM2
PGND1
PGND2
AGND
MAX20808 SINGLE-OUTPUT DUAL-PHASE APPLICATION CIRCUIT
2.7V TO 16V INPUT
MAX20808
VDDH1
VDDH2
LDOIN
BST2
LX2
OUTPUT: 0.5V TO 5.8V, 8A
OPTIONAL 2.5V TO 5.5V
AVDD
COUPLED
INDUCTOR
OR
DISCRETE
INDUCTORS
SNSP2
BST1
VCC
AVDD
PGOOD1
PGOOD2
EN1
LX1
SNSP1
EN2
PGM0
PGM1
PGM2
PGND1
PGND2
AGND
19-XXXXXX; Rev 0; MM/YY
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Absolute Maximum Ratings
PGND to AGND ................................................ -0.3V to +0.3V
VDDH1, VDDH2 to PGND (Note 1).........................-0.3V to +19V
LX1, LX2 to PGND (DC).....................................-0.3V to +19V
LX1, LX2 to PGND (AC) (Note 2) ........................-10V to +23V
VCC to PGND.................................................... -0.3V to +2.5V
AVDD to AGND................................................. -0.3V to +2.5V
EN1, EN2 to AGND.............................................. -0.3V to +4V
PGOOD1, PGOOD2 to AGND............................. -0.3V to +4V
SNSP1, SNSP2 to AGND ....................... -0.3V to AVDD+0.3V
LDOIN to AGND................................................... -0.3V to +6V
PGM0, PGM1, PGM2 to AGND .............. -0.3V to AVDD+0.3V
Peak LX_ Current ............................................... -12A to +19A
Junction Temperature (TJ) ........................................... +150°C
Storage Temperature Range ......................... -65°C to +150°C
Peak Reflow Temperature Lead-Free.......................... +260°C
VDDH1 to LX1 (DC) (Note 1)................................-0.3V to +19V
VDDH1 to LX1 (AC) (Note 2).................................-10V to +19V
VDDH2 to LX2 (DC) (Note 1)................................-0.3V to +19V
VDDH2 to LX2 (AC) (Note 2).................................-10V to +19V
BST1, BST2 to PGND (DC).............................-0.3V to +21.5V
BST1, BST2 to PGND (AC) (Note 2) ..................-7V to +25.5V
BST1 to LX1......................................................-0.3V to +2.5V
BST2 to LX2......................................................-0.3V to +2.5V
Note 1:
Note 2:
Input high-frequency (HF) capacitors placed not more than 40 mils away from the VDDH_ pins are required to keep inductive
voltage spikes within the Absolute Maximum limits.
AC is limited to 25ns.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
21 FC2QFN
Part Number
MAX20808 (Open Top)
F213A4F+1
MAX20808T (Closed Top)
F213A4F+2
Package Code
Outline Number
21-100394
21-100513
Land Pattern Number
Thermal Resistance, Four Layer Board:
90-100134
90-100184
Junction-to-Ambient Thermal Resistance (θJA) JEDEC 44.96°C/W
43.9°C/W
20°C/W
Junction-to-Ambient Thermal Resistance (θJA) on
20°C/W
MAX20808EVKIT#
Junction-to-Case Thermal Resistance (θJC)
0.51°C/W
10.1°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations,
refer to www.maximintegrated.com/thermal-tutorial.
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Maxim Integrated | 3
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Electrical Characteristics
(Refer to Typical Application Circuits, V
= V
DDH2
= 12V, V
= 3.3V, T = T = -40°C to +125°C, unless otherwise noted.
LDOIN A J
DDH1
Specifications are production tested at T = +32°C; limits within the operating temperature range are guaranteed by design and
A
characterization.)
PARAMETER
INPUT SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
V
2.7
16
V
DDH
V
V
= 3.3V, EN_ = AGND
= AVDD, EN_ = AGND
0.1
2.2
LDOIN
Input Supply Current
I
mA
VDDH
LDOIN
Linear Regulator Input
Voltage
V
2.5
5.5
V
mA
V
LDOIN
LDOIN
V
V
= 3.3V, EN_ = AGND
2.6
Linear Regulator Input
Current
LDOIN
I
= 3.3V, EN_ = 1.8V, f
= 1MHz
22.1
LDOIN
SW
Internal LDO Regulated
Output
V
1.71
1.95
CC
V
V
V
= AVDD
= 3.3V
80
LDOIN
Linear Regulator
Current Limit
100
mA
LDOIN
< 1.6V
20
CC
AVDD Undervoltage
Lockout
AVDD Undervoltage
Lockout Hysteresis
AVDD
Rising
1.65
2.4
1.67
1.70
2.6
V
mV
V
UVLO
55
2.5
100
2.3
100
V
Undervoltage
DDH_
Lockout
V
Rising
DDH_UVLO
V
Undervoltage
DDH_
mV
V
Lockout Hysteresis
LDOIN Undervoltage
Lockout
LDOIN Undervoltage
Lockout Hysteresis
VLDOIN_UVLO
2.2
2.4
V
mV
LDOIN_UVLO
OUTPUT VOLTAGE RANGE AND ACCURACY
MAX20808
MAX20808T
0.4945
0.496
0.497
0.500
0.500
0.500
0.5055
0.504
0.503
Internal Reference
Voltage
V
T
= T = 0°C to +85°C
J
A
A
Voltage Sense Leakage
Current
I
T
= T = +25°C
1
µA
SNSP_
J
SWITCHING FREQUENCY
500
750
1000
1500
2000
3000
Switching Frequency
f
kHz
%
SW_
Switching Frequency
Accuracy
-10
+10
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Maxim Integrated | 4
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
(Refer to Typical Application Circuits, V
= V
DDH2
= 12V, V
= 3.3V, T = T = -40°C to +125°C, unless otherwise noted.
LDOIN A J
DDH1
Specifications are production tested at T = +32°C; limits within the operating temperature range are guaranteed by design and
A
characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
180
40
MAX
UNITS
Phase Shift Between
Two Outputs/Phases
f
= f
SW2
°
SW1
MAX20808, I
OUT
= 0A (Note 3)
47
40
Minimum Controllable
On-Time
MAX20808T, I
= 0A (Note 3)
OUT
32
ns
ns
MAX20808T, I
= 1A (Note 3)
27
37
OUT
Minimum Controllable
Off-Time
I
= 0A (Note 3)
100
110
OUT
ENABLE AND STARTUP
Initialization Time
t
800
µs
V
INIT
Rising
Falling
0.9
EN_ Threshold
0.6
t
t
EN_RISING_DE
LAY
Rising
Falling
200
EN_ Filtering Delay
Soft-Start Time
µs
EN_FALLING_D
ELAY
2
3
t
ms
SS
POWER GOOD AND FAULT PROTECTIONS
PGOOD_ Output Low
I
= 4mA
0.4
-10
V
PGOOD
Output Undervoltage
(UV) Threshold
Output UV Deglitch
Delay
Output Overvoltage
Protection (OVP)
Threshold
-16
10
-13
4
%
μs
%
13
2
16
Output OVP Deglitch
Delay
μs
Positive Overcurrent
Protection (POCP)
Threshold
Inductor Peak Current, POCP = 5.3A
Inductor Peak Current, POCP = 4A
4.80
3.58
5.33
4.00
36
5.86
4.50
POCP
A
ns
A
POCP Deglitch Delay
Fast Positive
Overcurrent Protection
(FPOCP) Threshold
Negative Overcurrent
Protection (NOCP)
Threshold to POCP
Threshold Ratio
FPOCP
NOCP
12.5
14.5
-83
16.5
With respect to POCP threshold (typ)
%
NOCP Accuracy
-20
+20
%
V
BST UVLO Threshold
V
Rising
1.47
1.57
60
1.62
BST
BST UVLO Threshold
Hysteresis
mV
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Maxim Integrated | 5
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
(Refer to Typical Application Circuits, V
= V
DDH2
= 12V, V
= 3.3V, T = T = -40°C to +125°C, unless otherwise noted.
LDOIN A J
DDH1
Specifications are production tested at T = +32°C; limits within the operating temperature range are guaranteed by design and
A
characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Overtemperature
Protection (OTP) Rising
Threshold
OTP
155
°C
OTP Accuracy
6
%
°C
ms
OTP Hysteresis
20
20
Hiccup Protection Time
DCM OPERATION MODE
t
HICCUP
POCP = 5.3A, Inductor Valley Current
POCP = 4A, Inductor Valley Current
-300
-215
DCM Comparator
Threshold to Enter DCM
mA
mA
DCM Comparator
Threshold to Exit DCM
Inductor Valley Current
100
PROGRAMMING PINS
PGM_ Pin Resistor
Range
PGM_ Resistor
Accuracy
R
0.095
-1
115
+1
kΩ
PGM_
%
Note 3:
Guaranteed by design.
Typical Operating Characteristics
(V
DDH
= 12V, tested on MAX20808EVKIT#, T = +25°C, unless otherwise noted.)
A
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Maxim Integrated | 6
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
(V
DDH
= 12V, tested on MAX20808EVKIT#, T = +25°C, unless otherwise noted.)
A
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Maxim Integrated | 7
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
(V
DDH
= 12V, tested on MAX20808EVKIT#, T = +25°C, unless otherwise noted.)
A
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Maxim Integrated | 8
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
(V
DDH
= 12V, tested on MAX20808EVKIT#, T = +25°C, unless otherwise noted.)
A
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Maxim Integrated | 9
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Pin Configurations
21
18
20
19
VDDH2
1
17
16
VDDH1
PGND2
2
PGND1
EN2
PGOOD1
PGM2
3
4
5
6
15
14
13
12
VCC
MAX20808/
MAX20808T
PGOOD2
PGM1
EN1
PGM0
7
8
9
10
11
(TOP VIEW)
Pin Descriptions
PIN
NAME
FUNCTION
and V should be connected on the PCB.
1
V
Regulator Input Supply for Output 2. V
DDH1
DDH2
DDH2
2
PGND2
EN2
Power Ground. PGND1 and PGND2 should be connected on the PCB.
Output Enable for Output 2.
3
4
PGOOD1 Open-Drain Power-Good Output for Output 1.
5
PGM2
PGM0
Program Input. Connect this pin to ground though a programming resistor.
Program Input. Connect this pin to ground though a programming resistor.
6
Output 2 Voltage Sense Feedback Pin. Connect SNSP2 to V
at the load. A resistive voltage-divider
OUT2
7
8
SNSP2
AVDD
can be inserted between the output and SNSP2 to regulate the output above the 0.5V fixed reference
voltage. Connect SNSP2 to AVDD to select dual-phase operation.
1.8V Supply for Analog Circuitry. Connect a 2.2Ω to 4.7Ω resistor from AVDD to V . Connect a 1μF or
CC
greater ceramic capacitor from AVDD to AGND.
Optional 2.5V to 5.5V LDO Input Supply. Connect this pin to AVDD or GND, or leave this pin floating if
unused.
9
LDOIN
AGND
10
Analog Ground.
Output 1 Voltage Sense Feedback Pin. Connect SNSP1 to V
at the load. A resistive voltage-divider
OUT1
11
12
SNSP1
EN1
can be inserted between the output and SNSP1 to regulate the output above the 0.5V fixed reference
voltage.
Output Enable for Output 1.
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Maxim Integrated | 10
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
13
14
15
16
17
18
19
20
21
PGM1
Program Input. Connect this pin to ground though a programming resistor.
PGOOD2 Open-Drain Power-Good Output for Output 2.
V
Internal 1.8V LDO Output. Connect a 2.2μF or greater ceramic capacitor from V
to PGND.
CC
CC
PGND1
Power Ground. PGND1 and PGND2 should be connected on the PCB.
V
Regulator Input Supply for Output 1. V
and V should be connected on the PCB.
DDH2
DDH1
DDH1
BST1
LX1
Bootstrap Pin for Output 1. Connect a 0.22μF ceramic capacitor from BST1 to LX1.
Switching Node of Output 1. Connect LX1 directly to the output inductor.
Switching Node of Output 2. Connect LX2 directly to the output inductor.
Bootstrap Pin for Output 2. Connect a 0.22μF ceramic capacitor from BST2 to LX2.
LX2
BST2
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Maxim Integrated | 11
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Block Diagram
EN1
PGOOD1
EN2
PGOOD2
AVDD
VCC
CLOCK
DIGITAL CORE
OTP BANK
LDO
LDOIN
TO ANALOG /
DIGITAL CORE
PGM0
PGM1
PGM2
TO
GATE
DRIVE
RADC
FAULT
DETECT
BST1
VDDH1
BST
SNSP1
MODULATOR1
HS
PWM
DRIVER
LOGIC
OVP
PGOOD
LX1
IRECON
LS
DRIVER
PGND1
ZERO
CROSS
OVP
PGOOD
FAULT
DETECT
BST2
VDDH2
BST
SNSP2
AGND
CONTROLLER2
MODULATOR2
HS
PWM
DRIVER
LOGIC
BANGAP
CORE
LX2
IRECON
LS
DRIVER
BIAS
PGND2
ZERO
MAX20808/
MAX20808T
CROSS
Detailed Description
Dual-Output or Dual-Phase Operation
The MAX20808/MAX20808T by default is configured as dual-output step-down regulators. These devices have two
independent control loops for the two outputs and the loop parameters can be independently selected.
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Maxim Integrated | 12
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
The MAX20808 only can also be configured as a single-output, dual-phase 8A converter by connecting the SNSP2 pin to
AVDD. When configured to dual-phase operation, only the control loop for OUTPUT1 works, and the control loop for
OUTPUT2 is bypassed. The EN1 and PGOOD1 pins are used in dual-phase operation mode to enable the device and
indicate power-good status. The EN2 and PGOOD2 pins can be disconnected.
Control Architecture
Fixed-Frequency, Peak Current-Mode Control Loop
The MAX20808/MAX20808T control loops are based on fixed-frequency, peak current-mode control architecture. A
simplified control architecture is shown in Figure 1. Each loop contains an error amplifier stage, internal voltage loop
compensation network, current sense, internal slope compensation, and a PWM modulator that generates the pulse-width
modulation (PWM) signals to drive high-side and low-side MOSFETs. The device has a fixed 0.5V reference voltage
(V
(V
(V
). The difference of V
and the sensed output voltage is amplified by the first error amplifier. Its output voltage
REF
REF
) is used as the input of the voltage loop compensation network. The output of the compensation network
ERR_
COMP_
) is fed to a PWM comparator with the current-sense signal (V
) and slope compensation (V
). The
RAMP_
ISENSE_
output of the PWM comparator is the input of the PWM modulator. The turning on of the high-side MOSFET is aligned
with an internal clock. It can either be a fixed-frequency clock or a phase-shifted clock if AMS is enabled.
AMS_ENABLE
CLOCK
FIXED_CLK
AMS_CLK
PWM
MODULATOR
V
REF
VOLTAGE LOOP
COMPENSATION
NETWORK
V
V
COMP_
ERR_
V
SNSP_
V
ISENSE_
V
RAMP_
Figure 1. Simplified Control Architecture
Advanced Modulation Scheme
The MAX20808/MAX20808T offers a selectable AMS to provide improved dynamic load transient response. The AMS
provides a significant advantage over conventional fixed-frequency PWM schemes. Enabling the AMS feature allows for
modulation at both leading and trailing edges, which results in a fast-switching response during large load transients.
Figure 2 shows the scheme to include leading-edge modulation to the traditional trailing-edge modulation when AMS is
enabled in the device. The modulation scheme allows the turn on and off with minimal delay. Since the total inductor
current increases very quickly, thus satisfying the load demand, the current drawn from the output capacitors is reduced.
With AMS enabled, the system closed-loop bandwidth can be extended without phase-margin penalty. As a result, the
output capacitance can be minimized.
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Maxim Integrated | 13
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
FIXED_CLK
-V
ERR_
AMS_RAMP
AMS_CLK
PWM
Figure 2. AMS Operation
Discontinuous Current Mode Operation
The discontinuous current mode operation can be enabled to improve light-load efficiency. It is required that V
is at
DDH
for the device to operate in DCM. The device has a DCM current-detection
least 2V higher than the desired V
OUT
comparator to monitor the inductor valley current while operating in continuous-conduction mode (CCM). At light load, if
the inductor valley current is below the DCM comparator threshold for 48 consecutive cycles, the device transitions
seamlessly to DCM. Once in DCM, the switching frequency decreases as load decreases. The MAX20808/MAX20808T
transitions back to CCM operation as soon as the inductor valley current is higher than 100mA.
Active Current Balancing
When the MAX20808 is configured to dual-phase operation, the MAX20808 operates with active current balancing for
enhanced dynamic-current sharing or balancing between two-phase currents. This feature maintains the current balance
during load transients, even at a load-step frequency close to the switching frequency or its harmonics. The active current-
balancing circuit adjusts the individual phase-current control signal in order to minimize the phase-current imbalance.
Internal Linear Regulator
The MAX20808/MAX20808T contains an internal 1.8V linear regulator. The 1.8V voltage on V
is derived from the
CC
pin by default. To improve efficiency, it is recommended to apply an external 2.5V to 5.5V bias input supply on
V
DDH1
the LDOIN pin so that the 1.8V voltage on V
is converted from the LDOIN pin instead. The LDOIN pin can be connected
CC
to the output voltage if the output voltage falls within the 2.5V–5.5V range. The optional LDOIN bias input supply can be
applied or removed anytime during regulation without affecting the regulation.
The 1.8V voltage on the V
pin supplies the current to the MOSFET drivers of both outputs. A decoupling capacitor of
CC
at least 2.2μF must be connected between V
and PGND. The AVDD pin also requires a 1.8V supply to power the
CC
device’s internal analog circuitry. A 2.2Ω to 4.7Ω resistor must be connected between AVDD and V . A 1μF or greater
CC
decoupling capacitor must be used between AVDD and AGND.
Startup and Shutdown
The startup and shutdown timing is shown in Figure 3. When the AVDD pin voltage is above its rising UVLO threshold,
the device goes through an initialization procedure. The dual-output or dual-phase operation is detected. Configuration
resistors on the PGM_ pins are read. Once initialization is complete, the device detects the V
UVLO and EN_ status.
DDH
When both are above their rising thresholds, soft-start begins and switching is enabled. The output voltage of the enabled
output starts to ramp up. The soft-start ramp time is 3ms. If there are no faults, the open-drain PGOOD_ pin is released
from being held low after the soft-start ramp is complete. The device supports smooth startup with the output prebiased.
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Maxim Integrated | 14
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
During operation, if either V
UVLO or EN_ falls below its threshold, switching is stopped immediately. The PGOOD_
DDH
pin is driven low. The output voltage is discharged by the load current.
V
DDH
V
CC
AND AVDD
EN_
t
INIT
t
SS
t
EN_FALLING_DELAY
V
OUT_
(PRE-BIASED)
INTERNAL
SOFT-START RAMP
t
EN_RISING_DELAY
PGOOD_
LX_
t
t
t
t
= 800µs
INIT
= 200µs
EN_RISING_DELAY
= 3ms
SS
= 2µs
EN_FALLING_DELAY
Figure 3. Startup and Shutdown Timing
Fault Handling
Input Undervoltage Lockout (V
UVLO)
DDH
The MAX20808/MAX20808T internally monitors V
with a UVLO circuit. When the input supply voltage is below the
DDH
UVLO threshold, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup
protection time if the V UVLO status is cleared. Refer to the Startup and Shutdown section for the startup sequence.
DDH
Output Overvoltage Protection (OVP)
The feedback voltage on SNSP_ is monitored for overvoltage once the soft-start ramp is complete. If the feedback voltage
is above the OVP threshold beyond the OVP deglitch filtering delay, the device stops switching and drives the PGOOD_
pin low. The device restarts after 20ms hiccup protection time if the OVP status is cleared. When configured to dual-
output operation, the OVP of one output does not affect the operation of the other output.
Positive Overcurrent Protection (POCP)
The device’s peak current mode control architecture provides inherent current limiting and short-circuit protection. The
inductor current is continuously monitored while switching. The inductor peak current is limited on a cycle-by-cycle basis.
In each switching cycle, once the sensed inductor current exceeds the POCP threshold, the device turns off the high-side
MOSFET and turns on the low-side MOSFET to allow the inductor current to be discharged by output voltage. An up-
down counter is used to accumulate the number of consecutive POCP events each switching cycle. If the counter exceeds
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Maxim Integrated | 15
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
1024, the device stops switching and drives the PGOOD_ pin low. The device restarts after 20ms hiccup protection time.
When configured to dual-output operation, the POCP of one output does not affect the operation of the other output.
The MAX20808 offers two POCP thresholds (5.3A and 4A) for each output, which can be selected by the PGM1 and
PGM2 pins (refer to Pin-Strap Programmability section). Due to POCP deglitch delay, for a specific application use case,
the actual POCP threshold should be higher (refer to Output Inductor Selection section).
Negative Overcurrent Protection (NOCP)
The device also has negative overcurrent protection against inductor valley current. The NOCP threshold is -83% of the
POCP threshold. In each switching cycle, once the sensed inductor current exceeds the NOCP threshold, the device
turns off the low-side MOSFET and turns on the high-side MOSFET for a fixed 180ns time to allow the inductor current
to be charged by input voltage. Same as the POCP, an up-down counter is used to accumulate the number of consecutive
NOCP events. If the counter exceeds 1024, the device stops switching and drives the PGOOD_ pin low. The device
restarts after 20ms hiccup protection time. When configured to dual-output operation, the NOCP of one output does not
affect the operation of the other output.
Overtemperature Protection (OTP)
The overtemperature protection threshold is +155°C with 20°C hysteresis. If the junction temperature reaches OTP
threshold during operation, the device stops switching and drives the PGOOD_ pin low. The device restarts if the OTP
status is cleared.
Pin-Strap Programmability
The MAX20808/MAX20808T has three program pins (PGM0, PGM1, and PGM2) to set some of the key configurations
of the device. A pin-strap resistor is connected from the PGM_ pin to AGND, and its value is read during startup
initialization. The PGM0 selects the common settings that apply to both outputs (AMS, DCM, and switching frequencies).
When the device is configured to dual-output operation, the PGM1 selects the POCP and internal compensation
parameters of OUTPUT1; the PGM2 selects the POCP and internal compensation parameters of OUTPUT2. When the
device is configured to dual-phase operation, the POCP and internal compensation parameters are selected only by
PGM1. Refer to the Internal Compensation Selection section for information about how to select the compensation
parameters for optimized control loop performance.
Table 1. PGM0 Configurations
PGM0
CODES
R
(Ω)
AMS
DCM
f
f
SW2
SW1
(kHz) (kHz)
0
1
2
95.3
200
309
Disable Disable
500
500
750
500
1000
750
3
4
422
536
750
1000
1500
500
5
6
649
768
1000 1000
1000 2000
7
909
1500
750
8
9
1050
1210
1400
1620
1870
2150
2490
2870
3740
8060
12400
16900
1500 1500
2000 1000
2000 2000
3000 3000
10
11
12
13
14
15
16
17
18
19
Enable
500
500
750
500
1000
750
750
1000
1500
500
1000 1000
1000 2000
1500
750
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Maxim Integrated | 16
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
20
21
22
23
24
25
26
27
28
29
30
31
21500
26100
30900
36500
42200
48700
56200
64900
75000
86600
100000
115000
1500 1500
2000 1000
2000 2000
3000 3000
Enable
500
500
750
500
1000
750
1000
500
1000 1000
1500 1500
2000 2000
3000 3000
Table 2. PGM1 Configurations for OUTPUT1 or Dual-Phase Operation
PGM1
CODES
R
(Ω)
POCP1
(A)
VOLTAGE
LOOP GAIN
MULTIPLIER 1
0.4
SLOPE1
(μA)
0
1
2
3
4
5
6
7
95.3
200
309
422
536
649
768
909
5.3
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
1.5
2.6
7.0
1.5
2.6
7.0
1.5
2.6
7.0
0.7
8
9
1050
1210
1400
1620
1870
2150
2490
2870
3740
8060
12400
16900
21500
26100
30900
36500
42200
48700
56200
64900
75000
86600
100000
115000
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1.5
4
0.4
0.7
1
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Maxim Integrated | 17
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Table 3. PGM2 Configurations for OUTPUT2
PGM2
CODES
0
R
(Ω)
95.3
200
309
422
536
649
POCP2
(A)
5.3
VOLTAGE LOOP GAIN
MULTIPLIER 2
0.4
SLOPE2
(μA)
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
8.0
1.5
2.6
3.7
6.0
7.0
1.5
2.6
7.0
1.5
2.6
7.0
1.5
2.6
7.0
1
2
3
4
5
6
7
8
768
909
0.7
1050
1210
1400
1620
1870
2150
2490
2870
3740
8060
12400
16900
21500
26100
30900
36500
42200
48700
56200
64900
75000
86600
100000
115000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1.5
4
0.4
0.7
1
Reference Design Procedure
Output Voltage Sensing
The MAX20808/MAX20808T has an internal 0.5V reference voltage. When the desired output voltage is higher than 0.5V,
it is required to use resistor-dividers R and R to sense the output voltage (refer to Typical Application Circuits). It
FB1
FB2
is recommended that the value R
does not exceed 5kΩ. The resistor-divider ratio is given by the following equation:
FB2
R
R
FB1
V
= V
1+
OUT
REF
FB2
where
V
V
= Output voltage
OUT
REF
= 0.5V fixed reference voltage
= Top resistor-divider
R
FB1
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Maxim Integrated | 18
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
R
FB2
= Bottom resistor-divider
Switching Frequency Selection
The MAX20808/MAX20808T offers a wide range of selectable switching frequencies from 500kHz to 3MHz. Switching
frequency selection can be optimized for different applications. Higher switching frequencies are recommended for
applications prioritizing solution size so that the value and size of output LC filter can be reduced. Lower switching
frequencies are recommended for applications prioritizing efficiency and thermal dissipation due to reduced switching
losses. The frequency must be selected so that the minimum controllable on-time and minimum controllable off-time are
not violated. The maximum recommended switching frequency is calculated by the following equation:
V
V
− V
OUT
DDHMIN OUT
f
= MIN
,
SWMAX
t
V
t
V
ONMIN
DDHMAX OFFMIN
DDHMIN
where
f
= Maximum selectable switching frequency
SWMAX
V
V
= Maximum input voltage
= Minimum input voltage
DDHMAX
DDHMIN
t
t
= Minimum controllable on-time
= Minimum controllable off-time
ONMIN
OFFMIN
Due to system noise injection, even at steady-state operation, typically the LX rising and falling edges would have some
random jittering noise. The selection of the switching frequency (f ) should take into consideration the jittering and be
SW
. To improve the LX jittering, it is recommended to use smaller inductor values and lower voltage loop
lower than f
SWMAX
gain to minimize the noise sensitivity.
Output Inductor Selection
The output inductor has an important influence on the overall size, cost, and efficiency of the voltage regulator. Since the
inductor is typically one of the larger components in the system, a minimum inductor value is particularly important in
space-constrained applications. Smaller inductor values also permit faster transient response, reducing the amount of
output capacitance needed to maintain transient tolerance.
To improve current loop noise immunity, typically the output inductor is selected so that the inductor current ripple is at
least 1A. The inductor value is calculated by the following equation:
V
(V
− V
)
OUT DDH
OUT
L =
V
I
f
DDH RIPPLE
SW
where
V
= Input voltage
DDH
I
= Inductor current ripple peak-to-peak value
RIPPLE
The inductor should also be selected so that maximum load current delivery can be guaranteed by the selected POCP
threshold. The MAX20808/MAX20808T offers two POCP thresholds (5.3A and 4A) for each output, which can be selected
by the PGM1 and PGM2 pins (refer to Pin-Strap Programmability section). Due to deglitch delay from the POCP
comparator tripping to the high-side MOSFET turning off, for a specific application use case, the adjusted POCP threshold
should take into consideration the inductor value, input voltage, and output voltage, which can be calculated by the
following equation:
(V
− V
) t
DDH
OUT POCP
POCP
= POCP +
ADJUST
L
where
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Maxim Integrated | 19
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
POCP
= Adjusted POCP threshold
ADJUST
POCP = POCP level specified in the EC table
= POCP deglitch delay (36ns, typ)
t
POCP
It needs to be verified that the peak inductor current in normal operation does not exceed the minimum adjusted POCP
threshold:
I
I
RIPPLE
OUTMAX
+
POCP
ADJUST(MIN)
N
2
where
N = Number of phases
I
= Maximum load current
OUTMAX
POCP
= Minimum adjusted POCP threshold, calculated with the minimum value of the POCP threshold.
ADJUST(MIN)
Table 4 shows some suitable inductor part numbers which are verified on the MAX20808/MAX20808T evaluation kit to
offer optimal performance.
Table 4. Recommended Inductors
COMPANY
VALUE (μH)
I
R
(mΩ)
FOOTPRINT
(mm)
HEIGHT
(mm)
1.2
PART NUMBER
SAT
(A)
9
8.4
26
DC
TDK
TDK
Pulse
Pulse
Pulse
Pulse
0.22
0.33
0.47
0.56
1.0
8
2.5 × 2.0
3.2 × 2.5
5.5 × 5.3
5.5 × 5.3
5.5 × 5.3
5.5 × 5.3
TFM252012ALMAR22MTAA
TFM322512ALMAR33MTAA
PA5003.471NLT
10
1.2
2.9
2.9
2.9
3.75
4.05
6.9
22.2
16.5
10
PA5003.561NLT
PA5003.102NLT
PA5003.222NLT
2.2
13.2
2.9
Output Capacitor Selection
One major factor in determining the total required output capacitance is the output-voltage ripple. To meet the output-
voltage ripple requirement, the minimum output capacitance should satisfy the following equation:
I
RIPPLE
C
OUT
8N f
(V
− ESRI
)
RIPPLE
SW
OUTRIPPLE
where
V
= Maximum allowed output-voltage ripple
OUTRIPPLE
ESR = ESR of output capacitors
The other important factors in determining the total required output capacitance are the maximum allowable output-voltage
overshoot and undershoot during load transients. For a given loading or unloading current step, the minimum required
output capacitance should also satisfy the following equation:
2
2
I
I
RIPPLE
I
N
I
N
RIPPLE
2
+
LN
− V
+
LN
2
C
MAX
,
OUT
2 V
V
(
2 V
V
)
OUT
DDH
OUT
OUT OUT
where
C
OUT
= Output capacitance
△I = Loading or unloading current step
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Maxim Integrated | 20
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
△V
= Maximum allowed output voltage undershoot or overshoot
OUT
Input Capacitor Selection
The input capacitance selection is determined by the input voltage ripple requirement. The V
and V
pins of the
DDH2
DDH1
MAX20808/MAX20808T should be connected on the PCB. When configured to dual-output operation, the input
capacitance is shared between the two outputs. The minimum required input capacitance is estimated by the following
equation:
I
V
I
V
OUT2(MAX) OUT2
OUT1(MAX)
OUT1
C
MAX
,
IN
f
V
V
f
V
V
SW1
DDH
INPP SW2
DDH INPP
where
C
IN
= Input capacitance
I
= Maximum output current of OUTPUT_
= Output voltage of OUTPUT_
OUT_(MAX)
V
OUT_
f
= Switching frequency of OUTPUT_
sw_
V
= Peak-to-peak input voltage ripple
INPP
When configured to dual-phase operation, the minimum required input capacitance is estimated by the following equation:
I
V
OUT
OUT(MAX)
C
IN
2 f
V
V
INPP
SW
Besides the minimum required input capacitance, it is also required to place 0.1μF and 1μF high-frequency decoupling
capacitors next to each V pin to suppress the high-frequency switching noises.
DDH
DDH_
Internal Compensation Selection
Voltage Loop Gain
For stability purposes, it is recommended that the voltage loop bandwidth (BW) be lower than one-fifth of the switching
frequency. Consider the case of using multilayer ceramic chip (MLCC) output capacitors that have nearly ideal impedance
characteristics in the frequency range of interest with negligible equivalent series resistance (ESR) and equivalent (or
effective) series inductance (ESL). The voltage loop BW can be estimated with the following equation:
R
R
VGA
10kΩ
FB2
+ R
N
R
FB2
FB1
BW =
2π 20mΩC
OUT
where
R
VGA
= Voltage loop gain resistance, which is set by the switching frequency and voltage loop gain multiplier selected by
PGM_ pin resistors (Table 5)
Table 5. Voltage Loop Gain Resistance
SWITCHING
VOLTAGE
R
VGA
FREQUENCY (kHz)
LOOP GAIN
(kΩ)
MULTIPLIER
500
0.4
0.7
1
15.6
27
37
1.5
0.4
52.2
22
750
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Maxim Integrated | 21
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
0.7
1
1.5
0.4
0.7
1
1.5
0.4
0.7
1
1.5
0.4
0.7
1
31
44.5
62.3
22
1000
1500
37
52.2
74.5
27
44.5
62.3
104.4
31
52.2
74.5
104.4
2000 or 3000
1.5
Slope Compensation
Slope compensation is applied to guarantee current loop stability when the duty cycle is higher than 50%. For applications
where the duty cycle is smaller than 50%, it is also recommended to apply slope compensation to improve current loop
noise immunity. The minimum and maximum slope compensation values are calculated by the following equation:
V
V
f
C
I
I
RIPPLE
1.6Ω
1.6Ω
OUT
IN SW
SLOPE
OUTMAX
C
SLOPE
800mV −
+
SLOPE
L
25
V
N
2
25
OUT
where
C
= 5pF
SLOPE
The slope-compensation options of MAX20808/MAX20808T can be selected by resistor values on the PGM1 and PGM2
pins. A higher slope value is recommended to help reduce the duty cycle jittering and improve stability.
Typical Reference Designs
Refer to Typical Application Circuits for examples of reference schematics. Reference design examples for some common
output voltages are shown in Table 6.
Table 6. Reference Design Examples
V
(V)
I
(A)
OUT
(PER
f
R
(kΩ)
R
(kΩ)
PGM0
(kΩ)
PGM1
OR
L
(μH)
C
(PER EACH
C
OUT
OUT
SW
FB1
FB2
IN
V
(kHz)
PIN)
DDH_
PHASE)
PGM2
(kΩ)
1.05
1.05
1.05
1.05
2.49
2.15
100
0.8
0.9
1.0
1.2
1.8
3.3
5.0
4
4
4
4
4
4
3
750
1.82
2.40
3.01
4.22
7.87
16.9
22.6
3.01
3.01
3.01
3.01
3.01
3.01
2.49
2.49
8.06
8.06
8.06
21.5
30.9
30.9
0.47
0.47
0.47
0.56
0.56
1.0
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
10μF +1μF +0.1μF
2 × 47μF
2 × 47μF
2 × 47μF
2 × 47μF
2 × 47μF
2 × 47μF
1 × 47μF
1000
1000
1000
1500
2000
2000
2.2
PCB Layout Guidelines
For electrical and thermal reasons, the second layer from the top and bottom of the PCB should be reserved for power
•
ground (PGND) planes.
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Maxim Integrated | 22
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
•
•
•
The input decoupling capacitor should be located the closest to the IC and no more than 40mils from the V
pins.
DDH_
The V
decoupling capacitors should be connected to PGND and placed as close as possible to V
CC
pin.
CC
An analog ground copper polygon or island should be used to connect all analog control-signal grounds. This “quiet”
analog ground copper polygon or island should be connected to the PGND through a single connection close to AGND
pin. The analog ground can be used as a shield and ground reference for the control signals (PGM_ and SNSP_).
•
•
The AVDD decoupling capacitors should be connected to AGND and placed as close as possible to AVDD pin.
The boost capacitors should be placed as close as possible to LX_ and BST_ pins, on the same side of the PCB with
the IC.
•
The feedback resistor-divider and optional external compensation network should be placed close to the IC to minimize
the noise injection.
•
•
•
Voltage sense line should be shielded by ground plane and be kept away from switching node and the inductor.
Multiple vias are recommended for all paths that carry high currents and for heat dissipation.
The input capacitors and output inductors should be placed near the IC and the traces to the components should be
kept as short and wide as possible to minimize parasitic inductance and resistance.
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Maxim Integrated | 23
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Typical Application Circuits
Dual-Output Operation
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Maxim Integrated | 24
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Dual-Phase Operation
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Maxim Integrated | 25
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Ordering Information
DUAL-PHASE
OPERATION
MINIMUM
CONTROLLABLE
ON-TIME
TEMPERATURE
PART NUMBER
PIN-PACKAGE
RANGE
MAX20808AFH+
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
21 FC2QFN (Open Top)
21 FC2QFN (Open Top)
21 FC2QFN (Closed Top)
21 FC2QFN (Closed Top)
YES
YES
NO
47ns
47ns
40ns
40ns
MAX20808AFH+T
MAX20808TAFH+*
MAX20808TAFH+T*
NO
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—contact factory for availability.
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Maxim Integrated | 26
MAX20808
Dual-Output 4A, 3MHz, 2.7V–16V Step-Down
Switching Regulator
Revision History
REVISION
NUMBER
0
REVISION
DATE
05/21
PAGES
CHANGED
—
DESCRIPTION
Initial release
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2021 Maxim Integrated Products, Inc.
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