MAX2769 [MAXIM]
Universal GPS Receiver; 通用的GPS接收器
| 型号： | MAX2769 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Universal GPS Receiver |
| 文件： | 总23页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-ꢀ791; Rev 2; 6/1ꢀ
Universal GPS Receiver
MAX2769
General Description
Features
o GPS/GLONASS/Galileo Receivers
The MAX2769 is the industry’s first global navigation
satellite system (GNSS) receiver covering GPS,
GLONASS, and Galileo navigation satellite systems on a
single chip. This single-conversion, low-IF GNSS receiver
is designed to provide high performance for a wide range
of consumer applications, including mobile handsets.
o No External IF SAW or Discrete Filters Required
o Programmable IF Frequency
o Fractional-N Synthesizer with Integrated VCO
Supports Wide Range of Reference Frequencies
o Dual-Input Uncommitted LNA for Separate
Designed on Maxim’s advanced, low-power SiGe
BiCMOS process technology, the MAX2769 offers the
highest performance and integration at a low cost.
Incorporated on the chip is the complete receiver
chain, including a dual-input LNA and mixer, followed
by the image-rejected filter, PGA, VCO, fractional-N
frequency synthesizer, crystal oscillator, and a multibit
ADC. The total cascaded noise figure of this receiver is
as low as 1.4dB.
Passive and Active Antenna Inputs
o 1.4dB Cascade Noise Figure
o Integrated Crystal Oscillator
o Integrated Active Antenna Sensor
o 10mA Supply Current in Low-Power Mode
o 2.7V to 3.3V Supply Voltage
o Small, 28-Pin, RoHS-Compliant, Thin QFN Lead-
Free Package (5mm x 5mm)
The MAX2769 completely eliminates the need for external
IF filters by implementing on-chip monolithic filters and
requires only a few external components to form a com-
plete low-cost GPS receiver solution.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN-EP*
Dice (In Wafer Form)
The MAX2769 is the most flexible receiver on the
market. The integrated delta-sigma fractional-N frequency
synthesizer allows programming of the IF frequency
within a 4ꢀ0z accuracy while operating with any refer-
ence or crystal frequencies that are available in the
host system. The integrated ADC outputs 1 or 2 quan-
tized bits for both I and Q channels, or up to 3 quan-
tized bits for the I channel. Output data is available
either at the CMOS logic or at the limited differential
logic levels.
MAX2769ETI+
MAX2769E/W
+Denotes a lead(Pb)-free/Ro0S-compliant package.
*EP = Exposed paddle.
Pin Configuration/Block Diagram
The MAX2769 is packaged in a compact 5mm x 5mm,
28-pin thin QFN package with an exposed paddle. The
part is also available in die form. Contact the factory for
further information.
21
20
19
18
17
16
15
14
VCCD
N.C.
22
23
24
25
26
27
28
Applications
VCCIF
VCCCP
CPOUT
13
12
11
MAX2769
Location-Enabled Mobile 0andsets
PNDs (Personal Navigation Devices)
PMPs (Personal Media Players)
PDAs (Personal Digital Assistants)
In-Vehicle Navigation Systems
IDLE
FILTER
LNA2
PGM
VCCVCO
VCO
LNA2
LNA1
10 CS
Telematics (Asset Tracking, Inventory
Management)
LNA1
9
8
SCLK
Recreational/Marine Navigation/Avionics
Software GPS
TSENS
SDATA
+
1
2
3
4
5
6
7
Laptops and Ultra-Mobile PCs
Digital Still Cameras and Camcorders
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Universal GPS Receiver
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND...........................................................-0.3V to +4.2V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (TQFN only, soldering, 10s) ..............+300°C
Soldering Temperature (reflow) .......................................+260°C
Other Pins to GND ..................-0.3V to +(Operating V
Maximum RF Input Power ..............................................+15dBm
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
28-Pin Thin QFN (derates 27mW/°C above +70°C)...2500mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX2769
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. Typical
A
CC
values are at V
= 2.85V and T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
Supply Voltage
CONDITIONS
MIN
2.7
15
TYP
2.85
18
MAX
3.3
22
UNITS
V
Default mode, LNA1 is active (Note 2)
Default mode, LNA2 is active (Note 2)
Idle Mode™, IDLE = low
12
15
19
mA
Supply Current
1.5
20
Shutdown mode, SHDN = low
μA
V
Voltage Drop at ANTBIAS from
VCCRF
Sourcing 20mA at ANTBIAS
0.2
Short-Circuit Protection Current
at ANTBIAS
ANTBIAS is shorted to ground
To assert logic-high at ANTFLAG
57
mA
mA
Active Antenna Detection Current
DIGITAL INPUT AND OUTPUT
Digital Input Logic-High
1.1
Measure at the SHDN pin
Measure at the SHDN pin
1.5
V
V
Digital Input Logic-Low
0.4
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
2
Universal GPS Receiver
MAX2769
AC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
A
CC
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.) (Note 1)
A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
dB
CASCADED RF PERFORMANCE
1575.42
1.4
RF Frequency
L1 band
LNA1 input active, default mode (Note 3)
LNA2 input active, default mode (Note 3)
Measured at the mixer input
Noise Figure
2.7
10.3
Out-of-Band 3rd-Order Input
Intercept Point
Measured at the mixer input (Note 4)
Measured at the mixer input
-7
dBm
dBm
In-Band Mixer Input Referred
1dB Compression Point
-85
Mixer Input Return Loss
Image Rejection
10
25
dB
dB
LO leakage
-101
-103
96
Spurs at LNA1 Input
dBm
Reference harmonics leakage
Measured from the mixer to the baseband analog output
Maximum Voltage Gain
Variable Gain Range
91
55
103
dB
dB
59
FILTER RESPONSE
Passband Center Frequency
4
2.5
4.2
8
MHz
MHz
FBW = 00
Passband 3dB Bandwidth
FBW = 10
FBW = 01
Lowpass 3dB Bandwidth
Stopband Attenuation
FBW = 11
9
MHz
dB
3rd-order filter, bandwidth = 2.5MHz, measured at 4MHz offset
5th-order filter, bandwidth = 2.5MHz, measured at 4MHzoffset
30
49.5
41
LNA
LNA1 INPUT
Power Gain
19
0.83
-1.1
10
dB
dB
Noise Figure
Input IP3
(Note 5)
(Note 5)
dBm
dB
Output Return Loss
Intput Return Loss
LNA2 INPUT
Power Gain
8
dB
13
1.14
1
dB
dB
Noise Figure
Input IP3
dBm
dB
Output Return Loss
Input Return Loss
19
11
dB
_______________________________________________________________________________________
3
Universal GPS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
CC
A
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.) (Note 1)
A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FREQUENCY SYNTHESIZER
LO Frequency Range
LO Tuning Gain
0.4V < V
< 2.4V
1550
1610
MHz
MHz/V
MHz
—
TUNE
MAX2769
57
Reference Input Frequency
Main Divider Ratio
8
36
1
44
32,767
1023
Reference Divider Ratio
—
ICP = 0
ICP = 1
0.5
1
Charge-Pump Current
mA
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER
Reference Input Level
Sine wave
0.4
÷4
V
P-P
Clock Output Multiply/Divide
Range
x2
—
ADC
ADC Differential Nonlinearity
ADC Integral Nonlinearity
AGC enabled, 3-bit output
AGC enabled, 3-bit output
0.1
0.1
LSB
LSB
Note 1: MAX2769 is production tested at T = +25°C. All min/max specifications are guaranteed by design and characterization
A
from -40°C to +85°C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must
program the registers upon power-up.
Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an
active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically
disabled and LNA2 becomes active. PLL is in an integer-N mode with f
= f / 16 = 1.023MHz and I = 0.5mA. The
CP
TCXO
COMP
complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output
data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3: The LNA output connects to the mixer input without a SAW filter between them.
Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz
at -60dBm/tone. Passive pole at the mixer output is programmed to be 13MHz.
Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the
GPS center frequency of 1575.42MHz at -60dBm per tone.
4
_______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Typical Operating Characteristics
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
A
CC
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.)
CC
A
CASCADED RECEIVER GAIN
LNA1 |S21| AND |S12|
vs. FREQUENCY
CASCADED GAIN AND NOISE FIGURE
vs. TEMPERATURE
vs. PGA GAIN CODE
MAX2769 toc02
120
100
80
40
30
2.0
1.5
1.0
0.5
0
120
115
110
105
100
95
|S21|
|S12|
T
A
= -40°C
20
AGC GAIN
10
T
A
= +25°C
0
NOISE FIGURE
-10
-20
-30
-40
-50
T
A
= +85°C
60
40
0
90
5
10 15 20 25 30 35 40 45 50 55 60 65
PGA GAIN CODE (DECIMAL FORMAT)
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
FREQUENCY (GHz)
-40
-15
10
35
60
85
TEMPERATURE (°C)
LNA1 GAIN AND NOISE FIGURE
vs. TEMPERATURE
LNA1 GAIN AND NOISE FIGURE
vs. LNA1 BIAS DIGITAL CODE
MAX2769 toc05
MAX2769 toc04
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
19.6
19.4
19.2
19.0
18.8
18.6
18.4
18.2
18.0
17.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
25
LNA BIAS = 1000
GAIN
20
15
10
5
NOISE FIGURE
NOISE FIGURE
GAIN
0
-40
-15
10
35
60
85
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
TEMPERATURE (°C)
LNA BIAS DIGITAL CODE (DECIMAL)
_______________________________________________________________________________________
5
Universal GPS Receiver
Typical Operating Characteristics (continued)
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
A
CC
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.)
A
CC
LNA1 INPUT 1dB COMPRESSION POINT
vs. LNA1 BIAS DIGITAL CODE
LNA2 |S21| AND |S12|
vs. FREQUENCY
LNA2 GAIN AND NOISE FIGURE
vs. TEMPERATURE
MAX2769 toc08
5.0
2.5
30
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
13.6
13.4
13.2
13.0
12.8
12.6
12.4
12.2
LNA BIAS = 10
|S21|
|S12|
MAX2769
0
10
-2.5
-5.0
-7.5
-10.0
-12.5
-15.0
0
-10
-20
-30
-40
-50
NOISE FIGURE
GAIN
35
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
FREQUENCY (GHz)
-40
-15
10
60
85
LNA BIAS DIGITAL CODE (DECIMAL)
TEMPERATURE (°C)
LNA INPUT RETURN LOSS
vs. FREQUENCY
LNA OUTPUT RETURN LOSS
vs. FREQUENCY
MIXER INPUT REFERRED IP1dB
vs. OFFSET FREQUENCY
0
-10
-20
-30
-40
-50
0
-5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
PGA GAIN = 32dB
LNA1
PGA GAIN = 51dB
LNA1
-10
-15
-20
LNA2
LNA2
P
= -100dBm
RF
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
FREQUENCY (GHz)
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
FREQUENCY (GHz)
0
50
100
150
200
250
300
OFFSET FREQUENCY (MHz)
6
_______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Typical Operating Characteristics (continued)
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
A
CC
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.)
CC
A
MIXER INPUT REFERRED NOISE FIGURE
vs. PGA GAIN
1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY
MAX2769 toc12a
MAX2769 toc12b
0
-5
16
14
12
10
8
-10
-15
-20
6
800
825
850
875
900
925
950
1800 1850 1900 1950 2000 2050 2100
5
15
25
35
45
55
65
JAMMER FREQUENCY (MHz)
PGA GAIN (dB)
5TH-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
10
MIXER INPUT REFERRED GAIN
vs. PGA GAIN CODE
3RD-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
10
100
80
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
T
A
= -40°C
T
= +25°C
A
60
T
A
= +85°C
40
20
1
2
3
4
5
6
7
8
9
10
0
5
10 15 20 25 30 35 40 45 50 55 60 65
PGA GAIN CODE (DECIMAL FORMAT)
1
2
3
4
5
6
7
8
9
10
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
_______________________________________________________________________________________
7
Universal GPS Receiver
Typical Operating Characteristics (continued)
(MAX2769 EV kit, V
= 2.7V to 3.3V, T = -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
A
CC
is driven from a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ || 7.5pF on each pin. Typical values
are at V
= 2.85V and T = +25°C, unless otherwise noted.)
CC
A
2-BIT ADC TRANSFER CURVE
3-BIT ADC TRANSFER CURVE
3.5
7
6
5
4
3
2
1
0
MAX2769
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8 1.0
-1.0 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL VOLTAGE (V)
DIFFERENTIAL VOLTAGE (V)
DIGITAL OUTPUT CMOS LOGIC
DIGITAL OUTPUT DIFFERENTIAL LOGIC
MAX2760 toc18
MAX2760 toc19
CLK
2V/div
CLK
1V/div
SIGN DATA
2V/div
SIGN+
1V/div
MAGNITUDE
DATA
2V/div
SIGN-
1V/div
20ns/div
40ns/div
CRYSTAL OSCILLATOR FREQUENCY
vs. DIGITAL TUNING CODE
CRYSTAL OSCILLATOR FREQUENCY
VARIATION vs. TEMPERATURE
16,368.10
16,368.05
16,368.00
16,367.95
16,367.90
16,367.85
10
8
6
T
= +25°C
A
4
2
0
T
A
= -40°C
-2
-4
-6
-8
-10
T
A
= +85°C
0
4
8
12 16 20 24 28 32
-40
-15
10
35
60
85
DIGITAL TUNING CODE (DECIMAL)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Typical Application Circuit
BASEBAND
OUTPUT
C11
C10
C7
TOP VIEW
C6
C5
21
20
19
18
17
16
15
VCCD
14
N.C.
22
23
24
25
26
27
28
C8
VCCCP
CPOUT
VCCIF
IDLE
13
12
11
10
9
MAX2769
C1
C2
FILTER
LNA2
PGM
VCCVCO
VCO
LNA2
LNA1
C4
CS
C0
LNA1
N.C.
SERIAL
INPUT
SCLK
SDATA
8
+
1
2
3
4
5
6
7
C3
C13
ACTIVE
ANTENNA BIAS
C12
Table 1. Component List
DESIGNATION QUANTITY
DESCRIPTION
C0
C1
1
1
1
6
2
1
1
1
0.47nF AC-coupling capacitor
27pF PLL loop filter capacitor
C2
0.47nF PLL loop filter capacitor
C3–C8
C10, C11
C12
0.1μF supply voltage bypass capacitor
10nF AC-coupling capacitor
0.47nF AC-coupling capacitor
0.1nF supply voltage bypass capacitor
20kΩ PLL loop filter resistor
C13
R1
_______________________________________________________________________________________
9
Universal GPS Receiver
Pin Description
PIN
NAME
FUNCTION
Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the
ANTBIAS pin.
1
ANTFLAG
2
3
LNAOUT
ANTBIAS
LNA Output. The LNA output is internally matched to 50Ω.
Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.
RF Section Supply Voltage. Bypass to GND with 100nF and 100pF capacitors in parallel as close as
possible to the pin.
MAX2769
4
VCCRF
5
6
7
8
MIXIN
LD
Mixer Input. The mixer input is internally matched to 50Ω.
Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.
Operation Control Logic Input. A logic-low shuts off the entire device.
Data Digital Input of 3-Wire Serial Interface
SHDN
SDATA
Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising
edge of the SCLK.
9
SCLK
Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high
when the loading action is completed.
10
11
12
CS
VCCVCO
CPOUT
VCO Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and
C (see the Typical Application Circuit).
PLL Charge-Pump Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the
pin.
13
VCCCP
14
15
16
17
18
19
20
21
22
23
VCCD
XTAL
CLKOUT
Q1
Digital Circuitry Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.
Reference Clock Output
Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
Q0
VCCADC
I0
ADC Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.
I1
N.C.
No Connection. Leave this pin unconnected.
VCCIF
IF Section Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.
Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active,
and all other blocks are off.
24
25
26
IDLE
LNA2
PGM
LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50Ω.
Logic Input. Connect to GND to use the serial interface. A logic-high allows programming to 8 hard-
coded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3.
LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50Ω (see the
Typical Application Circuit).
27
28
—
LNA1
N.C.
EP
No connection. Leave this pin open.
Exposed Paddle. Ultra-low-inductance connection to ground. Place several vias to the PCB ground
plane.
10 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Detailed Description
BASEBAND
Integrated Active Antenna Sensor
The MAX2769 includes a low-dropout switch to bias an
external active antenna. To activate the antenna switch
output, set ANTEN in the Configuration 1 register to
logic 1. This closes the switch that connects the anten-
na bias pin to VCCRF to achieve a low 200mV dropout
for a 20mA load current. A logic-low in ANTEN disables
the antenna bias. The active antenna circuit also fea-
tures short-circuit protection to prevent the output from
being shorted to ground.
CLOCK
CLKOUT
16
10nF
MAX2769
XTAL
15
23pF
Low-Noise Amplifier (LNA)
The MAX2769 integrates two low-noise amplifiers. LNA1
is typically used with a passive antenna. This LNA
requires an AC-coupling capacitor. In the default mode,
the bias current is set to 4mA, the typical noise figure and
IIP3 are approximately 0.8dB and -1.1dBm, respectively.
LNA1 current can be programmed through ILNA in
Configuration 1 register. In the low-current mode of 1mA,
the typical noise figure is degraded to 1.2dB and the IIP3
is lowered to -15dBm. LNA2 is typically used with an
active antenna. The LNA2 is internally matched to 50Ω
and requires a DC-blocking capacitor. Bits LNAMODE in
the Configuration 1 register control the modes of the two
LNAs. See Table 6 for the LNA mode settings and current
selections.
Figure 1. Schematic of the Crystal Oscillator in the MAX2679
EV Kit
through a control word (GAINREF). The desired magni-
tude bit density is expressed as a value of GAINREF in
a decimal format divided by the counter length of 512.
For example, to achieve the magnitude bit density of
33%, which is optimal for a 2-bit converter, program the
GAINREF to 170, so that 170 / 512 = 33%.
Baseband Filter
The baseband filter of the receiver can be programmed to
be a lowpass filter or a complex bandpass filter. The low-
pass filter can be configured as a 3rd-order Butterworth
filter for a reduced group delay by setting bit F3OR5 in the
Configuration 1 register to be 1 or a 5th-order Butterworth
filter for a steeper out-of-band rejection by setting the
same bit to be 0. The two-sided 3dB corner bandwidth
can be selected to be 2.5MHz, 4.2MHz, 8MHz, or 18MHz
(only to be used as a lowpass filter) by programming bits
FBW in the Configuration 1 register. When the complex
filter is enabled by changing bit FCENX in the
Configuration 1 register to 1, the lowpass filter becomes a
bandpass filter and the center frequency can be
programmed by bits FCEN in the Configuration 1 register.
Mixer
The MAX2769 includes a quadrature mixer to output low-
IF or zero IF I and Q signals. The quadrature mixer is
internally matched to 50Ω and requires a low-side LO
injection. The output of the LNA and the input of the mixer
are brought off-chip to facilitate the use of a SAW filter.
Programmable Gain Amplifier (PGA)
The MAX2769 integrates a baseband programmable
gain amplifier that provides 59dB of gain control range.
The PGA gain can be programmed through the serial
interface by setting bits GAININ in the Configuration 3
register. Set bits 12 and 11 (AGCMODE) in the
Configuration 2 register to 10 to control the gain of the
PGA directly from the 3-wire interface.
Synthesizer
The MAX2769 integrates a 20-bit sigma-delta fractional-N
synthesizer allowing the device to tune to a required
VCO frequency with an accuracy of approximately
40Hz. The synthesizer includes a 10-bit reference
divider with a divisor range programmable from 1 to
1023, a 15-bit integer portion main divider with a divisor
range programmable from 36 to 32767, and also a 20-bit
fractional portion main divider. The reference divider is
programmable by bits RDIV in the PLL integer division
ratio register (see Table 10), and can accommodate ref-
erence frequencies from 8MHz to 44MHz. The reference
divider needs to be set so the comparison frequency
falls between 0.05MHz to 32MHz.
Automatic Gain Control (AGC)
The MAX2769 provides a control loop that automatically
programs PGA gain to provide the ADC with an input
power that optimally fills the converter and establishes
a desired magnitude bit density at its output. An algo-
rithm operates by counting the number of magnitude
bits over 512 ADC clock cycles and comparing the
magnitude bit count to the reference value provided
______________________________________________________________________________________ 11
Universal GPS Receiver
Table 2. Output Data Format
SIGN/MAGNITUDE
UNSIGNED BINARY
TWO’S COMPLEMENT BINARY
INTEGER
VALUE
1b
0
1.5b
01
01
01
00
00
10
10
10
2b
01
01
00
00
10
10
11
11
2.5b
011
001
001
000
000
101
101
111
3b
1b
1
1.5b
10
10
10
11
11
01
01
01
2b
11
11
10
10
01
01
00
00
2.5b
101
100
100
011
011
001
001
000
3b
1b
0
1.5b
01
01
01
00
00
11
11
11
2b
01
01
00
00
11
11
10
10
2.5b
101
100
100
011
011
111
111
110
3b
7
5
011
010
001
000
100
101
110
111
111
110
101
110
011
010
001
000
011
010
001
000
111
110
101
100
0
1
0
3
0
1
0
1
0
1
0
MAX2769
-1
-3
-5
-7
1
0
1
1
0
1
1
0
1
1
0
1
The PLL loop filter is the only external block of the syn-
thesizer. A typical PLL filter is a classic C-R-C network
at the charge-pump output. The charge-pump output
sink and source current is 0.5mA by default, and the
LO tuning gain is 57MHz/V. As an example, see the
Typical Application Circuit for the recommended loop-
and to center the crystal-oscillator frequency. Take the
parasitic loss of interconnect traces on the PCB into
account when optimizing the load capacitance. For
example, the MAX2769 EV kit utilizes a 16.368MHz
crystal that is designed for a 12pF load capacitance. A
series capacitor of 23pF is used to center the crystal
oscillator frequency, see Figure 1. In addition, the 5-bit
serial-interface word, XTALCAP in the PLL Configuration
register, can be used to vary the crystal-oscillator
frequency electronically. The range of the electronic
adjustment depends on how much the chosen crystal
frequency can be pulled by the varying capacitor. The
frequency of the crystal oscillator used on the MAX2769
EV kit has a range of approximately 200Hz.
filter component values for f
bandwidth = 50kHz.
= 1.023MHz and loop
COMP
The desired integer and fractional divider ratios can be
calculated by dividing the LO frequency (f ) by
LO
f
. f
can be calculated by dividing the TCXO
COMP COMP
frequency (f
) by the reference division ratio
TCXO
(RDIV). For example, let the TCXO frequency be
20MHz, RDIV be 1, and the nominal LO frequency be
1575.42MHz. The following method can be used when
calculating divider ratios supporting various reference
and comparison frequencies:
The MAX2769 provides a reference clock output. The
frequency of the clock can be adjusted to crystal-oscil-
lator frequency, a quarter of the oscillator frequency, a
half of the oscillator frequency, or twice the oscillator
frequency, by programming bits REFDIV in the PLL
Configuration register.
ƒ
20MHz
1
TCXO
ComparisonFrequency =
=
= 20MHz
RDIV
ƒ
1575.42MHz
LO
LOFrequency Divider =
=
= 78.771
ƒ
20MHz
ADC
The MAX2769 features an on-chip ADC to digitize the
downconverted GPS signal. The maximum sampling
rate of the ADC is approximately 50Msps. The sampled
output is provided in a 2-bit format (1-bit magnitude
and 1-bit sign) by default and also can be configured
as a 1-bit, 1.5-bit, or 2-bit in both I and Q channels, or
1-bit, 1.5-bit, 2-bit, 2.5-bit, or 3-bit in the I channel only.
The ADC supports the digital outputs in three different
formats: the unsigned binary, the sign and magnitude,
or the two’s complement format by setting bits FORMAT
in Configuration register 2. MSB bits are output at I1 or
Q1 pins and LSB bits are output at I0 or Q0 pins, for I or
Q channel, respectively. In the case of 2.5-bit or 3-bit,
output data format is selected in the I channel only, the
COMP
Integer Divider = 78(d) = 000 000 0100 1110
(binary)
Fractional Divider = 0.771 x 220 = 808452
(decimal) = 1100 0101 0110 0000 0100
In the fractional mode, the synthesizer should not be
operated with integer division ratios greater than 251.
Crystal Oscillator
The MAX2769 includes an on-chip crystal oscillator. A
parallel mode crystal is required when the crystal oscil-
lator is being used. It is recommended that an AC-cou-
pling capacitor be used in series with the crystal and
the XTAL pin to optimize the desired load capacitance
12 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
011
01
010
001
00
000
-7
-6
-2
-1
-5
-4
-3
3
4
5
1
2
6
7
100
10
T = 1
101
110
11
111
Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases
MSB is output at I1, the second bit is at I0, and the LSB
is at Q1.
divide-by-5 periods. The fractional division ratio is
given by:
Figure 2 illustrates the ADC quantization levels for 2-
and 3-bit cases and also describes the sign/magnitude
data mapping. The variable T = 1 designates the loca-
tion of the magnitude threshold for the 2-bit case.
f
/ f = L
/ (4096 - M
+ L
)
OUT IN
COUNT
COUNT
COUNT
where L
and M
are the 12-bit counter val-
COUNT
COUNT
ues programmed through the serial interface.
DSP Interface
Fractional Clock Divider
A 12-bit fractional clock divider is located in the clock
path prior to the ADC and can be used to generate the
ADC clock that is a fraction of the reference input
clock. In a fractional divider mode, the instantaneous
division ratio alternates between integer division ratios
to achieve the required fraction. For example, if the
fractional output clock is 4.5 times slower than the input
clock, an average division ratio of 4.5 is achieved
through an equal series of alternating divide-by-4 and
GPS data is output from the ADC as the four logic sig-
nals (bit , bit , bit , and bit ) that represent sign/magni-
0
1
2
3
tude, unsigned binary, or two’s complement binary data
in the I (bit and bit ) and Q (bit and bit ) channels. The
0
1
2
3
resolution of the ADC can be set up to 3 bits per chan-
nel. For example, the 2-bit I and Q data in sign/magni-
tude format is mapped as follows: bit = I
MAG
, bit =
1
0
SIGN
. The data can be
I
, bit = Q
, and bit = Q
2
SIGN
3
MAG
serialized in 16-bit segments of bit , followed by bit ,
0
1
bit , and bit . The number of bits to be serialized is con-
2
3
trolled by the bits STRMBITS in the Configuration 3 regis-
______________________________________________________________________________________ 13
Universal GPS Receiver
STRM_EN
PIN 21
PIN 20
PIN 17
PIN 18
I
OUTPUT
DRIVER
ADC
Q
DATA_OUT
CLK_SER
BIT 0
BIT 1
MAX2769
BIT 2
BIT 3
DATA_SYNC
TIME_SYNC
STRM_EN
STRM_START
STRM_STOP
STRM_EN
STRM_COUNT<2:0>
DIEID<1:0>
STRM_BITS<1:0>
FRM_COUNT<27:0>
STAMP_EN
CONTROL
SIGNALS
FROM 3-WIRE
INTERFACE
DAT_SYNCEN
TIME_SYNCEN
STRM_RST
CLK_ADC CLK_SER
L_CNT<11:0>
M_CNT<11:0>
ADCCLK_SEL
CLK_IN CLK_OUT
REF/XTAL
PIN 15
THROUGH
/2
/4
x2
FRCLK_SEL
SERCLK_SEL
REFDIV<1:0>
Figure 3. DSP Interface Top-Level Connectivity and Control Signals
ter. This selects between bit ; bit and bit ; bit and bit ;
At the end of the 16-bit ADC cycle, the data is trans-
ferred into four shift registers and shifted serially to the
output during the next 16-bit ADC cycle. Shift registers
are clocked by a serial clock that must be chosen fast
enough so that all data is shifted out before the next set
of data is loaded from the ADC. An all-zero pattern fol-
lows the data after all valid ADC data are streamed to the
output. A DATASYNC signal is used to signal the begin-
ning of each valid 16-bit data slice. In addition, there is a
TIME_SYNC signal that is output every 128 to 16,384
cycles of the ADC clock.
0
0
1
0
2
and bit , bit , bit , and bit cases. If only bit is serial-
0
1
2
3
0
ized, the data stream consists of bit data only. If a seri-
0
alization of bit and bit (or bit ) is selected, the stream
0
1
2
data pattern consists of 16 bits of bit data followed by
0
16 bits of bit (or bit ) data, which, in turn, is followed by
1
2
16 bits of bit data, and so on. In this case, the serial
0
clock must be at least twice as fast as the ADC clock. If a
4-bit serialization of bit , bit , bit , and bit is chosen, the
0
1
2
3
serial clock must be at least four times faster than the
ADC clock.
The ADC data is loaded in parallel into four holding reg-
isters that correspond to four ADC outputs. Holding reg-
isters are 16 bits long and are clocked by the ADC clock.
14 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
The serial interface is controlled by three signals: SCLK
(serial clock), CS (chip select), and SDATA (serial data).
The control of the PLL, AGC, test, and block selection is
performed through the serial-interface bus from the base-
band controller. A 32-bit word, with the MSB (D27) being
sent first, is clocked into a serial shift register when the
chip-select signal is asserted low. The timing of the inter-
face signals is shown in Figure 4 and Table 4 along with
typical values for setup and hold time requirements.
Preconfigured Device States
When a serial interface is not available, the device can
be used in preconfigured states that don’t require pro-
gramming through the serial interface. Connecting the
PGM pin to logic-high and SCLK, SDATA, and CS pins
to either logic-high or low sets the device in one of the
preconfigured states according to Table 3.
Serial Interface, Address,
and Bit Assignments
A serial interface is used to program the MAX2769 for
configuring the different operating modes.
Table 3. Preconfigured Device States
DEVICE ELECTRICAL CHARACTERISTICS
3-WIRE CONTROL PINS
0
1
2
3
4
5
6
7
16.368
16.368
16.368
32.736
19.2
16
16
16
32
96
18
65
16
1536
1536
1536
1536
7857
1539
7857
1536
I
I
I
I
I
I
I
I
1
1
2
2
2
2
2
1
Differential
Differential
CMOS
4.092
4.092
4.092
4.092
4.092
1.023*
4.092
4.092
5th
3rd
5th
5th
5th
5th
5th
5th
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CMOS
CMOS
18.414
13
CMOS
CMOS
16.368
CMOS
*If the IF center frequency is programmed to 1.023MHz, the filter passband extends from 0.1MHz to 2.6MHz.
CS
t
CSH
t
t
CSS
CSW
SCLK
t
t
DH
t
CH
DS
t
CL
DATA
MSB
DATA
LSB
ADDR
MSB
ADDR
LSB
SDATA
Figure 4. 3-Wire Timing Diagram
______________________________________________________________________________________ 15
Universal GPS Receiver
Table 4. Serial-Interface Timing Requirements
SYMBOL
PARAMETER
Falling edge of CS to rising edge of the first SCLK time.
Data to serial-clock setup time.
TYP VALUE
UNITS
ns
t
10
10
10
25
25
10
1
CSS
t
ns
DS
DH
CH
t
t
Data to clock hold time.
ns
Serial clock pulse-width high.
ns
t
Clock pulse-width low.
ns
CL
MAX2769
t
Last SCLK rising edge to rising edge of CS.
CS high pulse width.
ns
CSH
CSW
t
clock
Table 5. Default Register Setting
REGISTER
NAME
ADDRESS
(A3:A0)
DEFAULT
(D27:D0)
DATA
CONF1
CONF2
CONF3
PLLCONF
DIV
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Configures RX and IF sections, bias settings for individual blocks.
Configures AGC and output sections.
Configures support and test functions for IF filter and AGC.
PLL, VCO, and CLK settings.
A2919A3
0550288
EAFF1DC
9EC0008
0C00080
8000070
8000000
10061B2
1E0F401
14C0402
PLL main and reference division ratios, other controls.
PLL fractional division ratio, other controls.
DSP interface number of frames to stream.
Fractional clock-divider values.
FDIV
STRM
CLK
TEST1
TEST2
Reserved for test mode.
Reserved for test mode.
16 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Detailed Register Definitions
Table 6. Configuration 1 (Address: 0000)
DEFAULT
DATA BIT LOCATION
VALUE
DESCRIPTION
Chip enable. Set 1 to enable the device and 0 to disable the entire device except the
serial bus.
CHIPEN
27
1
IDLE
ILNA1
ILNA2
ILO
26
0
1000
10
Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode.
LNA1 current programming.
25:22
21:20
19:18
17:16
LNA2 current programming.
10
LO buffer current programming.
IMIX
01
Mixer current programming.
Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or
set 0 to program the pole at 13MHz.
MIXPOLE
15
0
LNA mode selection, D14:D13 = 00: LNA selection gated by the antenna bias circuit, 01:
LNA2 is active; 10: LNA1 is active; 11: both LNA1 and LNA2 are off.
LNAMODE
14:13
00
MIXEN
ANTEN
FCEN
12
11
1
1
Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer.
Antenna bias enable. Set 1 to enable the antenna bias and 0 to shut down the antenna bias.
10:5
001101
IF center frequency programming. Default for f
= 4MHz, BW = 2.5MHz.
CENTER
IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 8MHz;
11: 18MHz (only used as a lowpass filter).
FBW
4:3
2
00
0
Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the
3rd-order Butterworth filter.
F3OR5
Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select
lowpass filter mode.
FCENX
FGAIN
1
0
1
1
IF filter gain setting. Set 0 to reduce the filter gain by 6dB.
______________________________________________________________________________________ 17
Universal GPS Receiver
Table 7. Configuration 2 (Address: 0001)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I
channel only.
IQEN
27
0
AGC gain reference value expressed by the number of MSB counts (magnitude bit
density).
GAINREF
—
26:15
14:13
170d
00
MAX2769
Reserved.
AGC mode control. Set D12:D11 = 00: independent I and Q; 01: I and Q gains are
locked to each other; 10: gain is set directly from the serial interface by GAININ;
11: disallowed state.
AGCMODE
12:11
00
Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X:
two’s complement binary.
FORMAT
BITS
10:9
8:6
01
010
00
Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: 1.5 bits; 010: 2 bits;
011: 2.5 bits, 100: 3 bits.
Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: limited differential logic; 1X:
analog outputs.
DRVCFG
5:4
LOEN
RESERVED
DIEID
3
2
1
0
LO buffer enable. Set 1 to enable LO buffer or 0 to disable the buffer.
Reserved.
1:0
00
Identifies a version of the IC.
18 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Table 8. Configuration 3 (Address: 0010)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
GAININ
FSLOWEN
HILOADEN
ADCEN
27:22
21
111010
PGA gain value programming from the serial interface in steps of dB per LSB.
Low value of the ADC full-scale enable. Set 1 to enable or 0 to disable.
Set 1 to enable the output driver to drive high loads.
1
0
1
1
1
1
20
19
ADC enable. Set 1 to enable ADC or 0 to disable.
DRVEN
18
Output driver enable. Set 1 to enable the driver or 0 to disable.
Filter DC offset cancellation circuitry enable. Set 1 to enable the circuitry or 0 to
FOFSTEN
FILTEN
17
16
IF filter enable. Set 1 to enable the filter or 0 to disable.
Highpass coupling enable. Set 1 to enable the highpass coupling between the filter
and PGA, or 0 to disable the coupling.
FHIPEN
15
1
—
14
13
12
1
1
0
Reserved.
PGAIEN
PGAQEN
I-channel PGA enable. Set 1 to enable PGA in the I channel or 0 to disable.
Q-channel PGA enable. Set 1 to enable PGA in the Q channel or 0 to disable.
DSP interface for serial streaming of data enable. This bit configures the IC such
that the DSP interface is inserted in the signal path. Set 1 to enable the interface
or 0 to disable the interface.
STRMEN
11
10
0
0
The positive edge of this command enables data streaming to the output. It also
enables clock, data sync, and frame sync outputs.
STRMSTART
The positive edge of this command disables data streaming to the output. It also
disables clock, data sync, and frame sync outputs.
STRMSTOP
STRMCOUNT
STRMBITS
9
0
8:6
5:4
111
01
Sets the length of the data counter from 128 (000) to 16,394 (111) bits per frame.
Number of bits streamed. D5:D4 = 00: I MSB; 01: I MSB, I LSB; 10: I MSB, Q MSB;
11: I MSB, I LSB, Q MSB, Q LSB.
The signal enables the insertion of the frame number at the beginning of each
frame. If disabled, only the ADC data is streamed to the output.
STAMPEN
3
2
1
1
This signal enables the output of the time sync pulses at all times when streaming
is enabled by the STRMEN command. Otherwise, the time sync pulses are
available only when data streaming is active at the output, for example, in the time
intervals bound by the STRMSTART and STRMSTOP commands.
TIMESYNCEN
This control signal enables the sync pulses at the DATASYNC output. Each pulse
is coincident with the beginning of the 16-bit data word that corresponds to a
given output bit.
DATSYNCEN
STRMRST
1
0
0
0
This command resets all the counters irrespective of the timing within the
stream cycle.
______________________________________________________________________________________ 19
Universal GPS Receiver
Table 9. PLL Configuration (Address: 0011)
DEFAULT
VALUE
DATA BIT
VCOEN
IVCO
LOCATION
DESCRIPTION
27
26
1
VCO enable. Set 1 to enable the VCO or 0 to disable VCO.
VCO current-mode selection. Set 1 to program the VCO in the low-current mode or
0 to program in the normal mode.
0
—
REFOUTEN
—
25
24
23
0
1
1
Reserved.
MAX2769
Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer.
Reserved.
Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2; 01:
clock frequency = XTAL frequency / 4; 10: clock frequency = XTAL frequency / 2; 11:
clock frequency = XTAL.
REFDIV
IXTAL
22:21
20:19
11
01
Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: oscillator normal
current; 01: buffer normal current; 10: oscillator medium current; 11: oscillator high
current.
XTALCAP
LDMUX
ICP
18:14
10000
Digital XTAL load cap programming.
13:10
0000
LD pin output selection. Set D13:D10 = 0000: PLL lock-detect signal.
Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA.
Set 0 for normal operation or 1 to disable the PLL phase frequency detector.
Reserved.
9
8
7
0
0
0
PFDEN
—
Charge-pump test. Set D6:D4 = 000: normal operation; X10: pump up; X01 = pump
down; 100 = high impedance; 111: both up and down on.
CPTEST
6:4
000
INT_PLL
PWRSAV
—
3
2
1
0
1
0
0
0
PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL.
PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable.
Reserved.
Reserved.
—
20 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Table 10. PLL Integer Division Ratio (Address 0100)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
NDIV
RDIV
—
27:13
12:3
2:0
1536d
16d
PLL integer division ratio.
PLL reference division ratio.
Reserved.
000
Table 11. PLL Division Ratio (Address 0101)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
FDIV
—
27:8
7:0
80000h
PLL fractional divider ratio.
01110000 Reserved.
Table 12. DSP Interface (Address 0110)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
This word defines the frame number at which to start streaming. This mode is active
when streaming mode is enabled by a command STRMEN, but a command
FRAMECOUNT
27:0
8000000h STRMSTART is not received. In this case, the frame counter is reset upon the assertion
of STRMEN, and it begins its count. When the frame number reaches the value defined
by FRMCOUNT, the streaming begins.
Table 13. Clock Fractional Division Ratio (Address 0111)
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
L_CNT
M_CNT
27:16
15:4
256d
Sets the value for the L counter.
Sets the value for the M counter.
1563d
Fractional clock divider. Set 1 to select the ADC clock to come from the fractional
clock divider, or 0 to bypass the ADC clock from the fractional clock divider.
FCLKIN
3
2
0
0
ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come
from the reference divider/multiplier.
ADCCLK
Serializer clock selection. Set 0 to select the serializer clock output to come from the
reference divider/multiplier.
SERCLK
MODE
1
0
1
0
DSP interface mode selection.
Table 14. Test Mode 1 (Address 1000)
Table 15. Test Mode 2 (Address 1001)
DEFAULT
VALUE
DEFAULT
VALUE
DATA BIT
LOCATION
DESCRIPTION
DATA BIT
LOCATION
DESCRIPTION
—
27:0
14C0402
Reserved.
—
27:0
1E0F401
Reserved.
______________________________________________________________________________________ 21
Universal GPS Receiver
IF center frequency. Either a fractional-N or an integer-
N mode of the frequency synthesizer can be used
depending on the choice of the reference frequency.
Applications Information
The LNA and mixer inputs require careful consideration
in matching to 50Ω lines. Proper supply bypassing,
grounding, and layout are required for reliable perfor-
mance from any RF circuit.
For Galileo reception, set the IF filter bandwidth to
4.2MHz (FBW = 10) and adjust the IF center frequency
through a control word FCEN to the middle of the down-
converted signal band. Alternatively, use wideband set-
tings of 8MHz and 18MHz when the receiver is in a
zero-IF mode.
Low-Power Operation
The MAX2769 can be operated in a low-power mode
by programming the bias current values of individual
blocks to their minimum recommended values. The list
below summarizes the recommended changes to serial
interface registers from their default states to achieve a
low-power operation:
MAX2769
For GLONASS as well as GPS P-code reception, a
zero-IF receiver configuration is used in which the IF fil-
ter is used in a lowpass filter mode (FCENX = 1) with a
two-sided bandwidth of 18MHz.
ILNA1 = 0010
ILNA2 = 00
ILO = 00
It is recommended that an active antenna LNA be used
in wide-bandwidth applications such that the PGA is
operated at lower gain levels for a maximum band-
width. If a PGA gain is programmed directly from a seri-
al interface, GAININ values between 32 and 38 are
recommended. Set the filter pole at the mixer output to
36MHz through MIXPOLE = 1.
IMIX = 00
F3OR5 = 1
ANTEN = 0
BITS = 000
IVCO = 0
Layout Issues
The MAX2769 EV kit can be used as a starting point for
layout. For best performance, take into consideration
grounding and routing of RF, baseband, and power-
supply PCB proper line. Make connections from vias to
the ground plane as short as possible. On the high-
impedance ports, keep traces short to minimize shunt
capacitance. EV kit Gerber files can be requested at
www.maxim-ic.com.
REFOUTEN = 0
PLLPWRSAV = 1
In this mode, LNA, mixer, LO, and VCO currents are
reduced to their minimum recommended values. The IF
filter is configured as a 3rd-order filter. The output data
is in a 1-bit CMOS mode in the I channel only. PLL is in
an integer-N power-saving mode, which can be used if
the main division ratio is divisible by 32. The antenna
bias circuitry is disabled.
Power-Supply Layout
To minimize coupling between different sections of the
IC, a star power-supply routing configuration with a large
decoupling capacitor at a central VCC node is recom-
mended. The VCC traces branch out from this node, each
going to a separate VCC node in the circuit. Place a
bypass capacitor as close as possible to each supply
pin This arrangement provides local decoupling at each
VCC pin. Use at least one via per bypass capacitor for a
low-inductance ground connection. Do not share the
capacitor ground vias with any other branch.
In the low-power mode, the total current consumption
reduces to 10mA, while the total cascaded noise figure
increases to 3.8dB.
Operation in Wideband Galileo and
GLONASS Applications
The use of the wideband receiver options is recom-
mended for Galileo and GLONASS applications. The
frequency synthesizer is used to tune LO to a desired
frequency, which, in turn, determines the choice of the
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
Chip Information
PROCESS: SiGe BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP
T2855+3
21-0140
WAFER
WDICE8
—
22 ______________________________________________________________________________________
Universal GPS Receiver
MAX2769
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
6/07
1/09
Initial release
—
Added MAX2769E/W, updated specifications
1, 4, 12, 16, 22
Removed references to temperature sensor function, changed four
specifications for SPF, and added soldering temperature
1–4, 8, 9, 10,
14–18, 22
2
6/10
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
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