MAX30001 [MAXIM]
Ultra-Low-Power, Single-Channel Integrated Biopotential (ECG, R-to-R, and Pace Detection) and Bioimpedance (BioZ) AFE;型号: | MAX30001 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Ultra-Low-Power, Single-Channel Integrated Biopotential (ECG, R-to-R, and Pace Detection) and Bioimpedance (BioZ) AFE |
文件: | 总87页 (文件大小:2502K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
General Description
Benefits and Features
● Can be Used in IEC 60601-2-47:2012 Compliant
The MAX30001 is a complete, biopotential and bioimpedance
(BioZ), analog front-end (AFE) solution for wearable
applications. It offers high performance for clinical
and fitness applications, with ultra-low power for long
battery life. The MAX30001 is a single biopotential
channel providing electrocardiogram (ECG) waveforms,
heart rate and pacemaker edge detection, and a single
bioimpedance channel capable of measuring respiration.
Systems
● Clinical-Grade ECG and BioZ AFE with High
Resolution Data Converter
• 15.9 Bits ENOB with 3.1µV
• 17 Bits ENOB with 1.1µV
(typ) Noise for ECG
Noise for BioZ
P-P
P-P
● Better Dry Starts Due to Much Improved Real World
CMRR and High Input Impedance
The biopotential and bioimpedance channels have ESD
protection, EMI filtering, internal lead biasing, DC leads-
off detection, ultra-low-power, leads-on detection during
standby mode, and extensive calibration voltages for built-
in self-test. Soft power-up sequencing ensures no large
transients are injected into the electrodes. Both channels
also have high input impedance, low noise, high CMRR,
programmable gain, various low-pass and high-pass filter
options, and a high resolution analog-to-digital converter.
The biopotential channel is DC coupled, can handle large
electrode voltage offsets, and has a fast recovery mode
to quickly recover from overdrive conditions, such as defi-
brillation and electro-surgery. The bioimpedance channel
includes integrated programmable current drive, works
with common electrodes, and has the flexibility for 2 or
4 electrode measurements. The bioimpedance channel
also has AC lead off detection.
• Fully Differential Input Structure with CMRR > 100dB
● Offers Better Common-Mode to Differential Mode
Conversion Due to High Input Impedance
● High Input Impedance > 1GΩ for Extremely Low
Common-to-Differential Mode
● Minimum Signal Attenuation at the Input During Dry
Start Due to High Electrode Impedance
● High DC Offset Range of ±650mV (1.8V, typ) Allows
to Be Used with Wide Variety of Electrodes
● High AC Dynamic Range of 65mV
for ECG and
P-P
90mV
for BioZ Will Help Prevent Saturation in the
P-P
Presence of Motion/Direct Electrode Hits
● Longer Battery Life Compared to Competing Solutions
• 85µW at 1.1V Supply Voltage for ECG
• 158µW at 1.1V Supply Voltage for BioZ
● Leads-On Interrupt Feature Allows to Keep the µC
in Deep Sleep Mode Until Valid Lead Condition is
Detected
The MAX30001 is available in a 30-bump wafer-level
package (WLP), operating over the 0°C to +70°C com-
mercial temperature range.
• Lead-On Detect Current: 0.7µA (typ)
Applications
● Single-Lead Event Monitors for Arrhythmia Detection
● Built-In Heart Rate Detection with Interrupt Feature
Eliminates the Need to Run HR Algorithm on the
µController
● Single-Lead Wireless Patches for
• Robust R-R Detection in High Motion Environment
at Extremely Low Power
In-Patient/Out-Patient Monitoring
● Chest Band Heart Rate Monitors for Fitness
● Configurable Interrupts Allows the µC Wake-Up Only
on Every Heart Beat Reducing the Overall System
Power
Applications
● Bio Authentication and ECG-On-Demand Applications
● Respiration and Hydration Monitors
● High Accuracy Allows for More Physiological Data
● Impedance Based Heart Rate Detection
Extractions
● 32-Word ECG and 8-Word BioZ FIFOs Allows the
MCU to Stay Powered Down for 256ms with Full
Data Acquisition
Ordering Information appears at end of data sheet.
● High-Speed SPI Interface
● Shutdown Current of 0.6µA (typ)
19-100133; Rev 2; 8/19
MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Functional Diagram
AVDD
DVDD
OVDD
MAX30001
PACE DETECT CHANNEL
AOUT
BUFFER
MUX
POL.
SW.
LPF
LPF
PACEP
PACEN
RESPIRATION
CANCEL,
DERIVATIVE,
SAMPLE/HOLD
WINDOW
COMPARE
AND
INPUT
AMP
PGA
RESYNC
BIOIMPEDANCE CHANNEL
AAF
CSB
SDI
HPF
BIP
BIN
ESD, EMI,
INPUT MUX,
DC LEAD
CHECK
20-BIT
INPUT
AMP
20-BIT
∑Δ ADC
DECIMATION
FILTER
f
-3dB
PGA
= 600Hz
SCLK
SDO
-20dB/dec
-40dB/dec
SPI INTERFACE,
ECG FIFO,
AND
CLOCK DIVIDER
w/ PHASE
ADJUST
REGISTERS
SELECTABLE PHASE
INTB
DRVP
DRVN
PUSH/PULL
CURRENT
SOURCE
INT2B
BIOPOTENTIAL CHANNEL
AAF
-3dB
= 600Hz
-40dB/dec
ECGP
ECGN
ESD, EMI,
INPUT MUX,
DC LEAD
CHECK
18-BIT
14-BIT
INPUT
AMP
18-BIT
∑Δ ADC
DECIMATION
FILTER
f
PGA
FAST
SETTLING
R-TO-R
DETECTOR
CAPP
CAPN
SUPPORT CIRCUITRY
COMMON-MODE
BUFFER
REFERENCE
BUFFER
FCLK
f
CLK
SEQUENCER
BANDGAP
BIASING
PLL
f
HFC
AGND
CPLL
DGND
V
V
BG
V
R
BIAS
CM
REF
Maxim Integrated
│ 2
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Absolute Maximum Ratings
AVDD to AGND ....................................................-0.3V to +2.0V
DVDD to DGND....................................................-0.3V to +2.0V
AVDD to DVDD ....................................................-0.3V to +0.3V
OVDD to DGND ...................................................-0.3V to +3.6V
AGND to DGND ...................................................-0.3V to +0.3V
CSB, SCLK, SDI, FCLK to DGND .......................-0.3V to +3.6V
SDO, INTB, INT2B
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (T = +70°C)
A
30-Bump WLP
(derate 24.3mW/ºC above +70ºC)..........................1945.5mW
Operating Temperature Range...............................0ºC to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (Soldering, 10sec).............................+300°C
Soldering Temperature (reflow).......................................+260°C
to DGND........ -0.3V to the lower of (3.6V and OVDD + 0.3V)
All Other Pins
to AGND ......... -0.3V to the lower of (2.0V and AVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 30 WLP
Package Code
W302L2+1
Outline Number
21-100074
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
44°C/W
JA
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Electrical Characteristics
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 1)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
-15
TYP
MAX
+15
UNITS
ECG CHANNEL
V
V
V
V
= +1.1V, THD < 0.3%
= +1.8V, THD < 0.3%
= +1.1V, shift from nominal gain < 2%
= +1.8V
AVDD
AC Differential Input Range
mV
P-P
±32.5
±650
AVDD
-300
+300
AVDD
AVDD
DC Differential Input Range
mV
V
= +1.1V, from V
, shift from nominal
AVDD
MID
-150
100
+150
gain < 2%
Common Mode Input Range
mV
dB
V
= +1.8V, from V
, shift from nominal
AVDD
MID
±550
gain < 2%
0Ω source impedance, f = 64Hz, T = +25˚C
(Note 2)
A
115
77
Common Mode Rejection Ratio
CMRR
With impedance mismatch (Note 3)
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.77
4.6
MAX
UNITS
µV
RMS
BW = 0.05 – 150Hz, G
= 20x
CH
µV
ECG Channel Input Referred
Noise
P-P
0.46
3.1
1.0
6.6
+1
µV
RMS
BW = 0.05 – 40Hz, G
= 20x (Note 2)
CH
µV
P-P
Input Leakage Current
Input Impedance (INA)
T
= +25°C
-1
±0.1
45
nA
A
Common-mode, DC
GΩ
MΩ
Differential, DC
1500
V
G
= +1.80V, V = 65mV , F = 64Hz,
IN P-P IN
= 20x, electrode offset = ±300mV
AVDD
0.025
ECG Channel Total Harmonic
Distortion
CH
THD
%
V
G
= +1.1V, V = 30mV , F = 64Hz,
IN P-P IN
= 20x, electrode offset = ±300mV
AVDD
0.3
CH
ECG Channel Gain Setting
G
Programmable, see ECG_GAIN[1:0]
20 to 160
V/V
%
CH
V
= +1.8V, G = 20x,
AVDD
CH
-2.5
-4.5
+2.5
+4.5
ECGP = ECGN = VMID
ECG Channel Gain Error
(Excluding Reference)
V
= +1.1V, G = 20x,
AVDD
CH
%
ECGP = ECGN = VMID
% of
FSR
ECG Channel Offset Error
ADC Resolution
(Note 4)
±0.1
18
Bits
125 to
512
ADC Sample Rate
Programmable, see ECG_RATE[1:0]
SPS
FHP = 1/(2π x R
x C
), C
=
HPF
HPF
HPF
CAPP to CAPN Impedance
R
320
450
600
kΩ
µA
ms
Hz
HPF
capacitance between CAPP and CAPN
Fast recovery enabled (1.8V)
Fast recovery enabled (1.1V)
Fast recovery disabled
160
55
Analog High-Pass Filter Slew
Current
0.09
C
= 10µF, Note: varies by sample rate,
HPF
Fast Settling Recovery Time
Digital Low-Pass Filter
500
see Table 3.
DLPF[0:1] = 01
DLPF[0:1] = 10
DLPF[0:1] = 11
40
Linear phase FIR filter.
ECG_RATE = 00, 01
100
150
0.5
Digital High-Pass Filter
Phase-corrected 1st-order IIR filter. DHPF = 1
Lead bias disabled, DC
Hz
dB
107
110
ECG Power Supply Rejection
PSRR
Lead bias disabled, f = 64Hz
Maxim Integrated
│ 4
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ECG INPUT MUX
IMAG[2:0] = 001
IMAG[2:0] = 010
IMAG[2:0] = 011
IMAG[2:0] = 100
IMAG[2:0] = 101
5
10
Pullup/
pulldown
DC Lead Off Check
20
nA
50
100
V
0.50
–
–
–
–
+
+
+
+
MID
VTH[1:0] = 11 (Note 5)
VTH[1:0] = 10 (Note 6)
VTH[1:0] = 01 (Note 7)
VTH[1:0] = 00
V
MID
0.45
DC Lead Off Comparator Low
Threshold
V
V
MID
0.40
V
MID
0.30
V
MID
VTH[1:0] = 11 (Note 5)
VTH[1:0] = 10 (Note 6)
VTH[1:0] = 01 (Note 7)
VTH[1:0] = 00
0.50
V
MID
0.45
DC Lead Off Comparator High
Threshold
V
V
MID
0.40
V
MID
0.30
RBIASV[1:0] = 00
RBIASV[1:0] = 01
RBIASV[1:0] = 10
50
Lead Bias Impedance
Lead bias enabled
100
200
MΩ
V
/
AVDD
2.15
Lead Bias Voltage
V
Lead bias enabled
Single-ended
V
MID
V
V
= 0
= 1
0.25
0.50
MAG
Calibration Voltage Magnitude
mV
MAG
Calibration Voltage Magnitude
Error
Single-ended (Note 8)
-3
+3
%
0.0156 to
256
Calibration Voltage Frequency
Programmable, see FCAL[2:0]
Hz
0.03052
to 62.474
FIFTY = 0
FIFTY = 1
ms
%
Programmable, see
THIGH[10:0]
Calibration Voltage Pulse Time
50
Maxim Integrated
│ 5
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BIOIMPEDANCE (BioZ) CHANNEL
Signal Generator Resolution
Square wave generator
1
Bits
DRVP/N Injected Full-Scale
Current
Programmable, see BIOZ_CGMAG[2:0]
8 to 96
μA
PK
Internal bias resistor, see EXT_RBIAS
-30
-10
+30
+10
DRVP/N Injected Current
Accuracy
%
External bias resistor (0.1%, 10ppm, 324kΩ)
DRVP/N Injected Current
Power Supply Rejection
<±1
50
%/V
DRVP/N Injected Current
Temperatue Coefficient
External bias resistor, 32μA , 0 to 70ºC
(0.1%, 10ppm, 324kΩ)
P-P
ppm/°C
±(V
-
AVDD
0.5)
DRVP/N Compliance Voltage
Current Injection Frequency
V
- V
V
P-P
DRVP
DRVN
0.125 to
131.072
Programmable, see BIOZ_FCGEN[3:0]
kHz
Shift from nominal gain < 1% (V
Shift from nominal gain < 1% (V
= 1.1V)
= 1.8V)
25
90
mV
mV
V/V
AVDD
AVDD
AC Differential Input Range
BioZ Channel Gain
ADC Sample Rate
ADC Resolution
Programmable, see BIOZ_GAIN[1:0]
10 to 80
24.98 to
64
Programmable, see BIOZ_RATE
sps
Bits
20
0.16
1.1
BW = 0.05 to 4Hz, Gain = 20x
BW = 0.05 to 4Hz, Gain = 20x
μV
RMS
Input Referred Noise
(BIP, BIN)
μV
P-P
DC to 4Hz, 32µA , 40kHz, Gain = 20x,
P-P
Impedance Resolution
40
mΩ
P-P
R
= 680Ω
BODY
125 to
7200
Input Analog High Pass Filter
Demodulation Phase Range
Programmable, see BIOZ_AHPF[2:0]
Programmable, see BIOZ_PHOFF[3:0]
Hz
0 - 168.75
°
°
Demodulation Phase
Resolution
11.25
BIOZ_DLPF[1:0] = 01
BIOZ_DLPF[1:0] = 10
BIOZ_DLPF[1:0] = 11
BIOZ_DHPF[1:0] = 01
BIOZ_DHPF[1:0] = 1x
4
8
Output Digital Low Pass Filter
Output Digital High Pass Filter
Hz
16
0.05
0.5
Hz
Hz
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BIOIMPEDANCE (BioZ) INPUT MUX
IMAG[2:0] = 001
IMAG[2:0] = 010
IMAG[2:0] = 011
IMAG[2:0] = 100
IMAG[2:0] = 101
5
10
DC Lead Off Check
20
nA
50
100
DCLOFF_VTH[1:0] = 11 (Note 5)
DCLOFF_VTH[1:0] = 10 (Note 6)
DCLOFF_VTH[1:0] = 01 (Note 7)
DCLOFF_VTH[1:0] = 00
V
V
V
V
- 0.50
MID
MID
MID
MID
MID
MID
MID
MID
- 0.45
- 0.40
- 0.30
+ 0.50
+ 0.45
+ 0.40
+ 0.30
DC Lead Off Comparator Low
Threshold
V
DCLOFF_VTH[1:0] = 11 (Note 5)
DCLOFF_VTH[1:0] = 10 (Note 6)
DCLOFF_VTH[1:0] = 01 (Note 7)
DCLOFF_VTH[1:0] = 00
V
V
V
V
DC Lead Off Comparator High
Threshold
V
Lead bias enabled, RBIASV[1:0] = 00
Lead bias enabled, RBIASV[1:0] = 01
Lead bias enabled, RBIASV[1:0] = 10
50
Lead Bias Impedance
100
200
MΩ
V
AVDD
2.15
/
Lead Bias Voltage
V
Lead bias enabled.
V
MID
Single-ended. V
Single-ended. V
= 0
= 1
0.25
0.50
MAG
MAG
Calibration Voltage Magnitude
mV
Calibration Voltage Error
Single-ended. (Note 8)
-3
+3
%
0.0156 to
256
Calibration Voltage Frequency
Programmable, see FCAL[2:0]
Hz
0.03052
to 62.474
FIFTY = 0
FIFTY = 1
ms
Programmable,
see THIGH[10:0]
Calibration Voltage Pulse Time
Resistive Load Nominal Value
50
%
R
Programmable, see BMUX_RNOM[2:0]
0.625 to 5.0
kΩ
VAL
Resistive Load Modulation
Value
R
Programmable, see BMUX_RMOD[2:0]
15 to 2960
mΩ
MOD
Resistive Load Modulation
Frequency
F
Programmable, see BMUX_FBIST[1:0]
0.625 to 4.0
Hz
MOD
Maxim Integrated
│ 7
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
PACE DETECTION
Pace Artifact Width
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.05 to 2.0
0.5
ms
Minimum Pace Artifact
Amplitude
mV
Time Resolution
16
µs
µs
Recovery Time
Large Pacer Pulse (100mV to 700mV)
500
100
AOUT Output Voltage Swing
f = 1kHz, THD < 0.2%
mV
P-P
INTERNAL REFERENCE/COMMON-MODE
V
V
Output Voltage
V
0.650
100
V
BG
BG
Output Impedance
kΩ
BG
External V
Capacitor
Compensation
BG
C
V
1
µF
VBG
V
V
V
V
Output Voltage
T
T
= +25ºC
0.995
1.000
10
1.005
V
REF
REF
REF
REF
REF
A
Temperature Coefficient
Buffer Line Regulation
Buffer Load Regulation
TC
= 0ºC to +70ºC
ppm/ºC
µV/V
REF
A
330
25
I
= 0 to 100µA
µV/µA
LOAD
External V
Capacitor
Compensation
REF
C
1
10
0.650
10
µF
V
REF
V
Output Voltage
V
CM
CM
External V
Capacitor
Compensation
CM
C
1
µF
CM
DIGITAL INPUTS (SDI, SCLK, CSB, FCLK)
Input-Voltage High
Input-Voltage Low
Input Hysteresis
Input Capacitance
Input Current
V
0.7 x V
V
V
IH
OVDD
V
0.3 x V
IL
OVDD
V
0.05 x V
V
HYS
OVDD
C
10
pF
µA
IN
I
-1
+1
IN
DIGITAL OUTPUTS (SDO, INTB, INT2B)
Output Voltage High
V
I
I
= 1mA
V
- 0.4
V
V
OH
SOURCE
OVDD
Output Voltage Low
V
= 1mA
SINK
0.4
+1
OL
Three-State Leakage Current
-1
µA
Three-State Output
Capacitance
15
pF
POWER SUPPLY
Analog Supply Voltage
Digital Supply Voltage
Interface Supply Voltage
V
Connect AVDD to DVDD
Connect DVDD to AVDD
Power for I/O drivers only
1.1
1.1
2.0
2.0
3.6
V
V
V
AVDD
DVDD
OVDD
V
V
1.65
Maxim Integrated
│ 8
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Electrical Characteristics (continued)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
76
MAX
120
150
190
270
285
190
205
250
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
= +1.1V
= +1.8V
= +2.0V
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
ECG channel
95
102
100
124
133
114
138
147
205
232
242
220
247
256
144
163
170
158
178
185
186
211
220
200
225
235
1.3
ECG channel with
Pace
(Note 2)
ECG channel with
Pace and AOUT
(Note 2)
ECG channel with
Pace, and BioZ,
LN_BIOZ = 0
ECG channel with
Pace, and BioZ,
LN_BIOZ = 1
I
+
AVDD
Supply Current
µA
I
DVDD
BioZ channel ,
LN_BIOZ = 0
(Note 2)
BioZ channel ,
LN_BIOZ = 1
(Note 2)
ECG channel and
BioZ, LN_BIOZ = 0 V
(Note 2)
V
V
ECG channel and
BioZ, LN_BIOZ = 1 V
(Note 2)
V
265
2.5
T
T
= +70ºC
= +25ºC
ULP Lead On
Detect
A
0.63
A
V
= +1.65V, ECG channel at 512sps
OVDD
0.2
0.6
(Note 9)
Interface Supply Current
Shutdown Current
I
µA
µA
OVDD
V
= 3.6V, ECG channel at 512sps
OVDD
1.6
(Note 9)
V = V
AVDD
T
T
= +70ºC
= +25ºC
1.3
I
+
A
SAVDD
I
DVDD
= 2.0V (Note 4)
0.58
2.5
1.1
SDVDD
SOVDD
A
I
V
= 3.6V, V
= V
= 2.0V
OVDD
AVDD
DVDD
Maxim Integrated
│ 9
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Timing Characteristics (Note 3)
(V
= V
= +1.1V to +2.0V, V
= +1.65V to +3.6V, f
= 32.768kHz, LN_BIOZ = 1, T = T
to T
, unless otherwise
MAX
DVDD
AVDD
OVDD
FCLK
A
MIN
noted. Typical values are at V
= V
= +1.8V, V = +2.5V, T = +25°C.) (Note 2)
OVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ESD PROTECTION
IEC 61000-4-2 Contact Discharge (Note 10)
IEC 61000-4-2 Air-Gap Discharge (Note 10)
JEDEC JESD22-A114 HBM Transient Pulse
±8
ECGP, ECGN, BIP, BIN
kV
kV
±15
±2.5
All Other Pins
TIMING CHARACTERISTICS (NOTE 3)
SCLK Frequency
f
0
12
MHz
ns
SCLK
SCLK Period
t
83
15
15
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
t
ns
CL
CSB Fall to SCLK Rise Setup
Time
t
To 1st SCLK rising edge (RE)
15
0
ns
ns
ns
CSS0
CSH0
CSH1
CSB Fall to SCLK Rise Hold
Time
t
t
Applies to inactive RE preceding 1st RE
Applies to 32nd RE, executed write
CSB Rise to SCLK Rise Hold
Time
10
CSB Rise to SCLK Rise
SCLK Rise to CSB Fall
t
t
Applies to 32nd RE, aborted write sequence
Applies to 32nd RE
15
100
20
8
ns
ns
ns
ns
ns
ns
CSA
CSF
CSB Pulse-Width High
t
CSPW
SDI-to-SCLK Rise Setup Time
SDI to SCLK Rise Hold Time
t
DS
DH
t
8
C
C
= 20pF
40
20
LOAD
SCLK Fall to SDO Transition
t
= 20pF, V
= V
≥ 1.8V,
DOT
LOAD
OVDD
AVDD
DVDD
ns
V
≥ 2.5V
SCLK Fall to SDO Hold
CSB Fall to SDO Fall
CSB Rise to SDO Hi-Z
FCLK Frequency
t
C
= 20pF
2
ns
ns
DOH
LOAD
t
Enable time, C
Disable time
= 20pF
LOAD
30
35
DOE
t
ns
DOZ
f
External reference clock
32.768
30.52
15.26
15.26
kHz
µs
FCLK
FCLK Period
t
FP
FCLK Pulse-Width High
FCLK Pulse-Width Low
t
50% duty cycle assumed
50% duty cycle assumed
µs
FH
t
µs
FL
Note 1:
All devices are 100% production tested at T = +25ºC. Specifications over the operating temperature range and relevant
A
supply voltage range are guaranteed by design and characterization.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Guaranteed by design and characterization. Not tested in production.
One electrode drive with <10Ω source impedance, the other driven with 51kΩ in parallel with a 47nF per IEC60601-2-47.
Inputs connected to 51kΩ in parallel with a 47nF to V
.
CM
Use this setting only for V
Use this setting only for V
Use this setting only for V
= V
= V
= V
≥ 1.65V.
≥ 1.55V.
≥ 1.45V.
AVDD
AVDD
AVDD
DVDD
DVDD
DVDD
This specification defines the accuracy of the calibration voltage source as applied to the ECG input, not as measured
through the ADC channel.
Note 9:
f
= 4MHz, burst mode, EFIT = 8, C
= C
= 50pF.
SCLK
SDO
INTB
Note 10: ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.
Maxim Integrated
│ 10
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
SDI
A6
A5
A4
A3
A2
A1
A0
R/WB
8
DIN23
DIN22
DIN1
DIN0
A6'
t
t
CP
DS
t
DH
SCLK
1
2
3
4
5
6
7
9
10
31
32
1'
t
CSA
t
CSH0
t
CL
t
CSH1
t
CSS0
t
CH
CSB
SDO
t
CSPW
Z
t
t
t
CSF
DOT
DOH
DO1
Z
DO23
DO22
DO0
t
DOZ
t
DOE
Figure 1a. SPI Timing Diagram
tFP
FCLK
tFH
tFL
Figure 1b. FCLK Timing Diagram
Maxim Integrated
│
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics
(V
= V
= 1.8V, V
= 2.5V, T = +25°C, unless otherwise noted.)
DVDD
AVDD
OVDD A
ECG NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 20, LPF = 150Hz
ECG NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 160, LPF = 40Hz
ECG NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 20, LPF = 40Hz
0
-20
0
-20
0
-20
-40
-40
-40
-60
-60
-60
-80
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
-200
0
64
128
192
256
0
0
0
64
128
192
256
0
64
128
192
256
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
ECG NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 160, LPF = 150Hz
BIOZ NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 10, LPF = 4Hz
BIOZ NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 10, LPF = 16Hz
0
-20
0
-50
0
-50
-40
-60
-80
-100
-150
-200
-250
-100
-150
-200
-250
-100
-120
-140
-160
-180
-200
0
64
128
192
256
8
16
24
32
0
8
16
24
32
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
BIOZ NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 80, LPF = 4Hz
BIOZ NOISE SPECTRUM vs. FREQUENCY
INPUTS SHORTED, GAIN = 80, LPF = 16Hz
ECG INPUT-REFERRED NOISE vs. TIME
GAIN = 20, LPF = 40Hz (10s)
0
-50
0
-50
4
3
2
1
-100
-150
-200
-250
-100
-150
-200
-250
0
-1
-2
-3
-4
0
8
16
24
32
8
16
24
32
0
2
4
6
8
10
FREQUENCY (Hz)
FREQUENCY (Hz)
TIME (s)
Maxim Integrated
│ 12
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V
= 2.5V, T = +25°C, unless otherwise noted.)
DVDD
AVDD
OVDD A
ECG INPUT-REFERRED NOISE vs. TIME
GAIN = 20, LPF = 150Hz (10s)
ECG INPUT-REFERRED NOISE vs. TIME
GAIN = 160, LPF = 40Hz (10s)
ECG INPUT-REFERRED NOISE vs. TIME
GAIN = 160, LPF = 150Hz (10s)
4
3
4
3
4
3
2
2
2
1
1
1
0
0
0
-1
-2
-3
-4
-1
-2
-3
-4
-1
-2
-3
-4
0
2
4
6
8
10
0
2
4
6
8
10
0
2
4
6
8
10
TIME (s)
TIME (s)
TIME (s)
ECG NOISE HISTOGRAM
GAIN = 20, LPF = 40Hz
ECG NOISE HISTOGRAM
GAIN = 20, LPF = 150Hz
ECG NOISE HISTOGRAM
GAIN = 160, LPF = 40Hz
1800
1600
1400
1200
1000
800
600
400
200
0
1000
900
800
700
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
STDEV = 0.47µV
OFFSET = -17.71µV
0
-50 -49 -48 -47 -46 -45 -44 -43 -42
ADC CODE
-54 -52 -50 -48 -46 -44 -42 -40 -38
ADC CODE
-45 -41 -37 -33 -29 -25 -21 -17 -13 -9 -5 -1
ADC CODE
3
ECG NOISE HISTOGRAM
GAIN = 160, LPF = 150Hz
ECG PSRR vs. FREQUENCY
ECG CMRR vs. FREQUENCY
130
120
110
100
90
200
180
160
140
120
100
80
1000
100
10
0Ω ON BOTH
INPUTS, GAIN = 20
0Ω ON BOTH INPUTS,
GAIN = 160
51kΩ || 47nF LOAD
ON BOTH INPUTS,
GAIN = 160
51kΩ || 47nF LOAD
ON BOTH INPUTS,
GAIN = 20
60
80
0Ω on ECGP,
51kΩ || 47nF on ECGN,
GAIN = 160
40
0Ω on ECGP,
51kΩ || 47nF on ECGN,
GAIN = 20
70
20
60
0
1
0
64
128
FREQUENCY (Hz)
192
256
-72 -65 -58 -51 -44 -37 -30 -23 -16 -9 -2
ADC CODE
5
12 19
0
0.5
1
1.5
2
2.5
FREQUENCY (MHz)
Maxim Integrated
│
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V = 2.5V, T = +25°C, unless otherwise noted.)
OVDD A
DVDD
AVDD
ECG DIFFERENTIAL INPUT
RESISTANCE vs. FREQUENCY
ECG COMMON-MODE
INPUT RESISTANCE vs. FREQUENCY
ECG DIFFERENTIAL INPUT
RESISTANCE vs. VOLTAGE
10000
1000
100
10
10000
1000
100
10
10000
1000
100
10
NO
LEAD BIAS
NO LEAD
200MΩ
200MΩ
LEAD BIAS
BIAS
LEAD BIAS
NO LEAD
BIAS
200MΩ
LEAD BIAS
50MΩ
LEAD BIAS
100MΩ
50MΩ
100MΩ
LEAD BIAS
LEAD BIAS
LEAD BIAS
100MΩ
LEAD BIAS
50MΩ
LEAD BIAS
1
1
1
0
64
128
192
256
0
64
128
FREQUENCY (Hz)
192
256
-500
-300
-100
100
300
500
FREQUENCY (Hz)
VECGP-VECGN (mV)
ECG COMMON-MODE
INPUT RESISTANCE vs. VOLTAGE
ECG DIFFERENTIAL INPUT
RESISTANCE vs. TEMPERATURE
ECG COMMON-MODE
INPUT RESISTANCE vs. TEMPERATURE
10000000
1000000
100000
10000
1000
10000
1000
100
10
1000000
100000
10000
1000
100
NO LEAD
200MΩ
BIAS
LEAD BIAS
NO LEAD
BIAS
NO LEAD
BIAS
200MΩ
LEAD BIAS
200MΩ
LEAD BIAS
100MΩ
LEAD BIAS
50MΩ
LEAD BIAS
100
10
100MΩ
50MΩ
LEAD BIAS
10
50MΩ
LEAD BIAS
100MΩ
LEAD BIAS
LEAD BIAS
1
1
1
-400
-200
0
200
400
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
VCM-VMID (mV)
TEMPERATURE (°C)
TEMPERATURE (°C)
BIOZ DIFFERENTIAL INPUT
RESISTANCE vs. VOLTAGE
BIOZ COMMON-MODE
INPUT RESISTANCE vs. VOLTAGE
ECG THD vs. FREQUENCY
0
-20
1000000
100000
10000
1000
1000000
100000
10000
1000
NO
LEAD BIAS
NO
LEAD BIAS
-40
ECG GAIN = 20
100MΩ
LEAD BIAS
200MΩ
LEAD BIAS
-60
50MΩ LEAD
BIAS
100MΩ
LEAD BIAS
200MΩ
LEAD BIAS
50MΩ
LEAD BIAS
ECG GAIN = 40
ECG GAIN = 80
-80
100
100
-100
-120
ECG GAIN = 160
64
10
10
0
128
192
256
-800 -600 -400 -200
0
200 400 600 800
-600
-400
-200
0
200
400
600
FREQUENCY (Hz)
VBIP-VBIN (mV)
VCM-VMID (mV)
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V = 2.5V, T = +25°C, unless otherwise noted.)
OVDD A
DVDD
AVDD
ECG FILTER RESPONSE
HPF = 0.5Hz, LPF = 40Hz
GAIN = 20V/V, SAMPLE RATE = 512
ECG FFT
ECG THD vs. INPUT AMPLITUDE
GAIN = 20, FIN = 25Hz, LPF BYPASSED
0
-20
20
0
0
-20
CHPF = 10µF
-40
-20
-40
-60
-80
-100
-120
-60
-40
-80
ECG GAIN = 20
-60
-100
-120
-140
-160
-180
-200
ECG GAIN = 80
-80
-100
ECG GAIN = 40
ECG GAIN =
160
-120
0
20
40
60
80
100
0
64
128
192
256
0.1
1
10
100
1000
AMPLITDUE (mVP-P
)
FREQUENCY (Hz)
FREQUENCY (Hz)
ECG FILTER RESPONSE
HPF = 0.5Hz, LPF = 100Hz
ECG FILTER RESPONSE
HPF = 0.5Hz, LPF = 150Hz
GAIN = 20V/V, SAMPLE RATE = 512
VREF vs. TEMPERATURE
GAIN = 20V/V, SAMPLE RATE = 512
20
0
20
0
1000.6
1000.5
1000.4
1000.3
1000.2
1000.1
1000
CHPF = 10µF
CHPF = 10µF
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
999.9
DHPF = 0.5Hz
DLPF = 100Hz
DHPF = 0.5Hz
DLPF = 150Hz
999.8
999.7
999.6
0.1
1
10
100
1000
0.1
1
10
100
1000
0
10
20
30
40
50
60
70
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
BIOZ DRIVE CURRENT vs. TEMPERATURE
INTERNAL BIASING
BIOZ DRIVE CURRENT vs. TEMPERATURE
EXTERNAL BIASING
DVDD SHUTDOWN CURRENT
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
96µA
VDVDD = +2.0V
80μA
80µA
64µA
VDVDD = +1.8V
48µA
32µA
32μA
8μA
16µA
8μA
VDVDD = +1.1V
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
│ 15
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V
= 2.5V, T = +25°C, unless otherwise noted.)
DVDD
AVDD
OVDD A
OVDD SHUTDOWN CURRENT
AVDD SHUTDOWN CURRENT
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.12
0.10
0.08
0.06
0.04
0.02
0.00
VOVDD = +1.5V
VAVDD = +2.0V
VAVDD = +1.8V
VOVDD = +1.1V
VOVDD = +2.0V
VOVDD = +1.8V
VAVDD = +1.5V
VAVDD = +1.1V
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
70
70
TEMPERATURE (°C)
TEMPERATURE (°C)
AVDD AND DVDD SUPPLY CURRENT
vs. TEMPERATURE
AVDD AND DVDD SUPPLY CURRENT
vs. TEMPERATURE
(ECG, PACE ENABLED)
(ECG ENABLED)
110
150
140
130
120
110
100
90
105
100
95
2.0V
1.8V
2.0V
1.8V
90
85
80
1.1V
75
1.1V
80
70
70
65
60
60
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
TEMPERATURE (°C)
TEMPERATURE (°C)
AVDD AND DVDD SUPPLY CURRENT
vs. TEMPERATURE
AVDD AND DVDD SUPPLY CURRENT
vs. TEMPERATURE
(BIOZ ENABLED, LN_BIOZ = 0)
(ECG, PACE, BIOZ ENABLED, LN_BIOZ = 0)
260
250
240
230
220
210
200
190
180
170
160
200
190
180
170
160
150
140
130
120
110
100
2.0V
1.8V
2.0V
1.8V
1.1V
1.1V
IDRV = 32 µA
IDRV = 32 µA
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
TEMPERATURE (°C)
TEMPERATURE (°C)
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, V
= 2.5V, T = +25°C, unless otherwise noted.)
DVDD
AVDD
OVDD A
AVDD AND DVDD ULP CURRENT
vs. TEMPERATURE
ECG PACEMAKER PULSE TOLERANCE
2mV, 2.0ms PULSE
ECG PACEMAKER PULSE TOLERANCE
200mV, 2.0ms PULSE
1.2
1
2.5
2
2.5
2
200mV 2.0ms
PULSE
2mv, 2.0ms
PULSE
ECG SIGNAL
ECG SIGNAL
1.5
1
1.5
1
2.0V
0.8
0.6
0.4
0.2
0
1.8V
0.5
0
0.5
0
1.5V
1.1V
-0.5
-1
-0.5
-1
-1.5
-1.5
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
0
10
20
30
40
50
60
70
TIME (s)
TIME (s)
TEMPERATURE (°C)
ECG PACEMAKER PULSE TOLERANCE
20mV, 0.1ms PULSE
ECG PACEMAKER PULSE TOLERANCE
2mV, 0.1ms PULSE
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
2mV, 0.1ms
20mV, 0.1ms
ECG SIGNAL
PULSE
ECG SIGNAL
Pulse
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
TIME (s)
TIME (s)
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Pin Configuration
TOP VIEW
MAX30001
(BUMP SIDE DOWN)
1
2
3
4
5
6
+
DRVP
DRVN
BIN
BIP
ECGP
ECGN
A
B
C
D
E
AGND
AGND
OVDD
SDO
AGND
AGND
AGND
SDI
CAPN
DGND
FCLK
SCLK
CAPP
CPLL
DVDD
CSB
V
R
BIAS
BG
AOUT
INTB
V
CM
V
REF
AVDD
INT2B
WLP
(2.7mm x 2.9mm)
Pin Description
BUMP
NAME
WLP
FUNCTION
Positive Output Current Source for Bio-Impedance Excitation. Requires a series capacitor between
pin and electrode.
A1
A2
DRVP
DRVN
Negative Output Current Source for Bio-Impedance Excitation. Requires a series capacitor
between pin and electrode.
A3
A4
A5
A6
B1
BIN
BIP
Bioimpedance Negative Input.
Bioimpedance Positive Input.
ECG Positive Input.
ECGP
ECGN
ECG Negative Input.
V
Bandgap Noise Filter Output. Connect a 1.0μF X7R ceramic capacitor between V
and AGND.
BG
BG
External Resistor Bias. Connect a low tempco resistor between R
and AGND. If external bias
BIAS
B2
R
BIAS
generator is not used then R
can be left floating.
BIAS
B3, B4, C3,
C4, D4
AGND
CAPN
Analog Power and Reference Ground. Connect into the printed circuit board ground plane.
Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (C ) between CAPP and CAPN to
HPF
B5
form a 0.5Hz high-pass response in the ECG channel. Select a capacitor with a high voltage rating
(25V) to improve linearity of the ECG signal path.
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Pin Description (continued)
BUMP
NAME
WLP
FUNCTION
Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (C
) between CAPP and CAPN to
HPF
B6
CAPP
form a 0.5Hz high-pass response in the ECG channel. Select a capacitor with a high voltage rating
(25V) to improve linearity of the ECG signal path.
C1
C2
V
Common Mode Buffer Output. Connect a 10μF X5R ceramic capacitor between V
and AGND.
CM
CM
Analog Output Voltage of the Pace Channel. Programmable to select where in the signal path to
output to AOUT.
AOUT
Digital Ground for Both Digital Core and I/O Pad Drivers. Recommended to connect toAGND
plane.
C5
DGND
CPLL
C6
D1
D2
D3
PLL Loop Filter Input. Connect 1nF C0G ceramic capacitor between CPLL and AGND.
V
ADC Reference Buffer Output. Connect a 10μF X7R ceramic capacitor between V
and AGND.
REF
REF
INTB
Interrupt Output. INTB is an active low status output. It can be used to interrupt an external device.
Logic Interface Supply Voltage.
OVDD
External 32.768kHz Clock that Controls the Sampling of the Internal Sigma-Delta Converters and
Decimator.
D5
FCLK
D6
E1
DVDD
AVDD
Digital Core Supply voltage. Connect to AVDD.
Analog Core Supply Voltage. Connect to DVDD.
Interrupt 2 Output. INT2B is an active-low status output. It can be used to interrupt an external
device.
E2
E3
INT2B
SDO
Serial Data Output. SDO will change state on the falling edge of SCLK when CSB is low. SDO is
three-stated when CSB is high.
E4
E5
E6
SDI
SCLK
CSB
Serial Data Input. SDI is sampled into the device on the rising edge of SCLK when CSB is low.
Serial Clock Input. Clocks data in and out of the serial interface when CSB is low.
Active-Low Chip-Select Input. Enables the serial interface.
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
EMI Filtering and ESD Protection
Detailed Description
EMI filtering of the ECGP and ECGN inputs consists of a
single pole, low pass, differential, and common mode filter
with the pole located at approximately 26MHz. The ECGP
and ECGN inputs also have input clamps that protect the
inputs from ESD events.
ECG Channel
Figure 2 illustrates the ECG channel block diagram,
excluding the ADC. The channel comprises an input
MUX, a fast-recovering instrumentation amplifier, an anti-
alias filter, and a programmable gain amplifier. The input
MUX includes several features such as ESD protection,
EMI filtering, lead biasing, leads off checking, and ultra-
low power leads-on checking. The output of this analog
channel drives an 18-bit Sigma-Delta ADC.
● ±8kV using the Contact Discharge method specified
in IEC61000-4-2 ESD
● ±15kV using the Air Gap Discharge method specified
in IEC61000-4-2 ESD
● For IEC61000-4-2 ESD protection, use 1kΩ series
resistors on ECGP and ECGN that are rated to with-
stand ±8kV surge voltages.
Input MUX
The ECG input MUX shown in Figure 3 contains integrated
ESD and EMI protection, DC leads off detect current
sources, lead-on detect, series isolation switches, lead
biasing, and a programmable calibration voltage source
to enable channel built in self-test.
PCB
AAF
ECGP
ESD, EMI, INPUT
MUX, DC LEAD
INPUT
AMP
PGA
ECGN
CHECK
f
= 600Hz
-3dB
-40dB/dec
FAST
SETTLING
CAPP
CHPF
MAX30001
CAPN
Figure 2. ECG Channel Input Amplifier and PGA Excluding the ADC
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
MAX30001
DC LEAD-OFF CHECK
ULP LEAD-ON
CHECK
LEAD
BIAS
CALIBRATION
VOLTAGE
ESD PROTECTION
AND
EMI FILTER
INPUT AND
POLARITY
SWITCHES
V
THH
AVDD
AVDD
AVDD
V
MID
50,
100,
15MΩ
200MΩ
5-100nA
0.25, 0.5mV,
UNI/BIPOLAR,
1/64 – 256Hz,
TIME HIGH
V
THL
TO ECG
INA IN+
ECGP
AVDD
AGND
AVDD
5-100nA
R
AGND
AGND
AGND
5-100nA
3R
AGND
TO ECG
INA IN-
ECGN
0.25, 0.5mV,
UNI/BIPOLAR,
1/64 – 256Hz,
TIME HIGH
V
THH
5-100nA
50,
100,
5MΩ
AGND
AGND
AGND
200MΩ
V
THL
AGND
AGND
AGND
V
MID
Figure 3. ECG Input MUX
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
DC Leads-Off Detection and
ULP Leads-On Detection
The input MUX leads-off detect circuitry consists of
programmable sink/source DC current sources that allow
for DC leads-off detection while the channel is powered
up in normal operation and an ultra-low-power (ULP)
leads-on detect while the channel is powered down.
VDD
VTH_H
VMID
VSS
ECGP,N
VTH_L
The MAX30001 accomplishes DC leads-off detection by
applying a DC current to pull the ECG input voltage up
ABOVE
THRESHOLD
BELOW
THRESHOLD
to above V
+ V
or down to below V - V . The
MID TH
MID
TH
>115ms
current sources have user selectable values of 0nA, 5nA,
10nA, 20nA, 50nA, and 100nA that allow coverage of dry
and wet electrode impedance ranges. Supported thresh-
<115ms
INTB
LDOFF_*H
BITS
olds are V
± 300mV (recommended), V
±400mV,
ASSERTED
MID
MID
V
MID
± 450mV, and V
± 500mV. A threshold of 400mV,
MID
450mV, and 500mV must only be used when V
≥
AVDD
Figure 4. Lead Off Detect Behavior
1.45V, 1.55V, and 1.65V, respectively. A dynamic com-
parator protects against false flags generated by the input
amplifier and input chopping. The comparator checks for a
minimum continuous violation (or threshold exceeded) of
115ms to 140ms depending on the setting of FMSTR[1:0]
before asserting any one of the LDOFF_xx interrupt flags
(Figure 4). See registers CNFG_GEN (0x10) and CNFG_
EMUX (0x14) for configuration settings and see Table 1
for recommended values given electrode type and supply
The common-mode voltage, V , can optionally be used
CM
as a body bias to drive the body to the common-mode
voltage by connecting V
to a separate electrode on the
CM
body through a 200kΩ or higher resistor to limit current
into the body according to IEC 60601-1:2005, 8.7.3. If
this is utilized then the internal lead bias resistors to V
can be disabled.
MID
voltage. The 0nA setting can also be used with the V
± 300mV threshold to monitor the input compliance of the
INA when DC lead off detection is not needed.
MID
Isolation and Polarity Switches
The series switches in the MAX30001 isolate the ECGP
and ECGN pins from the internal signal path, isolating it
from the subject being monitored. The series switches are
disabled by default. They must be enabled to record ECG.
There are also polarity switches that will swap the inputs
so that ECGP goes to the minus INA input and ECGN
goes to the plus INA input.
The ULP lead on detect operates by pulling ECGN low
with a pulldown resistance larger than 5MΩ and pulling
ECGP high with a pullup resistance larger than 15MΩ.
A low-power comparator determines if ECGP is pulled
below a predefined threshold that occurs when both
electrodes make contact with the body. When the
impedance between ECGP and ECGN is less than 20MΩ,
an interrupt LONINT is asserted, alerting the µC to a
leads-on condition.
Calibration Voltage Sources
Calibration voltage sources are available to provide
±0.25mV (0.5mV ) or ±0.5mV (1.0mV ) inputs to
P-P
P-P
the ECG channel with programmable frequency and duty
Lead Bias
cycle. The sources can be unipolar/bipolar relative to V
.
MID
The MAX30001 limits the ECGP and ECGN DC input
Figure 5 illustrates the possible calibration waveforms.
Frequency selections are available in 4X increments from
15.625mHz to 256Hz with selected pulse widths varying
from 30.5µs to 31.723ms and 50% duty cycle. Signals
can be single-ended, differential, or common mode. This
flexibility allows end-to-end channel-testing of the ECG
signal path.
common mode range to V
±150mV at V
= 1.1V
MID
AVDD
or V
± 550mV (typ) at V
= 1.8V. This range can
MID
AVDD
be maintained either through external or internal lead-
biasing.
Internal DC lead-biasing consists of 50MΩ, 100MΩ,
or 200MΩ selectable resistors to V
electrodes within the input common mode requirements
of the ECG channel and can drive the connected body
to the proper common mode voltage level. See register
CNFG_GEN (0x10) to select a configuration.
that drive the
MID
When applying calibration voltage sources with the device
connected to a subject, the series input switches must be
disconnected so as not to drive signals into the subject.
See registers CNFG_CAL (0x12) and CNFG_EMUX
(0x14) to select configuration.
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Table 1. Recommended Lead Bias, Current Source Values, and Thresholds for
Electrode Impedance
ELECTRODE IMPEDANCE
I
V
DC
TH
100kΩ –
200kΩ
200kΩ –
400kΩ
400kΩ –
1MΩ
1MΩ –
2MΩ
2MΩ –
4MΩ
4MΩ –
10MΩ
10MΩ –
20MΩ
<100kΩ
All settings of R
b
I
I
= 10nA
= 20nA
DC
DC
V
= V
± 300mV, ± 400mV
TH
MID
All settings
of R
b
All settings of R
V
=V
b
TH MID
All settings of V
± 400mV,
±450mV,
±500mV
TH
All settings
of R
b
All settings of R
b
I
= 50nA
V
=V
DC
TH MID
All settings of V
TH
±450mV,
±500mV
All settings
of R
b
All settings of R
V
=V
b
TH MID
I
= 100nA
DC
All settings of V
± 400mV,
±450mV,
±500mV
TH
CALIBRATION VOLTAGE SOURCE OPTIONS
VMID + 0.25mV
CAL_VMODE = 1
VMID
V
+ 0.25mV
- 0.25mV
+ 0.50mV
MID
CAL_VMODE = 0
CAL_VMAG= 0
V
MID
CAL_VMAG= 0
VMID - 0.25mV
V
MID
VMID + 0.50mV
V
MID
VCALP
VCALN
CAL_VMODE = 0
CAL_VMAG= 1
CAL_VMODE = 1
CAL_VMAG= 1
VMID
V
MID
V
MID
- 0.50mV
V
MID
- 0.50mV
T
HIGH
T
CAL
Figure 5. Calibration Voltage Source Options
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Gain Settings, Input Range, and Filtering
Converting ECG Samples to Voltage
The device’s ECG channel contains an input instru-
mentation amplifier that provides low-noise, fixed-gain
amplification (gain of 20) of the differential signal, rejects
differential DC voltage due to electrode polarization,
rejects common-mode interference primarily due to AC
mains interference, and provides high input impedance
to guarantee high CMRR even in the presence of severe
electrode impedance mismatch (see Figure 2). The differ-
ential DC rejection corner frequency is set by an external
ECG samples are recorded in 18-bit, left justified two’s
compliment format. After converting to signed magnitude
format, the ECG input voltage is calculated by the follow-
ing equation:
17
V
(mV) = ADC x V
/ (2 x ECG_GAIN)
ECG
REF
ADC is the ADC counts in signed magnitude format, V
REF
is 1000mV (typ) (refer to the Electrical Characteristics
section), and ECG_GAIN is 20V/V, 40V/V, 80V/V, or
160V/V, set in CNFG_ECG (0x15).
capacitor (C
) placed between pins CAPP and CAPN,
HPF
refer to Table 2 for appropriate value selection. There are
three recommended options for the cutoff frequency: 5Hz,
0.5Hz, and 0.05Hz. Setting the cutoff frequency to 5Hz
provides the most motion artifact rejection at the expense
of ECG waveform quality, making it best suited for heart
rate monitoring. For ambulatory applications requiring
more robust ECG waveforms with moderate motion
artifact rejection, 0.5Hz is recommended. Select 0.05Hz
for patient monitoring applications in which ECG wave-
form quality is the primary concern and poor rejection of
motion artifacts can be tolerated. The high-pass corner
frequency is calculated by the following equation:
Fast Recovery Mode
The input instrumentation amplifier has the ability to
rapidly recover from an excessive overdrive event such
as a defibrillation pulse, high-voltage external pacing,
and electro-surgery interference. There are two modes of
recovery that can be used: automatic or manual recovery.
The mode is programmed by the FAST[1:0] bits in the
MNGR_DYN (0x05) register.
Table 2. ECG Analog HPF Corner
Frequency Selection
HPF CORNER
FREQUENCY
1/(2π x R
x C
)
C
HPF
HPF
HPF
R
is specified in the Electrical Characteristics table.
HPF
0.1µF
1.0µF
10µF
≤ 5Hz
≤ 0.5Hz
≤ 0.05Hz
Following the instrumentation amplifier is a 2-pole active
anti-aliasing filter with a 600Hz -3dB frequency that pro-
vides 57dB of attenuation at half the modulator sampling
rate (approximately 16kHz) and a PGA with program-
mable gains of 1, 2, 4, and 8V/V for an overall gain of 20,
40, 80, and 160V/V. The instrumentation amplifier and
PGA are chopped to minimize offset and 1/f noise. Gain
settings are configured via the CNFG_ECG (0x15) regis-
Table 3. Fast Recovery Mode Recovery
Time vs. Number of Samples
SAMPLE
RATE (sps)
NUMBER OF
SAMPLES
RECOVERY TIME
(APPROXIMATE) (ms)
ter. The usable common-mode range is V
±150mV at
MID
512
256
128
500
250
125
200
199.8
255
127
63
498
496
492
498
496
512
495
495.5
V
AVDD
= 1.1V or V
±550mV (typ) at V
= 1.8V.
MID
AVDD
Internal lead biasing can be used to meet this require-
ment. The usable DC differential range is ±300mV at
V
AVDD
= 1.1V or ±650mV (typ) at V
= 1.8V to allow
AVDD
249
124
64
for electrode polarization voltages on each electrode. The
input AC differential range is ±32.5mV or 65mV
.
P-P
99
99
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Automatic mode engages once the saturation counter
exceeds approximately 125ms (t ). The counter is
(Table 3). ECG samples are tagged if they were taken
while fast settling mode was asserted (Figure 6).
SAT
activated the first time the ADC output exceeds the sym-
metrical threshold defined by the FAST_TH[5:0] bits in the
MNGR_DYN (0x05) register and accumulates the time
that the ADC output exceeds either the positive or nega-
tive threshold. If the saturation counter exceeds 125ms,
it triggers the fast settling mode (if enabled) and resets.
The saturation counter can also be reset prior to trigger-
ing the fast settling mode if the ADC output falls below the
In manual mode, a user algorithm running on the host
microcontroller or an external stimulus input will gener-
ate the trigger to enter fast recovery mode. The host
microcontroller then enables the manual fast recovery
mode in the MNGR_DYN (0x05) register. The manual fast
recovery mode can be of a much shorter duration than the
automatic mode and allows for more rapid recovery. One
such example is recovery from external high-voltage pac-
ing signals in a few milliseconds to allow the observation
of a subsequent p-wave.
threshold continuously for 125ms (t ). This feature is
BLW
designed to avoid false triggers due to the QRS complex.
Once triggered, fast settling mode is engaged for 500ms,
tBLW
125ms
tSAT
125ms
VDD
VMID
VSS
VSAT_THH
ECG
VSAT_THL
COUNTER
START STOP
RESET
DISABLED
NORMAL
START
RESET
tFAST
FAST
SETTLING
ENABLED
DISABLED
NORMAL
FAST
ETAG
Figure 6. Automatic Fast Settling Behavior
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
delaya approximately 40Hz, 100Hz, or 150Hz corner
frequencies, depending on the sampling rate. See reg-
ister CNFG_ ECG (0x15) to configure the filters. Table 4
illustrates the ECG latency in samples and time for each
ADC data rate.
Decimation Filter
The decimation filter consists of an FIR decimation filter
to the data rate followed by a programmable IIR and FIR
filter to implement HPF and LPF selections.
The high-pass filter options include a 1st-order IIR
Butterworth filter with a 0.4Hz corner frequency along with
a pass through setting for DC coupling. Low-pass filter
options include a 12-tap linear phase (constant group
Noise Measurements
Table 5 shows the noise performance of the ECG channel
of MAX30001 referred to the ECG inputs.
Table 4. ECG Latency in Samples and Time as a Function of ECG Data Rate and Decimation
ECG CHANNEL SETTINGS
LATENCY
INPUT SAMPLE OUTPUT DATA DECIMATION
WITHOUT LPF WITH LPF
(INPUT SAMPLES) (INPUT SAMPLES)
WITHOUT LPF
(ms)
WITH LPF
(ms)
RATE (Hz)
RATE (sps)
RATIO
32,768
32,000
32,768
32,000
32,000
31,968
32,768
32,000
512
500
256
250
200
199.8
128
125
64
650
1,034
1,034
3,690
3,690
2,202
2,202
4,906
4,906
19.836
20.313
89.172
91.313
38.813
38.851
102.844
105.313
31.555
32.313
112.610
115.313
68.813
68.881
149.719
153.313
64
650
128
128
160
160
256
256
2,922
2,922
1,242
1,242
3,370
3,370
Table 5. ECG Channel Noise Performance
GAIN
BANDWIDTH
NOISE
SNR
dB
ENOB
µV
V/V
Hz
40
RMS
µV
Bits
15.9
15.5
15.2
15.1
14.7
14.4
14.3
13.8
13.5
13.4
12.8
12.5
P-P
0.46
3.04
97.7
94.9
93.2
92.9
90.3
88.6
88.0
84.9
83.1
82.4
79.1
77.2
20
40
100
150
40
0.64
0.77
0.40
0.54
0.66
0.35
0.50
0.62
0.34
0.49
0.61
4.20
4.60
2.64
3.56
4.34
2.31
3.33
4.09
2.22
3.24
4.01
100
150
40
80
100
150
40
160
100
150
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
The detection circuit consists of several digital filters
and signal processing delays. These depend on the
WNDW[3:0] bits in the CNFG_RTOR (0x1D) register. The
R-to-R Detection
The MAX30001 contains built-in hardware to detect R-R
intervals using an adaptation of the Pan-Tompkins QRS
detection algorithm*. The timing resolution of the R-R
interval is approximately 8ms and depends on the set-
ting of FMSTR [1:0] in CNFG_GEN (0x10) register. See
Table 26 for the timing resolution of each setting.
detection delay (t
equation:
) is described by the following
R2R_DET
t
= 5,376 + 256 x WNDW in FMSTR clocks
R2R_DET
where WNDW is an integer from 0 to 15
When an R event is identified, the RRINT status bit is
asserted and the RTOR_REG (0x25) register is updated
with the count seen since the last R event. Figure 7
illustrates the R-R interval on a QRS complex. Refer
to registers CNFG_RTOR1 (0x1D) and CNFG_RTOR2
(0x1E) for selection details.
and the total latency (t ) is the sum of the two
delays and summarized in the equation below:
R2R_DEL
t
= t + t = 3,370 + 5,376 +
R2R_DEL
R2R_DEC
R2R_DET
256 x WNDW in FMSTR clocks where WNDW is an inte-
ger from 0 to 15.
The total R-to-R latency minus the ECG latency is the
delay of the R-to-R value relative to the ECG data and
can be used to place the first R-to-R value on the ECG
data plot. The succeeding values in the R-to-R Interval
Memory Register can be used as is to locate subsequent
R-to-R values on the ECG data plot relative to the initial
placement.
The latency of the R-to-R value written to the RTOR
Interval Memory Register is the sum of the R-to-R deci-
mation delay and the R-to-R detection delay blocks. The
R-to-R decimation factor is fixed at 256 and the decima-
tion delay (t
) is always 3,370 FMSTR clocks, as
R2R_DEC
shown in Table 6.
R-R INTERVAL
Figure 7. R-to-R Interval Illustration
Table 6. R-to-R Decimation Delay vs. Register Settings
RTOR TIME
RESOLUTION
(ms)
DELAY IN R-TO-R DECIMATION
FMSTR FREQ
(Hz)
FMSTR [1:0]
FMSTR FREQ
DECIMATION
FMSTR CLKs
(ms)
00
01
10
11
FCLK
32,768
32,000
256
256
256
256
7.8125
8.0
3370
3370
3370
3370
102.844
105.313
105.313
105.415
FCLK x 625/640
FCLK x 625/640
FCLK x 640/656
32,000
8.0
31,968.78
8.0078
*J. Pan and W.J. Tompkins, “A Real-Time QRS Detection Algorithm,” IEEE Trans. Biomed. Eng., vol. 32, pp. 230-236
Maxim Integrated
│ 27
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
being interpreted as a pace event. A single-ended analog
signal is provided at pin AOUT to allow digitization of the
PACE pulses with an external analog to digital converter.
See register CNFG_PACE (0x1A) for gain, low pass and
high pass filter options and AOUT signal selection.
Pace Channel
MAX30001 provides an analog based pace detection for
up to three chamber pacing with data logging and ECG
tagging for up to three rising and falling edges per ECG
sample. See register CNFG_PACE (0x1A) to select con-
figuration and ECG FIFO and PACE memory for detailed
descriptions of the ECG and PACE FIFOs.
BioZ Channel
Figure 8 illustrates the BioZ channel block diagram,
excluding the ADC. The channel comprises an input
MUX, an instrumentation amplifier, a mixer, an anti-alias
filter, and a programmable gain amplifier. The MUX
includes several features such as ESD protection, EMI
filtering, lead biasing, leads off checking, and ultra-low
power leads-on checking. The output of this analog chan-
nel drives a 20-bit Sigma-Delta ADC.
Real time monitoring of pace edge events can be accom-
plished by unmasking PEDGE via EN_INT (0x02) and
EN_INT2 (0x03) and using the self-clear behavior; see
CLR_PEDGE=1 in register MNGR_INT (0x04).
Current injection rates for Bio-Impedance measurements
are limited to 40kHz and 80kHz when pace detection
is enabled to avoid glitches caused by current injection
PCB
To PACE CHANNEL
HPF
AAF
BIP
BIN
ESD, EMI,
INPUT MUX,
DC LEAD
CHECK
INPUT
AMP
f
-3dB
PGA
=600Hz
-20dB/dec
-40dB/dec
SELECTABLE PHASE
DRVP
DRVN
PUSH/PULL
CURRENT
SOURCE
MAX30001
Figure 8. BioZ Channel Input Amplifier, Mixer, and PGA Excluding the ADC and Current Drive Output
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
the pole located at approximately 26MHz. The BIP and
BIN inputs also have input clamps that protect the inputs
from ESD events.
Input MUX
The BioZ input MUX shown in Figure 9 contains integrated
ESD and EMI protection, DC leads off detect current
sources and comparators, lead-on detect, series isolation
switches, lead biasing, a programmable calibration voltage
source to enable channel built in self-test for the pace
channel, and a built in programmable resistor load.
● ±8kV using the Contact Discharge method specified
in IEC61000-4-2 ESD
● ±15kV using the Air Gap Discharge method specified
in IEC61000-4-2 ESD
EMI Filtering and ESD Protection
EMI filtering of the BIP and BIN inputs consists of a single
pole, low pass, differential, and common mode filter with
● For IEC61000-4-2 ESD protection, use 1kΩ series
resistors on BIP and BIN that is rated to withstand
±8kV surge voltages
MAX30001
DC LEAD-OFF CHECK
ESD PROTECTION
ULP LEAD-ON
CHECK
LEAD
BIAS
CALIBRATION
VOLTAGE
INPUT AND R
LOAD
AND
EMI FILTER
SWITCHES
V
THH
AVDD
AVDD
AVDD
V
MID
50,
100,
15MΩ
200MΩ
5-100nA
0.25, 0.5mV,
UNI/BIPOLAR,
1/64 – 256Hz,
TIME HIGH
V
THL
TO BIOZ
INA IN+
BIP
AVDD
AGND
AVDD
5-100nA
R
AGND
AGND
AGND
5-100nA
3R
AGND
TO BIOZ
INA IN-
BIN
0.25, 0.5mV,
UNI/BIPOLAR,
1/64 – 256Hz,
TIME HIGH
V
THH
5-100nA
50,
100,
5MΩ
AGND
AGND
AGND
200MΩ
V
THL
AGND
AGND
AGND
V
MID
ESD PROTECTION
FROM DRVP CURRENT
GENERATOR
DRVP
PROGRAMMABLE
RESISTOR LOAD
AGND
AGND
FROM DRVN CURRENT
GENERATOR
DRVN
AGND
AGND
Figure 9. BioZ Input MUX
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
The 0nA setting can also be used with the V
threshold to monitor the input compliance of the INA when
DC lead off detection is not needed.
± 300mV
Leads-Off Detection and ULP Leads-On Detection
MID
MAX30001 provides the capability of detecting lead off
scenarios that involve two electrode and four electrode
configurations through the use of digital threshold and
analog threshold comparisons. There are three methods
to detect lead-off for the BioZ channel. There is a com-
pliance monitor for the current generator on the DRVP
and DRVN pins detecting when the voltage on the pins
is outside its operating range. The BIOZ_CGMON bit in
the CNFG_BIOZ (0x18) register enables this function
and the BCGMON, BCGMP, and BCGMN bits in the
STATUS (0x01) register indicate if the DRVP and DRVN
pins are out of compliance. There is a DC lead-off circuit
on the BIP and BIN pins (same as on the ECGP and
ECGN pins, see ECG description) that sinks or sources a
programmable DC current and window comparators with
a programmable threshold to detect the condition. There
is a digital AC lead off detection monitoring the output of
the BioZ ADC with programmable under and overvoltage
levels performing a digital comparison. The EN_BLOFF
bit in the CNFG_GEN (0x10) register enables this
function and the BLOFF_HI_IT[7:0] and BLOFF_LO_
IT[7:0] bits in the MNGR_DYN (0x05) register sets the
digital threshold for detection. Refer to Table 7 for lead
off conditions and register settings to allow detection.
The ULP lead-on detect operates by pulling BIN low with a
pulldown resistance larger than 5MΩ and pulling BIP high
with a pullup resistance larger than 15MΩ. A low-power
comparator determines if BIP is pulled below a predefined
threshold that occurs when both electrodes make contact
with the body. When the impedance between BIP and BIN
is less than 20MΩ, an interrupt LONINT is asserted, alert-
ing the µC to a leads-on condition.
Lead Bias
The MAX30001 limits the BIP and BIN DC input common
mode range to V
±150mV at V = 1.1V or V
AVDD MID
MID
±550mV (typ) at V
= 1.8V. This range can be main-
AVDD
tained either through external/internal lead-biasing.
Internal DC lead-biasing consists of 50MΩ, 100MΩ,
or 200MΩ selectable resistors to V
that drive the
MID
electrodes within the input common mode requirements
of the ECG channel and can drive the connected body
to the proper common mode voltage level. See the EN_
RBIAS[1:0], RBIASV[1:0], RBIASP, and RBIASN bits in the
CNFG_GEN (0x10) register to select a configuration.
Table 7. BioZ Lead Off Detection Configurations
MEASURED
SIGNAL
CONFIGURATION CONDITION DRVP/N
BIP/N
REGISTER SETTING TO DETECT
Two-Electrode
(Shared DRV/BI)
1 Electrode
Rail to
Rail
Rail to Rail
CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11
Rail to Rail
Off
(Saturated Inputs) MNGR_DYN (0x05), BLOFF_HI_IT[7:0]
1 DRV
Electrode Off,
Large Body
Coupling
Rail to
Rail
Normal
½ Signal
CNFG_BIOZ (0x18), BIOZ_CGMON=1
1 DRV
Electrode Off,
Small Body
Coupling
Rail to Rail
(Saturated
Inputs)
Rail to
Rail
CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11
MNGR_DYN (0x05), BLOFF_HI_IT[7:0]
Rail to Rail
Four-Electrode
(Force/Sense)
1 BI (sense)
Electrode Off
Normal
Normal
Floating
Floating
½ Signal
CNFG_GEN (0x10), EN_DCLOFF=10
Both BIP/N
(sense)
Electrodes Off
CNFG_GEN (0x10), EN_BLOFF[1:0] = 01 or 11
MNGR_DYN (0x05), BLOFF_LO_IT[7:0]
No Signal
Wide Swing,
Dependent on
Body Coupling
1 DRV and 1 BI Rail to
Electrode Off Rail
CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11
MNGR_DYN (0x05), BLOFF_HI_IT[7:0]
Rail to Rail
Maxim Integrated
│ 30
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
The common-mode voltage, V , can optionally be used
CM
as a body bias to drive the body to the common-mode
Figure 10 illustrates the possible calibration waveforms.
Frequency selections are available in 4X increments from
15.625mHz to 256Hz with selected pulse widths varying
from 30.5µs to 31.723ms and 50% duty cycle. Signals
can be single-ended, differential, or common mode. This
flexibility allows end-to-end channel-testing of the Pace
signal path and is primarily used for pacemaker pulse
detection validation.
voltage by connecting V
to a separate electrode on the
CM
body through a 200kΩ or higher resistor to limit current
into the body according to IEC 60601-1:2005, 8.7.3. If
this is utilized then the internal lead bias resistors to V
MID
can be disabled. If ECGP/ECGN pins are shared with the
BIP/BIN pins then it is only necessary to enable lead bias
on ECG or BioZ.
When applying calibration voltage sources with the device
connected to a subject, the series input switches must be
disconnected so as not to drive signals into the subject.
See registers CNFG_CAL (0x12) and CNFG_BMUX
(0x14) to select configuration.
Calibration Voltage Sources
Calibration voltage sources are available to provide
±0.25mV (0.5mV ) or ±0.5mV (1.0mV ) inputs to the
P-P
P-P
BioZ/Pace channel with programmable frequency and duty
cycle. The sources can be unipolar/bipolar relative to V
.
MID
CALIBRATION VOLTAGE SOURCE OPTIONS
VMID + 0.25mV
CAL_VMODE = 1
VMID
V
V
V
+ 0.25mV
- 0.25mV
+ 0.50mV
MID
MID
MID
CAL_VMODE = 0
CAL_VMAG = 0
CAL_VMAG = 0
VMID - 0.25mV
VMID + 0.50mV
V
V
V
MID
MID
MID
VCALP
VCALN
CAL_VMODE = 0
CAL_VMAG = 1
CAL_VMODE = 1
CAL_VMAG = 1
VMID
V
- 0.50mV
- 0.50mV
MID
T
HIGH
T
CAL
Figure 10. Calibration Voltage Source Options
9.65kΩ
150Ω
100Ω
55Ω
DRVP_INT
10kΩ
5kΩ
2.5kΩ
1.25kΩ
10kΩ
10kΩ
10kΩ
10kΩ
45Ω
R
<0>
VAL
R
<1>
VAL
R
<2>
VAL
R
<0>
R
<1>
R
<2>
R
<3>
MOD
MOD
MOD
MOD
DRVN_INT
Figure 11. Programmable Resistive Load Topology
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
of nominal and modulated resistor values. Modulation rate
can be programmed between 625mHz to 4Hz.
Programmable Resistive Load
The programmable resistive load on the DRVP/DRVN
pins allows a built in self-test of the current generator
(CG) and the entire BioZ channel. Refer to Figure 11 for
implementation details.
See registers CNFG_CAL (0x12) and CNFG_BMUX
(0x17) to select configuration for modulation rate and
resistor value.
Nominal resistance can be varied between 5kΩ and
625Ω. The modulation resistance is used to switch the
Current Generator
The current generator provides square-wave modulating
differential current that is AC injected into the body via
pins DRVP and DRVN with the bio-impedance sensed
differentially through pins BIP and BIN. Two and four
electrode configurations are supported for typical wet and
dry electrode impedances.
load resistance between R
and (R
- R ) at
MOD
NOM
NOM
the selected modulation rate. The modulation resistance
is dependent on the nominal resistance value with resolu-
tion of 50.4mΩ to 2.96Ω at the largest nominal resistance
(5kΩ) and 15.3mΩ to 46.3mΩ with the smallest nominal
resistance (625Ω). Refer to Table 8 for a complete listing
Table 8. Programmable Resistive Load Values
R
R
MOD
R
(mΩ)
VAL
MOD
R
(Ω)
NOM
<2>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
<1>
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
<0>
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
<3>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<2>
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<1>
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
<0>
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
-
2960.7
980.6
247.5
-
5000.000
2500.000
1666.667
740.4
245.2
61.9
-
329.1
109.0
27.5
-
1250.000
1000.000
833.333
714.286
625.000
185.1
61.3
-
118.5
39.2
-
82.3
27.2
-
60.5
20.0
-
46.3
15.3
Maxim Integrated
│ 32
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Current amplitudes between 8µA to 96µA are select-
Current Selection and Resolution Calculation
Example 1 (Two Terminal with Common
Protection)
Selection of the appropriate current is accomplished by
first calculating the resistive component of the network
impedance at the injection frequency. Worst case elec-
trode impedances should be used.
PK
PK
able with current injection frequencies between 125Hz
and 131.072kHz in power of two increments. See register
CNFG_BIOZ (0x18) for configuration selections.
Current amplitude should be chosen so as not exceed
90mV
at the BIP and BIN pins based on the network
P-P
impedance at the current injection frequency. A 47nF DC
blocking capacitor is required between both DRVP and
DRVN and their respective electrodes.
Given Figure 12 and a current injection frequency of
80kHz, the resistive component of the network imped-
ance is:
The current generator also includes a phase offset adjust-
ment, which delays the drive current modulator with
respect to the input mixer. The phase can be adjusted in
11.25° increments from 0° to 168.75° for injection frequen-
2R
E
R
+ 2R + 2R + 2R + Re{
} = 2.7kΩ
BODY
P1
P2
S
1+ jωR C
E
E
cies up to f
. For injection frequencies of 2 x f
, the phase resolution is reduced to 22.5°
MSTR
MSTR
where R
= 100Ω, R
= 1kΩ, R = 200Ω,
P2
BODY
P1
and 4 x f
MSTR
R
S
= 100Ω, R = 1MΩ, C = 5nF. The maximum cur-
E E
and 45° respectively. See CNFG_BIOZ (0x18) for details.
rent injection is the maximum AC input differential range
(90mV ) divided by the network impedance (2.7kΩ) or
Converting BioZ Samples to Ωs
PK
33.3µA . The closest selectable lower value is 32µA
.
PK
PK
BioZ samples are recorded in 20-bit, left justified two’s
compliment format. After converting to signed magnitude
format, BioZ is calculated by the following equation:
Given the current injection value and the channel band-
width (refer to register CNFG_BIOZ (0x18) for digital LPF
selection) the resolvable impedance can be calculated by
dividing the appropriate input referred noise by the current
injection value. For example, with a bandwidth of 4Hz, the
19
BioZ (Ω) = ADC x V
/ (2 x BIOZ_CGMAG
REF
x BIOZ_GAIN)
ADC is the ADC counts in signed magnitude format, V
REF
input referred noise with a gain of 20V/V is 0.16µV
or
RMS
is 1V (typ) (refer to the Electrical Characteristics sec-
1.1µV . The resolvable impedance is therefore 1.1µV
P-P
P-P
-6
tion), BIOZ_CGMAG is 8 to 96 x 10 A, and BIOZ_GAIN
/ 32µA = 69mΩ
or 5mΩ
.
PK
P-P
RMS
is 10V/V, 20V/V, 40V/V, or 80V/V. BIOZ_CGMAG and
BIOZ_GAIN are set in CNFG_BIOZ (0x18).
PCB
DRVP
47nF
C
= 5nF
E
R
= 100Ω
R
R
P2
S
P1
BIP
1kΩ
200Ω
10pF
R
E
= 1MΩ
PHYSICAL
ELECTRODES
DEFIB
PROTECTION
R
100Ω
BODY
ELECTRODE MODELS
= 5nF
47pF
MAX30001
C
E
10pF
RS = 100Ω
R
R
P2
P1
BIN
1kΩ
200Ω
R
= 1MΩ
E
47nF
DRVN
Figure 12. Example Configuration – Two Terminal with Common Protection
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
selection) the resolvable impedance can be calculated by
dividing the appropriate input referred noise by the current
injection value. For example, with a bandwidth of 4Hz, the
Current Selection and Resolution Calculation
Example 2 (Four Terminal)
Selection of the appropriate current is accomplished by
first calculating the resistive component of the network
impedance at the injection frequency. Worst case elec-
trode impedances should be used.
input referred noise with a gain of 40V/V is 0.12µV
RMS
or 0.78µV . The resolvable impedance is therefore
P-P
0.78µV /96µA = 8mΩ
or 1.2mΩ
.
P-P
PK
P-P
RMS
Given Figure 13 and a current injection frequency of
80kHz, the resistive component of the network imped-
ance is:
Decimation Filter
The decimation filter consists of an FIR decimation filter
to the data rate followed by a programmable IIR and FIR
filter to implement HPF and LPF selections.
2R
E
R
+ 2R
+ 2R
+ 2R + Re {
} = 2.7kΩ
BODY
DP1
DP2
S
The high-pass filter options include a fourth-order IIR
Butterworth filter with a 0.05Hz or 0.5Hz corner frequency
along with a pass through setting for DC coupling.
Lowpass filter options include a 12-tap linear phase
(constant group delay) FIR filter with 4Hz, 8Hz, or 16Hz
corner frequencies. See register CNFG_BIOZ (0x18) to
configure the filters. Table 9 illustrates the BioZ latency in
samples and time for each ADC data rate.
1+ jωR C
E
E
where R
= 100Ω, R
= 1kΩ, R = 200Ω,
DP2
BODY
DP1
R = 100Ω, R = 1MΩ, C = 5nF. The maximum current
S
E
E
injection is the maximum DRVP/N Compliance Voltage
(V -0.5V = 0.6V for V = 1.1V) divided by the network
DD
DD
impedance (2.7kΩ) or 222.2µA . The closest selectable
PK
lower value is 96µA
.
PK
Given the current injection value and the channel band-
width (refer to register CNFG_BIOZ (0x18) for digital LPF
PCB
C
= 5nF
E
R
= 100Ω
R
R
DP2
S
DP1
DRVP
1kΩ
200Ω
47nF
R
E
= 1MΩ
C
= 5nF
E
R
= 100Ω
R
R
BP2
S
BP1
BIP
1kΩ
200Ω
10pF
10pF
R
= 1MΩ
E
PHYSICAL
ELECTRODES
DEFIB
PROTECTION
R
100Ω
BODY
ELECTRODE MODELS
= 5nF
47pF
MAX30001
C
E
RS = 100Ω
R
R
BP2
BP1
BIN
1kΩ
200Ω
R
= 1MΩ
E
C
= 5nF
E
RS = 100Ω
47nF
R
R
DP2
DP1
DRVN
1kΩ
200Ω
R
= 1MΩ
E
Figure 13. Example Configuration—Four Terminal
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
A common-mode buffer is provided to buffer 650mV
which is used to drive common mode voltages for internal
Noise Measurements
Table 10 shows the noise performance of the BioZ channel
of MAX30001 referred to the BioZ inputs.
blocks. Use a 10µF external capacitor between V
to
CM
AGND to provide compensation and noise filtering. The
Reference and Common Mode Buffer
common-mode voltage, V , can optionally be used as a
CM
body bias to drive the body to the common-mode voltage
The MAX30001 features internally generated reference
by connecting V
through a 200kΩ or higher resistor to limit current into the
to a separate electrode on the body
voltages. The bandgap output (V ) pin requires an
external 1.0µF capacitor to AGND and the reference
CM
BG
body according to IEC 60601-1:2005, 8.7.3. If this is uti-
output (V
) pin requires a 10µF external capacitor to
REF
lized then the internal lead bias resistors to V
may be
AGND for compensation and noise filtering.
MID
disabled if the input signals are within the common-mode
input range.
Table 9. BioZ Latency in Samples and Time as a Function of BioZ Data Rate and
Decimation
BioZ CHANNEL SETTINGS
LATENCY
INPUT
SAMPLE RATE
(Hz)
WITHOUT
LPF (INPUT
SAMPLES)
WITH LPF
(INPUT
SAMPLES)
OUTPUT DATA
RATE (sps)
DECIMATION
WITHOUT
LPF(ms)
WITH LPF (ms)
RATIO
32,768
32,000
32,000
31,968
32,768
32,000
32,000
31,968
64
62.5
50
512
512
3,397
3,397
5,189
5,189
7,557
7,557
9,605
9,605
6,469
6,469
103.668
106.156
162.156
162.319
230.621
236.156
300.156
300.457
197.418
202.156
282.156
282.439
418.121
428.156
540.156
540.697
640
9,029
49.95
32
640
9,029
1,024
1,024
1,280
1,280
13,701
13,701
17,285
17,285
31.25
25
24.975
Table 10. BioZ Channel Noise Performance
GAIN
BANDWIDTH
NOISE
SNR
dB
ENOB
Bits
16.6
16.3
16.0
17.1
16.9
16.5
17.6
17.1
16.7
17.7
17.2
16.7
µV
V/V
Hz
4
RMS
µV
P-P
0.23
1.55
101.6
100.0
98.0
10
20
40
80
8
0.28
0.35
0.16
0.19
0.26
0.12
0.16
0.22
0.11
0.15
0.21
1.87
2.34
1.10
1.27
1.68
0.78
1.07
1.48
0.72
1.01
1.42
16
4
104.9
103.4
100.9
107.6
104.9
102.0
108.3
105.3
102.4
8
16
4
8
16
4
8
16
SNR = 20log(V (RMS)/V (RMS)), ENOB = (SNR – 1.76)/6.02
IN
N
V
= 100mV, V
= 35.4mV for a gain of 10V/V. The input amplitude is reduced accordingly for high gain settings.
INRMS
IN(P-P)
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
and the internal FIFO read pointer will be incremented in
response to the 30th SCLK rising edge, allowing for inter-
nal synchronization operations to occur. See the data tag
structures used within each FIFO for means of detecting
end-of-file (EOF) samples, invalid (empty samples) and
other aides for efficiently using and managing normal
mode read back operations.
SPI Interface Description
32 Bit Normal Mode Read/Write Sequences
The MAX30001 interface is SPI/QSPI/Micro-wire/DSP
compatible. The operation of the SPI interface is shown
in Figure 1a. Data is strobed into the MAX30001 on SCLK
rising edges. The device is programmed and accessed by
a 32 cycle SPI instruction framed by a CSB low interval.
The content of the SPI operation consists of a one byte
command word (comprised of a seven bit address and a
Read/Write mode indicator, i.e., A[6:0] + R/W) followed by
a three-byte data word. The MAX30001 is compatible with
CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1 modes of
operation.
Burst Mode Read Sequence
The MAX30001 provides commands to read back the
ECG, BioZ or PACE FIFO memory in a burst mode to
increase data transfer efficiency. Burst mode uses differ-
ent register addresses than the normal read sequence
register addresses. A modified burst mode is supported
for each PACE FIFO word group (see description of
PACE0 to PACE5 register group). The first 32 SCLK
cycles operate exactly as described for the normal mode.
If the µC continues to provide SCLK edges beyond the
32nd rising edge, the MSB of the next available FIFO
word will be presented on the next falling SCLK edge,
allowing the µC to sample the MSB of the next word on
the 33rd SCLK rising edge. Any affected interrupts and/or
FIFO read pointers will be incremented in response to the
(30+nx24)th SCLK rising edge where n is an integer start-
ing at 0. (i.e., on the 30th, 54th, and 78th SCLK rising-
edges for a three-word, burst-mode transfer).
Write mode operations will be executed on the 32nd SCLK
rising edge using the first four bytes of data available. In
write mode, any data supplied after the 32nd SCLK rising
edge will be ignored. Subsequent writes require CSB to
de-assert high and then assert low for the next write com-
mand. In order to abort a command sequence, the rise
of CSB must precede the updating (32nd) rising-edge of
SCLK, meeting the t
requirement.
CSA
Read mode operations will access the requested data
on the 8th SCLK rising edge, and present the MSB of
the requested data on the following SCLK falling edge,
allowing the µC to sample the data MSB on the 9th SCLK
rising edge. Configuration, Status, and FIFO data are all
available via normal mode read back sequences. If more
than 32 SCLK rising edges are provided in a normal read
sequence then the excess edges will be ignored and the
device will read back zeros.
This mode of operation will continue for every 24 cycle
sub frame, as long as there is valid data in the FIFO. See
the data tag structures used within each FIFO for means
of detecting end-of-file (EOF) samples, invalid (empty
samples) and other aides for efficiently using and manag-
ing burst mode read back operations.
If accessing the STATUS register or the ECG, BioZ or
PACE FIFO memories, all interrupt updates will be made
There is no burst mode equivalent in write mode.
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
CSB
SDI
A6 A5 A4 A3 A2 A1 A0
W
D23
9
D16 D15
16 17
D8 D7
D0 DON’T CARE
24
25
32
33
SCLK
1
8
IGNORE
D EDGES
COMMAND
EXECUTED
Z
Z
SDO
SPI NORMAL MODE WRITE TRANSACTION
CSB
SDI
A6 A5 A4 A3 A2 A1 A0
1
R
DON’T CARE
DON’T CARE
16 17
DON’T CARE
DON’T CARE
24
25
30
32
33
SCLK
8 9
IGNORE
D EDGES
INTERRUPT /READ POINTER
UPDATED (IF APPLICABLE
)
Z
DO23
DO16 DO15
DO
8
DO
7
DO
0
SDO
SPI NORMAL MODE READ TRANSACTION
Figure 14. SPI Normal Mode Transaction Diagram
SDI
A6 A5 A4 A3 A2 A1 A0
1
R
DON’T CARE
DON’T CARE
16 17
DON’T CARE
24 25
30
32
SCLK
8 9
READ POINTER
UPDATED (TO B)
DA8 DA7
Z
SDO
DA23
DA16 DA15
DA0 DB23
CONTINUED TRANSACTION (SUB-FRAME 2)
CSB
33
40 41
48 49
56
54
SCLK
READ POINTER
UPDATED (TO C)
DB23
DB16DB15
DB8 DB7
D 0
B
SDO
DC23
CONTINUED TRANSACTION (SUB-FRAME 3)
CSB
57
64 65
72 73
78
80
SCLK
READ POINTER
UPDATED (TO D)
Z
DC16 DC15
SDO
DC23
DC8 DC7
DC0
Figure 15. SPI Burst Mode Read Transactions Diagram
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
User Command and Register Map
DATA INDEX
REG
R/W
NAME
[6:0]
MODE
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
0x00
0x01
NO-OP
R/W
R
x / x / x
x / x / x
x / x / x
x / x / x
x / x / x
x / x / x
x / x / x
x / x / x
DCLO
FFINT
EINT
EOVF
FSTINT
BINT
BOVF
BOVER
BUNDR
STATUS
BCGMON
x
PINT
x
POVF
BCGMP
EN_
PEDGE
BCGMN
EN_
LONINT
RRINT
SAMP
PLLINT
LDOFF_PH
LDOFF_PL
LDOFF_NH
LDOFF_NL
EN_EINT
EN_EOVF
EN_BINT
EN_BOVF
EN_BOVER
EN_SAMP
EN_BUNDR
EN_ PLLINT
FSTINT DCLOFFINT
0x02
0x03
EN_INT
R/W
EN_INT2
EN_BCGMON EN_PINT EN_POVF EN_PEDGE EN_ LONINT EN_ RRINT
x
x
x
x
x
x
INTB_TYPE[1:0]
EFIT[4:0]
x
BFIT[2:0]
x
x
x
x
x
x
x
x
0x04 MNGR_ INT
R/W
R/W
CLR_
FAST
CLR_RRINT[1:0]
CLR_PEDGE CLR_ SAMP
FAST_TH[5:0]
SAMP_IT[1:0]
FAST[1:0]
MNGR_
0x05
DYN
BLOFF_HI_IT[7:0]
BLOFF_LO_IT[7:0]
0x08
0x09
SW_RST
SYNCH
W
W
W
Data Required for Execution = 0x000000
Data Required for Execution = 0x000000
Data Required for Execution = 0x000000
1 REV_ID[3:0]
0x0A FIFO_ RST
0
x
x
1
x
x
0
0
x
0x0F
INFO
R
1
x
x
x
x
x
x
x
x
x
x
EN_ULP_LON[1:0]
EN_BLOFF[1:0]
VTH[1:0]
FMSTR[1:0]
EN_ECG
IPOL
EN_BIOZ
EN_PACE
IMAG[2:0]
RBIASP
x
0x10 CNFG_ GEN R/W
EN_DCLOFF[1:0]
EN_RBIAS[1:0]
VMAG
RBIASV[1:0]
RBIASN
x
x
x
EN_VCAL VMODE
x
FIFTY
x
CNFG_
0x12
0x14
R/W
R/W
FCAL[2:0]
THIGH[10:8]
CAL
THIGH[7:0]
ECG_
ECG_
ECG_POL
x
ECG_CALP_SEL[1:0]
ECG_CALN_SEL[1:0]
OPENP
OPENN
CNFG_
EMUX
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ECG_RATE[1:0]
ECG_GAIN[1:0]
CNFG_
ECG
ECG_
DHPF
0x15
R/W
x
x
ECG_DLPF[1:0]
x
x
x
x
x
x
x
x
x
x
x
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
User Command and Register Map (continued)
DATA INDEX
REG
R/W
NAME
[6:0]
MODE
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
BMUX_
OPENP
BMUX_
OPENN
x
x
BMUX_CALP_SEL[1:0]
BMUX_CALN_SEL[1:0]
CNFG_
BMUX
0x17
0x18
R/W
BMUX_EN_
BIST
x
x
BMUX_CG_MODE[1:0]
BMUX_RNOM[2:0]
x
BMUX_RMOD[2:0]
BIOZ_AHPF[2:0]
BIOZ_DLPF[1:0]
x
x
BMUX_FBIST[1:0]
BIOZ_GAIN[1:0]
BIOZ_RATE
EXT_RBIAS
LN_BIOZ
BIOZ_DHPF[1:0]
BIOZ_FCGEN[3:0]
BIOZ_PHOFF[3:0]
PACE_GAIN[2:0]
CNFG_
BioZ
R/W
R/W
BIOZ_
BIOZ_CGMAG[2:0]
CGMON
PACE_POL
x
x
x
x
DIFF_OFF
x
CNFG_
PACE
AOUT_
LBW
0x1A
0x1D
AOUT[1:0]
x
x
x
PACE_DACP[3:0]
PACE_DACN[3:0]
RGAIN[3:0]
WNDW[3:0]
x
CNFG_
RTOR1
R/W
R/W
EN_RTOR
PAVG[1:0]
RAVG[1:0]
PTSF[3:0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
HOFF[5:0]
CNFG_
RTOR2
0x1E
0x20
x
x
RHSF[2:0]
x
x
x
x
ECG_ FIFO_
BURST
R+
R
ECG FIFO Burst Mode Read Back
ECG FIFO Normal Mode Read Back
See FIFO Description for details
See FIFO Description for details
0x21 ECG_ FIFO
BIOZ_
0x22
FIFO_
R+
BioZ FIFO Burst Mode Read Back
See FIFO Description for details
BURST
0x23 BIOZ_ FIFO
R
R
BioZ FIFO Normal Mode Read Back
R-to-R Interval Register Read Back
See FIFO Description for details
See FIFO Description for details
0x25
0x30
RTOR
PACE0_
BURST
R
PACE0 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x31
0x32
0x33
PACE0_A
PACE0_B
PACE0_C
R
R
R
PACE0 (Data Sets 0 and 1) Normal Mode Read Back
PACE0 (Data Sets 2 and 3) Normal Mode Read Back
PACE0 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
PACE1_
BURST
0x34
R
PACE1 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x35
0x36
0x37
PACE1_A
PACE1_B
PACE1_C
R
R
R
PACE1 (Data Sets 0 and 1) Normal Mode Read Back
PACE1 (Data Sets 2 and 3) Normal Mode Read Back
PACE1 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
User Command and Register Map (continued)
DATA INDEX
REG
R/W
NAME
[6:0]
MODE
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
PACE2_
BURST
0x38
R+
PACE2 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x39
0x3A
0x3B
PACE2_A
PACE2_B
PACE2_C
R
R
R
PACE2 (Data Sets 0 and 1) Normal Mode Read Back
PACE2 (Data Sets 2 and 3) Normal Mode Read Back
PACE2 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
PACE3_
BURST
0x3C
R+
PACE3 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x3D
0x3E
0x3F
PACE3_A
PACE3_B
PACE3_C
R
R
R
PACE3 (Data Sets 0 and 1) Normal Mode Read Back
PACE3 (Data Sets 2 and 3) Normal Mode Read Back
PACE3 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
PACE4_
BURST
0x40
R+
PACE4 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x41
0x42
0x43
PACE4_A
PACE4_B
PACE4_C
R
R
R
PACE4 (Data Sets 0 and 1) Normal Mode Read Back
PACE4 (Data Sets 2 and 3) Normal Mode Read Back
PACE4 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
PACE5_
BURST
0x44
R+
PACE5 (Data Sets 0 to 5) Burst Mode Read Back
See PACE Description for details
0x45
0x46
0x47
0x7F
PACE5_A
PACE5_B
PACE5_C
NO-OP
R
R
PACE5 (Data Sets 0 and 1) Normal Mode Read Back
PACE5 (Data Sets 2 and 3) Normal Mode Read Back
PACE5 (Data Sets 4 and 5) Normal Mode Read Back
See PACE Description for details
See PACE Description for details
See PACE Description for details
R
R/W
x/x/x
x/x/x
x/x/x
x/x/x
x/x/x
x/x/x
x/x/x
x/x/x
Note: R/W Mode R+ denotes burst mode.
x = Don’t Care
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Register Description
NO_OP (0x00 and 0x7F) Registers
No Operation (NO_OP) registers are read-write registers that have no internal effect on the device. If these registers are
read back, DOUT remains zero for the entire SPI transaction. Any attempt to write to these registers is ignored without
impact to internal operation.
STATUS (0x01) Register
STATUS is a read-only register that provides a comprehensive overview of the current status of the device. The first
two bytes indicate the state of all interrupt bits (regardless of whether interrupts are enabled in registers EN_INT (0x02)
or EN_INT2 (0x03)). All interrupt bits are active high. The last byte includes detailed status information for conditions
associated with the other interrupt bits.
Table 11. STATUS (0x01) Register Map
REG
NAME
R/W
23/15/7
EINT
22/14/6 21/13/5
20/12/4
DCLOFFINT
PEDGE
19/11/3
BINT
18/10/2
BOVF
17/9/1
BOVER
SAMP
16/8/0
BUNDR
PLLINT
EOVF
PINT
FSTINT
POVF
BCGMON
LONINT
RRINT
0x01 STATUS
R
LDOFF_
PH
LDOFF_
PL
LDOFF_
NH
LDOFF_
NL
x
x
BCGMP
BCGMN
Table 12. Status (0x01) Register Meaning
INDEX
NAME
MEANING
ECG FIFO Interrupt. Indicates that ECG records meeting/exceeding the ECG FIFO Interrupt
Threshold (EFIT) are available for readback. Remains active until ECG FIFO is read back to the
extent required to clear the EFIT condition.
D[23]
EINT
ECG FIFO Overflow. Indicates that the ECG FIFO has overflown and the data record has been
corrupted. Remains active until a FIFO Reset (recommended) or SYNCH operation is issued.
D[22]
D[21]
EOVF
ECG Fast Recovery Mode. Issued when the ECG Fast Recovery Mode is engaged (either manually
or automatically). Status and Interrupt Clear behavior is defined by CLR_FAST, see MNGR_INT for
details.
FSTINT
DC Lead-Off Detection Interrupt. Indicates that the MAX30001 has determined it is in an ECG leads
off condition (as selected in CNFG_GEN) for more than 90ms. Remains active as long as the leads-
off condition persists, then held until cleared by STATUS read back (32nd SCLK).
D[20]
DCLOFFINT
BioZ FIFO Interrupt. Indicates BioZ records meeting/exceeding the BioZ FIFO Interrupt Threshold
(BFIT) are available for read back. Remains active until BioZ FIFO is read back to the extent
required to clear the BFIT condition.
D[19]
D[18]
BINT
BioZ FIFO Overflow. Indicates the BioZ FIFO has overflowed and the data record has been
corrupted. Remains active until a FIFO Reset (recommended) or SYNCH operation is issued.
BOVF
BioZ Over Range. Indicates the BioZ output magnitude has exceeded the BioZ High Threshold
(BLOFF_HI_IT) for at least 100ms, recommended for use in 2 and 4 electrode BioZ Lead Off
detection. Remains active as long as the condition persists, then held until cleared by STATUS read
back (32nd SCLK).
D[17]
D[16]
BOVER
BUNDR
BioZ Under Range. Indicates the BioZ output magnitude has been bounded by the BioZ Low
Threshold (BLOFF_LO_IT) for at least 1.7 seconds, recommended for use in 4 electrode BioZ Lead
Off detection. Remains active as long as the condition persists, then held until cleared by STATUS
read back (32nd SCLK).
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Table 12. Status (0x01) Register Meaning (continued)
INDEX
NAME
MEANING
BioZ Current Generator Monitor. Indicates the DRVP and/or DRVN current generator has been in a
Lead Off condition for at least 128ms, recommended for use in 4 electrode BioZ Lead Off detection.
Remains active as long as the condition persists, then held until cleared by STATUS read back (32nd
SCLK).
D[15]
BCGMON
PACE FIFO Interrupt. Indicates PACE records are available for read back (should be used in
conjunction with EINT). Remains active until all available PACE FIFO records have been read back.
D[14]
D[13]
PINT
PACE FIFO Overflow. Indicates the PACE FIFO has overflowed and the data record has been
corrupted. Remains active until a FIFO Reset (recommended) or SYNCH operation is issued.
POVF
PACE Edge Detection Interrupt. Real time PACE edge indicator showing when the MAX30001 has
determined a PACE edge occurred (note this is different than the PINT interrupt, which indicates
when the detected edges are logged into the PACE FIFO). Clear behavior is defined by CLR_
PEDGE[1:0], see the MNGR_INT (0x04) register for details.
D[12]
PEDGE
LONINT
Ultra-Low Power (ULP) Leads-On Detection Interrupt. Indicates that the MAX30001 has determined
it is in a leads-on condition (as selected in CNFG_GEN).
LONINT is asserted whenever EN_ULP_LON[1:0] in register CNFG_GEN is set to either 01 or 10
to indicate that the ULP leads on detection mode has been enabled. The STATUS register has to be
read back once after ULP leads on detection mode has been activated to clear LONINT and enable
leads on detection.
D[11]
LONINT remains active while the leads-on condition persists, then held until cleared by STATUS
read back (32nd SCLK).
ECG R-to-R Detector R Event Interrupt. Issued when the R-to-R detector has identified a new R
event. Clear behavior is defined by CLR_RRINT[1:0]; see MNGR_INT for details.
D[10]
D[9]
RRINT
SAMP
Sample Synchronization Pulse. Issued on the ECG base-rate sampling instant, for use in assisting
µC monitoring and synchronizing other peripheral operations and data, generally recommended for
use as a dedicated interrupt.
Frequency is selected by SAMP_IT[1:0], see MNGR_INT for details.
Clear behavior is defined by CLR_SAMP, see MNGR_INT for details.
PLL Unlocked Interrupt. Indicates that the PLL has not yet achieved or has lost its phase lock.
PLLINT will only be asserted when the PLL is powered up and active (ECG and/or BioZ Channel
enabled).
D[8]
PLLINT
Remains asserted while the PLL unlocked condition persists, then held until cleared by STATUS read
back (32nd SCLK).
BioZ Current Generator Monitor Positive Output. Indicates the DRVP current generator has been in
a Lead Off condition for at least 128ms. This is not strictly an interrupt bit, but is a detailed status bit,
covered by the BCGMON interrupt bit.
D[5]
D[4]
BCGMP
BCGMN
BioZ Current Generator Monitor Negative Output. Indicates the DRVN current generator has been in
a Lead Off condition for at least 128ms. This is not strictly an interrupt bit, but is a detailed status bit,
covered by the BCGMON interrupt bit.
DC Lead Off Detection Detailed Status. Indicates that the MAX30001 has determined (as selected by
CNFG_GEN):
D[3]
D[2]
D[1]
D[0]
LDOFF_PH
LDOFF_PL
LDOFF_NH
LDOFF_NL
ECGP is above the high threshold (V
), ECGP is below the low threshold (V
), ECGN is above
THL
THH
the high threshold (VT ), ECGN is below the low threshold (V
), respectively.
HH
THL
Remains active as long as the leads-off detection is active and the leads-off condition persists, then
held until cleared by STATUS read back (32nd SCLK). LDOFF_PH to LDOFF_NL are detailed status
bits that are asserted at the same time as DCLOFFINT.
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
EN_INT (0x02) and EN_INT2 (0x03) Registers
EN_INT and EN_INT2 are read/write registers that govern the operation of the INTB output and INT2B output, respectively.
The first two bytes indicate which interrupt input bits are included in the interrupt output OR term (ex. a one in an EN_INT
register indicates that the corresponding input bit is included in the INTB interrupt output OR term). See the STATUS register
for detailed descriptions of the interrupt bits. The power-on reset state of all EN_INT bits is 0 (ignored by INT).
EN_INT and EN_INT2 can also be used to mask persistent interrupt conditions in order to perform other interrupt-driven
operations until the persistent conditions are resolved.
INTB_TYPE[1:0] allows the user to select between a CMOS or an open-drain NMOS mode INTB output. If using open-
drain mode, an option for an internal 125kΩ pullup resistor is also offered.
All INTB and INT2B types are active-low (INTB low indicates the device requires servicing by the µC); however, the open-
drain mode allows the INTB line to be shared with other devices in a wired-or configuration.
In general, it is suggested that INT2B be used to support specialized/dedicated interrupts of use in specific applications,
such as the self-clearing versions of SAMP or RRINT.
Table 13. EN_INT (0x02) and EN_INT2 (0x03) Register Maps
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
EN_
EOVF
EN_
FSTINT
EN_DCL
OFFINT
EN_
BOVER
EN_
BUNDR
EN_EINT
EN_BINT
EN_BOVF
0x02
0x03
EN_INT
EN_INT2
R/W
EN_
BCGMON
EN_
PEDGE
EN_
LONINT
EN_
RRINT
EN_
SAMP
EN_
PLLINT
EN_PINT
x
EN_POVF
x
x
x
x
x
INTB_TYPE[1:0]
Table 14. EN_INT (0x02 and 0x03) Register Meaning
INDEX
NAME
DEFAULT
FUNCTION
EN_EINT EN_
EOVF EN_FSTINT
EN_DCLOFFINT
EN_BINT
EN_BOVF
EN_BOVER
EN_BUNDR
EN_BCGMON
EN_PINT
Interrupt Enables for interrupt bits in STATUS[23:8]
0 = Individual interrupt bit is not included in the interrupt OR term
1 = Individual interrupt bit is included in the interrupt OR term
D[23:8]
0x0000
EN_POVF
EN_PEDGE
EN_LONINT EN_
RRINT EN_SAMP
EN_PLLINT
INTB Port Type (EN_INT Selections)
00 = Disabled (high impedance)
11
11
01 = CMOS Driver
10 = Open-Drain NMOS Driver
11 = Open-Drain NMOS Driver with Internal 125kΩ Pullup Resistance
D[1:0]
INTB_TYPE[1:0]
INT2B Port Type (EN_INT2 Selections)
00 = Disabled (high impedance)
01 = CMOS Driver
10 = Open-Drain nMOS Driver
11 = Open-Drain nMOS Driver with Internal 125kΩ Pullup Resistance
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
MNGR_INT (0x04)
MNGR_INT is a read/write register that manages the operation of the configurable interrupt bits in response to ECG and
BioZ FIFO conditions (see the STATUS register and ECG and BioZ FIFO descriptions for more details). Finally, this reg-
ister contains the configuration bits supporting the sample synchronization pulse (SAMP) and RTOR heart rate detection
interrupt (RRINT).
Table 15. MNGR_INT (0x04) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
EFIT[4:0]
x
20/12/4
19/11/3
18/10/2
17/9/1
BFIT[2:0]
x
16/8/0
x
x
x
x
x
x
x
MNGR_
INT
0x04
R/W
CLR_
FAST
CLR_
PEDGE
CLR_
SAMP
CLR_RRINT[1:0]
SAMP_IT[1:0]
Table 16. MNGR_INT (0x04) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
ECG FIFO Interrupt Threshold (issues EINT based on number of unread
FIFO records)
D[23:19]
EFIT[4:0]
01111
00000 to 11111 = 1 to 32, respectively (i.e. EFIT[4:0]+1 unread records)
BioZ FIFO Interrupt Threshold (issues BINT based on number of unread
FIFO records)
000 to 111 = 1 to 8, respectively (i.e. BFIT[2:0]+1 unread records)
D[18:16]
D[6]
BFIT[2:0]
011
FAST MODE Interrupt Clear Behavior:
0 = FSTINT remains active until the FAST mode is disengaged (manually or
automatically), then held until cleared by STATUS read back (32nd SCLK).
1 = FSTINT remains active until cleared by STATUS read back (32nd SCLK), even
if the MAX30001 remains in FAST recovery mode. Once cleared, FSTINT will
not be re-asserted until FAST mode is exited and re-entered, either manually or
automatically.
CLR_FAST
0
RTOR R Detect Interrupt (RRINT) Clear Behavior:
00 = Clear RRINT on STATUS Register Read Back
01 = Clear RRINT on RTOR Register Read Back
10 = Self-Clear RRINT after one ECG data rate cycle, approximately 2ms to 8ms
11 = Reserved. Do not use.
D[5:4]
CLR_RRINT[1:0]
00
PACE Edge Detect Interrupt (PEDGE) Clear Behavior
0 = Clear PEDGE on STATUS Register Read Back
1 = Self-Clear PEDGE after one PACE comparison cycle, roughly 16µs
Note: Self-Clear mode is recommended for INT2B use only.
D[3]
D[2]
CLR_PEDGE
CLR_SAMP
0
1
Sample Synchronization Pulse (SAMP) Clear Behavior:
0 = Clear SAMP on STATUS Register Read Back (recommended for debug/
evaluation only).
1 = Self-clear SAMP after approximately one-fourth of one data rate cycle.
Sample Synchronization Pulse (SAMP) Frequency
00 = issued every sample instant
D[1:0]
SAMP_IT[1:0]
00
01 = issued every 2nd sample instant
10 = issued every 4th sample instant
11 = issued every 16th sample instant
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
MNGR_DYN (0x05)
MNGR_DYN is a read/write register that manages the settings of any general/dynamic modes within the device. The
ECG Fast Recovery modes and thresholds are managed here. This register also contains the interrupt thresholds for
BioZ AC Lead-Off Detection (see CNFG_GEN for more details). Unlike many CNFG registers, changes to dynamic
modes do not impact FIFO operations or require a SYNCH operation (though the affected circuits may require time to
settle, resulting in invalid/corrupted FIFO output voltage information during the settling interval).
Table 17. MNGR_DYN (0x05) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
FAST[1:0]
FAST_TH[5:0]
MNGR_
DYN
0x05
R/W
BLOFF_HI_IT[7:0]
BLOFF_LO_IT[7:0]
Table 18. MNGR_DYN (0x05) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass):
00 = Normal Mode (Fast Recovery Mode Disabled)
01 = Manual Fast Recovery Mode Enable (remains active until disabled)
10 = Automatic Fast Recovery Mode Enable (Fast Recovery automatically
activated when/while ECG outputs are saturated, using FAST_TH).
11 = Reserved. Do not use.
D[23:22]
FAST[1:0]
00
Automatic Fast Recovery Threshold:
If FAST[1:0] = 10 and the output of an ECG measurement exceeds the symmetric
thresholds defined by 2048*FAST_TH for more than 125ms, the Fast Recovery
mode will be automatically engaged and remain active for 500ms.
For example, the default value (FAST_TH = 0x3F) corresponds to an ECG output
upper threshold of 0x1F800, and an ECG output lower threshold of 0x20800.
D[21:16]
FAST_TH[5:0]
0x3F
BioZ AC Lead Off Over-Range Threshold
If EN_BLOFF[1:0] = 1x and the ADC output of a BioZ measurement exceeds the
symmetric thresholds defined by ±2048*BLOFF_HI_IT for over 128ms, the BOVER
interrupt bit will be asserted.
For example, the default value (BLOFF_IT= 0xFF) corresponds to a BioZ output
upper threshold of 0x7F800 or about 99.6% of the full scale range, and a BioZ
output lower threshold of 0x80800 or about 0.4% of the full scale range with the
LSB weight ≈ 0.4%.
D[15:8]
D[7:0]
BLOFF_HI_IT[7:0]
BLOFF_LO_IT[7:0]
0xFF
0xFF
BioZ AC Lead Off Under-Range Threshold
If EN_BLOFF[1:0] = 1x and the output of a BioZ measurement is bounded by the
symmetric thresholds defined by ±32*BLOFF_LO_IT for over 128ms, the BUNDR
interrupt bit will be asserted.
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and Bioimpedance (BioZ) AFE
SW_RST (0x08)
SW_RST (Software Reset) is a write-only register/command that resets the MAX30001 to its original default conditions at
the end of the SPI SW_RST transaction (i.e. the 32nd SCLK rising edge). Execution occurs only if DIN[23:0] = 0x000000.
The effect of a SW_RST is identical to power-cycling the device.
Table 19. SW_RST (0x08) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
D[23:16] = 0x00
D[15:8] = 0x00
D[7:0] = 0x00
0x08
SW_RST
W
SYNCH (0x09)
SYNCH (Synchronize) is a write-only register/command that begins new ECG/BioZ operations and recording, beginning
on the internal MSTR clock edge following the end of the SPI SYNCH transaction (i.e. the 32nd SCLK rising edge).
Execution occurs only if DIN[23:0] = 0x000000. In addition to resetting and synchronizing the operations of any active
ECG, RtoR, BioZ, and PACE circuitry, SYNCH will also reset and clear the FIFO memories and the DSP filters (to mid-
scale), allowing the user to effectively set the “Time Zero” for the FIFO records. No configuration settings are impacted.
For best results, users should wait until the PLL has achieved lock before synchronizing if the CNFG_GEN settings have
been altered.
Once the device is initially powered up, it will need to be fully configured prior to launching recording operations. Likewise,
anytime a change to CNFG_GEN, CNFG_ ECG, or CNFG_BIOZ registers are made there may be discontinuities in the
ECG and BioZ records and possibly changes to the size of the time steps recorded in the FIFOs. The SYNCH command
provides a means to restart operations cleanly following any such disturbances.
During multi-channel operations, if a FIFO overflow event occurs and a portion of the record is lost, it is recommended
to use the SYNCH command to recover and restart the recording (avoiding issues with missing data in one or more
channel records). Note that the two channel records cannot be directly synchronized within the device, due to significant
differences in group delays, depending on filter selections—alignment of the records will have to be done externally.
Table 20. SYNCH (0x09) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
D[23:16] = 0x00
D[15:8] = 0x00
D[7:0] = 0x00
0x09
SYNCH
W
FIFO_RST (0x0A)
FIFO_RST (FIFO Reset) is a write-only register/command that begins a new ECG and BioZ recordings by resetting the
FIFO memories and resuming the record with the next available ECG and BioZ data. Execution occurs only if DIN[23:0]
= 0x000000. Unlike the SYNCH command, the operations of any active ECG, R-to-R, BioZ, and PACE circuitry are not
impacted by FIFO_RST, so no settling/recovery transients apply. FIFO_RST can also be used to quickly recover from a
FIFO overflow state (recommended for single ECG or BioZ channel use, see above).
Table 21. FIFO_RST (0x0A) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
D[23:16] = 0x00
D[15:8] = 0x00
D[7:0] = 0x00
0x0A
FIFO_RST
W
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
INFO (0x0F)
INFO is a read-only register that provides information about the MAX30001. The first nibble contains an alternating bit pattern
to aide in interface verification. The second nibble contains the revision ID. The third nibble includes part ID information.
Note: Due to internal initialization procedures, this command will not read-back valid data if it is the first com-
mand executed following either a power-cycle event, or a SW_RST event.
Table 22. INFO (0x0F) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
0
x
x
1
x
x
0
0
x
1
1
x
REV_ID[3:0]
0x0F
INFO
R
x
x
x
x
x
x
x
x
Table 23. INFO (0x0F) Register Meaning
INDEX
NAME
MEANING
Revision ID
D[19:16]
REV_ID[3:0]
CNFG_GEN (0x10)
CNFG_GEN is a read/write register which governs general settings, most significantly the master clock rate for all internal
timing operations. Anytime a change to CNFG_GEN is made, there may be discontinuities in the ECG and BioZ records
and possibly changes to the size of the time steps recorded in the FIFOs. The SYNCH command can be used to restore
internal synchronization resulting from configuration changes. Note when EN_ECG and EN_BIOZ are both logic-low, the
device is in one of two ultra-low power modes (determined by EN_ULP_LON).
Table 24. CNFG_GEN (0x10) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
EN_ECG
IPOL
18/10/2
17/9/1
EN_PACE
IMAG[2:0]
RBIASP
16/8/0
EN_ULP_LON[1:0]
EN_BLOFF[1:0]
VTH[1:0]
FMSTR[1:0]
EN_BIOZ
x
CNFG_
GEN
0x10
R/W
EN_DCLOFF[1:0]
EN_RBIAS[1:0]
RBIASV[1:0]
RBIASN
Table 25. CNFG_GEN (0x10) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
Ultra-Low Power Lead-On Detection Enable
00 = ULP Lead-On Detection disabled
01 = ECG ULP Lead-On Detection enabled
10 = Reserved. Do not use.
EN_ULP_LON
[1:0]
D[23:22]
00
11 = Reserved. Do not use.
ULP mode is only active when the ECG channel is powered down/disabled.
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Table 25. CNFG_GEN (0x10) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
Master Clock Frequency. Selects the Master Clock Frequency (FMSTR), and Timing
Resolution (T
), which also determines the ECG and CAL timing characteristics.
RES
These are generated from FCLK, which is always 32.768kHz.
D[21:20]
FMSTR[1:0]
00
00 = F
01 = F
10 = F
11 = F
= 32768Hz, T
= 32000Hz, T
= 32000Hz, T
= 15.26µs (512Hz ECG progressions)
= 15.63µs (500Hz ECG progressions)
= 15.63µs (200Hz ECG progressions)
MSTR
MSTR
MSTR
MSTR
RES
RES
RES
= 31968.78Hz, T
= 15.64µs (199.8049Hz ECG progressions)
RES
ECG Channel Enable
0 = ECG Channel disabled
1 = ECG Channel enabled
D[19]
EN_ECG
0
Note: The ECG channel must be enabled to allow R-to-R operation.
BioZ Channel Enable
D[18]
D[17]
EN_BIOZ
EN_PACE
0
0
0 = BioZ Channel disabled
1 = BioZ Channel enabled
PACE Channel Enable
0 = PACE Channel disabled
1 = PACE Channel enabled if ECG channel also enabled (EN_ECG=1)
BioZ Digital Lead Off Detection Enable
00 = Digital Lead Off Detection disabled
01 = Lead Off Under Range Detection, 4 electrode BioZ applications
10 = Lead Off Over Range Detection, 2 and 4 electrode BioZ applications
11 = Lead Off Over & Under Range Detection, 4 electrode BioZ applications
AC Method, requires active BioZ Channel , enables BOVER & BUNDR interrupt
behavior. Uses BioZ excitation current set in CNFG_BIOZ with digital thresholds set
in MNGR_DYN.
D[15:14]
EN_BLOFF[1:0]
00
DC Lead-Off Detection Enable
00 = DC Lead-Off Detection disabled
01 = DCLOFF Detection applied to the ECGP/N pins
10 = Reserved. Do not use.
11 = Reserved. Do not use.
DC Method, requires active selected channel, enables DCLOFF interrupt and status
bit behavior.
Uses current sources and comparator thresholds set below.
D[13:12]
D[11]
EN_DCLOFF
00
DC Lead-Off Current Polarity (if current sources are enabled/connected)
DCLOFF_ IPOL
0
0 = ECGP - Pullup
ECGN – Pulldown
1 = ECGP - Pulldown ECGN – Pullup
DC Lead-Off Current Magnitude Selection
000 = 0nA (Disable and Disconnect Current Sources)
001 = 5nA
010 = 10nA
D[10:8]
IMAG[2:0]
000
011 = 20nA
100 = 50nA
101 = 100nA
110 = Reserved. Do not use.
111 = Reserved. Do not use.
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Ultra-Low-Power, Single-Channel Integrated
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and Bioimpedance (BioZ) AFE
Table 25. CNFG_GEN (0x10) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
DC Lead-Off Voltage Threshold Selection
00 = V
01 = V
10 = V
11 = V
± 300mV
± 400mV
± 450mV
± 500mV
MID
MID
MID
MID
D[7:6]
VTH[1:0]
00
Enable and Select Resistive Lead Bias Mode
00 = Resistive Bias disabled
01 = ECG Resistive Bias enabled if EN_ECG is also enabled
10 = BioZ Resistive Bias enabled if EN_BIOZ is also enabled
11 = Reserved. Do not use.
If EN_ECG or EN_BIOZ is not asserted at the same time or prior to EN_RBIAS[1:0]
being enabled, then EN_RBIAS[1:0] will remain set to 00.
D[5:4]
D[3:2]
EN_RBIAS[1:0]
RBIASV[1:0]
00
01
Resistive Bias Mode Value Selection
00 = R
01 = R
10 = R
= 50MΩ
= 100MΩ
= 200MΩ
BIAS
BIAS
BIAS
11 = Reserved. Do not use.
Enables Resistive Bias on Positive Input
D[1]
D[0]
RBIASP
RBIASN
0
0
0 = ECGP/BIP is not resistively connected to V
MID
1 = ECGP/BIN is connected to V
through a resistor (selected by RBIASV).
MID
Enables Resistive Bias on Negative Input
0 = ECGN is not resistively connected to V
MID
1 = ECGN is connected to V
through a resistor (selected by RBIASV).
MID
Table 26 shows the ECG and BioZ data rates that can be realized with various setting of FMSTR, along with RATE con-
figuration bits available in the CNFG_ECG and CNFG_BIOZ registers. Note FMSTR also determines the timing resolu-
tion of the PACE detection block (and the resulting record depth with respect to the ECG_RATE selection) as well as the
timing resolution of the CAL waveform generator.
Table 26. Master Frequency Summary Table
MASTER
FMSTR FREQUENCY
ECG
RTOR TIMING
RESOLUTION
(RTOR_RES)
(ms)
PACE TIMING
RESOLUTION
(PACE_RES)
(μs)
PACE FIFO
RECORD
DEPTH
CALIBRATION BioZ DATA
DATA RATE
(ECG_RATE)
(sps)
TIMING
RATES
(B_RATE)
(sps)
[1:0]
(f
)
RESOLUTION
MSTR
(Hz)
(ECG_RATE) (CAL_RES) (μs)
00 = 512
01 = 256
10 = 128
00 = 128
01 = 256
1x = 512
0 = 64
1 = 32
00
01
32,768
32,000
7.8125
8.000
15.26
15.63
30.52
31.25
00 = 500
01 = 250
10 = 125
00 = 128
01 = 256
1x = 512
0 = 62.50
1 = 31.25
0 = 50
1 = 25
10
11
32,000
31,968
10 = 200
8.000
8.008
15.63
15.64
320
320
31.25
31.28
0 = 49.95
1 = 24.98
10 = 199.8049
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
CNFG_CAL (0x12)
CNFG_CAL is a read/write register that configures the operation, settings, and function of the Internal Calibration Voltage
Sources (VCALP and VCALN). The output of the voltage sources can be routed to the ECG or BioZ/PACE inputs through
the channel input MUXes to facilitate end-to-end testing operations. Note if a VCAL source is applied to a connected
device, it is recommended that the appropriate channel MUX switches be placed in the OPEN position.
Table 27. CNFG_CAL (0x12) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
VMODE
20/12/4
19/11/3
x
18/10/2
17/9/1
x
16/8/0
x
x
EN_VCAL
VMAG
x
x
CNFG_
CAL
0x12
R/W
FCAL[2:0]
FIFTY
THIGH[10:8]
THIGH[7:0]
Table 28. CNFG_CAL (0x12) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
Calibration Source (VCALP and VCALN) Enable
0 = Calibration sources and modes disabled
1 = Calibration sources and modes enabled
D[22]
EN_VCAL
0
Calibration Source Mode Selection
D[21]
D[20]
VMODE
VMAG
0
0
0 = Unipolar, sources swing between V
± V
and V
MID
MAG MID
1 = Bipolar, sources swing between V
+ V
and V
- V
MID MAG
MID
MAG
Calibration Source Magnitude Selection (V
0 = 0.25mV
1 = 0.50mV
)
MAG
Calibration Source Frequency Selection (FCAL)
000 = F
001 = F
010 = F
011 = F
100 = F
101 = F
110 = F
/128
(256, 250, or 249.75Hz)
MSTR
MSTR
MSTR
MSTR
MSTR
MSTR
MSTR
MSTR
/512 (64, 62.5, or 62.4375Hz)
/2048 (16, 15.625, or 15.609375Hz)
/8192 (4, 3.90625, or 3.902344Hz)
15
/2
/2
/2
(1, 0.976563, or 0.975586Hz)
(0.25, 0.24414, or 0.243896Hz)
(0.0625, 0.061035Hz, or 0.060974Hz)
(0.015625, 0.015259, or 0.015244Hz)
D[14:12]
FCAL[2:0]
100
17
19
21
111 = F
/2
Actual frequencies are determined by FMSTR selection (see CNFG_GEN for
details), frequencies in parenthesis are based on 32,768, 32,000, or 31,968Hz
clocks (FMSTR[1:0] = 00). TCAL = 1/FCAL.
Calibration Source Duty Cycle Mode Selection
D[11]
FIFTY
1
0 = Use CAL_THIGH to select time high for VCALP and VCALN
1 = THIGH = 50% (CAL_THIGH[10:0] are ignored)
Calibration Source Time High Selection
If FIFTY = 1, t
= 50% (and THIGH[10:0] are ignored), otherwise THIGH =
HIGH
D[10:0]
THIGH[10:0]
0x000
THIGH[10:0] x CAL_RES
CAL_RES is determined by FMSTR selection (see CNFG_GEN for details);
for example, if FMSTR[1:0] = 00, CAL_RES = 30.52µs.
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CALIBRATION VOLTAGE SOURCE OPTIONS
V
V
V
+ 0.25mV
- 0.25mV
+ 0.50mV
V
V
V
+ 0.25mV
- 0.25mV
+ 0.50mV
MID
MID
MID
MID
MID
MID
CAL_VMODE = 0
CAL_VMAG = 0
CAL_VMODE = 1
CAL_VMAG = 0
V
V
V
V
MID
MID
MID
MID
MID
MID
VCALP
VCALN
CAL_VMODE = 0
CAL_VMAG = 1
CAL_VMODE = 1
CAL_VMAG = 1
V
V
- 0.50mV
- 0.50mV
T
HIGH
T
CAL
Figure 16. Calibration Voltage Source Options
CNFG_EMUX (0x14)
CNFG_EMUX is a read/write register which configures the operation, settings, and functionality of the Input Multiplexer
associated with the ECG channel.
Table 29. CNFG_EMUX (0x14) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
ECG_
OPENP
ECG_
OPENN
ECG_POL
x
ECG_CALP_SEL[1:0]
ECG_CALN_SEL[1:0]
CNFG_
EMUX
0x14
R/W
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Table 30. CNFG_EMUX (0x14) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
ECG Input Polarity Selection
0 = Non-inverted
D[23]
ECG_POL
0
1 = Inverted
Open the ECGP Input Switch (most often used for testing and calibration)
0 = ECGP is internally connected to the ECG AFE Channel
1 = ECGP is internally isolated from the ECG AFE Channel
D[21]
D[20]
ECG_OPENP
ECG_OPENN
1
1
Open the ECGN Input Switch (most often used for testing and calibration)
0 = ECGN is internally connected to the ECG AFE Channel
1 = ECGN is internally isolated from the ECG AFE Channel
ECGP Calibration Selection
00 = No calibration signal applied
ECG_CALP_
SEL[1:0]
D[19:18]
D[17:16]
00
00
01 = Input is connected to V
MID
10 = Input is connected to VCALP (only available if CAL_EN_VCAL = 1)
11 = Input is connected to VCALN (only available if CAL_EN_VCAL = 1)
ECGN Calibration Selection
00 = No calibration signal applied
ECG_CALN_
SEL[1:0]
01 = Input is connected to V
MID
10 = Input is connected to VCALP (only available if CAL_EN_VCAL = 1)
11 = Input is connected to VCALN (only available if CAL_EN_VCAL = 1)
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CNFG_ECG (0x15)
CNFG_ECG is a read/write register which configures the operation, settings, and functionality of the ECG channel.
Anytime a change to CNFG_ECG is made, there may be discontinuities in the ECG record and possibly changes to the
size of the time steps recorded in the ECG FIFO. The SYNCH command can be used to restore internal synchronization
resulting from configuration changes.
Table 31. CNFG_ECG (0x15) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
ECG_RATE[1:0]
x
x
x
x
x
x
x
x
ECG_GAIN[1:0]
CNFG_
ECG
0x15
R/W
x
x
ECG_DHPF
x
ECG_DLPF[1:0]
x
x
x
x
x
x
Table 32. CNFG_ECG (0x15) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
ECG Data Rate (also dependent on FMSTR selection, see CNFG_GEN Table 33):
FMSTR = 00: f
00 = 512sps
01 = 256sps
10 = 128sps
= 32768Hz, t
= 15.26µs (512Hz ECG progressions)
= 15.63µs (500Hz ECG progressions)
= 15.63µs (200Hz ECG progressions)
= 15.64µs (199.8Hz ECG progressions)
MSTR
RES
RES
RES
RES
11 = Reserved. Do not use.
FMSTR = 01: f
00 = 500sps
01 = 250sps
10 = 125sps
= 32000Hz, t
MSTR
11 = Reserved. Do not use.
D[23:22]
ECG_RATE[1:0]
10
FMSTR = 10: f = 32000Hz, t
MSTR
00 = Reserved. Do not use.
01 = Reserved. Do not use.
10 = 200sps
11 = Reserved. Do not use.
FMSTR = 11: f
= 31968Hz, t
MSTR
00 = Reserved. Do not use.
01 = Reserved. Do not use.
10 = 199.8sps
11 = Reserved. Do not use.
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Table 32. CNFG_ECG (0x15) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
ECG Channel Gain Setting
00 = 20V/V
D[17:16]
ECG_GAIN[1:0]
00
01 = 40V/V
10 = 80V/V
11 = 160V/V
ECG Channel Digital High-Pass Filter Cutoff Frequency
D[14]
ECG_DHPF
1
0 = Bypass (DC)
1 = 0.50Hz
ECG Channel Digital Low-Pass Filter Cutoff Frequency
00 = Bypass (Decimation only, no FIR filter applied)
01 = approximately 40Hz (Except for 125 and 128sps settings, see Table 33)
10 = approximately 100Hz (Available for 512, 256, 500, and 250sps ECG Rate
selections only)
D[13:12]
ECG_DLPF[1:0]
01
11 = approximately 150Hz (Available for 512 and 500sps ECG Rate selections only)
Note: See Table 33. If an unsupported DLPF setting is specified, the 40Hz setting
(ECG_DLPF[1:0] = 01) will be used internally; the CNFG_ECG register will continue
to hold the value as written, but return the effective internal value when read back.
Table 33. Supported ECG_RATE and ECG_DLPF Options
ECG_DLPF[1:0]/DIGITAL LPF CUTOFF
ECG_RATE[1:0]
SAMPLE RATE
(sps)
CNFG_GEN
FMSTR[1:0]
00
01 (Hz)
10 (Hz)
11 (Hz)
00 = 512
01 = 256
10 = 128
00 = 500
01 = 250
10 = 125
10 = 200
10 = 199.8
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
Bypass
40.96
40.96
28.35
40.00
40.00
27.68
40.00
39.96
102.4
102.4
28.35
100.0
100.0
27.68
40.00
39.96
153.6
40.96
28.35
150.0
40.00
27.68
40.00
39.96
00 = 32,768Hz
01 = 32,000Hz
10 = 32,000Hz
11 = 31,968Hz
Note: Combinations shown in grey are unsupported and will be internally mapped to the default settings shown.
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CNFG_BMUX(0x17)
CNFG_BMUX is a read/write register which configures the operation, settings, and functionality of the input multiplexer
associated with the BioZ channel.
Table 34. CNFG_BMUX (0x17) Register Map
REG
NAME
R/W 23/15/7 22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
BMUX_
OPENN
x
x
x
BMUX_OPENP
BMUX_CALP_SEL[1:0]
BMUX_CALN_SEL[1:0]
CNFG_
BMUX
0x17
R/W
BMUX_
x
x
BMUX_CG_MODE[1:0]
BMUX_RMOD[2:0]
BMUX_RNOM[2:0]
BMUX_FBIST[1:0]
EN_BIST
x
x
Table 35. CNFG_BMUX (0x17) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
Open the BIP Input Switch (most often used for testing and calibration)
0 = BIP is internally connected to the BioZ channel
1 = BIP is internally isolated from the BioZ channel
BMUX_
OPENP
D[21]
1
Open the BIN Input Switch (most often used for testing and calibration)
0 = BIN is internally connected to the BioZ channel
1 = BIN is internally isolated from the BioZ channel
BMUX_
OPENN
D[20]
1
BIP Calibration Selection (VCAL application to BIP/N inputs intended for use in PACE
testing only.)
BMUX_CALP_
SEL[1:0]
00 = No calibration signal applied
01 = Input is connected to VMID
D[19:18]
00
10 = Input is connected to VCALP (only available if CAL_EN_VCAL=1)
11 = Input is connected to VCALN (only available if CAL_EN_VCAL=1)
BIN Calibration Selection (VCAL application to BIP/N inputs intended for use in PACE
testing only.)
BMUX_CALN_
SEL[1:0]
00 = No calibration signal applied
01 = Input is connected to VMID
D[17:16]
00
10 = Input is connected to VCALP (only available if CAL_EN_VCAL=1)
11 = Input is connected to VCALN (only available if CAL_EN_VCAL=1)
BioZ Current Generator Mode Selection
00 = Unchopped Sources with Low Pass Filter
(higher noise, excellent 50/60Hz rejection, recommended for ECG,
BioZ applications)
01 = Chopped Sources without Low Pass Filter
(low noise, no 50/60Hz rejection, recommended for BioZ applications
with digital LPF, possibly battery powered ECG, BioZ applications)
10 = Chopped Sources with Low Pass Filter
BMUX_CG_
MODE[1:0]
D[13:12]
00
(low noise, excellent 50/60Hz rejection)
11 = Chopped Sources with Resistive CM Setting
(Not recommended to be used for drive currents >32µA)
(low noise, excellent 50/60Hz rejection, lower input impedance)
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Table 35. CNFG_BMUX (0x17) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
BioZ Modulated Resistance Built-In-Self-Test (RMOD BIST) Mode Enable
0 = RMOD BIST Disabled
1 = RMOD BIST Enabled
BMUX_EN_
BIST
Note: Available only when CNFG_CAL EN_VCAL= 0
To avoid body interference, the BIP/N switches should be open in this mode.
When enabled, the DRVP/N isolation switches are opened and the DRVP/N-to-BIP/N
internal switches are engaged. Also, the lead bias resistors are applied to the BioZ
inputs in 200MΩ mode.
D[11]
0
BMUX_
RNOM[2:0]
BioZ RMOD BIST Nominal Resistance Selection
See RMOD BIST Settings Table for details.
D[10:8]
D[6:4]
000
100
BioZ RMOD BIST Modulated Resistance Selection (See RMOD BIST Settings Table
for details.)
000 = Modulated Resistance Value 0
001 = Modulated Resistance Value 1
010 = Modulated Resistance Value 2
BMUX_
RMOD[2:0]
011 = Reserved, Do Not Use
1xx = All SWMOD Switches Open - No Modulation (DC value = RNOM)
BioZ RMOD BIST Frequency Selection
Calibration Source Frequency Selection (FCAL)
13
00 = f
01 = f
10 = f
11 = f
/2
/2
/2
(Approximately
(Approximately
(Approximately 1/4 Hz)
(Approximately 1/16 Hz)
4 Hz)
1 Hz)
MSTR
MSTR
MSTR
15
17
BMUX_
FBIST[1:0]
D[1:0]
00
19
/2
MSTR
Actual frequencies are determined by FMSTR selection (see CNFG_GEN for details),
approximate frequencies are based on a 32,768 Hz clock (FMSTR[1:0]=00). All
selections use 50% duty cycle.
Table 36. CNFG_BMUX (0x17) RMOD BIST Settings
NOMINAL RESISTANCE
(Ω)
MODULATED RESISTANCE
(mΩ)
BMUX_RNOM[2:0]
BMUX_RMOD[2:0]
000
001
010
1xx
2960.7
980.6
247.5
000
5000
2500
1667
Unmodulated
000
001
010
1xx
740.4
245.2
61.9
001
010
Unmodulated
000
001
010
1xx
329.1
109.0
27.5
Unmodulated
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Table 36. CNFG_BMUX (0x17) RMOD BIST Settings (continued)
BMUX_RNOM[2:0]
AND SWNOM
SWITCHES ENGAGED
NOMINAL RESISTANCE
MODULATED RESISTANCE
(mΩ)
BMUX_RMOD[2:0]
(Ω)
000
001
1xx
185.1
61.3
Unmodulated
011
100
101
110
111
1250
000
001
1xx
118.5
39.2
Unmodulated
1000
833
714
625
000
001
1xx
82.3
27.2
Unmodulated
000
001
1xx
60.5
20.0
Unmodulated
000
001
1xx
46.3
15.3
Unmodulated
CNFG_BIOZ(0x18)
CNFG_BIOZ is a read/write register which configures the operation, settings, and function of the BioZ channel, including
the associated modulated current generator. Anytime a change to CNFG_BIOZ is made, there may be discontinuities in
the BioZ record and possibly changes to the size of the time steps recorded in the BioZ FIFO. The SYNCH command
can be used to restore internal synchronization resulting from configuration changes.
Table 37. CNFG_BIOZ (0x18) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
BIOZ_
RATE
EXT_
RBIAS
BIOZ_AHPF[2:0]
LN_BIOZ
BIOZ_GAIN[1:0]
CNFG_
BioZ
0x18
R/W
BIOZ_DHPF[1:0]
BIOZ_DLPF[1:0]
BIOZ_CGMAG[2:0]
BIOZ_FCGEN[3:0]
BIOZ_PHOFF[3:0]
BIOZ_
CGMON
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Table 38. CNFG_BIOZ (0x18) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
BioZ Data Rate (also dependent on FMSTR selection, see CNFG_GEN):
FMSTR = 00: f
0 = 64sps
1 = 32sps
= 32,768Hz (512Hz ECG/BioZ progressions)
= 32,000Hz (500Hz ECG/BioZ progressions)
= 32,000 Hz (200Hz ECG/BioZ progressions)
= 31,968 Hz (199.8Hz ECG/BioZ progressions)
MSTR
MSTR
MSTR
MSTR
FMSTR = 01: f
0 = 62.50sps
1 = 31.25sps
D[23]
BIOZ_RATE
0
FMSTR = 10: f
0 = 50sps
1 = 25sps
FMSTR = 11: f
0 = 49.95sps
1 = 24.98sps
BioZ/PACE Channel Analog High-Pass Filter Cutoff Frequency and Bypass
000 = 125Hz
001 = 300Hz
BIOZ_
AHPF[2:0]
010 = 800Hz
D[22:20]
010
011 = 2000Hz
100 = 3700Hz
101 = 7200Hz
11x = Bypass AHPF
External Resistor Bias Enable
0 = Internal Bias Generator used
1 = External Bias Generator used
Note: Use of the external resistor bias will improve the temperature coefficient of all
biases within the product, but the main benefit is improved control of BioZ current
generator magnitude. If enabled, the user must include the required external resistor
D[19]
EXT_RBIAS
LN_BIOZ
0
between R
and GND, and the temperature coefficent achieved will be determined
BIAS
by the combined performance of the internal bandgap and the external resistor.
BioZ Channel Instrumentation Amplifier (INA) Power Mode
0 = BioZ INA is in low power mode
D[18]
0
1 = BioZ INA is in low noise mode
BioZ Channel Gain Setting
00 = 10V/V
01 = 20V/V
BIOZ_
GAIN[1:0]
D[17:16]
00
10 = 40V/V
11 = 80V/V
BioZ Channel Digital High-Pass Filter Cutoff Frequency
BIOZ_
DHPF[1:0]
00 = Bypass (DC)
01 = 0.05Hz
D[15:14]
00
1x = 0.50Hz
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Table 38. CNFG_BIOZ (0x18) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
BioZ Channel Digital Low-Pass Filter Cutoff Frequency
00 = Bypass (Decimation only, no FIR filter)
01 = 4Hz
10 = 8Hz
BIOZ_
DLPF[1:0]
D[13:12]
01
11 = 16Hz (Available for 64, 62.5, 50, and 49.95sps BioZ Rate selections only)
Note: See Table 39 below. If an unsupported DLPF setting is specified, the 4Hz
setting (BIOZ_DLPF[1:0] = 01) will be used internally; the CNFG_BIOZ register will
continue to hold the value as written, but return the effective internal value when read
back.
BioZ Current Generator Modulation Frequency
0000 = 4*f
0001 ≈ 2*f
(approximately 128000Hz) 1000 = f
/64 (approximately 500Hz)
/128 (approximately 250Hz)
/256 (approximately 125Hz)
MSTR
MSTR
MSTR
(approximately 80000Hz) 1001 = f
(approximately 40000Hz) 101x = f
MSTR
0010 ≈ f
0011 ≈ f
MSTR
MSTR
/2
(approximately 18000Hz) 11xx = f /256 (approximately 125Hz)
MSTR
MSTR
0100 = f
0101 = f
0110 = f
/4
/8
(approximately 8000Hz)
(approximately 4000Hz)
MSTR
MSTR
MSTR
BIOZ_
FCGEN[3:0]
D[11:8]
1000
/16 (approximately 2000Hz)
/32 (approximately 1000Hz)
0111 = f
MSTR
Actual frequencies determined by FMSTR selection, see CNFG_GEN register and
table below for details. Frequencies expected between approximately16kHz and
approximately 64kHz are offset to approximately18kHz to approximately 80kHz
to reduce ECG/PACE channel crosstalk. PACE operation is only supported at
approximately 40kHz and approximately 80kHz offset selections: FCGEN[3:0] =
0001,0010, at other selections, PACE will be rendered inoperable.
BioZ Current Generator Monitor
0 = Current Generator Monitors disabled
BIOZ_
CGMON
1 = Current Generator Monitors enabled, requires active BioZ channel and Current
Generators. Enables BCGMON interrupt and status bit behavior. Monitors current
source compliance levels, useful in detecting DRVP/DRVN lead off conditions with 4
electrode BioZ applications.
D[7]
0
BioZ Current Generator Magnitude
000 = Off (DRVP and DRVN floating, Current Generators Off)
001 = 8µA
010 = 16µA
011 = 32µA
100 = 48µA
101 = 64µA
BIOZ_
CGMAG[2:0]
D[6:4]
000
110 = 80µA
111 = 96µA
See Table 40 and 41 below for a list of allowed BIOZ_CGMAG settings vs. FCGEN
selections.
BioZ Current Generator Modulation Phase Offset
Phase Resolution and Offset depends on BIOZ_FCGEN setting:
BIOZ_
PHOFF[3:0]
D[3:0]
0000
BIOZ_FCGEN[3:0] ≥ 0010: Phase Offset = BIOZ_PHOFF[3:0]*11.25° (0 to 168.75°)
BIOZ_FCGEN[3:0] = 0001: Phase Offset = BIOZ_PHOFF[3:1]*22.50° (0 to 157.50°)
BIOZ_FCGEN[3:0] = 0000: Phase Offset = BIOZ_PHOFF[3:2]*45.00° (0 to 135.00°)
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Table 39. Supported BIOZ_RATE and BIOZ_DLPF Options
BIOZ_DLPF[1:0] / Digital LPF Cut Off
CNFG_GEN
FMSTR[1:0]
BIOZ_RATE
Sample Rate
00
01
10
11
0 = 64sps
1 = 32sps
16.384Hz
4.096Hz
16.0Hz
4.0Hz
00 = 32,768Hz
01 = 32,000Hz
10 = 32,000Hz
11 = 31,968Hz
Bypass
4.096Hz
8.192Hz
0 = 62.5sps
1 = 31.25sps
0 = 50sps
Bypass
Bypass
Bypass
4.0Hz
4.0Hz
8.0Hz
8.0Hz
16.0Hz
4.0Hz
1 = 25sps
0 = 49.95sps
1 = 25.98sps
15.984Hz
3.996Hz
3.996Hz
7.992Hz
Note: Combinations shown in grey are unsupported and will be internally mapped to the default settings shown.
Table 40. Actual BioZ Current Generator Modulator Frequencies vs.
FMSTR[1:0] Selection
BioZ Current Generator Modulation Frequency (Hz)
BIOZ_FCGEN[3:0]
FMSTR[1:0] = 00
= 32,768Hz
FMSTR[1:0] = 01
= 32,000Hz
FMSTR[1:0] = 10
= 32,000Hz
FMSTR[1:0] = 11
f
f
f
f
= 31,968Hz
MSTR
MSTR
MSTR
MSTR
0000
0001
131,072
81,920
40,960
18,204
8,192
4,096
2,048
1,024
512
128,000
80,000
40,000
17,780
8,000
4,000
2,000
1,000
500
128,000
80,000
40,000
17,780
8,000
4,000
2,000
1,000
500
127,872
81,920
40,960
18,204
7,992
3,996
1,998
999
0010
0011
0100
0101
0110
0111
1000
500
1001
256
250
250
250
101x, 11xx
128
125
125
125
Note: Shaded selections are intentionally offset to improve ECG/PACE system crosstalk.
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Table 41. Allowed CGMAG Option vs. FCGEN Selections
APPROXIMATE CURRENT
GENERATOR
MODULATION FREQUENCY (Hz)
CURRENT GENERATOR
MAGNITUDE
CGMAG[2:0]
OPTIONS ALLOWED
FCGEN[3:0]
OPTIONS ALLOWED (µA
)
P-P
0000
0001
12,8000
80,000
40,000
18,000
8,000
4,000
2,000
1,000
500
All
All
0010
0011
0100
All except 111
000, 001, 010, 011
000, 001, 010
All except 96
Off, 8, 16, 32
Off, 8, 16
0101
0110
0111
1000
000, 001
Off, 8
1001
250
101x, 11xx
125
CNFG_PACE (0x1A) Register
CNFG_PACE is a read/write register which configures the operation, settings, and function of the PACE detection chan-
nel. Portions of the PACE AFE are shared with the BioZ channel so anytime a change to CNFG_BIOZ or CNFG_PACE
is made, there may be discontinuities in the combined ECG/PACE FIFO output. The SYNCH command can be used to
restore internal synchronization resulting from configuration changes.
Note if enabling the PACE function, the Analog High-Pass Filter in the shared BioZ/PACE AFE must be set to the desired
value via BIOZ_AHPF[1:0] in the CNFG_BIOZ register, even if the BioZ function is disabled (EN_BIOZ = 0 in CNFG_GEN
register.
Table 42. CNFG_PACE (0x1A) Register Map
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
DIFF_OFF
x
18/10/2
17/9/1
16/8/0
PACE_
POL
x
x
x
PACE_GAIN[2:0]
CNFG_
PACE
0x1A
R/W
x
AOUT_LBW
AOUT[1:0]
x
x
x
PACE_DACP[3:0]
PACE_DACN[3:0]
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Table 43. CNFG_PACE (0x1A) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
PACE Input Polarity Selection
0 = Non-Inverted
D[23]
PACE_POL
0
1 = Inverted
PACE Differentiator (Derivative) Mode
D[19]
DIFF_OFF
0
0 = Enable Differentiator function (default)
1 = Disable Differentiator function, using Sample and Hold function
PACE Channel Gain Selection
Normal Mode
(AOUT = 00)
45*4*3 = 540
45*2*3 = 270
20*4*3 = 240
20*2*3 = 120
INA OUT Mode
(AOUT = 01)
45*1.125 = 50.625
45*1.125 = 50.625
20*1.125 = 22.500
20*1.125 = 22.500
PGA OUT Mode
(AOUT = 10)
45*4*1.125 = 202.50
45*2*1.125 = 101.25
20*4*1.125 = 90.00
20*2*1.125 = 45.00
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
D[18:16]
PACE_
GAIN[2:0]
000
5*4*3
5*2*3
=
=
60
30
5*1.125
5*1.125
5*1.125
5*1.125
=
=
=
=
5.625
5.625
5.625
5.625
5*4*1.125
5*2*1.125
5*4*1.125
5*2*1.125
=
=
=
=
22.50
11.25
22.50
11.25
2.2*4*3 = 26.4
2.2*2*3 = 13.2
PACE Analog Output Buffer Bandwidth Mode
0 = Maximum BW (approximately 100kHz)
1 = Limited BW (approximately 16kHz)
D[14]
AOUT_LBW
AOUT[1:0]
0
This selection is only relevant when the AOUT buffer is active AOUT ≠ 00.
PACE Single Ended Analog Output Buffer Signal Monitoring Selection
00 = Analog Output Buffer Disabled
01 = PACE INA Output
D[13:12]
00
10 = PACE PGA Output
11 = PACE Input to Comparators
PACE_
DACP[3:0]
PACE Detector Positive Comparator Threshold
VDACP = PACE_DACP[3:0]*22.5mV (+112.5mV default)
D[7:4]
D[3:0]
0101
0101
PACE_
DACN[3:0]
PACE Detector Negative Comparator Threshold
VDACN = -PACE_DACN[3:0]*22.5mV (-112.5mV default)
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CNFG_RTOR1 and CNFG_RTOR2 (0x1D and 0x1E)
CNFG_RTOR is a two-part read/write register that configures the operation, settings, and function of the R-to-R heart
rate detection block. The first register contains algorithmic voltage gain and threshold parameters, the second contains
algorithmic timing parameters.
Table 44. CNFG_RTOR1 and CNFG_RTOR2 (0x1D and 0x1E) Register Maps
REG
NAME
R/W
23/15/7
22/14/6
21/13/5
20/12/4
19/11/3
18/10/2
17/9/1
16/8/0
WNDW[3:0]
RGAIN[3:0]
CNFG_
RTOR1
EN_
RTOR
0x1D
R/W
x
PAVG[1:0]
PTSF[3:0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
HOFF[5:0]
CNFG_
RTOR2
0x1E
R/W
RAVG[1:0]
x
x
RHSF[2:0]
x
x
x
Table 45. CNFG_RTOR1 (0x1D) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
CNFG_RTOR1 (0x1D)
This is the width of the averaging window, which adjusts the algorithm sensitivity to
the width of the QRS complex.
R-to-R Window Averaging (Window Width = WNDW[3:0]*8ms)
0000 = 6 x RTOR_RES
0001 = 8 x RTOR_RES
0010 = 10 x RTOR_RES
0011 = 12 x RTOR_RES
0100 = 14 x RTOR_RES
0101 = 16 x RTOR_RES
0110 = 18 x RTOR_RES
0111 = 20 x RTOR_RES
1000 = 22 x RTOR_RES
1001 = 24 x RTOR_RES
1010 = 26 x RTOR_RES
1011 = 28 x RTOR_RES
(default = 96ms)
D[23:20]
WNDW[3:0]
0011
1100 = Reserved. Do not use.
1101 = Reserved. Do not use.
1110 = Reserved. Do not use.
1111 = Reserved. Do not use.
The value of RTOR_RES is approximately 8ms, see Table 26.
R-to-R Gain (where Gain = 2^RGAIN[3:0], plus an auto-scale option). This is used to
maximize the dynamic range of the algorithm.
0000 =
0001 =
0010 =
0011 =
1
2
4
8
1000 = 256
1001 = 512
1010 = 1024
1011 = 2048
D[19:16]
RGAIN[3:0]
1111
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1100 = 4096
1101 = 8192
1110 = 16384
1111 = Auto-Scale (default)
In Auto-Scale mode, the initial gain is set to 64.
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Table 45. CNFG_RTOR1 (0x1D) Register Functionality (continued)
INDEX
NAME
DEFAULT
FUNCTION
ECG R-to-R Detection Enable
0 = R-to-R Detection disabled
D[15]
EN_RTOR
0
1 = R-to-R Detection enabled if EN_ECG is also enabled.
R-to-R Peak Averaging Weight Factor
This is the weighting factor for the current R-to-R peak observation vs. past peak
observations when determining peak thresholds. Lower numbers weight current peaks
more heavily.
D[13:12]
D[11:8]
PAVG[1:0]
PTSF[3:0]
10
00 = 2
01 = 4
10 = 8 (default)
11 = 16
Peak_Average(n) = [Peak(n) + (PAVG-1) x Peak_Average(n-1)] / PAVG.
R-to-R Peak Threshold Scaling Factor
This is the fraction of the Peak Average value used in the Threshold computation.
Values of 1/16 to 16/16 are selected by (PTSF[3:0]+1)/16, default is 4/16.
0011
Table 46. CNFG_RTOR2 (0x1E) Register Functionality
CNFG_RTOR2 (0x1E)
R-to-R Minimum Hold Off
This sets the absolute minimum interval used for the static portion of the Hold Off
criteria. Values of 0 to 63 are supported, default is 32
= HOFF[5:0] * t , where t is approximately 8ms, as
t
HOLD_OFF_MIN
RTOR
RTOR
D [21:16]
HOFF[5:0]
10_0000
determined by FMSTR[1:0] in the CNFG_GEN register.
(representing approximately ¼ second).
The R-to-R Hold Off qualification interval is
t
= MAX(t
, t
) (see below).
Hold_Off
Hold_Off_Min Hold_Off_Dyn
R-to-R Interval Averaging Weight Factor
This is the weighting factor for the current R-to-R interval observation vs. the past
interval observations when determining dynamic holdoff criteria. Lower numbers
weight current intervals more heavily.
D[13:12]
RAVG[1:0]
10
00 = 2
01 = 4
10 = 8 (default)
11 = 16
Interval_Average(n) = [Interval(n) + (RAVG-1) x Interval_Average(n-1)] / RAVG.
R-to-R Interval Hold Off Scaling Factor
This is the fraction of the R-to-R average interval used for the dynamic portion of the
holdoff criteria (t
).
HOLD_OFFDYN
D[10:8]
RHSF[2:0]
100
Values of 0/8 to 7/8 are selected by RTOR_RHSF[3:0]/8, default is 4/8.
If 000 (0/8) is selected, then no dynamic factor is used and the holdoff criteria is
determined by HOFF[5:0] only (see above).
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The write pointer is governed internally. To aide data
management and reduce µC overhead, the device pro-
FIFO Memory Description
The device provides read only FIFO memory for ECG,
BioZ, and PACE information. A single memory register
is also supported for heart rate detection output data
(R-to-R). The operation of these FIFO memories and reg-
isters is detailed in the following sections.
vides a user-programmable ECG FIFO Interrupt Threshold
(EFIT[4:0]) governing the ECG interrupt bit (EINT). This
threshold can be programmed with values from 1 to 32, rep-
resenting the number of unread ECG FIFO entries required
before the EINT bit will be asserted, alerting the µC that
there is a significant amount of data in the ECG FIFO ready
for read back (see MNGR_INT (0x04) for details).
Table 47 summarizes the method of access and data
structure within the FIFO memory.
ECG FIFO Memory (32 Words x 24 Bits)
The ECG FIFO memory is a standard circular FIFO con-
sisting of 32 words, each with 24 bits of information.
Do not read beyond the last valid FIFO word to prevent
possible data corruption.
If the write pointer ever traverses the entire FIFO array
and catches up to the read pointer (due to failure of the
µC to read/maintain FIFO data), a FIFO overflow will
occur and data will be corrupted. The EOVF STATUS
and tag bits will indicate this condition and the FIFO
should be cleared before continuing measurements using
either a SYNCH or FIFO_RST command—note overflow
events will result in the loss of samples and thus timing
information, so these conditions should not occur in well-
designed applications.
The ECG FIFO is independently managed by internal
read and write pointers. The read pointer is updated in
response to the 32nd SCLK rising edge in a normal mode
read back transaction and on the (32 + n x 24)th SCLK
rising edge(s) in a burst mode transaction where n = 0 to
up to 31. Once a FIFO sample is marked as read, it can-
not be accessed again.
Table 47. FIFO Memory Access and Data Structure Summary
DATA STRUCTURE (D[23:0])
FIFO
AND
REG
MODE
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
3
2
2
1
0
0
ECG
Burst
ETAG
[2:0]
PTAG
[2:0]
0x20
0x21
ECG Sample Voltage Data [17:0]
ETAG
[2:0]
PTAG
[2:0]
ECG
ECG Sample Voltage Data [17:0]
23 22 21 20 19 18 17 16 15 14 13 12 11 10
BioZ Sample Voltage Data [19:0]
4
3
1
BioZ
Burst
BTAG
[2:0]
0x22
0x23
0
BTAG
[2:0]
BioZ
BioZ Sample Voltage Data [19:0]
0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x25
RTOR
RTOR Interval Timing Data [13:0]
0
0
0
0
0
0
0
0
0
0
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and recommended handling within the continuous ECG
record.
ECG FIFO Data Structure
The data portion of the word contains the 18-bit ECG volt-
age information measured at the requested sample rate in
left justified two’s complement format. The remaining six
bits of data hold important data tagging information (see
details in Table 48 and Table 49).
VALID: ETAG = 000 indicates that ECG data for this
sample represents both a valid voltage and time step in
the ECG record.
FAST: ETAG = 001 indicates that ECG data for this
sample was taken in the FAST settling mode and that the
voltage information in the sample should be treated as
transient and invalid. Note that while the voltage data is
invalid, samples of this type do represent valid time steps
in the ECG record.
After converting the data portion of the sample to signed
magnitude format, the ECG input voltage is calculated by
the following equation:
17
V
(mV) = ADC x V
/ (2 x ECG_GAIN)
ECG
REF
where:
VALID EOF: ETAG = 010 indicates that ECG data for this
sample represents both a valid voltage and time step in
the ECG record, and that this is the last sample currently
available in the ECG FIFO (End-of-File, EOF). The µC
should wait until further samples are available before
requesting more data from the ECG FIFO.
ADC = ADC counts in signed magnitude format, V
=
REF
1000mV (typ) (refer to the Electrical Characteristics sec-
tion), and ECG_GAIN = 20V/V, 40V/V, 80V/V, or 160V/V,
set in CNFG_ECG (0x15).
ECG Data Tags (ETAG)
FAST EOF: ETAG = 011 indicates that ECG data for this
sample was taken in the FAST settling mode and that the
voltage information in the sample should be treated as
transient and invalid. Note that while the voltage data is
Three bits in the sample record are used as an ECG
data tag (ETAG[2:0] = D[5:3]). This section outlines the
meaning of the various data tags used in the ECG FIFO
Table 48. ECG FIFO - ECG Data Tags (ETAG[2:0] = D[5:3])
ETAG
[2:0]
DATA
VALID VALID
TIME
MEANING
DETAILED DESCRIPTION
RECOMMENDED USER ACTION
Log sample into ECG record and increment
the time step.
Continue to gather data from the ECG FIFO.
000
Valid Sample This is a valid FIFO sample.
Yes
No
Yes
Yes
This sample was taken while the ECG
Discard, note, or post-process this voltage
sample, but increment the time base.
Continue to gather data from the ECG FIFO.
Fast Mode
Sample
channel was in a FAST recovery mode.
The voltage information is not valid, but
the sample represents a valid time step.
001
010
011
Log sample into ECG record and increment
the time step.
Suspend read back operations on the ECG
FIFO until more samples are available.
This is a valid FIFO sample, but this is
the last sample currently available in
the FIFO (End of File indicator).
Last Valid
Sample (EOF)
Yes
No
Yes
Yes
See above (ETAG=001), but in addition, Discard, note, or post-process this voltage
Last Fast Mode
Sample
this is the last sample currently
available in the FIFO (End of File
indicator).
sample, but increment the time base.
Suspend read back operations on the ECG
FIFO until more samples are available.
(EOF)
10x
110
Unused
--
--
Discard this sample, without incrementing the
time base.
Suspend read back operations on this FIFO
until more samples are available.
This is an invalid sample provided in
response to an SPI request to read an
empty FIFO.
FIFO Empty
(Exception)
No
No
Issue a FIFO_RST command to clear the
FIFO Overflow The FIFO has been allowed to overflow FIFOs or re-SYNCH if necessary.
111
No
No
(Exception)
– the data is corrupted.
Note the corresponding halt and resumption
in ECG/BioZ time/voltage records.
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invalid, samples of this type do represent valid time steps
in the ECG record. In addition, this is the last sample cur-
rently available in the ECG FIFO (End-of-File, EOF). The
µC should wait until further samples are available before
requesting more data from the ECG FIFO.
Depending on the application, it may also be necessary
to resynchronize the MAX30001 internal channel opera-
tions to move forward with valid recordings, the SYNCH
command can perform this function while also resetting
the FIFO memories.
EMPTY: ETAG = 110 is appended to any requested read
back data from an empty ECG FIFO. The presence of this
tag alerts the user that this FIFO data does not represent
a valid sample or time step. Note that if handled properly
by the µC, an occurrence of an empty tag will not com-
promise the integrity of a continuous ECG record – this
tag only indicates that the read back request was either
premature or unnecessary.
ECG PACE Data Tag (PTAG)
The PACE FIFO data content is closely linked to ECG
FIFO content. If an ECG FIFO samples has related PACE
information, this is indicated by a three bit PACE tag
(PTAG[2:0] = D[2:0]) appended to and read back at the
end of the ECG FIFO sample.
A PACE tag (PTAG) value between 000 and 101 (inclu-
sive) indicates that a PACE event was detected during the
sample interval associated with and following the tagged
ECG sample. In these cases, PTAG stores a pointer to
the appropriate location within the PACE FIFO where
the relevant PACE information is stored (see PACE FIFO
Memory for more details). A PTAG value of 111 indicates
no PACE events were associated with the ECG Sample.
OVERFLOW: ETAG = 111 indicates that the ECG FIFO
has overflowed and that there are interruptions or missing
data in the sample records. The ECG Overflow (EOVF) bit
is also included in the STATUS register. A FIFO_RESET
is required to resolve this situation, effectively clearing
the FIFO so that valid sampling going forward is assured.
Table 49. ECG FIFO - PACE Data Tags (PTAG[2:0] = D[2:0])
PTAG [2:0]
DETAILED DESCRIPTION
PACE GROUP
RECOMMENDED USER ACTION
Associate PACE Group 0 data with this ECG data
sample. Follow ETAG recommended user actions.
000
PACE event detected
0
Associate PACE Group 1 data with this ECG data
sample. Follow ETAG recommended user actions.
PACE event detected
PACE event detected
PACE event detected
PACE event detected
1
2
3
4
001
010
Associate PACE Group 2 data with this ECG data
sample. Follow ETAG recommended user actions.
Associate PACE Group 3 data with this ECG data
sample. Follow ETAG recommended user actions.
011
100
Associate PACE Group 4 data with this ECG data
sample. Follow ETAG recommended user actions.
Associate PACE Group 5 data with this ECG data
sample. Follow ETAG recommended user actions.
101
110
111
PACE event detected
Unused
5
-
-
Associate PACE Group 0 with this ECG data sample.
Follow ETAG recommended user actions.
No PACE detected
-
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either a SYNCH or FIFO_RST command—note overflow
events will result in the loss of samples and thus timing
information, so these conditions should not occur in well-
designed applications.
BioZ FIFO Memory (8 Words x 24 Bits)
The BioZ FIFO memory is a standard circular FIFO con-
sisting of 8 words, each with 24 bits of information. The
BioZ FIFO is independently managed by internal read and
write pointers. The read pointer is updated in response
to the 32nd SCLK rising edge in a normal mode read
back transaction and on the (32 + n x 24)th SCLK rising
edge(s) in a burst mode transaction where n = 0 to up to
31. Once a FIFO sample is marked as read, it cannot be
accessed again.
Do not read beyond the last valid FIFO word to prevent
possible data corruption.
BioZ FIFO Data Structure
The data portion of the word contains the 20-bit BioZ volt-
age information measured at the requested sample rate
in left justified two’s complement format. One bit is set to
0 and the remaining three bits of data hold important data
tagging information (see details in Table 50).
The write pointer is governed internally. To aide data
management and reduce µC overhead, the device pro-
vides a user-programmable BioZ FIFO Interrupt Threshold
(BFIT[2:0]) governing the BioZ Interrupt bit (BINT). This
threshold can be programmed with values from 1 to 8, rep-
resenting the number of unread BioZ FIFO entries required
before the BINT bit will be asserted, alerting the µC that
there is a significant amount of data in the BioZ FIFO ready
for read back (see MNGR_INT (0x04) for details).
After converting the data portion of the sample to signed
magnitude format, BioZ is calculated by the following
equation:
19
BioZ (Ω) = ADC x V
/ (2 x BIOZ_CGMAG x
REF
BIOZ_GAIN)
where:
ADC = ADC counts in signed magnitude format, V
If the write pointer ever traverses the entire FIFO array
and catches up to the read pointer (due to failure of the
µC to read/maintain FIFO data), a FIFO overflow will
occur and data will be corrupted. The BOVF STATUS
and tag bits will indicate this condition and the FIFO
should be cleared before continuing measurements using
REF
= 1V (typ) (refer to the Electrical Characteristics sec-
-6
tion), BIOZ_CGMAG = 8 to 96 x 10 A, and BIOZ_GAIN
= 10V/V, 20V/V, 40V/V, or 80V/V. BIOZ_CGMAG and
BIOZ_GAIN are set in CNFG_BIOZ (0x18).
Table 50. BioZ FIFO BioZ Data Tags (BTAG[2:0] = D[2:0])
BTAG [2:0]
DESCRIPTION
RECOMMENDED USER ACTION
DATA VALID
TIME VALID
Log sample into BioZ record and increment the time
step. Continue to read data from the BioZ FIFO.
000
Valid Sample
Yes
Yes
Log sample into BioZ record and increment the time
step. Determine if the data is valid or a lead off
condition. Continue to read data from the BioZ FIFO.
Over/Under Range
Sample
001
010
?
Yes
Yes
Log sample into BioZ record and increment the time
step. Suspend read of the BioZ FIFO until more
samples are available.
Last Valid Sample
(EOF)
Yes
Log sample into BioZ record and increment the time
Last Over/Under Range step. Determine if the data is valid or a lead off
011
?
Yes
Sample (EOF)
condition. Suspend read of the BioZ FIFO until more
samples are available.
10x
110
Unused
-
-
-
Discard this sample without incrementing the time
base. Suspend read of the BioZ FIFO until more
samples are available.
FIFO Empty
(exception)
No
No
Discard this sample without incrementing the time
base. Issue a FIFO_RST command to clear the FIFOs
or re-SYNCH if necessary. Note the corresponding
halt and resumption in all the FIFOs.
FIFO Overflow
(exception)
111
No
No
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command can perform this function while also resetting
the FIFO memories.
BioZ Data Tags (BTAG)
The final three bits in the sample are used as a data tag
(BTAG[2:0] = D[2:0]) to assist in managing data transfers.
The BTAG structure used is detailed below.
R-to-R Interval Memory Register
(1 Word x 24 Bits)
VALID: BTAG = 000 indicates that BioZ data for this
sample represents both a valid voltage and time step in
the BioZ record.
The R-to-R Interval (RTOR) memory register is a single
read-only register consisting of 14 bits of timing interval
information, left justified (and 10 unused bits, set to zero).
OVER or UNDER RANGE: BTAG = 001 indicates that
BioZ data for this sample violated selected range thresh-
olds (see MNGR_DYN and CNFG_GEN) and that the
voltage information in the sample should be evaluated to
see if it is valid or indicative of a leads-off condition. Note
that while the voltage data may be invalid, samples of this
type do represent valid time steps in the BioZ record.
The RTOR register stores the time interval between the
last two R events, as identified by the R-to-R detection
circuitry, which operates on the ECG output data. Each
LSB in the RTOR register is approximately equal to 8ms
(CNFG_GEN for exact figures). The resulting 14-bit stor-
age interval can thus be approximately 130 seconds in
length, again depending on device settings.
VALID EOF: BTAG = 010 indicates that BioZ data for
this sample represents both a valid voltage and time
step in the BioZ record, and that this is the last sample
currently available in the BioZ FIFO (End-of-File, EOF).
The µC should wait until further samples are available
before requesting more data from the BioZ FIFO.
Each time the R-to-R detector identifies a new R event,
the RTOR register is updated, and the RRINT interrupt bit
is asserted (see STATUS register for details).
Users wishing to log heart rate based on RTOR register
data should set CLR_RRINT equals 01 in the MNGR_INT
register. This will clear the RRINT interrupt bit after the
RTOR register has been read back, preparing the device
for identification of the next R-to-R interval.
OVER or UNDER RANGE EOF: BTAG = 011 indicates
that BioZ data for this sample violated selected range
thresholds (see MNGR_DYN and CNFG_GEN) and that
the voltage information in the sample should be evaluated
to see if it is valid or indicates a leads-off condition. Note
that while the voltage data may be invalid, samples of
this type do represent valid time steps in the BioZ record.
This is also the last sample currently available in the BioZ
FIFO (End-of-File, EOF). The µC should wait until further
samples are available before requesting more data from
the BioZ FIFO.
Users wishing to log heart rate based on the time elapsed
between RRINT assertions using the µC to keep track of
the time base (and ignoring the RTOR register data) have
two choices for interrupt management. If CLR_RRINT
equals 00 in the MNGR_INT register, the RRINT inter-
rupt bit will clear after each STATUS register read back,
preparing the device for identification of the next R-to-R
interval. If CLR_RRINT equals 10 in the MNGR_INT reg-
ister, the RRINT interrupt bit will self-clear after each one
full ECG data cycle has passed, preparing the device for
identification of the next R-to-R interval (this mode is rec-
ommended only if using the INT2B as a dedicated heart
rate indicator).
EMPTY: BTAG = 110 is appended to any requested read
back data from an empty BioZ FIFO. The presence of this
tag alerts the user that this FIFO data does not represent
a valid sample or time step. Note that if handled properly
by the µC, an occurrence of an empty tag will not com-
promise the integrity of a continuous BioZ record – this
tag only indicates that the read back request was either
premature or unnecessary.
If CLR_RRINT = 0x (interrupt mode) and the R-to-R detec-
tor reaches an overflow state after several minutes without
detection of an R event, it will assert the RRINT term with
a RTOR register value = 0x3FFF, indicating the overflow
condition. This interrupt creates a time stamp, allowing
the µC to keep track of the time interval between detected
R events, even if the signal is lost for a prolonged amount
of time. This is important if the RTOR register data is the
sole source to keep track of the time base. In the event
of an overflow, the RTOR register will be reset after being
read back, allowing the µC to track multiple subsequent
overflow conditions. RRINT is reset independently of the
RTOR register by an appropriate read back operation as
specified by the setting of CLR_RRINT.
OVERFLOW: BTAG = 111 indicates that the BioZ FIFO
has overflowed and that there are interruptions or missing
data in the sample records. The BioZ Overflow (BOVF) bit
is also included in the STATUS register. A FIFO_RESET
is required to resolve this situation, effectively clearing
the FIFO so that valid sampling going forward is assured.
Depending on the application, it may also be necessary
to resynchronize the MAX30001 internal channel operations
to move forward with valid recordings, the SYNCH
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and Bioimpedance (BioZ) AFE
If CLR_RRINT = 1x (indicator mode) and the R-to-R
detector reaches an overflow state after several minutes
without detection of an R event, the counter will simply roll
over, and the lack of the RRINT activity on the dedicated
INT2B line will inform the µC that no R-to-R activity was
detected. Generating an interrupt to keep track of the
absolute time is not required in this case, as this mode will
be used in a system where the µC is used to keep track
of the time base.
by the pacemaker detection circuitry. Each pace regis-
ter group stores data for up to six pace edges detected
between two consecutive ECG data samples stored in the
ECG_FIFO register and are associated with the leading
ECG data sample. The PTAG[2:0] bits for the associated
ECG data sample indicate if one or more pace edges
were detected and which pace group it was written to.
Each pace register group is organized into three sub-
group registers denoted by an A, B, or C suffix that are
divided into two segments each holding pace edge data
for a total of 6 pace edges per group and a grand total of
36 pace edges in 18 registers.
PACE0 to PACE5 (0x30 to 0x47) Register
Groups
The PACE0 to PACE5 register groups are six read only
memories used to store pace edge information detected
Table 51. PACE0 to PACE5 (0x30 to 0x47) Register Map
REG
NAME
R/W 23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
0x30 PACE0_BURST
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Burst read of PACE0_A, PACE0_B & PACE0_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x31
0x32
0x33
PACE0_A
PACE0_B
PACE0_C
PACE0_0DATA[9:0]
PACE0_2DATA[9:0]
PACE0_4DATA[9:0]
P0_0RFB P0_0LST
P0_2RFB P0_2LST
P0_4RFB P0_4LST
PACE0_1DATA[9:0]
PACE0_3DATA[9:0]
PACE0_5DATA[9:0]
P0_1RFB P0_1LST
P0_3RFB P0_3LST
P0_5RFB P0_5LST
0x34 PACE1_BURST
Burst read of PACE1_A, PACE1_B & PACE1_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x35
0x36
0x37
PACE1_A
PACE1_B
PACE1_C
PACE1_0DATA[9:0]
PACE1_2DATA[9:0]
PACE1_4DATA[9:0]
P1_0RFB P1_0LST
P1_2RFB P1_2LST
P1_4RFB P1_4LST
PACE1_1DATA[9:0]
PACE1_3DATA[9:0]
PACE1_5DATA[9:0]
P1_1RFB P1_1LST
P1_3RFB P1_3LST
P1_5RFB P1_5LST
0x38 PACE2_BURST
Burst read of PACE2_A, PACE2_B & PACE2_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x39
0x3A
0x3B
PACE2_A
PACE2_B
PACE2_C
PACE2_0DATA[9:0]
PACE2_2DATA[9:0]
PACE2_4DATA[9:0]
P2_0RFB P2_0LST
P2_2RFB P2_2LST
P2_4RFB P2_4LST
PACE2_1DATA[9:0]
PACE2_3DATA[9:0]
PACE2_5DATA[9:0]
P2_1RFB P2_1LST
P2_3RFB P2_3LST
P2_5RFB P2_5LST
0x3C PACE3_BURST
Burst read of PACE3_A, PACE3_B & PACE3_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x3D
0x3E
0x3F
PACE3_A
PACE3_B
PACE3_C
PACE3_0DATA[9:0]
PACE3_2DATA[9:0]
PACE3_4DATA[9:0]
P3_0RFB P3_0LST
P3_2RFB P3_2LST
P3_4RFB P3_4LST
PACE3_1DATA[9:0]
PACE3_3DATA[9:0]
PACE3_5DATA[9:0]
P3_1RFB P3_1LST
P3_3RFB P3_3LST
P3_5RFB P3_5LST
0x40 PACE4_BURST
Burst read of PACE4_A, PACE4_B & PACE4_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x41
0x42
0x43
PACE4_A
PACE4_B
PACE4_C
PACE4_0DATA[9:0]
PACE4_2DATA[9:0]
PACE4_4DATA[9:0]
P4_0RFB P4_0LST
P4_2RFB P4_2LST
P4_4RFB P4_4LST
PACE4_1DATA[9:0]
PACE4_3DATA[9:0]
PACE4_5DATA[9:0]
P4_1RFB P4_1LST
P4_3RFB P4_3LST
P4_5RFB P4_5LST
0x44 PACE5_BURST
Burst read of PACE5_A, PACE5_B & PACE5_C registers (80-bit frame: 8-bit command + 3*24-bit data)
0x45
0x46
0x47
PACE5_A
PACE5_B
PACE5_C
PACE5_0DATA[9:0]
PACE5_2DATA[9:0]
PACE5_4DATA[9:0]
P5_0RFB P5_0LST
P5_2RFB P5_2LST
P5_4RFB P5_4LST
PACE5_1DATA[9:0]
PACE5_3DATA[9:0]
PACE5_5DATA[9:0]
P5_1RFB P5_1LST
P5_3RFB P5_3LST
P5_5RFB P5_5LST
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and Bioimpedance (BioZ) AFE
The pace register groups are written sequentially in time
as groups of pace edges are found between ECG data
samples starting with PACE0 and written in a circular
fashion such that after PACE5 is written then PACE0
will be the next group written. Within each pace group,
the data for each pace edge is also written sequentially
in time by segment starting with edge 0 but is not writ-
ten in a circular fashion such that only the first six pace
edges between ECG data samples is written to each pace
group. If there are more than six edges in a pace group
then this data will not be stored and will be lost. A sub-
group register written with data for either one or two pace
edges is marked as unread and if just the first segment
is written then the second segment will be set to 0xFFF.
A sub-group register not written with any pace edge data
will be set to 0xFFF FFF and marked as read. All unread
subgroups need to be read in order for the pace group to
be marked as read. A register is marked as read on the
32nd SCLK rising edge in a normal (single word) mode
read. There are burst mode registers for each pace regis-
ter group in order to read all three sub-groups (A, B, and
C) during the same serial data transfer. During the burst
mode, the sub-groups are marked as read on the 32nd,
56th, and 80th SCLK rising edges for sub-groups A, B,
and C, respectively. Burst mode cycles beyond the 80th
SCLK edge will not continue read back with the next pace
register group; instead the data returned will read 0xFFF.
Whenever a set of pace edges are detected between
ECG data samples, the pace Interrupt bit (PINT) is assert-
ed, alerting the µC that there is new pace data ready for
read back. The µC should first read back the ECG FIFO
data to the point where the PTAG’d samples are identi-
fied, and then read back the linked PACE register group,
ensuring the pace events are associated with the correct
ECG data samples. Examples are provided below. If new
pace edge information is written to a previously written
and unread PACE register group then the pace overflow
status bit, POVR will be asserted and the association with
the ECG data sample will be corrupted. In the event that
the data is corrupted then either a SYNCH or FIFO_RST
command should be executed to restore synchronization
between the ECG data samples and the PACE register
groups.
Table 52. PACE0 to PACE5 (0x30 to 0x47) Register Functionality
INDEX
NAME
DEFAULT
FUNCTION
Pace Edge Timing Data
Pace Edge Timing = PACEx_yDATA[9:0]*t
where t
= 1/(2*f
) and is
RES
RES
MSTR
set by the FMSTR[1:0] bits in the CNFG_GEN register. The time is relative to the
associated ECG data sample.
x = 0 to 5 and is the pace group associated with a specific ECG data output
sample.
D[23:14],
D[11:2]
PACEx_yDATA[9:0]
0x3FF
y = 0 to 5 and is the numbered order of the pace edges detected in time.
Pace Edge Polarity
0 = Falling Edge
D[13],
D[1]
1 = Rising Edge
Px_yRFB
Px_yLST
1
1
x = 0 to 5 and is the pace group associated with a specific ECG data output
sample.
y = 0 to 5 and is the numbered order of the pace edges detected in time.
Last Pace Edge
0 = Additional pace edges detected in the group
1 = Last pace edge detected in the group or an empty record.
x = 0 to 5 and is the pace group associated with a specific ECG data output
sample.
D[12],
D[0]
y = 0 to 5 and is the numbered order of the pace edges detected in time.
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Table 53 shows the internal state of the ECG FIFO for pur-
poses of these examples. The example assumes informa-
tion in locations 0-7 were previously read back (indicated
by Y in the READ column) and that data in locations 16
and beyond was either previously read back or empty
(indicated by <Y> in the READ column).
ECG and PACE Data Management Examples
and Use Cases
The figures and examples below illustrate several valid
means of managing an example set of ECG FIFO and
PACE register group data. Data for use in the examples
is given in the tables below.
Table 53. ECG FIFO Example
ECG FIFO DATA D[23:0]
ECG_DATA[17:0]
18 17 16 15 14 13 12 11 10
READ INDEX
ETAG[2:0] PTAG[2:0]
23 22 21 20
19
9
8
7
6
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
-
3
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
0
1
ECG Sample 00 Voltage Data [17:0] = 0x000
ECG Sample 01 Voltage Data [17:0] = 0x001
ECG Sample 02 Voltage Data [17:0] = 0x002
ECG Sample 03 Voltage Data [17:0] = 0x003
ECG Sample 04 Voltage Data [17:0] = 0x004
ECG Sample 05 Voltage Data [17:0] = 0x005
ECG Sample 06 Voltage Data [17:0] = 0x006
ECG Sample 07 Voltage Data [17:0] = 0x007
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00B
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
EMPTY
-
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
<Y>
<Y>
EMPTY
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and Bioimpedance (BioZ) AFE
Table 54 shows the internal state of the first four groups in
the PACE register group for purposes of these examples.
The example assumes information in group 0 was previ-
ously read back (indicated by Y in the READ column), that
unused words in active groups 1 and 2 were internally
marked as read (indicated by <Y> in the READ column),
and that the empty groups 3, 4, and 5 are also internally
marked as read and filled with default data.
Table 54. PACE FIFO Example
PACE DATA D[23:0]
READ INDEX
Edge Timing Data Segment [9:0]
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
23 22 21 20 19 18 17 16 15
14
13
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y
Y
Y
0A
0B
0C
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
5A
5B
5C
Group 0: Edge 0 Timing Data [9:0] = 0x000
Group 0: Edge 2 Timing Data [9:0] = 0x022
Group 0: Edge 4 Timing Data [9:0] = 0x3FF
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 1: Edge 4 Timing Data [9:0] = 0x3FF
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
Group 2: Edge 2 Timing Data [9:0] = 0x3FF
Group 2: Edge 4 Timing Data [9:0] = 0x3FF
Group 3: Edge 0 Timing Data [9:0] = 0x3FF
Group 3: Edge 2 Timing Data [9:0] = 0x3FF
Group 3: Edge 4 Timing Data [9:0] = 0x3FF
Group 4: Edge 0 Timing Data [9:0] = 0x3FF
Group 4: Edge 2 Timing Data [9:0] = 0x3FF
Group 4: Edge 4 Timing Data [9:0] = 0x3FF
Group 5: Edge 0 Timing Data [9:0] = 0x3FF
Group 5: Edge 2 Timing Data [9:0] = 0x3FF
Group 5: Edge 4 Timing Data [9:0] = 0x3FF
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Group 0: Edge 1 Timing Data [9:0] = 0x011
Group 0: Edge 3 Timing Data [9:0] = 0x033
Group 0: Edge 5 Timing Data [9:0] = 0x3FF
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 1: Edge 5 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
Group 2: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 5 Timing Data [9:0] = 0x3FF
Group 3: Edge 1 Timing Data [9:0] = 0x3FF
Group 3: Edge 3 Timing Data [9:0] = 0x3FF
Group 3: Edge 5 Timing Data [9:0] = 0x3FF
Group 4: Edge 1 Timing Data [9:0] = 0x3FF
Group 4: Edge 3 Timing Data [9:0] = 0x3FF
Group 4: Edge 5 Timing Data [9:0] = 0x3FF
Group 5: Edge 1 Timing Data [9:0] = 0x3FF
Group 5: Edge 3 Timing Data [9:0] = 0x3FF
Group 5: Edge 5 Timing Data [9:0] = 0x3FF
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
<Y>
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and Bioimpedance (BioZ) AFE
ECG Interrupt Driven Normal Mode Example
In this example, the µC reads back ECG and pace data in response to EINT being asserted and interrupting the µC via
INTB or INT2B and that EFIT=8. For the samples given, the following SPI transactions might result:
The example below will read back complete and correct results but better use could be made of the ECG ETAG and pace
information to realize more efficient µC communications.
Table 55. ECG FIFO and PACE Register Read Back Example (EINT, Normal Mode)
FIFO DATA D[23:0]
CMD
FIFO INDEX 23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
8
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00B
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
ECG Empty Voltage Data [17:0] = 0x000
0
0
0
0
0
0
0
0
1
1
4
0
1
1
0
0
1
1
1
1
1
2
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
9
0
0
0
0
0
0
0
1
5
0
0
0
0
0
0
0
0
3
10
11
12
13
14
15
--
23 22 21 20 19 18 17 16 15 14
Edge Timing Data Segment [9:0]
13
12
11 10
9
8
7
6
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x35 PACE
0x36 PACE
0x37 PACE
0x39 PACE
0x3A PACE
0x3B PACE
1A
1B
1C
2A
2B
2C
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 1: Edge 4 Timing Data [9:0] = 0x3FF
Group 2: Edge 0 Timing Data [9:0] = 0x3FF
Group 2: Edge 2 Timing Data [9:0] = 0x3FF
Group 2: Edge 4 Timing Data [9:0] = 0x3FF
1
1
1
0
1
1
0
1
1
1
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 1: Edge 5 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
Group 2: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 5 Timing Data [9:0] = 0x3FF
0
1
1
1
1
1
0
1
1
1
1
1
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and Bioimpedance (BioZ) AFE
The example transactions below will read back identical results, but µC communication efficiency is improved by only
reading back necessary locations, as indicated by the ECG ETAG and PACE LST bits.
Table 56. ECG FIFO and PACE Register Read Back Example (EINT, Normal Mode,
Reduced Transactions)
FIFO DATA D[23:0]
CMD FIFO INDEX
23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
8
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00C
ECG Sample 12 Voltage Data [17:0] = 0x00D
ECG Sample 13 Voltage Data [17:0] = 0x00E
ECG Sample 14 Voltage Data [17:0] = 0x00F
ECG Sample 15 Voltage Data [17:0] = 0x00F
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
1
4
0
0
0
0
0
0
0
0
3
1
1
0
0
1
1
1
1
2
1
1
0
1
1
1
1
1
1
1
9
1
1
0
1
1
1
1
0
10
11
12
13
14
15
23 22 21 20 19 18 17 16 15 14
Edge Timing Data Segment [9:0]
13
12
11 10
9
8
7
6
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x35 PACE
0x36 PACE
0x39 PACE
1A
1B
2A
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
1
1
0
0
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
0
1
1
0
1
1
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and Bioimpedance (BioZ) AFE
PACE Interrupt Driven Normal Mode Example
In this example, the µC reads back data in response to PINT, which will be asserted in response to the two detected
pace events (before EINT will be issued since the EFIT=8 threshold is not met). Note the ECG information should still
be read first in order to properly locate the pace events in time. For the samples given, the following SPI transactions
might result (note: other combinations of ETAGs are possible depending on the state of the ECG FIFO when the PINT
interrupts were serviced).
Table 57. ECG FIFO and PACE Register Read Back Example (PINT, Normal Mode)
FIFO DATA D[23:0]
REG
FIFO
INDEX
23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
ECG
ECG
ECG
8
9
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
10
Edge Timing Data Segment [9:0]
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x35
0x36
0x37
PACE
PACE
PACE
1A
1B
1C
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 1: Edge 4 Timing Data [9:0] = 0x3FF
1
1
1
0
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 1: Edge 5 Timing Data [9:0] = 0x3FF
ETAG[2:0]
0
1
1
0
1
1
ECG Sample Voltage Data [17:0]
ECG Sample 11 Voltage Data [17:0] = 0x00B
Edge Timing Data Segment [9:0] RFB LST
PTAG[2:0]
0x21
ECG
11
0
0
0
0
1
0
Edge Timing Data Segment [9:0]
RFB LST
0x39
PACE
2A
2B
2C
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
Group 2: Edge 2 Timing Data [9:0] = 0x3FF
Group 2: Edge 4 Timing Data [9:0] = 0x3FF
0
1
1
1
1
1
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
Group 2: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 5 Timing Data [9:0] = 0x3FF
ETAG[2:0]
1
1
1
1
1
1
0x3A PACE
0x3B PACE
ECG Sample Voltage Data [17:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
ECG
12
13
14
15
--
ECG Sample 12 Voltage Data [17:0] = 0x00D
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
ECG Empty Voltage Data [17:0] = 0x000
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
In the example above, the µC will read back complete and correct results but better use could be made of the ECG ETAG
and pace information to realize more efficient µC communications as shown below.
The example transactions above will read back identical results, but the efficiency is improved by only reading back loca-
tions indicated by the ECG ETAG and PACE LST bits.
Table 58. ECG FIFO and PACE Register Read Back Example (PINT, Normal Mode,
Reduced Transactions)
FIFO DATA D[23:0]
REG FIFO INDEX
23 22 21 20 19 18 17 16 15 14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
ECG
ECG
ECG
8
9
0
0
0
0
0
1
1
0
1
1
0
1
1
1
0
0
0
0
10
Edge Timing Data Segment [9:0]
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x35 PACE
0x36 PACE
1A
1B
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
1
1
0
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
ETAG[2:0]
0
0
1
1
ECG Sample Voltage Data [17:0]
PTAG[2:0]
0x21
ECG
11
ECG Sample 11 Voltage Data [17:0] = 0x00B
0
0
0
0
1
0
Edge Timing Data Segment [9:0]
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x39 PACE
2A
0
1
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
1
1
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
12
13
14
15
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Burst Mode Example
In this example, the µC reads data in response to the EINT bit and that EFIT = 8. For the samples given, the following
Burst Mode SPI transactions might result.
The example burst mode transactions below will read back complete and correct results. Note that to achieve this read
back in burst mode only three commands are issued: ECG Burst 8 + (9 x 24) SCLK cycles, PACE Group 1 Burst 8 +
(3 x 24) SCLK cycles, and PACE Group 2 Burst 8 + (3 x 24) SCLK cycles; however, better use could be made of the
ECG ETAG and pace information to realize more efficient µC communications.
Table 59. ECG FIFO and PACE Register Read Back Example (EINT, Burst Mode)
FIFO DATA D[23:0]
REG FIFO INDEX
23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x20
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
8
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00B
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
ECG Empty Voltage Data [17:0] = 0x000
0
0
0
0
0
0
0
0
1
5
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
3
1
1
0
0
1
1
1
1
1
2
1
1
0
1
1
1
1
1
1
1
1
9
1
1
0
1
1
1
1
1
0
10
11
12
13
14
15
--
23 22 21 20 19 18 17 16 15 14
Edge Timing Data Segment [9:0]
13
12
11 10
9
8
7
6
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x34 PACE
PACE
1A
1B
1C
2A
2B
2C
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 1: Edge 4 Timing Data [9:0] = 0x3FF
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
Group 2: Edge 2 Timing Data [9:0] = 0x3FF
Group 2: Edge 4 Timing Data [9:0] = 0x3FF
1
1
1
0
1
1
0
1
1
1
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 1: Edge 5 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
Group 2: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 5 Timing Data [9:0] = 0x3FF
0
1
1
1
1
1
0
1
1
1
1
1
PACE
0x38 PACE
PACE
PACE
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
The example burst mode transactions below will read back identical results, but the efficiency is improved by only read-
ing back locations indicated by the ECG ETAG and PACE LST bits. To achieve this read back in burst mode only three
commands are issued: ECG Burst 8 + (8 x 24) SCLK cycles, PACE Group 1 Burst 8 + (2 x 24) SCLK cycles, and PACE
Group 2 Burst 8 + 24 SCLK cycles.
Table 60. ECG FIFO and PACE Register Read Back Example (EINT, Burst Mode,
Reduced Transactions)
FIFO DATA (D[23:0])
REG
FIFO INDEX
23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x20
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
8
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00B
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
1
4
0
0
0
0
0
0
0
0
3
1
1
0
0
1
1
1
1
2
1
1
0
1
1
1
1
1
1
1
9
1
1
0
1
1
1
1
0
10
11
12
13
14
15
23 22 21 20 19 18 17 16 15 14
Edge Timing Data Segment [9:0]
13
12
11 10
9
8
7
6
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x34 PACE
PACE
1A
1B
2A
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
1
1
0
0
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
0
1
1
0
1
1
0x38 PACE
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Resulting Data Record Example
In this example, the µC reads data in response to EINT and that EFIT=8. For the complete FIFO samples given
and the resulting two interrupts, the following SPI transactions might have resulted (starting from the beginning of the
FIFO record).
Table 61. Complete Read Back Example (EINT, Normal Mode)
FIFO DATA (D[23:0])
REG
FIFO INDEX
23 22 21 20 19 18 17 16 15 14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
ECG Sample Voltage Data [17:0]
ETAG[2:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
0
1
2
3
4
5
6
7
--
ECG Sample 00 Voltage Data [17:0] = 0x000
ECG Sample 01 Voltage Data [17:0] = 0x001
ECG Sample 02 Voltage Data [17:0] = 0x002
ECG Sample 03 Voltage Data [17:0] = 0x003
ECG Sample 04 Voltage Data [17:0] = 0x004
ECG Sample 05 Voltage Data [17:0] = 0x005
ECG Sample 06 Voltage Data [17:0] = 0x006
ECG Sample 07 Voltage Data [17:0] = 0x007
ECG Empty Voltage Data [17:0] = 0x000
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
Edge Timing Data Segment [9:0]
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x31 PACE
0x32 PACE
0x33 PACE
0A
0B
0C
Group 0: Edge 0 Timing Data [9:0] = 0x000
Group 0: Edge 2 Timing Data [9:0] = 0x022
Group 0: Edge 4 Timing Data [9:0] = 0x3FF
1
1
1
0
0
1
Group 0: Edge 1 Timing Data [9:0] = 0x011
Group 0: Edge 3 Timing Data [9:0] = 0x033
Group 0: Edge 5 Timing Data [9:0] = 0x3FF
ETAG[2:0]
0
0
1
0
1
1
ECG Sample Voltage Data [17:0]
PTAG[2:0]
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
0x21
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
ECG
8
ECG Sample 08 Voltage Data [17:0] = 0x008
ECG Sample 09 Voltage Data [17:0] = 0x009
ECG Sample 10 Voltage Data [17:0] = 0x00A
ECG Sample 11 Voltage Data [17:0] = 0x00B
ECG Sample 12 Voltage Data [17:0] = 0x00C
ECG Sample 13 Voltage Data [17:0] = 0x00D
ECG Sample 14 Voltage Data [17:0] = 0x00E
ECG Sample 15 Voltage Data [17:0] = 0x00F
ECG Empty Voltage Data [17:0] = 0x000
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
9
1
1
0
1
1
1
1
1
10
11
12
13
14
15
--
Edge Timing Data Segment [9:0]
RFB LST
Edge Timing Data Segment [9:0]
RFB LST
0x35 PACE
0x36 PACE
0x37 PACE
0x39 PACE
0x3A PACE
0x3B PACE
1A
1B
1C
2A
2B
2C
Group 1: Edge 0 Timing Data [9:0] = 0x100
Group 1: Edge 2 Timing Data [9:0] = 0x110
Group 1: Edge 4 Timing Data [9:0] = 0x3FF
Group 2: Edge 0 Timing Data [9:0] = 0x0A0
Group 2: Edge 2 Timing Data [9:0] = 0x3FF
Group 2: Edge 4 Timing Data [9:0] = 0x3FF
1
1
1
0
1
1
0
1
1
1
1
1
Group 1: Edge 1 Timing Data [9:0] = 0x108
Group 1: Edge 3 Timing Data [9:0] = 0x3FF
Group 1: Edge 5 Timing Data [9:0] = 0x3FF
Group 2: Edge 1 Timing Data [9:0] = 0x3FF
Group 2: Edge 3 Timing Data [9:0] = 0x3FF
Group 2: Edge 5 Timing Data [9:0] = 0x3FF
0
1
1
1
1
1
0
1
1
1
1
1
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
The µC must now prepare a complete record of the ECG
waveform given the data observed thus far. All empty
samples, which do not represent valid ECG time steps
or valid pace edges, will be filtered out. Then the pace
edges will be interleaved within the appropriate ECG
sample intervals. For purposes of this example, assume
FMSTR[1:0] = 01 and ECG_RATE[1:0] = 10 (in CNFG_
GEN and CNFG_ECG registers, respectively), thus:
F
= 125sps
ECG
T
= 1/F
= 8ms
ECG
F
ECG
= 64,000Hz
PACE
PACE_RES = 1/ F
= 15.625µs
PACE
Table 62. Example Post-Processed ECG and PACE Record
TIME
(ms)
VOLTAGE
(LSBs)
F*
C**
P***
NOTE
0.000
8.000
0x000
0x001
0x002
0x003
0x004
●
●
FAST mode engaged – ECG voltage may be invalid
FAST mode engaged – ECG voltage may be invalid
16.000
24.000
32.000
Pace edge(s) detected during current sample interval - ECG voltage might be
impacted
40.000
0x005
●
40.000
40.266
40.531
40.797
↑
↓
↑
↓
Pace rising edge detected ( 0*15.625µs = 0.000ms delayed)
Pace falling edge detected (17*15.625µs = 0.256ms delayed)
Pace rising edge detected (34*15.625µs = 0.531ms delayed)
Pace falling edge detected (51*15.625µs = 0.797ms delayed)
Pace edge(s) detected during preceding sample interval - ECG voltage might
be impacted
48.000
0x006
●
●
56.000
64.000
72.000
0x007
0x008
0x009
Pace edge(s) detected during current sample interval - ECG voltage might be
impacted
80.000
0x00A
84.000
84.125
84.250
↑
↓
↑
Pace rising edge detected (256*15.625µs = 4.000ms delayed)
Pace falling edge detected (264*15.625µs = 4.125ms delayed)
Pace rising edge detected (272*15.625µs = 4.250ms delayed)
Pace edge(s) detected during preceding & current sample interval - ECG
voltage might be impacted
88.000
90.500
96.000
0x00B
0x00C
●
●
↓
Pace falling edge detected (160*15.625µs = 2.500ms delayed)
Pace edge(s) detected during preceding sample interval - ECG voltage might
be impacted
104.000
112.000
0x00D
0x00E
0x00F
120.000
*F = Fast mode
**C = Sample corrupted by Pace activity
***P = Pace edge
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Body Bias Electrode
Applications Information
Compliance with the common mode input range of the
ECG and BioZ channels is achieved by using internal
lead bias or by adding a third electrode to drive the body
External Filters
External filters are recommended in environments with
high levels of EMI to improve noise rejection on the inputs.
Select corner frequencies according to the requirements
of the channel. The typical application circuits in Figure
17 show examples of input filters, but component values
must be modified according to application requirements.
to V . The body bias drive electrode improves perfor-
CM
mance in applications with high electrode impedance or
high 50Hz/60Hz coupling. Using V
drive also improves
CM
the input impedance because internal lead bias is dis-
abled.
The differential ECG signal occupies frequencies from
about 0.05Hz to 200Hz. For applications that require less
detail such as fitness monitors, the corner frequency can
be lowered to about 40Hz, trading noise immunity for
ECG detail. Place the common mode corner frequency
about a decade below the AM radio band (535kHz).
IEC 60601-2-47 Compliance
IEC 60601-2-47:2012 concerns the basic safe-
ty and essential performance of AMBULATORY
ELECTROCARDIOGRAPHIC SYSTEMS and the
MAX30001 can be used in such systems and be compli-
ant. The MAX30001 has been tested according to the
clauses and subclauses that pertain to the analog front
end and A/D conversion portions of such systems. With
proper system design, a system including the MAX30001
can be certified to the standard.
The BioZ filter depends on the drive frequency used in the
application. Place the differential mode corner frequency
several decades higher than the maximum drive frequen-
cy. Place the common mode corner frequency higher than
the differential mode corner frequency, but lower than the
AM radio band.
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Application Circuits
1.65V TO
3.6V
10µF
1.1V TO 2.0V
10µF
0.1µF
0.1µF
0.1µF
AVDD
DVDD
OVDD
47nF
DRVP
AOUT
ECGP
CAPP
CAPN
ECGN
200kΩ
10pF
CSB
SDI
CSB
2nF
1µF
MOSI
SCLK
MISO
INTB
10pF
200kΩ
SCLK
SDO
MAX30001
MCU
ELECTRODES
BIP
INTB
INT2B
FCLK
200Ω
200Ω
10pF
10pF
INT2B
FCLK
47pF
BIN
RBIAS
CPLL
324kΩ
DRVN
47nF
1nF
DGND
V
V
REF
AGND
BG
V
CM
OPTIONAL BODY BIAS DRIVE
200k
1µF
10µF
10µF
Figure 17a. Two-Electrode ECG and Respiration Monitor Typical Application Circuit
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Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Typical Application Circuits (continued)
1.1V TO 2.0V
1.65V TO 3.6V
10µF
0.1µF
0.1µF
0.1µF
10µF
AVDD
DVDD
OVDD
47nF
DRVP
AOUT
ECGP
CAPP
CAPN
ECGN
200kΩ
200kΩ
10pF
10pF
CSB
SDI
CSB
2nF
1µF
MOSI
SCLK
MISO
INTB
SCLK
SDO
ELECTRODES
MCU
MAX30001
BIP
INTB
INT2B
FCLK
200Ω
200Ω
10pF
10pF
INT2B
FCLK
47pF
47nF
BIN
RBIAS
CPLL
324kΩ
DRVN
1nF
DGND
V
V
REF
AGND
BG
V
CM
OPTIONAL BODY BIAS DRIVE
200k
1µF
10µF
10µF
Figure 17b. Four-Electrode ECG and Respiration Monitor Typical Application Circuit
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Four Electrode ECG and Respiration
Monitoring Application
See Figure 19 for an example of a clinical application for
monitoring ECG and respiration using four electrodes
and with optional defibrillation protection circuitry. The
electrode models are shown to illustrate the electrical
characteristics of the physical electrodes.
Application Diagrams
See Figure 18 for an example of a clinical application for
monitoring ECG and respiration using just two electrodes
and with optional shared defibrillation protection circuitry.
The electrode models are shown to illustrate the electrical
characteristics of the physical electrodes.
PCB
DRVP
ECGP
CAPP
CAPN
ECGN
OPTIONAL
DEFIB
PROTECTION
PHYSICAL
ELECTRODES
R
BODY
ELECTRODE MODELS
EXTERNAL EMI FILTERS
MAX30001
BIP
BIN
DRVN
Figure 18. Two Electrode ECG and Respiration Monitoring with Optional Common Defibrillation Protection.
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
PCB
DRVP
ECGP
CAPP
CAPN
ECGN
OPTIONAL
DEFIB
PROTECTION
PHYSICAL
ELECTRODES
ELECTRODE MODELS
EXTERNAL EMI FILTERS
MAX30001
R
BODY
BIP
BIN
DRVN
Figure 19. Four Electrode ECG and Respiration Monitoring with Optional Defibrillation Protection.
Maxim Integrated
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX30001CWV+
MAX30001CWV+T
0°C TO +70°C
0°C TO +70°C
30 WLP
30 WLP
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Chip Information
PROCESS: CMOS
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MAX30001
Ultra-Low-Power, Single-Channel Integrated
Biopotential (ECG, R-to-R, and Pace Detection)
and Bioimpedance (BioZ) AFE
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
8/17
Initial release
—
9/17
Added figures and updated tables
1–86
Updated the General Description, Benefits and Features, Absolute Maximum
Ratings, Package Information, Electrical Characteristics, Pin Configuration, Pin
Description, ECG Channel, EMI Filtering and ESD Protection, DC Leads-Off
Detection and ULP Leads-On Detection, Lead Bias, Gain Settings, Input Range,
and Filtering, Fast Recovery, Decimation Filter, BioZ Channel, EMI Filtering
and ESD Protection, Leads-Off Detection and ULP Leads-On Detection, Lead
Bias, Programmable Resistive Load, Current Generator, Current Selection and
Resolution Calculation Example 1 (Two Terminal with Common Protection), Current
Selection and Resolution Calculation Example 2 (Four Terminal), Reference and
Common Mode Buffer, Table 11, Table 14, Table 19 to Table 21, CNFG_GEN
(0x10), Table 32, Table 33, ECG FIFO Data Structure, BioZ FIFO Data Structure,
Table 62, and Ordering Information sections; replaced the Functional Diagram,
Figure 1a, TOC10-TOC12, TOC17, TOC27, TOC28, TOC34-TOC35, TOC38,
Figure 3, Figure 9, Figure 17a, Figure 17b; added the Converting ECG Samples
to Voltage, Converting BioZ Samples to Ohms (use symbol), and Application
Information section; corrected typos through for subscripting and consistency of
symbols
1-8, 10-11, 13-16,
18-22, 24-26, 28-34,
41, 43, 46-47, 53,
65, 67, 80-83, 86
2
8/19
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 87
相关型号:
MAX30001_V01
Ultra-Low-Power, Single-Channel Integrated Biopotential (ECG, R-to-R, and Pace Detection) and Bioimpedance (BioZ) AFE
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