MAX30002CWV+T_技术文档

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

General Description

Beneﬁts and Features

● BioZ AFE with High Resolution Data Converter

The MAX30002 is a complete bioimpedance (BioZ),

analog front-end (AFE) solution for wearable applications.

It offers high performance for clinical and fitness

applications, with ultra-low-power for long battery life. The

MAX30002 is a single bioimpedance channel capable of

measuring respiration.

• 17 Bits ENOB with 1.1µV Noise for BioZ

P-P

● High AC Dynamic Range of 90mV

Will Help

P-P

Prevent Saturation in the Presence of Motion/Direct

Electrode Hits

● Longer Battery Life Compared to Competing Solutions

The bioimpedance channel has ESD protection, EMI

filtering, internal lead biasing, DC leads-off detection,

ultra-low-power leads-on detection during standby mode,

and a programmable resistive load for built-in self-test.

Soft power-up sequencing ensures no large transients

are injected into the electrodes. The channel also has

high input impedance, low noise, high CMRR, program-

mable gain, various low-pass and high-pass filter options,

and a high resolution analog-to-digital converter. The

bioimpedance channel includes integrated programmable

current drive, works with common electrodes, and has the

flexibility for 2 or 4 electrode measurements. It also has

AC lead off detection.

• 158µW at 1.1V Supply Voltage

● Leads-On Interrupt Feature Allows to Keep µC in

Deep Sleep Mode Until Valid Lead Condition is

Detected

• Lead-On Detect Current: 0.63µA (typ)

● High Accuracy Allows for More Physiological Data

Extractions

● 8-Word FIFO Allows the MCU to Stay Powered Down

for 256ms with Full Data Acquisition

● High-Speed SPI Interface

● Shutdown Current of 0.58µA (typ)

The MAX30002 is available in a 28-pin TQFN and

30-bump wafer-level package (WLP), operating over the

0°C to +70°C commercial temperature range.

Ordering Information appears at end of data sheet.

Applications

● Single-Lead Wireless Patches for

In-Patient/Out-Patient Monitoring

● Respiration and Hydration Monitors

● Impedance Based Heart Rate Detection

19-100289; Rev 0, 3/18

MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Functional Diagram

AV DD

DVDD

OV DD

MAX30002

BIOIMPEDANCE CHANNEL

CSB

SDI

HPF

AAF

BIP

ESD, EMI,

INPUT MUX,

DC LEAD

CHECK

20-BIT

INPUT

AMP

20-BIT

ΣΔ ADC

DECIMATION

FIL TE R

f_-3dB

PGA

BIN

=600Hz

SCLK

SDO

SPI INTERFACE,

FIFO,

AND

REGISTERS

-20dB/dec

-40dB/dec

CLOCK

DIVI DE R

w/ PHASE

ADJUST

SELECTABLE PHASE

INTB

DRV P

DRV N

PUSH/PULL

CURRENT

SOURCE

INT2B

SUPPORT CIRCUITRY

COMMO N-MODE

BUFFER

REFERENCE

BUFFER

f_CLK

f_HFC

FCLK

SEQUENCER

BANDGAP

BIASING

PLL

AG ND

VCM

VBG

VREF

RBIAS

CPLL

DGND

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Absolute Maximum Ratings

AVDD to AGND ....................................................-0.3V to +2.0V

DVDD to DGND....................................................-0.3V to +2.0V

AVDD to DVDD ....................................................-0.3V to +0.3V

OVDD to DGND ...................................................-0.3V to +3.6V

AGND to DGND ...................................................-0.3V to +0.3V

CSB, SCLK, SDI, FCLK to DGND .......................-0.3V to +3.6V

SDO, INTB, INT2B

to DGND........ -0.3V to the lower of (3.6V and OVDD + 0.3V)

All Other Pins

to AGND ......... -0.3V to the lower of (2.0V and AVDD + 0.3V)

Maximum Current into Any Pin.........................................±50mA

Continuous Power Dissipation (T = +70ºC)

A

28-Pin TQFN

(derate 34.5mW/ºC above +70ºC)..........................2758.6mW

30-Bump WLP

(derate 24.3mW/ºC above +70ºC)..........................1945.5mW

Operating Temperature Range...............................0ºC to +70°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -65°C to +150°C

Lead Temperature (Soldering, 10sec).............................+300°C

Soldering Temperature (reflow).......................................+260°C

(Note 1)

Package Thermal Characteristics

TQFN

WLP

Junction-to-Ambient Thermal Resistance (θ ) ..........29°C/W

Junction-to-Ambient Thermal Resistance (θ ) ..........44°C/W

JA

Junction-to-Case Thermal Resistance (θ ).................2°C/W

JC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, LN_BIOZ = 1, T = T

to T

, unless otherwise

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

noted. Typical values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

BIOIMPEDANCE (BIOZ) CHANNEL

Signal Generator Resolution

Square wave generator

1

Bits

DRVP/N Injected Full-Scale

Current

Programmable, see Register Map

8 to 96

μA

P-P

Internal bias resistor

-30

-10

+30

+10

DRVP/N Injected Current

Accuracy

%

External bias resistor (0.1%, 10ppm, 324kΩ)

DRVP/N Injected Current

Power Supply Rejection

<±1

50

%/V

DRVP/N Injected Current

Temperatue Coeﬃcient

External bias resistor, 32μA , 0 to 70ºC

(0.1%, 10ppm, 324kΩ)

P-P

ppm/°C

±(V

-

AVDD

0.5)

DRVP/N Compliance Voltage

Current Injection Frequency

V

- V

V

P-P

DRVP

DRVN

0.125 to

131.072

Programmable, see Register Map

kHz

mV

Shift from nominal gain < 1% (1.1V)

Shift from nominal gain < 1% (1.8V)

Programmable, see Register Map

25

90

AC Diﬀerential Input Range

BioZ Channel Gain

ADC Sample Rate

10 to 80

V/V

sps

24.98 to

64

Programmable, see Register Map

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, LN_BIOZ = 1, T = T

to T

, unless otherwise

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

noted. Typical values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

20

MAX

UNITS

ADC Resolution

Bits

BW = 0.05 to 4Hz, Gain = 20x

0.16

1.1

μV

Input Referred Noise

(BIP, BIN)

RMS

μV

P-P

DC to 4Hz, 32µA , 40kHz, Gain = 20x,

P-P

Impedance Resolution

40

mΩ

P-P

R

= 680Ω

BODY

125 to

7200

Input Analog High Pass Filter

Demodulation Phase Range

Programmable, see Register Map

Hz

0-180

°

Demodulation Phase

Resolution

11.25

DLPF[1:0] = 01

DLPF[1:0] = 10

DLPF[1:0] = 11

DHPF[1:0] = 01

DHPF[1:0] = 1x

4

8

Output Digital Low Pass Filter

Hz

16

0.05

0.5

Output Digital High Pass Filter

BIOIMPEDANCE (BIOZ) INPUT MUX

IMAG[2:0] = 001

IMAG[2:0] = 010

IMAG[2:0] = 011

IMAG[2:0] = 100

IMAG[2:0] = 101

5

10

DC Lead Oﬀ Check

20

nA

50

100

V

0.50

–

MID

VTH[1:0] = 11 (Note 4)

VTH[1:0] = 10 (Note 5)

VTH[1:0] = 01 (Note 6)

VTH[1:0] = 00

V

–

MID

0.45

DC Lead Oﬀ Comparator Low

Threshold

V

MID

0.40

V

MID

0.30

VTH[1:0] = 11 (Note 4)

V

+ 0.50

+ 0.45

+ 0.40

+ 0.30

MID

VTH[1:0] = 10 (Note 5)

DC Lead Oﬀ Comparator High

Threshold

VTH[1:0] = 01 (Note 6)

VTH[1:0] = 00

Lead bias enabled, RBIASV[1:0] = 00

Lead bias enabled, RBIASV[1:0] = 01

Lead bias enabled, RBIASV[1:0] = 10

50

Lead Bias Impedance

Lead Bias Voltage

100

200

MΩ

Lead bias enabled. Programmable,

see Register Map

V

/

AVDD

2.15

V

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, LN_BIOZ = 1, T = T

to T

, unless otherwise

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

noted. Typical values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

kΩ

Resistive Load Nominal Value

Resistive Load Modulation Value

R

Programmable, see Register Map

0.625 to 5.0

15 to 2960

VAL

R

mΩ

MOD

Resistive Load Modulation

Frequency

F

Programmable, see Register Map

0.625 to 4.0

Hz

MOD

INTERNAL REFERENCE/COMMON-MODE

V

Output Voltage

V

0.650

100

V

BG

Output Impedance

kΩ

BG

External V

Capacitor

Compensation

BG

C

1

µF

BG

V

Output Voltage

V

T

= +25ºC

0.995

1.000

10

1.005

V

REF

A

Temperature Coeﬃcient

Buﬀer Line Regulation

Buﬀer Load Regulation

TC

= 0ºC to +70ºC

ppm/ºC

µV/V

REF

A

330

25

I

= 0 to 100µA

µV/µA

LOAD

External V

Capacitor

Compensation

REF

C

1

10

0.650

10

µF

V

REF

VCM Output Voltage

V

CM

External V

Capacitor

Compensation

CM

C

1

µF

CM

DIGITAL INPUTS (SDI, SCLK, CSB, FCLK)

Input-Voltage High

Input-Voltage Low

Input Hysteresis

Input Capacitance

Input Current

V

0.7 x V

V

IH

OVDD

V

0.3 x V

IL

OVDD

V

0.05 x V

V

HYS

OVDD

C

10

pF

µA

IN

I

-1

+1

IN

DIGITAL OUTPUTS (SDO, INTB, INT2B)

Output Voltage High

V

I

= 1mA

V

- 0.4

V

OH

SOURCE

OVDD

Output Voltage Low

V

= 1mA

SINK

0.4

+1

OL

Three-State Leakage Current

-1

µA

Three-State Output

Capacitance

15

pF

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, LN_BIOZ = 1, T = T

to T

, unless otherwise

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

noted. Typical values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

POWER SUPPLY

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Analog Supply Voltage

Digital Supply Voltage

Interface Supply Voltage

V

Connect AVDD to DVDD

Connect DVDD to AVDD

Power for I/O drivers only

1.1

2.0

3.6

V

AVDD

DVDD

OVDD

V

1.65

V

= V

= +1.1V

= +1.8V

= +2.0V

= +1.1V

= +1.8V

= +2.0V

144

163

170

158

178

185

AVDD

DVDD

BioZ channel ,

LN_BIOZ = 0

CGMAG[2:0] = 011

190

I

+

AVDD

I

Supply Current

µA

BioZ channel ,

LN_BIOZ = 1

CGMAG[2:0] = 011

DVDD

V

T

205

2.5

= +70ºC

= +25ºC

1.3

ULP Lead On

Detect

A

T

0.63

A

V

= +1.65V, BioZ channel at 64sps

OVDD

0.1

0.2

(Note 7)

Interface Supply Current

I

µA

OVDD

V

= 3.6V, BioZ channel at 64sps

OVDD

1.1

(Note 7)

V = V

AVDD

T

= +70ºC

= +25ºC

1.3

I

+

A

SAVDD

I

DVDD

= 2.0V

Shutdown Current

0.58

2.5

1.1

SDVDD

SOVDD

A

I

V

= 3.6V, V

= V

= 2.0V

OVDD

AVDD

DVDD

ESD PROTECTION

BIP, BIN, DRVP, DRVN

IEC 61000-4-2 Contact Discharge (Note 8)

IEC 61000-4-2 Air-Gap Discharge (Note 8)

HMM (Human Metal Model)

±8

±15

±8

kV

TIMING CHARACTERISTICS (NOTE 3)

SCLK Frequency

f

0

12

MHz

ns

SCLK

SCLK Period

t

83

15

CP

CH

SCLK Pulse Width High

SCLK Pulse Width Low

t

ns

t

ns

CL

CSB Fall to SCLK Rise Setup

Time

t

To 1st SCLK rising edge (RE)

15

0

ns

CSS0

CSH0

CSH1

CSB Fall to SCLK Rise Hold

Time

t

Applies to inactive RE preceding 1st RE

CSB Rise to SCLK Rise Hold

Time

Applies to 32nd RE, executed write

10

15

ns

CSB Rise to SCLK Rise

t

Applies to 32nd RE, aborted write sequence

CSA

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, LN_BIOZ = 1, T = T

to T

, unless otherwise

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

noted. Typical values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

100

20

8

TYP

MAX

UNITS

ns

SCLK Rise to CSB Fall

t

Applies to 32nd RE

CSF

CSB Pulse-Width High

t

ns

CSPW

SDI-to-SCLK Rise Setup Time

SDI to SCLK Rise Hold Time

t

ns

DS

t

8

ns

DH

C

= 20pF

40

20

ns

LOAD

SCLK Fall to SDO Transition

t

= 20pF, V

≥ 2.5V

= V

≥ 1.8V,

DOT

LOAD

DVDD

AVDD

DVDD

ns

V

SCLK Fall to SDO Hold

CSB Fall to SDO Fall

CSB Rise to SDO Hi-Z

FCLK Frequency

t

C

= 20pF

2

ns

DOH

LOAD

t

Enable time, C

Disable time

= 20pF

LOAD

30

35

DOE

t

ns

DOZ

f

External reference clock

32.768

30.52

15.26

kHz

µs

FCLK

FCLK Period

t

FP

FCLK Pulse-Width High

FCLK Pulse-Width Low

t

50% duty cycle assumed

µs

FH

t

µs

FL

Note 2:

All devices are 100% production tested at T = +25ºC. Specifications over the operating temperature range and relevant

A

supply voltage range are guaranteed by design and characterization.

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Guaranteed by design and characterization. Not tested in production.

Use this setting only for V

= V

≥ 1.65V.

≥ 1.55V.

≥ 1.45V.

AVDD

DVDD

f

= 4MHz, burst mode, BFIT[2:0] = 111, C

= C

= 50pF.

SCLK

SDO

INTB

ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

SDI

A6

A5

t_DS

A4

A3

t_DH

A2

t_CP

A1

A0

R/WB D_IN23 D_IN22

D_IN1

D_IN0

A6'

SCLK

1

2

3

4

5

6

7

8

9

10

31

32

1'

t_CSA

t_CSH0

t_CH

t_CSH1

t_CSS0

t_CL

CSB

t_CSPW

t_DOT

t_DOH

t_CSF

Z

D_O23

D_O22

D_O1

D_O0

SDO

t_DOZ

t_DOE

Figure 1a. SPI Timing Diagram

t_FP

FCLK

t_FH

t_FL

Figure 1b. FCLK Timing Diagram

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Typical Operating Characteristics

(V

= V

= 1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

BIOZ NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 10, LPF = 16Hz

BIOZ NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 10, LPF = 4Hz

BIOZ NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 80, LPF = 4Hz

0

-50

0

-50

0

-50

-100

-150

-200

-250

-100

-150

-200

-250

-100

-150

-200

-250

0

8

16

24

32

0

8

16

24

32

0

8

16

24

32

FREQUENCY (Hz)

BIOZ NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 80, LPF = 16Hz

BIOZ DIFFERENTIAL INPUT

RESISTANCE vs. VOLTAGE

0

-50

1000000

100000

10000

1000

NO

LEAD BIAS

-100

-150

-200

-250

100MΩ

LEAD BIAS

200MΩ

LEAD BIAS

50MΩ LEAD

BIAS

100

10

0

8

16

24

32

-800 -600 -400 -200

0

200 400 600 800

FREQUENCY (Hz)

V_BIP-V_BIN(mV)

BIOZ COMMON-MODE

INPUT RESISTANCE vs. VOLTAGE

VREF vs. TEMPERATURE

1000000

100000

10000

1000

1000.6

1000.5

1000.4

1000.3

1000.2

1000.1

1000

NO

LEAD BIAS

100MΩ

LEAD BIAS

200MΩ

LEAD BIAS

50MΩ

LEAD BIAS

999.9

999.8

999.7

999.6

100

10

-600

-400

-200

0

200

400

600

0

10

20

30

40

50

60

70

V_CM-V_MID(mV)

TEMPERATURE (°C)

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Typical Operating Characteristics (continued)

(V

= V

= 1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

DVDD SHUTDOWNCURRENT

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

V_DVDD= +2.0V

V_DVDD= +1.8V

V_DVDD= +1.1V

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

AVDD SHUTDOWNCURRENT

OVDD SHUTDOWN CURRENT

0.12

0.10

0.08

0.06

0.04

0.02

0.30

0.25

0.20

0.15

0.10

0.05

0.00

V_OVDD= +1.5V

V_AVDD= +2.0V

V_AVDD= +1.8V

V_OVDD= +1.1V

V_OVDD= +1.8V

V_OVDD= +2.0V

V_AVDD= +1.5V

V_AVDD= +1.1V

0.00

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

AVDD AND DVDD SUPPLY CURRENT

vs. TEMPERATURE

(BIOZ ENABLED, LN_BIOZ = 0)

AVDD AND DVDD ULPCURRENT

vs. TEMPERATURE

200

190

180

170

160

150

140

130

120

110

100

1.2

1

2.0V

1.8V

2.0V

0.8

0.6

0.4

0.2

0

1.8V

1.5V

1.1V

IDRV = 32 ∝A

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Pin Conﬁgurations

TEXTOP VIEW

(BUMP SIDE DOWN)

MAX30002

1

2

3

4

5

6

+

21 20 19 18 17 16 15

DRVP

DRVN

BIN

BIP

I.C.

22

23

24

25

26

27

28

14

AVDD

VREF

I.C.

FCLK

13 DVDD

12

A

B

VBG

VCM

RBIAS

I.C.

AGND

OVDD

SDO

AGND

SDI

I.C.

CPLL

DVDD

CSB

DGND

11 CPLL

MAX30002

VCM

10

9

RBIAS

VBG

I.C.

DGND

FCLK

SCLK

I.C.

C

*EP

+

8

AGND

VREF

AVDD

INTB

INT2B

1

2

3

4

5

6

7

D

E

TQFN

(5mm x 5mm)

*CONNECT EP TO AGND

WLP

(2.7mm x 2.9mm)

Pin Description

BUMP

WLP

NAME

FUNCTION

TQFN

Positive Output Current Source for Bio-Impedance Excitation. Requires a series

capacitor between pin and electrode.

A1

A2

1

2

DRVP

DRVN

Negative Output Current Source for Bio-Impedance Excitation. Requires a series

capacitor between pin and electrode.

A3

A4

4

5

BIN

BIP

Bioimpedance Negative Input.

Bioimpedance Positive Input.

A5, A6, B5,

B6, C2

6, 7, 9,

10, 24

I.C.

Internally Connected. Connect to AGND.

Bandgap Noise Filter Output. Connect a 1.0μF X7R ceramic capacitor between

VBG and AGND.

B1

B2

27

26

VBG

External Resistor Bias. Connect a low tempco resistor between RBIAS and AGND.

If external bias generator is not used then RBIAS can be left ﬂoating.

RBIAS

AGND

B3, B4, C3,

C4, D4

Analog Power and Reference Ground. Connect into the printed circuit board ground

plane.

3, 8, 28

Common Mode Buﬀer Output. Connect a 10μF X5R ceramic capacitor between

VCM and AGND.

C1

25

VCM

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Pin Description (continued)

BUMP

WLP

NAME

FUNCTION

TQFN

Digital Ground for Both Digital Core and I/O Pad Drivers. Recommended to connect

toAGND plane.

C5

12

DGND

C6

D1

11

23

CPLL

VREF

PLL Loop Filter Input. Connect 1nF capacitor between CPLL and AGND.

ADC Reference Buﬀer Output. Connect a 10μF X5R ceramic capacitor between

V

and AGND.

REF

Interrupt Output. INTB is an active-low status output. It can be used to interrupt an

external device. INTB is three-stated when disabled.

D2

D3

21

19

INTB

OVDD

Logic Interface Supply Voltage.

32.768kHz Clock Input. FCLK Controls the sampling of the internal sigma-delta

converter and decimator and derives all the internal clocks.

D5

14

FCLK

D6

E1

13

22

DVDD

AVDD

Digital Core Supply Voltage. Connect to AVDD.

Analog Core Supply Voltage. Connect to DVDD.

Interrupt 2 Output. INT2B is an active-low status output. It can be used to interrupt

an external device. INT2B is three-stated when disabled.

E2

E3

E4

20

18

17

INT2B

SDO

SDI

Serial Data Output. SDO will change state on the falling edge of SCLK when CSB is

low. SDO is three-stated when CSB is high.

Serial Data Input. SDI is sampled into the device on the rising edge of SCLK when

CSB is low.

E5

E6

16

15

SCLK

CSB

—

Serial Clock Input. Clocks data in and out of the serial interface when CSB is low.

Active-Low Chip-Select Input. Enables the serial interface.

Exposed Pad. Connect EP toAGND.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

EMI Filtering and ESD Protection

Detailed Description

EMI filtering of the BIP and BIN inputs consists of a single

pole, low pass, differential, and common mode filter with

the pole located at approximately 2MHz. The BIP and BIN

inputs also have input clamps that protect the inputs from

ESD events. The DRVP and DRVN outputs also feature

ESD protection.

BioZ Channel

Figure 2 illustrates the BioZ channel block diagram,

excluding the ADC. The channel comprises an input

MUX, a programmable analog high-pass filter, an

instrumentation amplifier, a mixer, an anti-alias filter,

and a programmable gain amplifier. The MUX includes

several features such as ESD protection, EMI filtering,

lead biasing, leads off checking, and ultra-low-power

leads-on checking. The output of this analog channel

drives a high-resolution ADC.

● ±8kV using the Contact Discharge method speciﬁed

in IEC61000-4-2 ESD.

● ±15kV using the Air Gap Discharge method speciﬁed

in IEC61000-4-2 ESD.

● ±8kV HMM

Input MUX

For IEC61000-4-2 ESD protection, use 1kΩ or larger

series resistors on BIP, BIN, DRVP, and DRVN that are

rated to withstand the appropriate surge voltages.

The BioZ input MUX shown in Figure 3 contains integrated

ESD and EMI protection, DC leads off detect current

sources and comparators, lead-on detect, series isolation

switches, lead biasing, and a built-in programmable

resistor load, for self test.

PCB

HPF

AAF

BIP

BIN

ESD, EMI,

INPUT MUX,

DC LEAD

CHECK

INPUT

AMP

f_-3dB

PGA

=600Hz

-20dB/dec

-40dB/dec

SELECTABLE PHASE

DRVP

DRVN

PUSH/PULL

CURRENT

SOURCE

MAX30002

Figure 2. BioZ Channel Input Amplifier, Mixer, and PGA Excluding the ADC and Current Drive Output

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

MAX30002

ESD PROTECTION

INPUT AND

R LOAD

ULP LEAD-ON

LEAD

BIAS

DC LEAD-OFF CHECK

AND

CHECK

EMI FILTER

SWITCHES

V_THH

AV_DD

V_MID

50,

100,

15MΩ

200MΩ

5-100nA

V_THL

To BioZ

INA IN+

BIP

AV_DD

5-100nA

R

AG ND

5-100nA

3R

AG ND

To BioZ

INA IN-

AG ND

BIN

V_THH

5-100nA

50,

100,

5MΩ

AG ND

200MΩ

V_THL

AG ND

V_MID

ESD

PROTECTION

From DRVP Current Generator

DRV P

Programmable

Resistor Load

AG ND

From DRVN Current Generator

DRV N

AG ND

Figure 3. BioZ Input MUX

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

The ULP lead-on detect operates by pulling BIN low with

a pulldown resistance larger than 5MΩ and pulling BIP

high with a pullup resistance larger than 15MΩ. A low-

power comparator determines if BIP is pulled below a

predefined threshold that occurs when both electrodes

make contact with the body. When the impedance

between BIP and BIN is less than 20MΩ, the LONINT status

bit is asserted, and when the interrupt is enabled on either the

INTB or INT2B pin, will alert the µC to a leads-on condition.

Leads-Oﬀ Detection and

ULP Leads-On Detection

MAX30002 provides the capability of detecting lead off

scenarios that involve two electrode and four electrode

configurations through the use of digital threshold and

analog threshold comparisons. There are three meth-

ods to detect lead-off for the BioZ channel. There is a

compliance monitor for the current generator on the

DRVP and DRVN pins detecting when the voltage on

the pins is outside its operating range. The CGMON bit

in the CNFG_BIOZ (0x18) register enables this func-

tion and the BCGMON, BCGMP, and BCGMN bits in

the STATUS (0x01) register indicate if the DRVP and

DRVN pins are out of compliance. There is a DC lead-off

circuit on the BIP and BIN pins that sinks or sources a

programmable DC current and window comparators with

a programmable threshold to detect the condition. There

is a digital lead off detection monitoring the output of the

BioZ ADC with programmable under and overvoltage

levels performing a digital comparison. The EN_BLOFF

bit in the CNFG_GEN (0x10) register enables this

function and the BLOFF_HI_IT[7:0] and BLOFF_LO_

IT[7:0] bits in the MNGR_DYN (0x05) register sets the

digital threshold for detection. Refer to Table 1 for lead off

conditions and register settings to allow detection.

A 0nA/V

± 300mV selection is available allowing

MID

monitoring of the input compliance of the INA during non-

DC lead-off checks.

Table 1. BioZ Lead Off Detection Configurations

MEASURED

SIGNAL

CONFIGURATION CONDITION DRVP/N

BIP/N

REGISTER SETTING TO DETECT

Two-Electrode

(Shared DRV/BI)

1 Electrode

Rail to

Rail

Rail to Rail

CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11

Rail to Rail

Oﬀ

(Saturated Inputs) MNGR_DYN (0x05), BLOFF_HI_IT[7:0]

1 DRV

Electrode Oﬀ,

Large Body

Coupling

Rail to

Rail

Normal

½ Signal

CNFG_BIOZ (0x18), CGMON = 1

1 DRV

Electrode Oﬀ,

Small Body

Coupling

Rail to

Rail

Rail to Rail

CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11

Rail to Rail

(Saturated Inputs) MNGR_DYN (0x05), BLOFF_HI_IT[7:0]

Four-Electrode

(Force/Sense)

1 BI (sense)

Electrode Oﬀ

Normal

Floating

½ Signal

CNFG_GEN (0x10), EN_DCLOFF = 10

Both BIP/N

(sense)

Electrodes Oﬀ

CNFG_GEN (0x10), EN_BLOFF[1:0] = 01 or 11

MNGR_DYN (0x05), BLOFF_LO_IT[7:0]

No Signal

Wide Swing,

Dependent on

Body Coupling

1 DRV and 1 BI Rail to

Electrode Oﬀ Rail

CNFG_GEN (0x10), EN_BLOFF[1:0] = 10 or 11

MNGR_DYN (0x05), BLOFF_HI_IT[7:0]

Rail to Rail

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Lead Bias

Programmable Resistive Load

The MAX30002 limits the BIP and BIN DC input common

The programmable resistive load on the DRVP/DRVN

mode range to V

tained either through external/internal lead-biasing.

±150mV. This range can be main-

pins allows a built in self-test of the current generator

(CG) and the entire BioZ channel. Refer to Figure 4 for

implementation details.

MID

Internal DC lead-biasing consists of 50MΩ, 100MΩ,

or 200MΩ selectable resistors to V

that drive the

Nominal resistance can be varied between 5kΩ and

625Ω. The modulation resistance is dependent on the

nominal resistance value with resolution of 247.5mΩ

to 2.96Ω at the largest nominal resistance (5kΩ) and

15.3mΩ to 46.3mΩ with the smallest nominal resistance

(625Ω). Refer to Table 2 for a complete listing of nominal

and modulated resistor values. Modulation rate can be

programmed between 62.5mHz to 4Hz.

MID

electrodes within the input common mode requirements

of the BioZ channel and can drive the connected body

to the proper common mode voltage level. See the EN_

RBIAS[1:0], RBIASV[1:0], RBIASP, and RBIASN bits in the

CNFG_GEN (0x10) register to select a configuration.

The common-mode voltage, V , can optionally be used

CM

as a body bias to drive the body to the common-mode

voltage by connecting V

body through a high value resistor such as 1MΩ to limit

to a separate electrode on the

See register CNFG_BMUX (0x17) to select the configuration

for modulation rate and resistor value.

CM

curent into the body. If this is utilized then the internal lead

bias resistors to V

can be disabled.

MID

9.65kΩ

150Ω

100Ω

55Ω

DRVP_INT

10kΩ

5kΩ

2.5kΩ

1.25kΩ

10kΩ

45Ω

R

<0>

VAL

R

<1>

VAL

R

<2>

VAL

R

<0>

R

<1>

R

<2>

R

<3>

MOD

DRVN_INT

Figure 4. Programmable Resistive Load Topology

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 2. Programmable Resistive Load Values

R

MOD

R

(mΩ)

VAL

MOD

R

(Ω)

NOM

<2>

0

1

<1>

0

1

0

1

<0>

0

1

0

1

0

1

0

1

<3>

0

<2>

0

1

0

1

0

1

0

<1>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

<0>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-

2960.7

980.6

247.5

—

5000.000

2500.000

1666.667

740.4

245.2

61.9

—

329.1

109.0

27.5

—

1250.000

1000.000

833.333

714.286

625.000

185.1

61.3

—

118.5

39.2

—

82.3

27.2

—

60.5

20.0

—

46.3

15.3

Current amplitudes between 8µA to 96µA are select-

Current Generator

PK

able with current injection frequencies between 128Hz

and 131.072kHz in power of two increments. See register

CNFG_BIOZ (0x18) for configuration selections.

The current generator provides square-wave modulating

differential current that is AC injected into the body via

pins DRVP and DRVN with the bio-impedance sensed

differentially through pins BIP and BIN. Two and four

electrode configurations are supported for typical wet and

dry electrode impedances.

Current amplitude should be chosen so as not exceed

90mV

at the BIP and BIN pins based on the network

P-P

impedance at the current injection frequency. A 47nF DC

blocking capacitor is required between both DRVP and

DRVN and their respective electrodes.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Current Selection and Resolution Calculation

Example 1 (Two Terminal with Common

Protection)

Selection of the appropriate current is accomplished by

first calculating the network impedance at the injection

frequency. Worst case electrode impedances should be

used.

Current Selection and Resolution Calculation

Example 2 (Four Terminal)

Selection of the appropriate current is accomplished by

first calculating the network impedance at the injection

frequency. Worst case electrode impedances should be

used.

Given Figure 6 and a current injection frequency of

80kHz, the network impedance is:

Given Figure 5 and a current injection frequency of

80kHz, the network impedance is:

2R

E

R

+ 2R

+ 2R +

S

= 2.7kΩ

BODY

DP1

DP2

2R

E

1+ jωR C

E

R

+ 2R + 2R + 2R +

S

= 2.8kΩ

BODY

P1

P2

1+ jωR C

E

where R

= 100Ω, R

= 1kΩ, R

= 200Ω,

BODY

DP1

DP2

where R

= 100Ω, R

= 1kΩ, R

= 200Ω,

R = 100Ω, R = 1MΩ, C = 5nF. The maximum current

S E E

BODY

P1

P2

R

= 100Ω, R = 1MΩ, C = 5nF. The maximum cur-

injection is the maximum DRVP/N Compliance Voltage

(V -0.5V = 0.6V for V = 1.1V) divided by the network

S

E

rent injection is the maximum AC input differential range

DD

(90mV ) divided by the network impedance (2.8kΩ) or

impedance (2.7kΩ) or 222.2µA . The closest selectable

PK

32.14µA . The closest selectable lower value is 32µA

.

lower value is 96µA

.

PK

Given the current injection value and the channel band-

width (refer to register CNFG_BIOZ (0x18) for digital LPF

selection) the resolvable impedance can be calculated by

dividing the appropriate input referred noise by the current

injection value. For example, with a bandwidth of 4Hz, the

Given the current injection value and the channel band-

width (refer to register CNFG_BIOZ (0x18) for digital LPF

selection) the resolvable impedance can be calculated by

dividing the appropriate input referred noise by the current

injection value. For example, with a bandwidth of 4Hz, the

input referred noise with a gain of 20V/V is 0.16µV

input referred noise with a gain of 40V/V is 0.12µV

RMS

or 1.1µV . The resolvable impedance is, therefore,

or 0.78µV . The resolvable impedance is therefore

P-P

1.1µV /32µA = 34mΩ

or 5mΩ

.

0.78µV /96µA = 8mΩ

or 1.2mΩ

.

P-P

PK

P-P

RMS

P-P

PK

P-P

RMS

PCB

DRVP

BIP

47nF

C

= 5nF

E

R

= 100Ω

R

S

P1

P2

1kΩ

200Ω

10pF

R

= 1MΩ

E

PHYSICAL

ELECTRODES

DEFIB

PROTECTION

R

100Ω

BODY

ELECTRODE MODELS

= 5nF

47pF

MAX30002

C

E

10pF

R_S= 100Ω

R

P2

P1

BIN

1kΩ

200Ω

R

= 1MΩ

E

47nF

DRVN

Figure 5. Example Configuration – Two Terminal with Common Protection

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

PCB

C

= 5nF

E

R

= 100Ω

R

DP2

S

DP1

DRVP

1kΩ

200Ω

47nF

R

= 1MΩ

E

C

= 5nF

E

R

= 100Ω

R

BP2

S

BP1

BIP

1kΩ

200Ω

10pF

R

= 1MΩ

E

PHYSICAL

ELECTRODES

DEFIB

PROTECTION

R

100Ω

BODY

ELECTRODE MODELS

= 5nF

47pF

MAX30002

C

E

R_S= 100Ω

R

BP2

BP1

BIN

1kΩ

200Ω

R

= 1MΩ

E

C

= 5nF

E

R_S= 100Ω

47nF

R

DP2

DP1

DRVN

1kΩ

200Ω

R

= 1MΩ

E

Figure 6. Example Configuration—Four Terminal

Filter Section

Reference and Common Mode Buﬀer

The filter section consists of an FIR decimation filter to

to convert the ADC sample rate to the final data rate,

followed by a programmable IIR and FIR filter to

implement HPF and LPF selections, respectively.

The MAX30002 features internally generated reference

voltages. The bandgap output (V ) pin requires an

BG

external 1.0µF capacitor to AGND and the reference

output (V

) pin requires a 10µF external capacitor to

REF

AGND for compensation and noise filtering.

The high-pass filter options include a fourth-order IIR

Butterworth filter with a 0.05Hz or 0.5Hz corner frequency

along with a pass through setting for DC coupling.

Lowpass filter options include a 12-tap linear phase

(constant group delay) FIR filter with 4Hz, 8Hz, or 16Hz

corner frequencies. See register CNFG_BIOZ (0x18) to

configure the filters. Table 3 illustrates the BioZ latency in

samples and time for each ADC data rate.

A common-mode buffer is provided to buffer 650mV

which is used to drive common mode voltages for internal

blocks. Use a 10µF external capacitor between V

to

CM

AGND to provide compensation and noise filtering. The

common-mode voltage, V , can optionally be used as

CM

a body bias to drive the body to the common-mode volt-

age by connecting V

to a separate electrode on the

CM

body through a high value resistor such as 1MΩ. If this is

utilized then the internal lead bias resistors to V may

be disabled if the input signals are within the common-

mode input range.

Noise Measurements

Table 4 shows the noise performance of the BioZ channel

of MAX30002 referred to the BioZ inputs.

MID

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 3. BioZ Latency in Samples and Time as a Function of BioZ Data Rate and

Decimation

BIOZ CHANNEL SETTINGS

LATENCY

INPUT

SAMPLE RATE

(Hz)

WITHOUT

LPF (INPUT

SAMPLES)

WITH LPF

(INPUT

SAMPLES)

OUTPUT DATA

RATE (sps)

DECIMATION

WITHOUT

LPF(ms)

WITH LPF (ms)

RATIO

32,768

32,000

31,968

32,768

32,000

31,968

64

62.5

50

512

3,397

5,189

7,557

9,605

6,469

103.668

106.156

162.156

162.319

230.621

236.156

300.156

300.457

197.418

202.156

282.156

282.439

418.121

428.156

540.156

540.697

640

9,029

49.95

32

640

9,029

1,024

1,280

13,701

17,285

31.25

25

24.975

Table 4. BioZ Channel Noise Performance

GAIN

BANDWIDTH

NOISE

SNR

dB

ENOB

Bits

16.6

16.3

16.0

17.1

16.9

16.5

17.6

17.1

16.7

17.7

17.2

16.7

µV

V/V

Hz

4

RMS

µV

P-P

0.23

1.55

101.6

100.0

98.0

10

20

40

80

8

0.28

0.35

0.16

0.19

0.26

0.12

0.16

0.22

0.11

0.15

0.21

1.87

2.34

1.10

1.27

1.68

0.78

1.07

1.48

0.72

1.01

1.42

16

4

104.9

103.4

100.9

107.6

104.9

102.0

108.3

105.3

102.4

8

16

4

8

16

4

8

16

SNR = 20log(V (RMS)/V (RMS)), ENOB = (SNR – 1.76)/6.02

IN

N

V

= 100mV, V

= 35.4mV for a gain of 10V/V. The input amplitude is reduced accordingly for high gain settings.

INRMS

INP-P

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

If accessing the STATUS register or the BIOZ FIFO mem-

ory, all interrupt updates will be made and the internal

FIFO read pointer will be incremented in response to the

30th SCLK rising edge, allowing for internal synchroniza-

tion operations to occur. See the data tag structures used

within the FIFO for means of detecting end-of-file (EOF)

samples, invalid (empty samples) and other aides for

efficiently using and managing normal mode read back

operations.

SPI Interface Description

32 Bit Normal Mode Read/Write Sequences

The MAX30002 interface is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

in Figure 1a. Data is strobed into the MAX30002 on SCLK

rising edges. The device is programmed and accessed by

a 32 cycle SPI instruction framed by a CSB low interval.

The content of the SPI operation consists of a one byte

command word (comprised of a seven bit address and a

Read/Write mode indicator, i.e., A[6:0] + R/W) followed by

a three-byte data word. The MAX30002 is compatible with

CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1 modes of

operation.

Burst Mode Read Sequence

The MAX30002 provides commands to read back the

BIOZ FIFO memory in a burst mode to increase data

transfer efficiency. Burst mode uses different regis-

ter addresses than the normal read sequence register

addresses. The first 32 SCLK cycles operate exactly as

described for the normal mode. If the µC continues to

provide SCLK edges beyond the 32nd rising edge, the

MSB of the next available FIFO word will be presented

on the next falling SCLK edge, allowing the µC to sample

the MSB of the next word on the 33rd SCLK rising edge.

Any affected interrupts and/or FIFO read pointers will be

incremented in response to the (30+nx24)th SCLK rising

edge where n is an integer starting at 0. (i.e., on the 30th,

54th, and 78th SCLK rising-edges for a three-word, burst-

mode transfer).

Write mode operations will be executed on the 32nd SCLK

rising edge using the first four bytes of data available. In

write mode, any data supplied after the 32nd SCLK rising

edge will be ignored. Subsequent writes require CSB to

de-assert high and then assert low for the next write com-

mand. In order to abort a command sequence, the rise

of CSB must precede the updating (32nd) rising-edge of

SCLK, meeting the t

requirement.

CSA

Read mode operations will access the requested data

on the 8th SCLK rising edge, and present the MSB of

the requested data on the following SCLK falling edge,

allowing the µC to sample the data MSB on the 9th SCLK

rising edge. Configuration, Status, and FIFO data are all

available via normal mode read back sequences. If more

than 32 SCLK rising edges are provided in a normal read

sequence then the excess edges will be ignored and the

device will read back zeros.

This mode of operation will continue for every 24 cycle

sub frame, as long as there is valid data in the FIFO. See

the data tag structures used within each FIFO for means

of detecting end-of-file (EOF) samples, invalid (empty

samples) and other aides for efficiently using and manag-

ing burst mode read back operations.

There is no burst mode equivalent in write mode.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

CSB

SDI

A6 A5 A4 A3 A2 A1 A0

W

D23

9

D16 D15

16 17

D8 D7

D0 DON’T CARE

24

25

32

33

SCLK

1

8

IGNORE

D EDGES

COMMAND

EXECUTED

Z

SDO

SPI NORMAL MODE WRITE TRANSACTION

CSB

SDI

A6 A5 A4 A3 A2 A1 A0

1

R

DON’T CARE

16 17

DON’T CARE

24

25

30

32

33

SCLK

8 9

IGNORE

D EDGES

INTERRUPT /READ POINTER

UPDATED (IF APPLICABLE

)

Z

D_O23

D_O16 D_O15

D_O

8

D_O

7

D_O

0

SDO

SPI NORMAL MODE READ TRANSACTION

Figure 7. SPI Normal Mode Transaction Diagram

SDI

A6 A5 A4 A3 A2 A1 A0

1

R

DON’T CARE

16 17

DON’T CARE

24 25

30

32

SCLK

8 9

READ POINTER

UPDATED (TO B)

D_A8 D_A7

Z

SDO

D_A23

D_A16 D_A15

D_A0 D_B23

CONTINUED TRANSACTION (SUB-FRAME 2)

CSB

33

40 41

48 49

56

54

SCLK

READ POINTER

UPDATED (TO C)

D_B23

D_B16D_B15

D_B8 D_B7

D 0

B

SDO

D_C23

CONTINUED TRANSACTION (SUB-FRAME 3)

CSB

57

64 65

72 73

78

80

SCLK

READ POINTER

UPDATED (TO D)

Z

D_C16 D_C15

SDO

D_C23

D_C8 D_C7

D_C0

Figure 8. SPI Burst Mode Read Transactions Diagram

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

User Command and Register Map

DATA INDEX

REG

[6:0]

R/W

NAME

MODE

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

0x00

0x01

NO-OP

R/W

R

x / x / x

DCLO

FFINT

x

BINT

BOVF

BOVER

BUNDR

STATUS

BCGMON

x

LONINT

x

SAMP

PLLINT

BCGMP

BCGMN

LDOFF_PH

LDOFF_PL

LDOFF_NH

LDOFF_NL

EN_

x

EN_BINT

EN_BOVF

EN_BOVER

EN_SAMP

EN_BUNDR

EN_ PLLINT

DCLOFFINT

0x02

0x03

EN_INT

R/W

EN_INT2

EN_BCGMON

x

EN_ LONINT

x

INTB_TYPE[1:0]

BFIT[2:0]

x

0x04 MNGR_ INT

R/W

x

CLR_PEDGE CLR_ SAMP

SAMP_IT[1:0]

x

MNGR_

0x05

DYN

BLOFF_HI_IT[7:0]

BLOFF_LO_IT[7:0]

0x08

0x09

SW_RST

SYNCH

W

Data Required for Execution = 0x000000

1 REV_ID[3:0]

0x0A FIFO_ RST

0

x

1

x

0

1

x

0x0F

INFO

R

0

x

EN_ULP_LON[1:0]

FMSTR[1:0]

x

EN_BIOZ

x

0x10 CNFG_ GEN R/W

CNFG_

EN_BLOFF[1:0]

VTH[1:0]

EN_DCLOFF[1:0]

EN_RBIAS[1:0]

IPOL

IMAG[2:0]

RBIASP

RBIASV[1:0]

CALP_SEL[1:0]

EN_BIST

RBIASN

x

OPENP

CG_MODE[1:0]

RMOD[2:0]

AHPF[2:0]

DLPF[1:0]

CGMAG[2:0]

OPENN

CALN_SEL[1:0]

RNOM[2:0]

FBIST[1:0]

GAIN[1:0]

0x17

0x18

0x22

R/W

R+

x

BMUX

x

RATE

EXT_RBIAS

LN_BIOZ

CNFG_

BIOZ

DHPF[1:0]

CGMON

FCGEN[3:0]

PHOFF[3:0]

BIOZ_

FIFO_

BIOZ FIFO Burst Mode Read Back

See FIFO Description for details

BURST

0x23 BIOZ_ FIFO

0x7F NO-OP

R

BIOZ FIFO Normal Mode Read Back

See FIFO Description for details

R/W

x/x/x

Note: R/W Mode R+ denotes burst mode.

x = Don’t Care

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Register Description

NO_OP (0x00 and 0x7F) Registers

No Operation (NO_OP) registers are read-write registers that have no internal effect on the device. If these registers are

read back, DOUT remains zero for the entire SPI transaction. Any attempt to write to these registers is ignored without

impact to internal operation.

STATUS (0x01) Register

STATUS is a read-only register that provides a comprehensive overview of the current status of the device. The first

two bytes indicate the state of all interrupt bits (regardless of whether interrupts are enabled in registers EN_INT (0x02)

or EN_INT2 (0x03)). All interrupt bits are active high. The last byte includes detailed status information for conditions

associated with the other interrupt bits.

Table 5. STATUS (0x01) Register Map

REG

NAME

R/W

23/15/7

x

22/14/6 21/13/5

20/12/4

DCLOFF INT

x

19/11/3

BINT

18/10/2

BOVF

x

17/9/1

BOVER

SAMP

16/8/0

BUNDR

PLLINT

x

BCGMON

LONINT

0x01 STATUS

R

LDOFF_

PH

LDOFF_

PL

LDOFF_

NH

LDOFF_

NL

x

BCGMP

BCGMN

Table 6. Status (0x01) Register Meaning

INDEX

NAME

MEANING

DC Lead-Oﬀ Detection Interrupt. Indicates that the MAX30002 has determined it is in a BioZ leads

oﬀ condition (as selected in CNFG_GEN) for more than 90ms. Remains active as long as the leads-

oﬀ condition persists, then held until cleared by STATUS read back (32nd SCLK).

D[20]

DCLOFFINT

BIOZ FIFO Interrupt. Indicates BIOZ records meeting/exceeding the BIOZ FIFO Interrupt Threshold

(BFIT) are available for read back. Remains active until BIOZ FIFO is read back to the extent

required to clear the BFIT condition.

D[19]

D[18]

BINT

BIOZ FIFO Overﬂow. Indicates the BIOZ FIFO has overﬂowed and the data record has been

corrupted. Remains active until a FIFO Reset (recommended) or SYNCH operation is issued.

BOVF

BIOZ Over Range. Indicates the BIOZ output magnitude has exceeded the BIOZ High Threshold

(BLOFF_HI_IT) for at least 100ms, recommended for use in 2 and 4 electrode BIOZ Lead Oﬀ

detection. Remains active as long as the condition persists, then held until cleared by STATUS read

back (32nd SCLK).

D[17]

D[16]

D[15]

BOVER

BUNDR

BIOZ Under Range. Indicates the BIOZ output magnitude has been bounded by the BIOZ Low

Threshold (BLOFF_LO_IT) for at least 1.7 seconds, recommended for use in 4 electrode BIOZ Lead

Oﬀ detection. Remains active as long as the condition persists, then held until cleared by STATUS

read back (32nd SCLK).

BIOZ Current Generator Monitor. Indicates the DRVP and/or DRVN current generator has been in a

Lead Oﬀ condition for at least 128ms, recommended for use in 4 electrode BIOZ Lead Oﬀ detection.

Remains active as long as the condition persists, then held until cleared by STATUS read back (32nd

SCLK).

BCGMON

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 6. Status (0x01) Register Meaning (continued)

INDEX

NAME

MEANING

Ultra-Low Power (ULP) Leads-On Detection Interrupt. Indicates that the MAX30002 has determined

it is in a leads-on condition (as selected in CNFG_GEN).

LONINT is asserted whenever EN_ULP_LON[1:0] in register CNFG_GEN is set to either 01 or 10

to indicate that the ULP leads on detection mode has been enabled. The STATUS register has to be

read back once after ULP leads on detection mode has been activated to clear LONINT and enable

leads on detection.

D[11]

LONINT

LONINT remains active while the leads-on condition persists, then held until cleared by STATUS

read back (32nd SCLK).

Sample Synchronization Pulse. Issued on the BioZ base-rate sampling instant, for use in assisting

µC monitoring and synchronizing other peripheral operations and data, generally recommended for

use as a dedicated interrupt.

Frequency is selected by SAMP_IT[1:0], see MNGR_INT for details.

Clear behavior is deﬁned by CLR_SAMP, see MNGR_INT for details.

D[9]

D[8]

SAMP

PLL Unlocked Interrupt. Indicates that the PLL has not yet achieved or has lost its phase lock.

PLLINT will only be asserted when the PLL is powered up and active (BIOZ Channel enabled).

Remains asserted while the PLL unlocked condition persists, then held until cleared by STATUS

read back (32nd SCLK).

PLLINT

BIOZ Current Generator Monitor Positive Output. Indicates the DRVP current generator has been in

a Lead Oﬀ condition for at least 128ms. This is not strictly an interrupt bit, but is a detailed status bit,

covered by the BCGMON interrupt bit.

D[5]

D[4]

BCGMP

BCGMN

BIOZ Current Generator Monitor Negative Output. Indicates the DRVN current generator has been

in a Lead Oﬀ condition for at least 128ms. This is not strictly an interrupt bit, but is a detailed status

bit, covered by the BCGMON interrupt bit.

DC Lead Oﬀ Detection Detailed Status. Indicates that the MAX30002 has determined

(as selected by CNFG_GEN):

D[3]

D[2]

D[1]

D[0]

LDOFF_PH

LDOFF_PL

LDOFF_NH

LDOFF_NL

BIP is above the high threshold (V

), BIP is below the low threshold (V

), BIN is above the high

THL

THH

threshold (VT ), BIN is below the low threshold (V

), respectively.

HH

THL

Remains active as long as the leads-oﬀ detection is active and the leads-oﬀ condition persists, then

held until cleared by STATUS read back (32nd SCLK). LDOFF_PH to LDOFF_NL are detailed status

bits that are asserted at the same time as DCLOFFINT.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

EN_INT (0x02) and EN_INT2 (0x03) Registers

EN_INT and EN_INT2 are read/write registers that govern the operation of the INTB output and INT2B output, respectively.

The first two bytes indicate which interrupt input bits are included in the interrupt output OR term (ex. a one in an EN_INT

register indicates that the corresponding input bit is included in the INTB interrupt output OR term). See the STATUS register

for detailed descriptions of the interrupt bits. The power-on reset state of all EN_INT bits is 0 (ignored by INT).

EN_INT and EN_INT2 can also be used to mask persistent interrupt conditions in order to perform other interrupt-driven

operations until the persistent conditions are resolved.

INTB_TYPE[1:0] allows the user to select between a CMOS or an open-drain NMOS mode INTB output. If using open-

drain mode, an option for an internal 125kΩ pullup resistor is also offered.

All INTB and INT2B types are active-low (INTB low indicates the device requires servicing by the µC); however, the open-

drain mode allows the INTB line to be shared with other devices in a wired-or configuration.

In general, it is suggested that INT2B be used to support specialized/dedicated interrupts of use in specific applications,

such as the self-clearing versions of SAMP or RRINT.

Table 7. EN_INT (0x02) and EN_INT2 (0x03) Register Maps

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

EN_DCL

OFFINT

EN_

BOVER

EN_

BUNDR

x

EN_BINT

EN_BOVF

0x02

0x03

EN_INT

EN_INT2

R/W

EN_

BCGMON

EN_

LONINT

EN_

SAMP

EN_

PLLINT

x

INTB_TYPE[1:0]

Table 8. EN_INT (0x02 and 0x03) Register Meaning

INDEX

NAME

DEFAULT

FUNCTION

EN_DCLOFFINT

EN_BINT

EN_BOVF

EN_BOVER

EN_BUNDR

EN_BCGMON

EN_LONINT

EN_SAMP

Interrupt Enables for interrupt bits in STATUS[23:8]

0 = Individual interrupt bit is not included in the interrupt OR term

1 = Individual interrupt bit is included in the interrupt OR term

D[23:8]

0x0000

EN_PLLINT

INTB Port Type (EN_INT Selections)

00 = Disabled (Three-state)

11

01 = CMOS Driver

10 = Open-Drain NMOS Driver

11 = Open-Drain NMOS Driver with Internal 125kΩ Pullup Resistance

D[1:0]

INTB_TYPE[1:0]

INT2B Port Type (EN_INT2 Selections)

00 = Disabled (three-state)

01 = CMOS Driver

10 = Open-Drain nMOS Driver

11 = Open-Drain nMOS Driver with Internal 125kΩ Pullup Resistance

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

MNGR_INT (0x04)

MNGR_INT is a read/write register that manages the operation of the configurable interrupt bits in response to BIOZ FIFO

conditions (see the STATUS register and BIOZ FIFO descriptions for more details).

Table 9. MNGR_INT (0x04) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

BFIT[2:0]

x

16/8/0

x

MNGR_

INT

0x04

R/W

CLR_

FAST

CLR_

SAMP

x

SAMP_IT[1:0]

Table 10. MNGR_INT (0x04) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread

FIFO records)

D[18:16]

BFIT[2:0]

011

000 to 111 = 1 to 8, respectively (i.e. BFIT[2:0]+1 unread records)

Sample Synchronization Pulse (SAMP) Clear Behavior:

0 = Clear SAMP on STATUS Register Read Back (recommended for debug/

evaluation only).

D[2]

CLR_SAMP

1

1 = Self-clear SAMP after approximately one-fourth of one data rate cycle.

Sample Synchronization Pulse (SAMP) Frequency

00 = issued every sample instant

D[1:0]

SAMP_IT[1:0]

00

01 = issued every 2nd sample instant

10 = issued every 4th sample instant

11 = issued every 16th sample instant

MNGR_DYN (0x05)

MNGR_DYN is a read/write register that manages the settings of any general/dynamic modes within the device. This

register contains the interrupt thresholds for BIOZ AC Lead-Off Detection (see CNFG_GEN for more details). Unlike

many CNFG registers, changes to dynamic modes do not impact FIFO operations or require a SYNCH operation (though

the affected circuits may require time to settle, resulting in invalid/corrupted FIFO output voltage information during the

settling interval).

Table 11. MNGR_DYN (0x05) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

x

MNGR_

DYN

0x05

R/W

BLOFF_HI_IT[7:0]

BLOFF_LO_IT[7:0]

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 12. MNGR_DYN (0x05) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

BIOZ AC Lead Oﬀ Over-Range Threshold

If EN_BLOFF[1:0] = 1x and the ADC output of a BIOZ measurement exceeds the

symmetric thresholds deﬁned by ±2048*BLOFF_HI_IT for over 128ms, the BOVER

interrupt bit will be asserted.

For example, the default value (BLOFF_IT= 0xFF) corresponds to a BIOZ output

upper threshold of 0x7F800 or about 99.6% of the full scale range, and a BIOZ

output lower threshold of 0x80800 or about 0.4% of the full scale range with the

LSB weight ≈ 0.4%.

D[15:8]

BLOFF_HI_IT[7:0]

0xFF

BIOZ AC Lead Oﬀ Under-Range Threshold

If EN_BLOFF[1:0] = 1x and the output of a BIOZ measurement is bounded by the

symmetric thresholds deﬁned by ±32*BLOFF_LO_IT for over 128ms, the BUNDR

interrupt bit will be asserted.

D[7:0]

BLOFF_LO_IT[7:0]

0xFF

SW_RST (0x08)

SW_RST (Software Reset) is a write-only register/command that resets the MAX30002 to its original default conditions at

the end of the SPI SW_RST transaction (i.e. the 32nd SCLK rising edge). Execution occurs only if DIN[23:0] = 0x000000.

The effect of a SW_RST is identical to power-cycling the device.

Table 13. SW_RST (0x08) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x08

SW_RST

R/W

SYNCH (0x09)

SYNCH (Synchronize) is a write-only register/command that begins new BIOZ operations and recording, beginning

on the internal MSTR clock edge following the end of the SPI SYNCH transaction (i.e. the 32nd SCLK rising edge).

Execution occurs only if DIN[23:0] = 0x000000. SYNCH will reset and clear the FIFO memory and the DSP filter (to mid-

scale), allowing the user to effectively set the “Time Zero” for the FIFO records. No configuration settings are impacted.

For best results, users should wait until the PLL has achieved lock before synchronizing if the CNFG_GEN settings have

been altered.

Once the device is initially powered up, it will need to be fully configured prior to launching recording operations. Likewise,

anytime a change to CNFG_GEN or CNFG_ BIOZ registers are made there may be discontinuities in the BIOZ records and

possibly changes to the size of the time steps recorded in the FIFOs. The SYNCH command provides a means to restart

operations cleanly following any such disturbances.

If a FIFO overflow event occurs and a portion of the record is lost, it is recommended to use the SYNCH command to

recover and restart the recording, (avoiding issues with missing data).

Table 14. SYNCH (0x09) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x09

SYNCH

R/W

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

FIFO_RST (0x0A)

FIFO_RST (FIFO Reset) is a write-only register/command that begins a new BIOZ recording by resetting the FIFO

memory and resuming the record with the next available BIOZ data. Execution occurs only if DIN[23:0] = 0x000000.

Unlike the SYNCH command, the operations of any active BIOZ circuitry are not impacted by FIFO_RST, so no settling/

recovery transients apply. FIFO_RST can also be used to quickly recover from a FIFO overflow state.

Table 15. FIFO_RST (0x0A) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x0A

FIFO_RST

R/W

INFO (0x0F)

INFO is a read-only register that provides information about the MAX30002. The first nibble contains an alternating bit pattern

to aide in interface verification. The second nibble contains the revision ID. The third nibble includes part ID information.

Note: Due to internal initialization procedures, this command will not read-back valid data if it is the first com-

mand executed following either a power-cycle event, or a SW_RST event.

Table 16. INFO (0x0F) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

0

x

1

x

0

1

x

1

0

x

REV_ID[3:0]

0x0F

INFO

R

x

Table 17. INFO (0x0F) Register Meaning

INDEX

NAME

MEANING

Revision ID

D[19:16]

REV_ID[3:0]

CNFG_GEN (0x10)

CNFG_GEN is a read/write register which governs general settings, most significantly the master clock rate for all internal

timing operations. Anytime a change to CNFG_GEN is made, there may be discontinuities in the BIOZ record and pos-

sibly changes to the size of the time steps recorded in the FIFOs. The SYNCH command can be used to restore internal

synchronization resulting from configuration changes. Note when EN_BIOZ is logic-low, the device is in one of two ultra-

low power modes (determined by EN_ULP_LON).

Table 18. CNFG_GEN (0x10) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

x

18/10/2

17/9/1

x

16/8/0

EN_ULP_LON[1:0]

EN_BLOFF[1:0]

VTH[1:0]

FMSTR[1:0]

EN_BIOZ

x

CNFG_

GEN

0x10

R/W

EN_DCLOFF[1:0]

EN_RBIAS[1:0]

IPOL

IMAG[2:0]

RBIASP

RBIASV[1:0]

RBIASN

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 19. CNFG_GEN (0x10) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Ultra-Low Power Lead-On Detection Enable

00 = ULP Lead-On Detection disabled

EN_ULP_LON

[1:0]

01 = Reserved. Do not use.

10 = BioZ ULP Lead-On Detection enabled.

11 = Reserved. Do not use.

D[23:22]

00

ULP mode is only active when the BioZ channel is powered down/disabled.

Master Clock Frequency. Selects the Master Clock Frequency (FMSTR), which also

determines the BioZ timing characteristics. These are generated from FCLK, which

is always 32.768kHz.

D[21:20]

D[18]

FMSTR[1:0]

EN_BIOZ

00

00 = F

01 = F

10 = F

11 = F

= 32768Hz

= 32000Hz

= 31968.78Hz

MSTR

BIOZ Channel Enable

0 = BIOZ Channel disabled

1 = BIOZ Channel enabled

0

BIOZ Digital Lead Oﬀ Detection Enable

00 = Digital Lead Oﬀ Detection disabled

01 = Lead Oﬀ Under Range Detection, 4 electrode BIOZ applications

10 = Lead Oﬀ Over Range Detection, 2 and 4 electrode BIOZ applications

11 = Lead Oﬀ Over & Under Range Detection, 4 electrode BIOZ applications

AC Method, requires active BIOZ Channel , enables BOVER & BUNDR interrupt

behavior. Uses BIOZ excitation current set in CNFG_BIOZ with digital thresholds

set in MNGR_DYN.

D[15:14]

EN_BLOFF[1:0]

00

DC Lead-Oﬀ Detection Enable

00 = DC Lead-Oﬀ Detection disabled

01 = Reserved. Do not use.

10 = DCLOFF Detection applied to the BIP/N pins.

11 = Reserved. Do not use.

DC Method, requires active selected channel, enables DCLOFF interrupt and status

bit behavior.

D[13:12]

D[11]

EN_DCLOFF

00

Uses current sources and comparator thresholds set below.

DC Lead-Oﬀ Current Polarity (if current sources are enabled/connected)

DCLOFF_ IPOL

0

0 = BIP - Pullup

BIN – Pulldown

1 = BIP - Pulldown BIN – Pullup

DC Lead-Oﬀ Current Magnitude Selection

000 = 0nA (Disable and Disconnect Current Sources)

001 = 5nA

010 = 10nA

D[10:8]

IMAG[2:0]

000

011 = 20nA

100 = 50nA

101 = 100nA

110 = Reserved. Do not use.

111 = Reserved. Do not use.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 19. CNFG_GEN (0x10) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

DC Lead-Oﬀ Voltage Threshold Selection

00 = V

01 = V

10 = V

11 = V

± 300mV

± 400mV

± 450mV

± 500mV

MID

D[7:6]

VTH[1:0]

00

Enable and Select Resistive Lead Bias Mode

00 = Resistive Bias disabled

01 = Reserved. Do not use.

D[5:4]

D[3:2]

EN_RBIAS[1:0]

RBIASV[1:0]

00

01

10 = BioZ Resistive Bias enabled if EN_BIOZ is also enabled

11 = Reserved. Do not use.

If EN_BIOZ is not asserted at the same time or prior to EN_RBIAS[1:0] being

enabled, then EN_RBIAS[1:0] will remain set to 00.

Resistive Bias Mode Value Selection

00 = R

01 = R

10 = R

= 50MΩ

= 100MΩ

= 200MΩ

BIAS

11 = Reserved. Do not use.

Enables Resistive Bias on Positive Input

D[1]

D[0]

RBIASP

RBIASN

0

0 = BIP is not resistively connected to V

MID

1 = BIP is connected to V

through a resistor (selected by RBIASV).

MID

Enables Resistive Bias on Negative Input

0 = BIN is not resistively connected to V

MID

1 = BIN is connected to V

through a resistor (selected by RBIASV).

MID

Table 20 shows BIOZ data rates that can be realized with various setting of FMSTR, along with RATE configuration bits

available in the CNFG_BIOZ register. Note FMSTR also determines the timing resolution of the CAL waveform generator.

Table 20. Master Frequency Summary Table

MASTER FREQUENCY

BIOZ DATA RATES

(B_RATE)

FMSTR

[1:0]

(f

)

MSTR

(Hz)

(sps)

0 = 64

1 = 32

00

01

10

11

32,768

32,000

31,968

0 = 62.50

1 = 31.25

0 = 50

1 = 25

0 = 49.95

1 = 24.98

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

CNFG_BMUX(0x17)

CNFG_BMUX is a read/write register which configures the operation, settings, and functionality of the input multiplexer

associated with the BIOZ channel.

Table 21. CNFG_BMUX (0x17) Register Map

REG

NAME

R/W 23/15/7 22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

CALN_SEL[1:0]

RNOM[2:0]

FBIST[1:0]

16/8/0

x

OPENP

OPENN

CALP_SEL[1:0]

CNFG_

BMUX

0x17

R/W

CG_MODE[1:0]

RMOD[2:0]

EN_BIST

x

Table 22. CNFG_BMUX (0x17) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Open the BIP Input Switch (most often used for testing and calibration)

0 = BIP is internally connected to the BIOZ channel

D[21]

OPENP

1

1 = BIP is internally isolated from the BIOZ channel

Open the BIN Input Switch (most often used for testing and calibration)

0 = BIN is internally connected to the BIOZ channel

D[20]

OPENN

1

1 = BIN is internally isolated from the BIOZ channel

BIP Calibration Selection

00 = No calibration signal applied

01 = Input is connected to VMID

10 = Reserved. Do not use.

11 = Reserved. Do not use.

CALP_

SEL[1:0]

D[19:18]

00

BIN Calibration Selection

00 = No calibration signal applied

01 = Input is connected to VMID

10 = Reserved. Do not use.

11 = Reserved. Do not use.

CALN_

SEL[1:0]

D[17:16]

00

BIOZ Current Generator Mode Selection

00 = Unchopped Sources with Low Pass Filter

(higher noise, excellent 50/60Hz rejection, recommended for BioZ applications)

01 = Chopped Sources without Low Pass Filter

(low noise, no 50/60Hz rejection, recommended for BioZ applications

with digital LPF, possibly battery powered BioZ applications)

10 = Chopped Sources with Low Pass Filter

CG_

MODE[1:0]

D[13:12]

00

(low noise, excellent 50/60Hz rejection)

11 = Chopped Sources with Resistive CM Setting

(Not recommended to be used for drive currents >32µA)

(low noise, excellent 50/60Hz rejection, lower input impedance)

BIOZ Modulated Resistance Built-In-Self-Test (RMOD BIST) Mode Enable

0 = RMOD BIST Disabled

1 = RMOD BIST Enabled

D[11]

EN_BIST

0

To avoid body interference, the BIP/N switches should be open in this mode.

When enabled, the DRVP/N isolation switches are opened and the DRVP/N-to-BIP/N

internal switches are engaged. Also, the lead bias resistors are applied to the BIOZ

inputs in 200MΩ mode.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 22. CNFG_BMUX (0x17) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

BIOZ RMOD BIST Nominal Resistance Selection

See RMOD BIST Settings Table for details.

D[10:8]

RNOM[2:0]

000

BIOZ RMOD BIST Modulated Resistance Selection (See RMOD BIST Settings table

for details.)

000 = Modulated Resistance Value 0

D[6:4]

RMOD[2:0]

100

001 = Modulated Resistance Value 1

010 = Modulated Resistance Value 2

011 = Reserved, Do Not Use

1xx = All SWMOD Switches Open - No Modulation (DC value = RNOM)

BIOZ RMOD BIST Frequency Selection

Calibration Source Frequency Selection (FCAL)

13

00 = f

01 = f

10 = f

11 = f

/2

(Approximately

(Approximately 1/4 Hz)

(Approximately 1/16 Hz)

4 Hz)

1 Hz)

MSTR

15

17

D[1:0]

FBIST[1:0]

00

19

/2

MSTR

Actual frequencies are determined by FMSTR selection (see CNFG_GEN for details),

approximate frequencies are based on a 32,768 Hz clock (FMSTR[1:0]=00). All

selections use 50% duty cycle.

Table 23. CNFG_BMUX (0x17) RMOD BIST Settings

NOMINAL RESISTANCE

MODULATED RESISTANCE

RNOM[2:0]

RMOD[2:0]

(Ω)

(mΩ)

000

001

010

1xx

2960.7

980.6

247.5

000

5000

2500

1667

Unmodulated

000

001

010

1xx

740.4

245.2

61.9

001

010

Unmodulated

000

001

010

1xx

329.1

109.0

27.5

Unmodulated

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 23. CNFG_BMUX (0x17) RMOD BIST Settings (continued)

RNOM[2:0]

AND SWNOM

SWITCHES ENGAGED

NOMINAL RESISTANCE

MODULATED RESISTANCE

RMOD[2:0]

(Ω)

(mΩ)

000

001

1xx

185.1

61.3

Unmodulated

011

100

101

110

111

1250

000

001

1xx

118.5

39.2

Unmodulated

1000

833

714

625

000

001

1xx

82.3

27.2

Unmodulated

000

001

1xx

60.5

20.0

Unmodulated

000

001

1xx

46.3

15.3

Unmodulated

CNFG_BIOZ(0x18)

CNFG_BIOZ is a read/write register which configures the operation, settings, and function of the BIOZ channel, including

the associated modulated current generator. Anytime a change to CNFG_BIOZ is made, there may be discontinuities in

the BIOZ record and possibly changes to the size of the time steps recorded in the BIOZ FIFO. The SYNCH command

can be used to restore internal synchronization resulting from configuration changes.

Table 24. CNFG_BIOZ (0x18) Register Map

REG

NAME

R/W

23/15/7

22/14/6

21/13/5

20/12/4

19/11/3

18/10/2

17/9/1

16/8/0

EXT_

RBIAS

RATE

AHPF[2:0]

LN_BIOZ

GAIN[1:0]

CNFG_

BIOZ

0x18

R/W

DHPF[1:0]

CGMON

DLPF[1:0]

CGMAG[2:0]

FCGEN[3:0]

PHOFF[3:0]

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 25. CNFG_BIOZ (0x18) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

BIOZ Data Rate (also dependent on FMSTR selection, see CNFG_GEN):

FMSTR = 00: f

0 = 64sps

1 = 32sps

= 32,768Hz

= 32,000Hz

= 32,000 Hz

= 31,968 Hz

MSTR

FMSTR = 01: f

0 = 62.50sps

1 = 31.25sps

D[23]

RATE

0

FMSTR = 10: f

0 = 50sps

1 = 25sps

FMSTR = 11: f

0 = 49.95sps

1 = 24.98sps

BIOZ Channel Analog High-Pass Filter Cutoﬀ Frequency and Bypass

000 = 125Hz

001 = 300Hz

010 = 800Hz

D[22:20]

AHPF[2:0]

010

011 = 2000Hz

100 = 3700Hz

101 = 7200Hz

11x = Bypass AHPF

External Resistor Bias Enable

0 = Internal Bias Generator used

1 = External Bias Generator used

Note: Use of the external resistor bias will improve the temperature coeﬃcient of all

biases within the product, but the main beneﬁt is improved control of BIOZ current

generator magnitude. If enabled, the user must include the required external resistor

between RBIAS and GND, and the temperature coeﬃcent achieved will be determined

by the combined performance of the internal bandgap and the external resistor.

D[19]

EXT_RBIAS

0

BIOZ Channel Instrumentation Ampliﬁer (INA) Power Mode

0 = BIOZ INA is in low power mode

1 = BIOZ INA is in low noise mode

D[18]

LN_BIOZ

GAIN[1:0]

0

BIOZ Channel Gain Setting

00 = 10V/V

01 = 20V/V

D[17:16]

00

10 = 40V/V

11 = 80V/V

BIOZ Channel Digital High-Pass Filter Cutoﬀ Frequency

00 = Bypass (DC)

01 = 0.05Hz

D[15:14]

DHPF[1:0]

00

1x = 0.50Hz

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 25. CNFG_BIOZ (0x18) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

BIOZ Channel Digital Low-Pass Filter Cutoﬀ Frequency

00 = Bypass (Decimation only, no FIR ﬁlter)

01 = 4Hz

10 = 8Hz

D[13:12]

DLPF[1:0]

01

11 = 16Hz (Available for 64, 62.5, 50, and 49.95sps BIOZ Rate selections only)

Note: See Table 39 below. If an unsupported DLPF setting is speciﬁed, the 4Hz

setting (DLPF[1:0] = 01) will be used internally; the CNFG_BIOZ register will continue

to hold the value as written, but return the eﬀective internal value when read back.

BIOZ Current Generator Modulation Frequency

0000 = 4*f

0001 ≈ 2*f

(approximately 128000Hz) 1000 = f

/64 (approximately 500Hz)

/128 (approximately 250Hz)

/256 (approximately 125Hz)

MSTR

(approximately 80000Hz) 1001 = f

(approximately 40000Hz) 101x = f

MSTR

0010 ≈ f

0011 ≈ f

MSTR

/2

(approximately 18000Hz) 11xx = f /256 (approximately 125Hz)

MSTR

D[11:8]

FCGEN[3:0]

1000

0100 = f

0101 = f

0110 = f

/4

/8

(approximately 8000Hz)

(approximately 4000Hz)

MSTR

/16 (approximately 2000Hz)

/32 (approximately 1000Hz)

0111 = f

MSTR

Actual frequencies determined by FMSTR selection, see CNFG_GEN register and

table below for details.

BIOZ Current Generator Monitor

0 = Current Generator Monitors disabled

1 = Current Generator Monitors enabled, requires active BIOZ channel and Current

Generators. Enables BCGMON interrupt and status bit behavior. Monitors current

source compliance levels, useful in detecting DRVP/DRVN lead oﬀ conditions with 4

electrode BIOZ applications.

D[7]

CGMON

0

BIOZ Current Generator Magnitude

000 = Oﬀ (DRVP and DRVN ﬂoating, Current Generators Oﬀ)

001 = 8µA

010 = 16µA

011 = 32µA

D[6:4]

CGMAG[2:0]

000

100 = 48µA

101 = 64µA

110 = 80µA

111 = 96µA

See Table 40 and 41 below for a list of allowed CGMAG settings vs. FCGEN

selections.

BIOZ Current Generator Modulation Phase Oﬀset

Phase Resolution and Oﬀset depends on FCGEN setting:

D[3:0]

PHOFF[3:0]

0000

FCGEN[3:0] ≥ 0010: Phase Oﬀset = PHOFF[3:0]*11.25° (0 to 168.75°)

FCGEN[3:0] = 0001: Phase Oﬀset = PHOFF[3:1]*22.50° (0 to 157.50°)

FCGEN[3:0] = 0000: Phase Oﬀset = PHOFF[3:2]*45.00° (0 to 135.00°)

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 26. Supported RATE and DLPF Options

DLPF[1:0] / Digital LPF Cut Oﬀ

CNFG_GEN

FMSTR[1:0]

RATE

Sample Rate

00

01

10

11

0 = 64sps

1 = 32sps

16.384Hz

4.096Hz

16.0Hz

4.0Hz

00 = 32,768Hz

01 = 32,000Hz

10 = 32,000Hz

11 = 31,968Hz

Bypass

4.096Hz

8.192Hz

0 = 62.5sps

1 = 31.25sps

0 = 50sps

Bypass

4.0Hz

8.0Hz

16.0Hz

4.0Hz

1 = 25sps

0 = 49.95sps

1 = 25.98sps

15.984Hz

3.996Hz

7.992Hz

Note: Combinations shown in grey are unsupported and will be internally mapped to the default settings shown.

Table 27. Actual BIOZ Current Generator Modulator Frequencies vs.

FMSTR[1:0] Selection

BIOZ Current Generator Modulation Frequency (Hz)

FCGEN[3:0]

FMSTR[1:0] = 00

= 32,768Hz

FMSTR[1:0] = 01

= 32,000Hz

FMSTR[1:0] = 10

= 32,000Hz

FMSTR[1:0] = 11

f

= 31,968Hz

MSTR

0000

0001

131,072

81,920

40,960

18,204

8,192

4,096

2,048

1,024

512

128,000

80,000

40,000

17,780

8,000

4,000

2,000

1,000

500

128,000

80,000

40,000

17,780

8,000

4,000

2,000

1,000

500

127,872

81,920

40,960

18,204

7,992

3,996

1,998

999

0010

0011

0100

0101

0110

0111

1000

500

1001

256

250

101x, 11xx

128

125

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Table 28. Allowed CGMAG Option vs. FCGEN Selections

APPROXIMATE CURRENT

GENERATOR

MODULATION FREQUENCY (Hz)

CURRENT GENERATOR

MAGNITUDE

CGMAG[2:0]

OPTIONS ALLOWED

FCGEN[3:0]

OPTIONS ALLOWED (µA

)

P-P

0000

0001

0010

0011

12,8000

80,000

40,000

18,000

All

0100

8,000

All except 111

All except 96

0101

0110

4,000

2,000

1,000

500

000, 001, 010, 011

000, 001, 010

Oﬀ, 8, 16, 32

Oﬀ, 8, 16

0111

1000

000, 001

Oﬀ, 8

1001

250

101x, 11xx

125

FIFO Memory Description

The device provides read only FIFO memory for BIOZ information. The operation of this FIFO memory is detailed in the

following sections.

Table 29 summarizes the method of access and data structure within the FIFO memory.

Table 29. FIFO Memory Access and Data Structure Summary

DATA STRUCTURE (D[23:0])

FIFO

AND

REG

MODE

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

BIOZ

Burst

BTAG

[2:0]

0x22

0x23

BIOZ Sample Voltage Data [19:0]

0

BTAG

[2:0]

BIOZ

0

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

If the write pointer ever traverses the entire FIFO array

and catches up to the read pointer (due to failure of the

µC to read/maintain FIFO data), a FIFO overflow will

occur and data will be corrupted. The BOVF STATUS

and tag bits will indicate this condition and the FIFO

should be cleared before continuing measurements using

either a SYNCH or FIFO_RST command—note overflow

events will result in the loss of samples and thus timing

information, so these conditions should not occur in well-

designed applications.

BIOZ FIFO Memory (8 Words x 24 Bits)

The BIOZ FIFO memory is a standard circular FIFO

consisting of 8 words, each with 24 bits of information.

The BIOZ FIFO is independently managed by internal

read and write pointers. The read pointer is updated in

response to the 32nd SCLK rising edge in a normal mode

read back transaction and on the (32 + n x 24)th SCLK

rising edge(s) in a burst mode transaction where n = 0 to

up to 31. Once a FIFO sample is marked as read, it can-

not be accessed again.

Do not read beyond the last valid FIFO word to prevent

possible data corruption.

The write pointer is governed internally. To aide data

management and reduce µC overhead, the device pro-

vides a user-programmable BIOZ FIFO Interrupt Threshold

(BFIT[2:0]) governing the BIOZ Interrupt bit (BINT). This

threshold can be programmed with values from 1 to 8, rep-

resenting the number of unread BIOZ FIFO entries required

before the BINT bit will be asserted, alerting the µC that

there is a significant amount of data in the BIOZ FIFO ready

for read back (see MNGR_INT (0x04) for details).

BIOZ FIFO Data Structure

The data portion of the word contains the 20-bit BIOZ volt-

age information measured at the requested sample rate

in left justified two’s complement format. One bit is set to

0 and the remaining three bits of data hold important data

tagging information (see details in Table 30).

Table 30. BIOZ FIFO BIOZ Data Tags (BTAG[2:0] = D[2:0])

DATA

VALID

TIME

VALID

BTAG [2:0]

DESCRIPTION

RECOMMENDED USER ACTION

Log sample into BIOZ record and increment the time

step. Continue to read data from the BIOZ FIFO.

000

Valid Sample

Yes

?

Yes

Log sample into BIOZ record and increment the

Over/Under Range Sample time step. Determine if the data is valid or a lead oﬀ

001

010

condition. Continue to read data from the BIOZ FIFO.

Log sample into BIOZ record and increment the time

step. Suspend read of the BIOZ FIFO until more

samples are available.

Last Valid Sample

Yes

?

Yes

(EOF)

Log sample into BIOZ record and increment the

Last Over/Under Range

Sample (EOF)

time step. Determine if the data is valid or a lead oﬀ

condition. Suspend read of the BIOZ FIFO until more

samples are available.

011

10x

110

Unused

-

Discard this sample without incrementing the time

base. Suspend read of the BIOZ FIFO until more

samples are available.

FIFO Empty

(exception)

No

Discard this sample without incrementing the time

base. Issue a FIFO_RST command to clear the FIFOs

or re-SYNCH if necessary. Note the corresponding

halt and resumption in all the FIFOs.

FIFO Overﬂow

(exception)

111

No

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

thresholds (see MNGR_DYN and CNFG_GEN) and that

the voltage information in the sample should be evaluated

to see if it is valid or indicates a leads-off condition. Note

that while the voltage data may be invalid, samples of this

type do represent valid time steps in the BIOZ record.

This is also the last sample currently available in the BIOZ

FIFO (End-of-File, EOF). The µC should wait until further

samples are available before requesting more data from

the BIOZ FIFO.

BIOZ Data Tags (BTAG)

The final three bits in the sample are used as a data tag

(BTAG[2:0] = D[2:0]) to assist in managing data transfers.

The BTAG structure used is detailed below.

VALID: BTAG = 000 indicates that BIOZ data for this

sample represents both a valid voltage and time step in

the BIOZ record.

OVER or UNDER RANGE: BTAG = 001 indicates that

BIOZ data for this sample violated selected range thresh-

olds (see MNGR_DYN and CNFG_GEN) and that the

voltage information in the sample should be evaluated to

see if it is valid or indicative of a leads-off condition. Note

that while the voltage data may be invalid, samples of this

type do represent valid time steps in the BIOZ record.

EMPTY: BTAG = 110 is appended to any requested read

back data from an empty FIFO. The presence of this tag

alerts the user that this FIFO data does not represent a

valid sample or time step. Note that if handled properly

by the µC, an occurrence of an empty tag will not com-

promise the integrity of a continuous FIFO record – this

tag only indicates that the read back request was either

premature or unnecessary.

VALID EOF: BTAG = 010 indicates that BIOZ data for

this sample represents both a valid voltage and time

step in the BIOZ record, and that this is the last sample

currently available in the BIOZ FIFO (End-of-File, EOF).

The µC should wait until further samples are available

before requesting more data from the BIOZ FIFO.

OVERFLOW: BTAG = 111 indicates that the FIFO has

overflowed and that there are interruptions or missing data

in the sample records. The BIOZ Overflow (BOVF) bit is

also included in the STATUS register. A FIFO_RESET is

required to resolve this situation, effectively clearing the

FIFO so that valid sampling going forward is assured.

OVER or UNDER RANGE EOF: BTAG = 011 indicates

that BIOZ data for this sample violated selected range

Typical Application Circuit

1.1V to 2.0V

1.65V to 3.6V

10µF

0.1µF

10µF

0.1µF

AVDD

DVDD

OVDD

CSB

SDI

CSB

DRVP

MOSI

SCLK

MISO

INTB

INT2B

FCLK

47nF

47pF

SCLK

SDO

BIP

MCU

200Ω

10pF

ELECTRODES

MAX30002

INTB

INT2B

FCLK

BIN

DRVN

RBIAS

CPLL

47nF

324kΩ

1nF

AGND

VCM

VBG

VREF

DGND

10µF

1µF

10µF

Figure 9. Two-Electrode Respiration Monitor Typical Application Circuit

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Four Electrode Respiration

Monitoring Application

See Figure 11 for an example of a clinical application

for monitoring respiration using four electrodes and with

optional defibrillation protection circuitry. The electrode

models are shown to illustrate the electrical characteristics

of the physical electrodes.

Application Diagrams

See Figure 10 for an example of a clinical application

for monitoring respiration using just two electrodes and

with optional shared defibrillation protection circuitry. The

electrode models are shown to illustrate the electrical

characteristics of the physical electrodes.

PCB

DRVP

47nF

C_E=5nF

R_S=100Ω

R_P1

R_P2

BIP

1kΩ

200Ω

10pF

R_E=1MΩ

R_BODY

100Ω

PHYSICAL

ELECTRODES

DEFIB

ELECTRODE MODELS

47pF

MAX30002

BIN

PROTECTION

C_E=5nF

R_S=100Ω

R_P1

R_P2

1kΩ

200Ω

R_E=1MΩ

47nF

DRVN

Figure 10. Two Electrode Respiration Monitoring with Optional Common Defibrillation Protection.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

PCB

C_E=5nF

R_S=100Ω

R_DP1

1kΩ

R_DP2

DRVP

200Ω

47nF

R_E=1MΩ

C_E=5nF

R_S=100Ω

R_BP1

1kΩ

R_BP2

BIP

200Ω

10pF

R_E=1MΩ

R_BODY

100Ω

PHYSICAL

ELECTRODES

DEFIB

PROTECTION

ELECTRODE MODELS

47pF

MAX30002

C_E=5nF

R_S=100Ω

R_BP1

R_BP2

BIN

1kΩ

200Ω

R_E=1MΩ

C_E=5nF

R_S=100Ω

R_DP1

1kΩ

R_DP2

47nF

DRVN

200Ω

R_E=1MΩ

Figure 11. Four Electrode Respiration Monitoring with Optional Defibrillation Protection.

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MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Ordering Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PART

TEMP RANGE

PIN-PACKAGE

28 TQFN-EP**

30WLP

MAX30002CTI+*

MAX30002CTI+T*

MAX30002CWV+

MAX30002CWV+T

0ºC TO +70ºC

30WLP

PACKAGE PACKAGE

OUTLINE

NO.

LAND PATTERN

NO.

TYPE

CODE

+Denotes lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*Future product. Contact factory for availability.

**EP = Exposed pad.

28-TQFN

T2855+8

21-0140

90-0028

Refer to

Application

Note 1891

30 WLP

W302L2+1

21-100074

Chip Information

PROCESS: CMOS

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www.maximintegrated.com

MAX30002

Ultra-Low-Power, Single-Channel Integrated

Bioimpedance (BioZ) AFE

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

3/18

Initial release

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For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2018 Maxim Integrated Products, Inc.

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型号：	MAX30002CWV+T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Ultra-Low-Power, Single-Channel Integrated Bioimpedance (BioZ) AFE
文件：	总44页 (文件大小：949K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX30002CWV+T [MAXIM]

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