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Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

MAX30003

General Description

Beneﬁts and Features

● Clinical-Grade ECG AFE with High-Resolution Data

The MAX30003 is a complete, biopotential, analog front-

end solution for wearable applications. It offers high

performance for clinical and fitness applications, with

ultra-low power for long battery life. The MAX30003 is a

single biopotential channel providing ECG waveforms and

heart rate detection.

Converter

• 15.5 Bits Eﬀective Resolution with 5µV

Noise

P-P

● Better Dry Starts Due to Much Improved Real World

CMRR and High Input Impedance

• Fully Diﬀerential Input Structure with CMRR > 100dB

The biopotential channel has ESD protection, EMI filtering,

internal lead biasing, DC leads-off detection, ultra-low

power leads-on detection during standby mode, and extensive

calibration voltages for built-in self-test. Soft power-up

sequencing ensures no large transients are injected into

the electrodes. The biopotential channel also has high

input impedance, low noise, high CMRR, programmable

gain, various low-pass and high-pass filter options, and

● Offers Better Common-Mode to Differential Mode

Conversion Due to High Input Impedance

• High Input Impedance > 500MΩ for Extremely Low

Common-to-Diﬀerential Mode Conversion

● Minimum Signal Attenuation at the Input During Dry

Start Due to High Electrode Impedance

● High DC Offset Range of ±650mV (1.8V, typ) Allows

to Be Used with Wide Variety of Electrodes

a

high resolution analog-to-digital converter. The

biopotential channel is DC coupled, can handle large

electrode voltage offsets, and has a fast recovery mode

to quickly recover from overdrive conditions, such as

defibrillation and electrosurgery.

● High AC Dynamic Range of 65mV

Will Help the

P-P

AFE Not Saturate in the Presence of Motion/Direct

Electrode Hits

● Longer Battery Life Compared to Competing Solutions

• 85µW at 1.1V Supply Voltage

The MAX30003 is available in a 28-pin TQFN and

30-bump wafer-level package (WLP), operating over the

0°C to +70°C commercial temperature range.

● Leads-On Interrupt Feature Allows to Keep µC in

Deep Sleep Mode with RTC Off Until Valid Lead

Condition is Detected

Applications

● Single-Lead Event Monitors for Arrhythmia Detection

● Single-Lead Wireless Patches for At-Home/

In-Hospital Monitoring

● Chest Band Heart Rate Monitors for Fitness Applications

● Bio Authentication and ECG-On-Demand Applications

• Lead-On Detect Current: 0.7µA (typ)

● Built-In Heart Rate Detection with Interrupt Feature

Eliminates the Need to Run HR Algorithm on the

µController

• Robust R-R Detection in High Motion Environment

at Extremely Low Power

● Conﬁgurable Interrupts Allows the µC Wake-Up Only on

Ordering Information appears at end of data sheet.

Every Heart Beat Reducing the Overall System Power

● High Accuracy Allows for More Physiological Data

Extractions

● 32-Word FIFO Allows You to Wake Up µController

Every 256ms with Full ECG Acquisition

● High-Speed SPI Interface

● Shutdown Current of 0.5µA (typ)

19-8558; Rev 3; 9/21

©

One Analog Way, Wilmington, MA 01887 U.S.A.

|

Tel: 781.329.4700

|

MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Functional Diagram

AVDD

DVDD

OVDD

MAX30003

ECG CHANNEL

AAF

ECGP

ECGN

ESD, EMI,

INPUT MUX ,

DC LEAD

CSB

18-BIT

Σ∆

ADC

DECIMATION

FILTER

INPUT

AMP

PGA

SDI

CHECK

f

_-3dB= 600Hz

-40dB/dec

SPI INTERFACE ,

FIFO, AND SETUP

REGISTERS

SCLK

SDO

INTB

INT2B

R TO R

DETECTOR

FAST

SETTLING

CAPP

CAPN

SUPPORT CIRCUITRY

COMMON-MODE

BUFFER

f

HFC

FCLK

INPUT

AMP

SEQUENCER

BANDGAP

BIASING

PLL

f

CLK

AGND

RBIAS

CPLL

V

REF

CM

BG

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Absolute Maximum Ratings

AV

to AGND.....................................................-0.3V to +2.0V

Continuous Power Dissipation (T = +70°C)

A

DD

DV

AV

to DGND ....................................................-0.3V to +2.0V

28-Pin TQFN (derate 34.5mW/°C above +70°C)...2758.6mW

30-Bump WLP (derate 24.3mW/°C

DD

to DV ......................................................-0.3V to +0.3V

DD

OV

to DGND....................................................-0.3V to +3.6V

above +70°C).....................................................1945.5mW

Operating Temperature Range...............................0°C to +70°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65ºC to +150°C

Lead Temperature (Soldering, 10sec).............................+300°C

Soldering Temperature (reflow).......................................+260°C

DD

AGND to DGND ...................................................-0.3V to +0.3V

CSB, SCLK, SDI, FCLK to DGND .......................-0.3V to +3.6V

SDO, INTB, INT2B to

DGND.............-0.3V to the lower of (3.6V and OV

All other pins to

+ 0.3V)

DD

AGND ..............-0.3V to the lower of (2.0V and AV

+ 0.3V)

DD

Maximum Current into Any Pin.........................................±50mA

(Note 1)

Package Thermal Characteristics

TQFN

WLP

Junction-to-Ambient Thermal Resistance (θ ) ..........29°C/W

Junction-to-Ambient Thermal Resistance (θ ) ..........44°C/W

JA

Junction-to-Case Thermal Resistance (θ ).................2°C/W

JC

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V

= +2.5V, T = +25°C.) (Note 2)

DVDD

AVDD

OVDD

A

PARAMETER

ECG CHANNEL

SYMBOL

CONDITIONS

MIN

-15

TYP

MAX

+15

UNITS

V

= +1.1V, THD < 0.3%

= +1.8V, THD < 0.3%

AVDD

AC Diﬀerential Input Range

DC Diﬀerential Input Range

mV

p-p

±32.5

±650

= +1.1V, shift from nominal gain < 2%

= +1.8V

-300

+300

mV

V

AVDD

= +1.1V, from V

, shift from

MID

-150

105

+150

nominal gain < 2%

Common Mode Input Range

mV

V

= +1.8V, from V

, shift from

AVDD

MID

±550

nominal gain < 2%

0W source impedance, f = 64Hz (Note 3)

115

77

Common Mode Rejection

Ratio

CMRR

dB

(Note 4)

0.82

µV

RMS

BW = 0.05 - 150Hz, G

= 20x

CH

5.4

0.53

3.5

µV

p-p

ECG Channel Input

Referred Noise

1.0

6.6

+1

RMS

BW = 0.05 - 40Hz, G

= 20x (Note 3)

CH

µV

p-p

Input Leakage Current

Input Impedance (INA)

T

= +25°C

-1

0.1

nA

A

Common-mode, DC

45

GΩ

MΩ

Diﬀerential, DC

1500

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V

= +2.5V, T = +25°C.) (Note 2)

DVDD

AVDD

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

G

= +1.80V, V = 65mV , F = 64Hz,

IN p-p IN

= 20x, electrode oﬀset = ±300mV

AVDD

0.025

ECG Channel Total

Harmonic Distortion

CH

THD

%

V

G

= +1.1V, V = 30mV , F = 64Hz,

IN p-p IN

= 20x, electrode oﬀset = ±300mV

AVDD

0.3

CH

ECG Channel Gain Setting

ECG Channel Gain Error

G

Programmable, see register map

20 to 160

V/V

%

CH

V

= +1.8V, G = 20x,

AVDD

CH

-2.5

-4.5

+2.5

+4.5

ECGP = ECGN = VMID

V

= +1.1V, G = 20x,

AVDD

CH

%

ECGP = ECGN = VMID

% of

FSR

ECG Channel Oﬀset Error

(Note 5)

0.1

ADC Resolution

18

Bits

ADC Sample Rate

Programmable, see register map

125 to 512

SPS

FHP = 1/(2R x R

capacitance between CAPP and CAPN

x C

), C

=

HPF

CAPP to CAPN Impedance

R

320

450

600

kΩ

HPF

Fast recovery enabled (1.8V)

Fast recovery enabled (1.1V)

Fast recovery disabled

160

55

Analog High-Pass Filter Slew

Current

µA

0.09

C

= 10µF, Note: varies by sample rate,

HPF

Fast Settling Recovery Time

Digital Low-Pass Filter

500

ms

Hz

see Table 3.

DLPF[0:1] = 01

DLPF[0:1] = 10

DLPF[0:1] = 11

40

Linear phase

FIR ﬁlter.

100

150

0.5

Digital High-Pass Filter

ECG Power Supply Rejection

ECG INPUT MUX

Phase-corrected 1st-order IIR ﬁlter. DHPF = 1

Hz

dB

Lead bias disabled, DC

107

110

PSRR

Lead bias disabled, f

= 64Hz

SW

DCLOFF_IMAG[2:0] = 001

DCLOFF_IMAG[2:0] = 010

DCLOFF_IMAG[2:0] = 011

DCLOFF_IMAG[2:0] = 100

DCLOFF_IMAG[2:0] = 101

5

10

Pullup/

pulldown

DC Lead Oﬀ Check

nA

20

50

100

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V

= +2.5V, T = +25°C.) (Note 2)

DVDD

AVDD

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

DCLOFF_VTH[1:0] = 11 (Note 6)

DCLOFF_VTH[1:0] = 10 (Note 7)

DCLOFF_VTH[1:0] = 01 (Note 8)

DCLOFF_VTH[1:0] = 00

MIN

TYP

- 0.50

MAX

UNITS

V

MID

- 0.45

- 0.40

- 0.30

+ 0.50

+ 0.45

+ 0.40

+ 0.30

DC Lead Oﬀ Comparator Low

Threshold

V

DCLOFF_VTH[1:0] = 11 (Note 6)

DCLOFF_VTH[1:0] = 10 (Note 7)

DCLOFF_VTH[1:0] = 01 (Note 8)

DCLOFF_VTH[1:0] = 00

V

DC Lead Oﬀ Comparator

High Threshold

V

RBIASV[1:0] = 00

50

Lead bias

enabled

Lead Bias Impedance

RBIASV[1:0] = 01

RBIASV[1:0] = 10

100

200

MΩ

V

/

AVDD

2.15

Lead Bias Voltage

V

Lead bias enabled

Single-ended

V

MID

VMAG = 0

VMAG = 1

0.25

0.50

Calibration Voltage

Magnitude

mV

Calibration Voltage

Magnitude Error

Single-ended (Note 9)

-2

+2

%

Calibration Voltage

Frequency

0.0156

to 256

Programmable, see register map

Hz

0.03052

to 62.474

FIFTY = 0

ms

Calibration Voltage Pulse

Time

Programmable,

see register map

FIFTY = 1

50

%

INTERNAL REFERENCE/COMMON-MODE

V

Output Voltage

V

0.650

100

V

BG

Output Impedance

kΩ

External V

Capacitor

Compensation

BG

C

1

µF

V

VBG

V

Output Voltage

V

T

= +25°C

0.995

1.000

10

1.005

REF

A

Temperature Coeﬃcient

Buﬀer Line Regulation

Buﬀer Load Regulation

TC

= 0°C to +70°C

ppm/°C

µV/V

µV/µA

REF

330

25

I

= 0 to 100µA

LOAD

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V

= +2.5V, T = +25°C.) (Note 2)

DVDD

AVDD

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

10

MAX

UNITS

µF

External V

Compensation

REF

C

1

REF

Capacitor

V

Output Voltage

V

0.650

10

V

CM

External V

Capacitor

Compensation

CM

C

1

µF

CM

DIGITAL INPUTS (SDI, SCLK, CSB, FCLK)

0.7 ×

Input-Voltage High

Input-Voltage Low

Input Hysteresis

V

IH

V

OVDD

0.3 ×

V

IL

V

OVDD

0.05 ×

V

HYS

V

OVDD

Input Capacitance

Input Current

C

10

pF

IN

I

-1

+1

µA

IN

DIGITAL OUTPUTS (SDO, INTB, INT2B)

V

– 0.04

OVDD

Output Voltage High

V

I

= 1mA

SOURCE

V

OH

Output Voltage Low

V

= 1mA

SINK

0.4

+1

V

OL

Three-State Leakage Current

-1

µA

Three-State Output

Capacitance

15

pF

POWER SUPPLY

Analog Supply Voltage

Digital Supply Voltage

Interface Supply Voltage

V

Connect V

to V

DVDD

1.1

2.0

3.6

V

AVDD

DVDD

OVDD

AVDD

DVDD

V

to V

AVDD

Power for I/O drivers only

1.65

V

= V

= +1.1V

= +1.8V

= +2.0V

76

AVDD

DVDD

ECG

channel

100

109

0.98

0.73

I

+

AVDD

I

Supply Current

120

2.5

µA

DVDD

T

= +70°C

= +25°C

A

ULP Lead

On Detect

V

= +1.65V, ECG channel at 512sps

OVDD

0.2

0.6

(Note 10)

Interface Supply Current

I

OVDD

V

= +3.6V, ECG channel at 512sps

OVDD

1.6

(Note 10)

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V

= +2.5V, T = +25°C.) (Note 2)

DVDD

AVDD

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

0.79

0.51

MAX

UNITS

V

= 2.0V

(Note 5)

= V

DVDD

AVDD

T = +70°C

A

I

+

SAVDD

I

SDVDD

Shutdown Current

µA

T

= +25°C

2.5

1.1

A

I

V

= +3.6V, V

= V

= +2.0V

SOVDD

OVDD

AVDD

DVDD

ESD PROTECTION

IEC61000-4-2 Contact Discharge (Note 11)

IEC61000-4-2 Air-Gap Discharge (Note 11)

HMM

±8

±15

±8

ECGP, ECGN

kV

Timing Characteristics

(V

V

= V

= +1.8V, V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DVDD

AVDD

OVDD

A

MIN

= +2.5V, T = +25°C.) (Notes 2, 3)

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS

SCLK Frequency

f

0

12

MHz

ns

SCLK

SCLK Period

t

83

15

CP

CH

SCLK Pulse Width High

SCLK Pulse Width Low

t

ns

t

ns

CL

CSB Fall to SCLK Rise

Setup Time

t

To 1st SCLK rising edge (RE)

15

0

ns

CSS0

CSH0

CSH1

CSB Fall to SCLK Rise

Hold Time

t

Applies to inactive RE preceding 1st RE

Applies to 32nd RE, executed write

CSB Rise to SCLK Rise

Hold Time

10

15

Applies to 32nd RE, aborted write

sequence

CSB Rise to SCLK Rise

t

CSA

SCLK Rise to CSB Fall

Applies to 32nd RE

100

20

8

ns

CSF

CSB Pulse-Width High

t

CSPW

SDI-to-SCLK Rise Setup Time

SDI to SCLK Rise Hold Time

t

DS

DH

t

8

C

= 20pf

40

20

LOAD

SCLK Fall to SDO Transition

SCLK Fall to SDO Hold

t

DOT

DOH

= 20pf, V

≥ 2.5V

= V

≥ 1.8V,

LOAD

AVDD

DVDD

ns

V

DVDD

t

C

= 20pf

2

LOAD

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Timing Characteristics (continued)

(V

V

= V

= +1.8V, V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DVDD

AVDD

OVDD

A

MIN

= +2.5V, T = +25°C.) (Notes 2, 3)

OVDD

A

PARAMETER

SYMBOL

CONDITIONS

= 20pf

MIN

TYP

MAX

30

UNITS

ns

CSB Fall to SDO Fall

CSB Rise to SDO Hi-Z

FCLK Frequency

t

Enable time, C

Disable time

DOE

LOAD

t

35

ns

DOZ

f

External reference clock

32.768

30.52

15.26

kHz

µs

FCLK

FCLK Period

t

FP

FH

FCLK Pulse-Width High

FCLK Pulse-Width Low

t

50% duty cycle assumed

µs

t

µs

FL

Note 2: Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are

A

guaranteed by design and characterization.

Note 3: Guaranteed by design and characterization. Not tested in production.

Note 4: One electrode drive with <10Ω source impedance, the other driven with 51kΩ in parallel with a 47nF per IEC60601-2-47.

Note 5: Inputs connected to 51kΩ in parallel with a 47nF to V

.

CM

Note 6: Use this setting only for V

Note 7: Use this setting only for V

Note 8: Use this setting only for V

= V

≥ 1.65V.

≥ 1.55V.

≥ 1.45V.

AVDD

DVDD

Note 9: This specification defines the accuracy of the calibration voltage source as applied to the ECG input, not as measured

through the ADC channel.

Note 10: f

= 4MHz, burst mode, EFIT = 8, C

= C

= 50pF.

SCLK

SDO

INTB

Note 11: ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.

SDI

A6

A5

t_DS

A4

A3

t_DH

A2

t_CP

A1

A0

R/WB D_IN23 D_IN22

D_IN1

D_IN0

A6'

SCLK

1

2

3

4

5

6

7

8

9

10

31

32

1'

t_CSA

t_CSH0

t_CH

t_CSH1

t_CSS0

t_CL

CSB

SDO

t_CSPW

Z

t_DOT

t_DOH

t_CSF

Z

D_O23

D_O22

D_O1

D_O0

t_DOZ

t_DOE

Figure 1a. SPI Timing Diagram

t_FP

FCLK

t_FH

t_FL

Figure 1b. FCLK Timing Diagram

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Typical Operating Characteristics

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

OVDD A

DVDD

AVDD

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Typical Operating Characteristics (continued)

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Typical Operating Characteristics (continued)

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Typical Operating Characteristics (continued)

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Pin Conﬁgurations

TEXTOP VIEW

(BUMP SIDE DOWN)

MAX30003

TOP VIEW

1

2

3

4

5

6

21 20 19 18 17 16 15

+

I.C.

ECGP

ECGN

22

23

24

25

26

27

28

14

AVDD

VREF

I.C.

FCLK

13 DVDD

12

A

B

VBG

VCM

I.C.

AGND

OVDD

SDO

AGND

SDI

CAPN

DGND

FCLK

SCLK

CAPP

CPLL

DVDD

CSB

DGND

11 CPLL

MAX30003

VCM

I.C.

10

9

CAPN

CAPP

AGND

VBG

AGND

*EP

C

8

VREF

AVDD

INTB

INT2B

1

2

3

4

5

6

7

D

E

TQFN

(5mm x 5mm)

*CONNECT EP TO AGND

WLP

(2.74mm x 2.9mm)

Pin Description

BUMP

WLP

NAME

FUNCTION

TQFN

1, 2, 4, 5, 24,

26

A1, A2, A3,

A4, B2, C2

I.C.

Internally Connected. Connect to AGND.

B3, B4, C3,

C4, D4

Analog Power and Reference Ground. Connect into the printed circuit board

ground plane.

3,8,28

AGND

6

7

A5

A6

ECGP

ECGN

ECG Positive Input

ECG Negative Input

Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (CHPF) between CAPP

and CAPN to form a 0.5Hz high-pass response in the ECG channel.

9

B6

CAPP

Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (CHPF) between CAPP

and CAPN to form a 0.5Hz high-pass response in the ECG channel.

10

11

12

13

B5

C6

C5

D6

CAPN

CPLL

PLL Loop Filter Input. Connect 1nF COG cap between CPLL and AGND.

Digital Ground for Both Digital Core and I/O Pad Drivers. Recommended to connect

to AGND plane.

DGND

DVDD

Digital Core Supply Voltage. Connect to AVDD

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Pin Description (continued)

BUMP

WLP

NAME

FUNCTION

TQFN

External 32.768kHz Clock that Controls the Sampling of the Internal Sigma-Delta

Converters and Decimator.

14

D5

FCLK

15

16

E6

E5

CSB

Active-Low Chip-Select Input. Enables the serial interface.

SCLK

Serial Clock Input. Clocks data in and out of the serial interface when CSB is low.

Serial Data Input. SDI is sampled into the device on the rising edge of SCLK when

CSB is low.

17

E4

SDI

Serial Data Output. SDO will change state on the falling edge of SCLK when CSB

is low. SDO is three-stated when CSB is high.

18

19

20

E3

D3

E2

SDO

OVDD

INT2B

Logic Interface Supply Voltage

Interrupt 2 Output. INT2B is an active-low status output. It can be used to interrupt

an external device.

Interrupt Output. INTB is an active low status output. It can be used to interrupt an

external device.

21

22

23

D2

E1

D1

INTB

AVDD

Analog Core Supply Voltage. Connect to DVDD.

ADC Reference Buﬀer Output. Connect a 10μF X5R ceramic capacitor between

V

REF

V

and AGND.

REF

Common Mode Buﬀer Output. Connect a 10μF X5R ceramic capacitor between

and AGND.

25

C1

V

CM

V

CM

Bandgap Noise Filter Output. Connect a 1.0μF X7R ceramic capacitor between

and AGND.

27

B1

—

V

BG

V

BG

EP

—

Exposed Paddle. Connect to AGND.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Input MUX

Detailed Description

The ECG input MUX shown in Figure 3 contains integrated

ESD and EMI protection, DC leads off detect current

sources, lead-on detect, series isolation switches, lead

biasing, and a programmable calibration voltage source

to enable channel built in self-test.

ECG Channel

Figure 2 illustrates the ECG channel block diagram,

excluding the ADC. The channel comprises an input

MUX, a fast-recovering instrumentation amplifier, an anti-

alias filter, and a programmable gain amplifier. The MUX

includes several features such as ESD protection, EMI

filtering, lead biasing, leads off checking, and ultra-low

power leads-on checking. The output of this analog channel

drives a high-resolution ADC.

EMI Filtering and ESD Protection

EMI filtering of the ECGP and ECGN inputs consists of a

single pole, low pass, differential, and common mode filter

with the pole located at approximately 2MHz. The ECGP

and ECGN inputs also have input clamps that protect the

inputs from ESD events.

PCB

AAF

ECGP

INPUT MUX/

DC LEAD

CHECK

INPUT

AMP

PGA

ECGN

f_-3dB= 600Hz

-40dB/dec

FAST

SETTLING

MAX30003

CAPP

C_HPF

CAPN

Figure 2. ECG Channel Input Amplifier and PGA Excluding the ADC

MAX30003

ULP

LEAD-ON

CHECK

ESD AND EMI FILTER

DC LEAD -OFF CHECK

LEAD BIAS

CAL VOLTAGE

V_DD

V_MID

~50-

200 MΩ

± 0.25mV,

± 0.50mV

>20 MΩ

GND

5-100nA

TO ECG

INA IP

GND

ECGP

ECGN

TO ECG

INA IN

5-100nA

GND

~50-

200 MΩ

± 0.25mV,

± 0.50mV

GND

V_DD

V_MID

GND

Figure 3. ECG Input MUX

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

● ±8kV using the Contact Discharge method specified

in IEC61000-4-2 ESD

V_DD

● ±15kV using the Air Gap Discharge method specified

in IEC61000-4-2 ESD

● ±8kV HBM

VTH_H

V_MID

ECGP,N

● For IEC61000-4-2 ESD protection, use 1kΩ series

resistors on ECGP and ECGN that is rated to with-

stand 8kV surge voltages.

VTH_L

VSS

ABOVE

BELOW

THRESHOLD

DC Leads-Oﬀ Detection and ULP Leads-On Detection

>115ms

<115ms

The input MUX leads-off detect circuitry consists of

programmable sink/source DC current sources that allow

for DC leads-off detection, while the channel is powered

up in normal operation and an ultra-low-power (ULP)

leads-on detect while the channel is powered-down.

INTB

LDOFF_*H

BITS

ASSERTED

Figure 4. Lead-Off Detect Behavior

The MAX30003 accomplishes DC leads-off detection by

applying a DC current to pull the ECG input voltage up

electrodes within the input common mode requirements

of the ECG channel and can drive the connected body

to the proper common mode voltage level. See register

CNFG_GEN (0x10) to select a configuration.

to above V

+ V

or down to below V

- V . The

MID TH

MID

TH

current sources have user selectable values of 0nA, 5nA,

10nA, 20nA, 50nA, and 100nA that allow coverage of dry

and wet electrode impedance ranges. Supported thresholds

are V

± 0.30V (recommended), V

± 0.40V, V ±

Isolation Switches

MID

0.45V, and V

and 500mV should only be used when V

± 0.50V. A threshold of 400mV, 450mV,

MID

The series switches in the MAX30003 isolate ECGP and

ECGN pins (subject) from the internal signal path. the

series switches are disabled by default. They must be

enabled to record ECG.

≥ 1.45V,

AVDD

1.55V, and 1.65V, respectively. A dynamic comparator

protects against false flags generated by the input amplifier

and input chopping. The comparator checks for a minimum

continuous violation (or threshold exceeded) of 115ms to

140ms depending on the setting of FMSTR[1:0] before

asserting any one of the LDOFF_* interrupt flags (Figure

4). See registers CNFG_GEN (0x10) and CNFG_EMUX

0x14) for configuration settings and see Table 1 for

recommended values given electrode type and supply voltage.

The ULP lead on detect operates by pulling ECGN low with

a pulldown resistance larger than 5mΩ and pulling ECGP

highwithapullupresistancelargerthan15MΩ.Alow-power

comparator determines if ECGP is pulled below a

predefined threshold that occurs when both electrodes

make contact with the body. When the impedance

between ECGP and ECGN is less than 20mΩ, an interrupt

LONINT is asserted, alerting the µC to a leads-on condition.

Calibration Voltage Sources

Calibration voltage sources are available to provide

±0.25mV (0.5mV ) or ±0.5mV (1.0mV ) inputs to

P-P

the ECG channel with programmable frequency and duty

cycle. The sources can be unipolar/bipolar relative to V

.

MID

Figure 5 illustrates the possible calibration waveforms.

Frequency selections are available in 4X increments from

15.625mHz to 256Hz with selected pulse widths varying

from 30.5µs to 31.723ms and 50% duty cycle. Signals

can be single-ended, differential, or common mode. This

flexibility allows end-to-end channel-testing of the ECG

signal path.

When applying calibration voltage sources with the device

connected to a subject, the series input switches must be

disconnected so as not to drive signals into the subject.

See registers CNFG_CAL (0x12) and CNFG_EMUX

(0x14) to select configuration.

A 0nA/V

± 300mV selection is available allowing

MID

monitoring of the input compliance of the INA during non-

DC lead-off checks.

Lead Bias

The MAX30003 limits the ECGP and ECGN DC input

common mode range to V

±150mV. This range can be

MID

maintained either through external/internal lead-biasing.

Internal DC lead-biasing consists of 50MΩ, 100MΩ,

or 200MΩ selectable resistors to V

that drive the

MID

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 1. Recommended Lead Bias, Current Source Values,

and Thresholds for Electrode Impedance

ELECTRODES IMPEDANCE

I

V

DC

TH

100kΩ -

200kΩ

200kΩ -

400kΩ

400kΩ -

1MΩ

1MΩ -

2MΩ

2MΩ - 4

MΩ

4MΩ -

10MΩ

10MΩ -

20MΩ

<100kΩ

All settings of R

b

I

= 10nA

V

= V

DC

TH MID

± 300mV, ± 400mV

All settings

of R

b

V

=

TH

All settings of R

All settings of V

b

= 20nA

MID

TH

± 400mV, ±

450mV, ±

500mV

All settings

of R

b

All settings of R

V

=

b

TH

I

= 50nA

DC

All settings of V

TH

MID

± 450mV, ±

500mV

All settings

of Rb

V

=

TH

All settings of R

b

= 100nA

DC

MID

All settings of V

TH

± 400mV, ±

450mV, ±

500mV

CALIBRATION VOLTAGE SOURCE OPTIONS

V_MID+ 0.25mV

CAL_VMODE = 1

V_MID

V

+ 0.25mV

- 0.25mV

+ 0.50mV

MID

CAL_VMODE = 0

CAL_VMAG = 0

V_MID- 0.25mV

V_MID+ 0.50mV

V_MID

V

MID

V

MID

V

MID

VCALP

VCALN

CAL_VMODE = 0

CAL_VMAG = 1

CAL_VMODE = 1

CAL_VMAG = 1

V

MID

- 0.50mV

T

HIGH

T

CAL

Figure 5. Calibration Voltage Source Options

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

in the MNGR_DYN (0x05) register and accumulates the

time that the ADC output exceeds either the positive or

negative threshold. If the saturation counter exceeds

125ms, it triggers the fast settling mode (if enabled) and

resets. The saturation counter can also be reset prior to

triggering the fast settling mode if the ADC output falls

Gain Settings and Input Range

The device’s ECG channel contains an input instrumentation

amplifier that provides low-noise, fixed-gain amplification

of the differential signal, rejects differential DC voltage

due to electrode polarization, rejects common-mode

interference primarily due to AC mains interference, and

provides high input impedance to guarantee high CMRR

even in the presence of severe electrode impedance

mismatch (see Figure 2). The differential DC rejection

below the threshold continuously for 125ms (t

). This

BLW

feature is designed to avoid false triggers due to the

QRS complex. Once triggered, fast settling mode will

be engaged for 500ms, see Figure 6. ECG samples are

tagged if they were taken while fast settling mode was

asserted.

corner frequency is set by an external capacitor (C

)

HPF

placed between pins CAPP and CAPN, refer to Table 2 for

appropriate value selection. There are three recommended

options for the cutoff frequency: 4.4Hz, 0.4Hz, and 0.04Hz.

Setting the cutoff frequency to 4.4Hz provides the most

motion artifact rejection at the expense of ECG waveform

quality, making it best suited for heart rate monitoring.

For ambulatory applications requiring more robust ECG

waveforms with moderate motion artifact rejection, 0.4Hz

is recommended. Select 0.04Hz for patient monitoring

applications in which ECG waveform quality is the

primary concern and poor rejection of motion artifacts can

be tolerated. The high-pass corner frequency is calculated

by the following equation:

In manual mode, a user algorithm running on the host

microcontroller or an external stimulus input will generate

the trigger to enter fast recovery mode. The host

microcontroller then enables the manual fast recovery

mode in the MNGR_DYN (0x05) register. The manual fast

recovery mode can be of a much shorter duration than

the automatic mode and allows for more rapid recovery.

One such example is recovery from external high-voltage

pacing signals in a few milliseconds to allow the observation

of a subsequent p-wave.

Table 2. ECG Analog HPF Corner

Frequency Selection

1/(2r x R

x C

)

HPF

RHPF is specified in the Electrical Characteristics table.

C

HPF CORNER FREQUENCY

Following the instrumentation amplifier is a 2-pole active

anti-aliasing filter with a 600Hz -3dB frequency that

provides57dBofattenuationathalfthemodulatorsampling

rate (approximately 16kHz) and a PGAwith programmable

gains of 1, 2, 4, and 8V/V for an overall gain of 20, 40, 80,

and 160V/V. The instrumentation amplifier and PGA are

chopped to minimize offset and 1/f noise. Gain settings are

configured via the CNFG_ECG (0x15) register. The

HPF

0.1µ

1.0µ

10µ

≤ 5Hz

≤ 0.5Hz

≤ 0.05Hz

Table 3. Fast Recovery Mode Recovery

Time vs. Number of Samples

RECOVERY TIME

useable common-mode range is V

±150mV, internal

MID

lead biasing can be used to meet this requirement. The

useable DC differential range is ±300mV to allow for

electrode polarization voltages on each electrode. The

SAMPLE

RATE (sps)

NUMBER OF

SAMPLES

(APPROXIMATE)

(ms)

512

256

128

500

250

125

200

199.8

255

127

63

498

input AC differential range is ±32.5mV or ±65mV

.

P-P

496

492

Fast Recovery Mode

The input instrumentation amplifier has the ability to

rapidly recover from an excessive overdrive event such

as a defibrillation pulse, high-voltage external pacing,

and electro-surgery interference. There are two modes of

recovery that can be used: automatic or manual recovery.

The mode is programmed by the FAST[1:0] bits in the

MNGR_DYN (0x05) register.

249

124

64

498

496

512

99

495

99

495.5

Automatic mode engages once the saturation counter

exceeds approximately 125ms (t

). The counter is

SAT

activated the first time the ADC output exceeds the

symmetrical threshold defined by the FAST_TH[5:0] bits

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

t_BLW

t_SAT

125ms

V_DD

V_{SAT_THH}

ECG

V_MID

V_{SAT_THL}

V_SS

COUNTER

START STOP

RESET

DISABLED

NORMAL

START

RESET

t_FAST

FAST

SETTLING

ENABLED

DISABLED

NORMAL

FAST

ETAG

Figure 6. Automatic Fast Settling Behavior

Low-pass filter options include a 12-tap linear phase

(constant group delay) FIR filter with approximately 40Hz,

100Hz, or 150Hz corner frequencies, depending on the

sampling rate. See register CNFG_ECG (0x15) to con-

figure the filters. Table 4 illustrates the ECG latency in

samples and time for each ADC data rate.

Decimation Filter

The decimation filter consists of a Cascaded Integrator

Comb (CIC) decimation filter to the data rate followed by

a programmable FIR filter to implement HPF and LPF

selections.

The high-pass filter options include a 1st-order IIR

Butterworth filter with

a 0.4Hz corner frequency

along with a pass-through setting for DC coupling.

Table 4. ECG Latency in Samples and Time as a Function of ECG Data Rate

and Decimation

ECG CHANNEL SETTINGS

LATENCY

INPUT

SAMPLE

RATE (Hz)

OUTPUT

DATA RATE

(sps)

WITHOUT

LFP (INPUT

SAMPLES)

WITH LPF

(INPUT

SAMPLES)

DECIMATION

WITHOUT

LFP (ms)

WITH LPF

(ms)

RATIO

32,768

32,000

32,768

32,000

31,968

32,768

32,000

512

500

256

250

200

199.8

128

125

64

650

1,034

3,690

2,202

4,906

19.836

20.313

89.172

91.313

38.813

38.851

102.844

105.313

31.555

32.313

112.610

115.313

68.813

68.881

149.719

153.313

64

650

128

160

256

2,922

1,242

3,370

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

When an R event is identified, the RRINT status bit is

asserted and the RTOR_REG (0x25) register is updated

with the count seen since the last R event. Figure 7

illustrates the R-R interval on a QRS complex. Refer

to registers CNFG_RTOR1 (0x1D) and CNFG_RTOR2

(0x1E) for selection details.

Noise Measurements

Table 5 shows the noise performance of the ECG channel

of MAX30003 referred to the ECG inputs.

R-to-R Detection

The MAX30003 contains built-in hardware to detect R-R

intervals using an adaptation of the Pan-Tompkins QRS

1

detection algorithm . The timing resolution of the R-R

interval is approximately 8ms and depends on the setting

of FMSTR [1:0] in CNFG_GEN (0x10) register. See Table 22

for the timing resolution of each setting.

Table 5. Biopotential (ECG) Channel Noise Performance

GAIN

BANDWIDTH

NOISE

SNR

dB

ENOB

Bits

V/V

Hz

40

µV

PP

RMS

0.53

3.50

4.20

5.44

2.64

3.56

4.34

2.31

3.33

4.09

2.22

3.24

4.01

96.5

94.9

92.6

92.9

90.3

88.6

88.0

84.9

83.1

82.4

79.1

77.2

15.7

15.5

15.1

14.7

14.4

14.3

13.8

13.5

13.4

12.8

12.5

20

40

100

150

40

0.64

0.82

0.40

0.54

0.66

0.35

0.50

0.62

0.34

0.49

0.61

100

150

40

80

100

150

40

160

100

150

V_IN(RMS)

Note:

SNR = 20log,

, ENOB = (SNR - 1.76)/6.02

V (RMS)

(

)

N

Note:

V

INP-P

= 100mV, V

= 35.4mV for a gain of 20V/V. The input amplitude is reduced accordingly for high

INRMS

gain settings.

R-R INTERVAL

Figure 7. R-to-R Interval Illustration

1

J. Pan and W.J. Tompkins, “A Real-Time QRS Detection

Algorithm,” IEEE Trans. Biomed. Eng., vol. 32, pp. 230-236

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

The latency of the R-to-R value written to the RTOR

Interval Memory Register is the sum of the R-to-R

decimation delay and the R-to-R detection delay blocks.

The R-to-R decimation factor is fixed at 256 and the

blocks. Use a 10µF external capacitor between V

AGND to provide compensation and noise filtering.

to

CM

SPI Interface Description

decimation delay (t

) is always 3,370 FMSTR

32 Bit Normal Mode Read/Write Sequences

R2R_DEC

clocks, as shown in Table 6.

The MAX30003 interface is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

in Figure 1. Data is strobed into the MAX30003 on SCLK

rising edges. The device is programmed and accessed by

a 32 cycle SPI instruction framed by a CSB low interval.

The content of the SPI operation consists of a one byte

command word (comprised of a seven bit address and a

Read/Write mode indicator, i.e., A[6:0] + R/W) followed by

a three-byte data word. The MAX30003 is compatible with

CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1 modes of

operation.

The detection circuit consists of several digital filters

and signal processing delays. These depend on the

WNDW[3:0] bits in the CNFG_RTOR (0x1D) register. The

detection delay (t

equation:

) is described by the following

R2R_DET

t

= 5,376 + 256 x WNDW in FMSTR clocks

R2R_DET

where WNDW is an integer from 0 to 15 and the total

latency (t ) is the sum of the two delays and

R2R_DEL

summarized in the equation below:

= t + t = 3,370 + 5,376 +

R2R_DET

t

R2R_DEL

R2R_DEC

Write mode operations will be executed on the 32nd SCLK

rising edge using the first four bytes of data available.

In write mode, any data supplied after the 32nd SCLK

rising edge will be ignored. Subsequent writes require CSB

to de-assert high and then assert low for the next write

command. In order to abort a command sequence, the

rise of CSB must precede the updating (32nd) rising-edge

256 x WNDW in FMSTR clocks where WNDW

is an integer from 0 to 15.

The total R-to-R latency minus the ECG latency is delay of

the R-to-R value relative to the ECG data and can be used

to place the first R-to-R value on the ECG data plot. The

succeeding values in the R-to-R Interval Memory Register

can be used as is to locate subsequent R-to-R values on

the ECG data plot relative to the initial placement.

of SCLK, meeting the t

requirement.

CSA

Read mode operations will access the requested data

on the 8th SCLK rising edge, and present the MSB of

the requested data on the following SCLK falling edge,

allowing the µC to sample the data MSB on the 9th SCLK

rising edge. Configuration, Status, and FIFO data are all

available via normal mode read back sequences. If more

than 32 SCLK rising edges are provided in a normal read

sequence then the excess edges will be ignored and the

device will read back zeros.

Reference and Common Mode Buﬀer

The MAX30003 features internally generated reference

voltages. The bandgap output (V ) pin requires an

BG

external 1.0µF capacitor to AGND and the reference

output (V

) pin requires a 10µF external capacitor to

REF

AGND for compensation and noise filtering.

A common-mode buffer is provided to buffer 650mV

which is used to drive common mode voltages for internal

Table 6. R to R Decimation Delay in ms and FMSTR CLK vs. Register Settings,

FCLK = 32.768Hz

DELAY IN R TO R DECIMATION

FMSTR

[1:0]

FMSTR FREQ

IN FCLKs

FMSTR

FREQ (Hz)

RTOR TIME

RESOLUTION (ms)

DECIMATION

IN FMSTR CLKs

IN ms

00

01

10

11

FCLK

32,768

32,000

256

7.8125

8.0

3370

102.844

105.313

105.415

FCLK x 625/640

FCLK x 640/656

32,000

8.0

31,968.78

8.0078

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

If accessing the STATUS register or the ECG FIFO

memories, all interrupt updates will be made and the

internal FIFO read pointer will be incremented in response

to the 30th SCLK rising edge, allowing for internal

synchronization operations to occur. See the data tag

structures used within each FIFO for means of detecting

end-of-file (EOF) samples, invalid (empty samples) and

other aides for efficiently using and managing normal

mode read back operations.

continues to provide SCLK edges beyond the 32nd rising

edge, the MSB of the next available FIFO word will be

presented on the next falling SCLK edge, allowing the µC

to sample the MSB of the next word on the 33rd SCLK

rising edge. Any affected interrupts and/or FIFO read

pointers will be incremented in response to the (30+n x

24)th SCLK rising edge where n is an integer starting at

0. (i.e., on the 30th, 54th, and 78th SCLK rising-edges for

a three-word, burst-mode transfer).

This mode of operation will continue for every 24 cycle

sub frame, as long as there is valid data in the FIFO. See

the data tag structures used within each FIFO for means

of detecting end-of-file (EOF) samples, invalid (empty

samples) and other aides for efficiently using and managing

burst mode read back operations.

Burst Mode Read Sequence

The MAX30003 provides commands to read back

the ECG FIFO memory in a burst mode to increase

data transfer efficiency. Burst mode uses different

register addresses than the normal read sequence

register addresses. The first 32 SCLK cycles operate

exactly as described for the normal mode. If the µC

There is no burst mode equivalent in write mode.

CSB

SDI

A6 A5 A4 A3 A2 A1 A0

1

W

D23

9

D16 D15

16 17

D8 D7

24 25

D0 DON’T CARE

32 33

SCLK

8

IGNORE

D EDGES

COMMAND

EXECUTED

Z

SDO

SPI NORMAL MODE WRITE TRANSACTION

CSB

SDI

A6 A5 A4 A3 A2 A1 A0

1

R

DON’T CARE

16 17

DON’T CARE

32 33

24 25

INTERRUPT/READ POINTER

30

SCLK

8 9

IGNORE

UPDATED (IF APPLICABLE)

D EDGES

Z

D_O23

D_O16 D_O15

D_O8 D_O7

D_O0

SDO

SPI NORMAL MODE READ TRANSACTION

Figure 8. SPI Normal Mode Transaction Diagrams

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

CSB

SDI

A6 A5 A4 A3 A2 A1 A0

R

DON’T CARE

16 17

DON’T CARE

24 25

30

32

SCLK

1

8 9

READ POINTER

UPDATED (TO B)

D_A8 D_A7

Z

D 23

B

SDO

D_A23

D_A16 D_A15

D_A0

CONTINUED TRANSACTION (SUB-FRAME 2)

CSB

33

40 41

48 49

56

54

SCLK

READ POINTER

UPDATED (TO C)

D_B23

D_B16D_B15

D_B8 D_B7

D 0

B

SDO

D_C23

CONTINUED TRANSACTION (SUB-FRAME 3)

CSB

57

64 65

72 73

78

80

SCLK

READ POINTER

UPDATED (TO D)

Z

D_C16 D_C15

SDO

D_C23

D_C8 D_C7

D_C0

SPI BURST MODE READ TRANSACTION (3 FIFO WORD EXAMPLE)

Figure 9. SPI Burst Mode Read Transactions Diagrams

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

STATUS (0x01) Register

Register Descriptions

STATUS is a read-only register that provides a compre-

hensive overview of the current status of the device. The

first two bytes indicate the state of all interrupt terms

(regardless of whether interrupts are enabled in registers

EN_INT (0x02) or EN_INT2 (0x03)). All interrupt terms

are active high. The last byte includes detailed status

information for conditions associated with the interrupt

terms.

NO_OP (0x00 and 0x7F) Registers

No Operation (NO_OP) registers are read-write registers

that have no internal effect on the device. If these

registers are read back, DOUT remains zero for the entire

SPI transaction. Any attempt to write to these registers is

ignored without impact to internal operation.

Table 7. STATUS (0x01) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

x

16 / 8 / 0

x

DCLOFF

EINT

EOVF

FSTINT

x

INT

0x01

STATUS

R

x

LONINT

RRINT

SAMP

PLLINT

LDOFF_

PH

LDOFF_

PL

LDOFF_

NH

LDOFF_

NL

x

Table 8. Status (0x01) Register Meaning

INDEX

NAME

MEANING

ECG FIFO Interrupt. Indicates that ECG records meeting/exceeding the ECG FIFO Interrupt

D[23]

EINT

Threshold (EFIT) are available for readback. Remains active until ECG FIFO is read back to the

extent required to clear the EFIT condition.

ECG FIFO Overﬂow. Indicates that the ECG FIFO has overﬂown and the data record has

been corrupted.

Remains active until a FIFO Reset (recommended) or SYNCH operation is issued.

D[22]

D[21]

EOVF

ECG Fast Recovery Mode. Issued when the ECG Fast Recovery Mode is engaged

(either manually or automatically).

FSTINT

Status and Interrupt Clear behavior is deﬁned by CLR_FAST, see MNGR_INT for details.

DC Lead-Oﬀ Detection Interrupt. Indicates that the MAX30003 has determined it is in an ECG

leads oﬀ condition (as selected in CNFG_GEN) for more than 115ms.

Remains active as long as the leads-oﬀ condition persists, then held until cleared by STATUS

read back (32nd SCLK).

D[20]

DCLOFFINT

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 8. Status (0x01) Register Meaning (continued)

INDEX

NAME

MEANING

Ultra-Low Power (ULP) Leads-On Detection Interrupt. Indicates that the MAX30003 has determined

it is in a leads-on condition (as selected in CNFG_GEN).

LONINT is asserted whenever EN_ULP_LON[1:0] in register CNFG_GEN is set to either 0b01 or

0b10 to indicate that the ULP leads on detection mode has been enabled. The STATUS register

has to be read back once after ULP leads on detection mode has been activated to clear LONINT

and enable leads on detection.

D[11]

LONINT

LONINT remains active while the leads-on condition persists, then held until cleared by STATUS read

back (32nd SCLK).

ECG R to R Detector R Event Interrupt. Issued when the R to R detector has identiﬁed a new R event.

Clear behavior is deﬁned by CLR_RRINT[1:0]; see MNGR_INT for details.

D[10]

D[9]

RRINT

SAMP

Sample Synchronization Pulse. Issued on the ECG base-rate sampling instant, for use in assisting

µC monitoring and synchronizing other peripheral operations and data, generally recommended for use

as a dedicated interrupt.

Frequency is selected by SAMP_IT[1:0], see MNGR_INT for details.

Clear behavior is deﬁned by CLR_SAMP, see MNGR_INT for details.

PLL Unlocked Interrupt. Indicates that the PLL has not yet achieved or has lost its phase lock.

PLLINT will only be asserted when the PLL is powered up and active (ECG and/or BIOZ Channel

enabled).

D[8]

PLLINT

Remains asserted while the PLL unlocked condition persists, then held until cleared by STATUS read

back (32nd SCLK).

D[3]

D[2]

D[1]

D[0]

LDOFF_PH

LDOFF_PL

LDOFF_NH

LDOFF_NL

DC Lead Oﬀ Detection Detailed Status. Indicates that the MAX30003 has determined (as selected by

CNFG_GEN):

ECGP is above the high threshold (V

ECGN is above the high threshold (V

), ECGP is below the low threshold (V

),

THL

THH

), ECGN is below the low threshold (V

), respectively.

THH

THL

Remains active as long as the leads-oﬀ detection is active and the leads-oﬀ condition persists, then

held until cleared by STATUS read back (32nd SCLK). LDOFF_PH to LDOFF_NL are detailed status

bits that are asserted at the same time as DCLOFFINT.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

INTB_TYPE[1:0] allows the user to select between a

CMOS or an open-drain NMOS mode INTB output. If

using open-drain mode, an option for an internal 125kΩ

pullup resistor is also offered.

EN_INT (0x02) and EN_INT2 (0x03) Registers

EN_INT and EN_INT2 are read/write registers that govern

the operation of the INTB output and INT2B output,

respectively. The first two bytes indicate which

interrupt input terms are included in the interrupt output OR

term (ex. a one in an EN_INT register indicates that the

corresponding input term is included in the INTB interrupt

output OR term). See the STATUS register for detailed

descriptions of the interrupt terms. The power-on reset

state of all EN_INT terms is 0 (ignored by INT).

All INTB and INT2B types are active-low (INTB low

indicates the device requires servicing by the µC);

however, the open-drain mode allows the INTB line to be

shared with other devices in a wired-or configuration.

In general, it is suggested that INT2B be used to

support specialized/dedicated interrupts of use in specific

applications, such as the self-clearing versions of SAMP

or RRINT.

EN_INT and EN_INT2 can also be used to mask persistent

interruptconditionsinordertoperformotherinterrupt-driven

operations until the persistent conditions are resolved.

Table 9. EN_INT (0x02) and EN_INT2 (0x03) Register Maps

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

EN_

EOVF

EN_

FSTINT

EN_DCL

OFFINT

EN_EINT

x

0x02

0x03

EN_INT

EN_INT2

R/W

EN_

LONINT

EN_

RRINT

EN_

SAMP

EN_

PLLINT

x

INTB_TYPE[1:0]

Table 10. EN_INT (0x02 and 0x03) Register Meaning

INDEX

NAME

DEFAULT

FUNCTION

EN_EINT

EN_EOVF

EN_FSTINT

EN_DCLOFFINT

EN_LONINT

EN_RRINT

Interrupt Enables for interrupt terms in STATUS[23:8]

0 = Individual interrupt term is not included in the interrupt OR term

1 = Individual interrupt term is included in the interrupt OR term

D[23:20]

D[11:8]

0x0000

EN_SAMP

EN_PLLINT

INTB Port Type (EN_INT Selections)

00 = Disabled (Three-state)

11

01 = CMOS Driver

10 = Open-Drain NMOS Driver

11 = Open-Drain NMOS Driver with Internal 125kΩ Pullup Resistance

D[1:0]

INTB_TYPE[1:0]

INT2B Port Type (EN_INT2 Selections)

00 = Disabled (three-state)

01 = CMOS Driver

10 = Open-Drain nMOS Driver

11 = Open-Drain nMOS Driver with Internal 125kΩ Pullup Resistance

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

FIFO descriptions for more details). Finally, this register

contains the configuration bits supporting the sample

synchronization pulse (SAMP) and RTOR heart rate

detection interrupt (RRINT).

MNGR_INT (0x04)

MNGR_INT is a read/write register that manages the

operation of the configurable interrupt bits in response to

ECG FIFO conditions (see the STATUS register and ECG

Table 11. MNGR_INT (0x04) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

EFIT[4:0]

x

MNGR_

INT

0x04

R/W

CLR_

FAST

CLR_

SAMP

CLR_RRINT[1:0]

SAMP_IT[1:0]

Table 12. MNGR_INT (0x04) Register Functionality

FUNCTION

INDEX

NAME

DEFAULT

ECG FIFO Interrupt Threshold (issues EINT based on number of unread

FIFO records)

D[23:19]

EFIT[4:0]

01111

00000 to 11111 = 1 to 32, respectively (i.e. EFIT[4:0]+1 unread records)

FAST MODE Interrupt Clear Behavior:

0 = FSTINT remains active until the FAST mode is disengaged (manually or

automatically), then held until cleared by STATUS read back (32nd SCLK).

1 = FSTINT remains active until cleared by STATUS read back (32nd SCLK),

even if the MAX30003 remains in FAST recovery mode. Once cleared,

FSTINT will not be re-asserted until FAST mode is exited and re-entered,

either manually or automatically.

D[6]

CLR_FAST

0

RTOR R Detect Interrupt (RRINT) Clear Behavior:

00 = Clear RRINT on STATUS Register Read Back

01 = Clear RRINT on RTOR Register Read Back

10 = Self-Clear RRINT after one ECG data rate cycle, approximately 2ms to 8ms

11 = Reserved. Do not use.

D[5:4]

D[2]

CLR_RRINT[1:0]

CLR_SAMP

00

1

Sample Synchronization Pulse (SAMP) Clear Behavior:

0 = Clear SAMP on STATUS Register Read Back (recommended for debug/

evaluation only).

1 = Self-clear SAMP after approximately one-fourth of one data rate cycle.

Sample Synchronization Pulse (SAMP) Frequency

00 = issued every sample instant

D[1:0]

SAMP_IT[1:0]

00

01 = issued every 2nd sample instant

10 = issued every 4th sample instant

11 = issued every 16th sample instant

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

MNGR_DYN (0x05)

SW_RST (0x08)

MNGR_DYN is a read/write register that manages the

settings of any general/dynamic modes within the device.

The ECG Fast Recovery modes and thresholds are

managed here. Unlike many CNFG registers, changes to

dynamic modes do not impact FIFO operations or require

a SYNCH operation (though the affected circuits may

require time to settle, resulting in invalid/corrupted FIFO

output voltage information during the settling interval).

SW_RST (Software Reset) is a write-only register/

command that resets the MAX30003 to its original default

conditions at the end of the SPI SW_RST transaction

(i.e. the 32nd SCLK rising edge). Execution occurs only

if DIN[23:0] = 0x000000. The effect of a SW_RST is

identical to power-cycling the device.

Table 13. MNGR_DYN (0x05) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

FAST[1:0] FAST_TH[5:0]

MNGR_

DYN

0x05

R/W

x

Table 14. MNGR_DYN (0x05) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass):

00 = Normal Mode (Fast Recovery Mode Disabled)

01 = Manual Fast Recovery Mode Enable (remains active until disabled)

10 = Automatic Fast Recovery Mode Enable (Fast Recovery automatically

activated when/while ECG outputs are saturated, using FAST_TH).

11 = Reserved. Do not use.

D[23:22]

FAST[1:0]

00

Automatic Fast Recovery Threshold:

If FAST[1:0] = 10 and the output of an ECG measurement exceeds the symmetric

thresholds deﬁned by 2048*FAST_TH for more than 125ms, the Fast Recovery

mode will be automatically engaged and remain active for 500ms.

For example, the default value (FAST_TH = 0x3F) corresponds to an ECG output

upper threshold of 0x1F800, and an ECG output lower threshold of 0x20800.

D[21:16]

FAST_TH[5:0]

0x3F

Table 15. SW_RST (080x) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x08

SW_RST

R/W

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

During multi-channel operations, if a FIFO overflow event

occurs and a portion of the record is lost, it is recommended

to use the SYNCH command to recover and restart the

recording (avoiding issues with missing data in one or

more channel records). Note that the two channel records

cannot be directly synchronized within the device, due to

significant differences in group delays, depending on filter

selections—alignment of the records will have to be done

externally.

SYNCH (0x09)

SYNCH (Synchronize) is a write-only register/command

that begins new ECG operations and recording, beginning

on the internal MSTR clock edge following the end of

the SPI SYNCH transaction (i.e. the 32nd SCLK rising

edge). Execution occurs only if DIN[23:0] = 0x000000.

In addition to resetting and synchronizing the operations

of any active ECG and RtoR circuitry, SYNCH will also

reset and clear the FIFO memories and the DSP filters

(to midscale), allowing the user to effectively set the “Time

Zero” for the FIFO records. No configuration settings

are impacted. For best results, users should wait until

the PLL has achieved lock before synchronizing if the

CNFG_GEN settings have been altered.

FIFO_RST (0x0A)

FIFO_RST (FIFO Reset) is a write-only register/command

that begins a new ECG recording by resetting the FIFO

memories and resuming the record with the next available

ECG data. Execution occurs only if DIN[23:0]=0x000000.

Unlike the SYNCH command, the operations of any active

ECG and R-to-R circuitry are not impacted by FIFO_RST,

so no settling/recovery transients apply. FIFO_RST can

also be used to quickly recover from a FIFO overflow

state (recommended for single-channel use, see above).

Once the device is initially powered up, it will need to be

fully configured prior to launching recording operations.

Likewise, anytime a change to CNFG_GEN or CNFG_

ECG registers are made there may be discontinuities in

the ECG record and possibly changes to the size of the

time steps recorded in the FIFOs. The SYNCH command

provides a means to restart operations cleanly following

any such disturbances.

Table 16. SYNCH (0x09) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x09

SYNCH

R/W

Table 17. FIFO_RST (0x0A) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x0A FIFO_RST R/W

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

INFO (0x0F)

CNFG_GEN (0x10)

INFO is a read-only register that provides information

about the MAX30003. The first nibble contains an alternating

bit pattern to aide in interface verification. The second

nibble contains the revision ID. The third nibble includes

part ID information. The final 3 nibbles contain a serial

number for Maxim internal use—note that individual

units are not given unique serial numbers, and these bits

should not be used as serial numbers for end products,

though they may be useful during initial development

efforts.

CNFG_GEN is a read/write register which governs

general settings, most significantly the master clock rate

for all internal timing operations. Anytime a change to

CNFG_GEN is made, there may be discontinuities in

the ECG record and possibly changes to the size of the

time steps recorded in the FIFOs. The SYNCH command

can be used to restore internal synchronization resulting

from configuration changes. Note when EN_ECG is logic-

low, the device is in one of two ultra-low power modes

(determined by EN_ULP_LON).

Note: due to internal initialization procedures, this

command will not read-back valid data if it is the first

command executed following either a power-cycle event,

or a SW_RST event.

Table 18. INFO (0x0F) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

0

x

1

x

0

1

x

1

x

REV_ID[3:0]

0x0F FIFO_RST R/W

x

Table 19. INFO (0x0F) Register Meaning

INDEX

NAME

MEANING

D[19:16]

REV_ID[3:0]

Revision ID

Table 20. CNFG_GEN (0x10) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

x

16 / 8 / 0

EN_ULP_LON[1:0]

FMSTR[1:0]

EN_DCLOFF[1:0]

EN_RBIAS[1:0]

EN_ECG

IPOL

x

CNFG_

GEN

0x10

R/W

x

IMAG[2:0]

RBIASP

VTH[1:0]

RBIASV[1:0]

RBIASN

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 21. CNFG_GEN (0x10) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Ultra-Low Power Lead-On Detection Enable

00 = ULP Lead-On Detection disabled

D[23:22]

EN_ULP_LON

[1:0]

01 = ECG ULP Lead-On Detection enabled

10 = Reserved. Do not use.

00

11 = Reserved. Do not use.

ULP mode is only active when the ECG channel is powered down/disabled.

Master Clock Frequency. Selects the Master Clock Frequency (FMSTR), and Timing

Resolution (T

), which also determines the ECG and CAL timing characteristics.

RES

These are generated from FCLK, which is always 32.768Khz.

D[21:20]

D[19]

FMSTR[1:0]

EN_ECG

00

00 =

01 =

10 =

11 =

F

= 32768Hz,

= 32000Hz,

T

= 15.26µs (512Hz ECG progressions)

= 15.63µs (500Hz ECG progressions)

= 15.63µs (200Hz ECG progressions)

= 15.64µs (199.8049Hz ECG progressions)

MSTR

RES

= 31968.78Hz, T

ECG Channel Enable

0 = ECG Channel disabled

1 = ECG Channel enabled

0

Note: The ECG channel must be enabled to allow R-to-R operation.

DC Lead-Oﬀ Detection Enable

00 = DC Lead-Oﬀ Detection disabled

01 = DCLOFF Detection applied to the ECGP/N pins

10 = Reserved. Do not use.

11 = Reserved. Do not use.

DC Method, requires active selected channel, enables DCLOFF interrupt

and status bit behavior.

Uses current sources and comparator thresholds set below.

D[13:12]

D[11]

EN_DCLOFF

00

DC Lead-Oﬀ Current Polarity (if current sources are enabled/connected)

DCLOFF_

IPOL

0

0 = ECGP - Pullup

1 = ECGP - Pulldown

ECGN – Pulldown

ECGN – Pullup

DC Lead-Oﬀ Current Magnitude Selection

000 = 0nA (Disable and Disconnect Current Sources)

001 = 5nA

010 = 10nA

011 = 20nA

100 = 50nA

DCLOFF_

IMAG[2:0]

D[10:8]

000

101 = 100nA

110 = Reserved. Do not use.

111 = Reserved. Do not use.

DC Lead-Oﬀ Voltage Threshold Selection

00 = V

01 = V

10 = V

11 = V

± 300mV

± 400mV

± 450mV

± 500mV

MID

DCLOFF_

VTH[1:0]

D[7:6]

D[5:4]

00

Enable and Select Resistive Lead Bias Mode

00 = Resistive Bias disabled

01 = ECG Resistive Bias enabled if EN_ECG is also enabled

10 = Reserved. Do not use.

EN_RBIAS[1:0]

11 = Reserved. Do not use.

If EN_ECG is not asserted at the same time as prior to EN_RBIAS[1:0] being set to

01, then EN_RBIAS[1:0] will remain set to 00.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 21. CNFG_GEN (0x10) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

Resistive Bias Mode Value Selection

00 = R

01 = R

10 = R

= 50MΩ

= 100MΩ

= 200MΩ

BIAS

D[3:2]

RBIASV[1:0]

01

11 = Reserved. Do not use.

Enables Resistive Bias on Positive Input

D[1]

D[0]

RBIASP

RBIASN

0

0 = ECGP is not resistively connected to V

MID

1 = ECGP is connected to V

through a resistor (selected by RBIASV).

MID

Enables Resistive Bias on Negative Input

0 = ECGN is not resistively connected to V

MID

1 = ECGN is connected to V

through a resistor (selected by RBIASV).

MID

Table 22 shows the ECG data rates that can be realized with various setting of FMSTR, along with RATE configuration bits

available in the CNFG_ECG register. Note FMSTR also determines the timing resolution of the CAL waveform generator.

Table 22. Master Frequency Summary Table

ECG DATA RATES & RELATED TIMING (RATE SELECTIONS)

CALIBRATION

MASTER

FREQUENCY

(f ) (Hz)

ECG

RTOR

FMSTR

[1:0]

TIMING

RESOLUTION

(CAL_RES) (µs)

DATA

RATE (sps)

TIMING RESOLUTION

(RTOR_RES) (ms)

MSTR

00 = 512

01 = 256

10 = 128

00

01

32768

7.8125

8.000

30.52

31.25

00 = 500

01 = 250

10 = 125

32000

10

11

32000

10 = 200

8.000

8.008

31.25

31.28

31968.78

10 =199.8049

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

CNFG_CAL (0x12)

CNFG_CAL is a read/write register that configures the operation, settings, and function of the Internal Calibration Voltage

Sources (VCALP and VCALN). The output of the voltage sources can be routed to the ECG inputs through the channel

input MUXes to facilitate end-to-end testing operations. Note if a VCAL source is applied to a connected device, it is

recommended that the appropriate channel MUX switches be placed in the OPEN position.

Table 23. CNFG_CAL (0x12) Register Map

REG

NAME

R/W 23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

x

16 / 8 / 0

EN_

VCAL

x

VMODE

VMAG

x

CNFG_

CAL

0x12

R/W

FCAL[14:12]

FIFTY

THIGH[10:8]

THIGH[7:0]

Table 24. CNFG_CAL (0x12) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Calibration Source (VCALP and VCALN) Enable

0 = Calibration sources and modes disabled

1 = Calibration sources and modes enabled

D[22]

EN_VCAL

0

Calibration Source Mode Selection

D[21]

D[20]

VMODE

VMAG

0

0 = Unipolar, sources swing between V

± V

and VMID

MID

MAG

1 = Bipolar, sources swing between V

+ V

and V

- V

MID MAG

MID

MAG

Calibration Source Magnitude Selection (V

0 = 0.25mV

1 = 0.50mV

)

MAG

Calibration Source Frequency Selection (FCAL)

000 = F

001 = F

010 = F

011 = F

100 = F

/128

(Approximately 256Hz)

MSTR

/512 (Approximately 64Hz)

/2048 (Approximately 16Hz)

/8192 (Approximately 4Hz)

/2¹⁵

(Approximately 1Hz)

101 = F

/2¹⁷

MSTR

D[14:12]

FCAL[2:0]

100

(Approximately 1/4Hz)

110 = F

/2¹⁹

MSTR

(Approximately 1/16Hz)

111 = F

/2²¹

MSTR

(Approximately 1/64Hz)

Actual frequencies are determined by FMSTR selection (see CNFG_GEN for

details), approximate frequencies are based on a 32768Hz clock (F

TCAL = 1/FCAL.

[2:0] = 000).

MSTR

Calibration Source Duty Cycle Mode Selection

D[11]

FIFTY

1

0 = Use CAL_THIGH to select time high for VCALP and VCALN

1 = THIGH = 50% (CAL_THIGH[10:0] are ignored)

Calibration Source Time High Selection

If FIFTY = 1, t

= 50% (and THIGH[10:0] are ignored),

HIGH

D[10:0]

THIGH[10:0]

0x000

otherwise THIGH = THIGH[10:0] x CAL_RES

CAL_RES is determined by FMSTR selection (see CNFG_GEN for details);

for example, if FMSTR[2:0] = 000,CAL_RES = 30.52µs.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

CALIBRATION VOLTAGE SOURCE OPTIONS

V_MID+ 0.25mV

V_MID

V_MID+ 0.25mV

V_MID

V_MID- 0.25mV

CAL_VMODE = 0

CAL_VMAG = 0

CAL_VMODE = 1

CAL_VMAG = 0

V

_MID- 0.25mV

V_MID+ 0.50mV

V_MID

V_MID+ 0.50mV

V_MID

V_CALP

V_CALN

CAL_VMODE = 0

CAL_VMAG = 1

CAL_VMODE = 1

CAL_VMAG = 1

V_MID- 0.50mV

t_HIGH

t_CAL

Figure 10. Calibration Voltage Source Options

CNFG_EMUX (0x14)

CNFG_EMUX is a read/write register which configures the operation, settings, and functionality of the Input Multiplexer

associated with the ECG channel.

Table 25. CNFG_EMUX (0x14) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

POL

x

OPENP

OPENN

CALP_SEL[1:0]

CALN_SEL[1:0]

CNFG_

EMUX

0x14

R/W

x

Table 26. CNFG_EMUX (0x14) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

ECG Input Polarity Selection

0 = Non-inverted

D[23]

POL

0

1 = Inverted

Open the ECGP Input Switch (most often used for testing and calibration studies)

0 = ECGP is internally connected to the ECG AFE Channel

1 = ECGP is internally isolated from the ECG AFE Channel

D[21]

D[20]

OPENP

OPENN

1

Open the ECGN Input Switch (most often used for testing and calibration studies)

0 = ECGN is internally connected to the ECG AFE Channel

1 = ECGN is internally isolated from the ECG AFE Channel

ECGP Calibration Selection

00 = No calibration signal applied

D[19:18]

D[17:16]

CALP_SEL[1:0]

CALN_SEL[1:0]

00

01 = Input is connected to V

10 = Input is connected to VCALP (only available if CAL_EN_VCAL = 1)

11 = Input is connected to VCALN (only available if CAL_EN_VCAL = 1)

MID

ECGN Calibration Selection

00 = No calibration signal applied

01 = Input is connected to V

MID

10 = Input is connected to VCALP (only available if CAL_EN_VCAL = 1)

11 = Input is connected to VCALN (only available if CAL_EN_VCAL = 1)

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

CNFG_ECG (0x15)

CNFG_ECG is a read/write register which configures the operation, settings, and functionality of the ECG channel.

Anytime a change to CNFG_ECG is made, there may be discontinuities in the ECG record and possibly changes to the

size of the time steps recorded in the ECG FIFO. The SYNCH command can be used to restore internal synchronization

resulting from configuration changes.

Table 27. CNFG_ECG (0x15) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

RATE[1:0]

DHPF

x

GAIN[1:0]

CNFG_

ECG

0x15

R/W

x

DLPF[1:0]

x

Table 28. CNFG_ECG (0x15) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

ECG Data Rate (also dependent on F

selection, see CNFG_GEN Table 29):

MSTR

FMSTR = 00: f

00 = 512sps

01 = 256sps

10 = 128sps

= 32768Hz, t

= 15.26µs (512Hz ECG progressions)

= 15.63µs (500Hz ECG progressions)

= 15.63µs (200Hz ECG progressions)

= 15.64µs (199.8Hz ECG progressions)

MSTR

RES

11 = Reserved. Do not use.

FMSTR = 01: f

00 = 500sps

01 = 250sps

10 = 125sps

= 32000Hz, t

MSTR

11 = Reserved. Do not use.

D[23:22]

RATE[1:0]

10

FMSTR = 10: f = 32000Hz, t

MSTR

00 = Reserved. Do not use.

01 = Reserved. Do not use.

10 = 200sps

11 = Reserved. Do not use.

FMSTR = 11: f

= 31968Hz, t

MSTR

00 = Reserved. Do not use.

01 = Reserved. Do not use.

10 = 199.8sps

11 = Reserved. Do not use.

ECG Channel Gain Setting

00 = 20V/V

D[17:16]

GAIN[1:0]

00

01 = 40V/V

10 = 80V/V

11 = 160V/V

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 28. CNFG_ECG (0x15) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

ECG Channel Digital High-Pass Filter Cutoﬀ Frequency

D[14]

DHPF

1

0 = Bypass (DC)

1 = 0.50Hz

ECG Channel Digital Low-Pass Filter Cutoﬀ Frequency

00 = Bypass (Decimation only, no FIR ﬁlter applied)

01 = approximately 40Hz (Except for 125 and 128sps settings) Note: See Table 33.

10 = approximately 100Hz (Available for 512, 256, 500, and 250sps ECG Rate

selections only)

D[13:12]

DLPF[1:0]

01

11 = approximately 150Hz (Available for 512 and 500sps ECG Rate selections only)

Note: See Table 29. If an unsupported DLPF setting is speciﬁed, the 40Hz setting

(DLPF[1:0] = 01) will be used internally; the CNFG_ECG register will continue to hold

the value as written, but return the eﬀective internal value when read back.

Table 29. Supported ECG_RATE and ECG_DLPF Options

RATE[1:0]

SAMPLE RATE

(sps)

DLPF[1:0]/DIGITAL LPF CUTOFF

CNFG_GEN

FMSTR[1:0]

00

01 (Hz)

10 (Hz)

11 (Hz)

00 = 512

01 = 256

10 = 128

00 = 500

01 = 250

10 = 125

10 = 200

10 = 199.8

Bypass

40.96

28.35

40.00

27.68

40.00

39.96

102.4

28.35

100.0

27.68

40.00

39.96

153.6

40.96

28.35

150.0

40.00

27.68

40.00

39.96

00 = 32768Hz

01 = 32000Hz

10 = 32000Hz

11 = 31968Hz

Note: Combinations shown in grey are unsupported and will be internally mapped to the default settings shown.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

CNFG_RTOR1 and CNFG_RTOR2 (0x1D & 0x1E)

CNFG_RTOR is a two-part read/write register that configures the operation, settings, and function of the RTOR heart

rate detection block. The first register contains algorithmic voltage gain and threshold parameters, the second contains

algorithmic timing parameters.

Table 30. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Maps

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

WNDW[3:0] GAIN[3:0]

CNFG_

RTOR1

EN_

RTOR

0x1D

R/W

x

PAVG[1:0]

RAVG[1:0]

PTSF[3:0]

x

HOFF[5:0]

CNFG_

RTOR2

0x1E

R/W

x

RHSF[2:0]

x

Table 31. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

CNFG_RTOR1 (0x1D)

This is the width of the averaging window, which adjusts the algorithm sensitivity to

the width of the QRS complex.

R to R Window Averaging (Window Width = RTOR_WNDW[3:0]*8ms)

0000 =

0001 =

6

8

0010 = 10

0011 = 12

0100 = 14

0101 = 16

0110 = 18

0111 = 20

1000 = 22

1001 = 24

1010 = 26

1011 = 28

(default = 96ms)

D[23:20]

eWNDW[3:0]

0011

1100 = Reserved. Do not use.

1101 = Reserved. Do not use.

1110 = Reserved. Do not use.

1111 = Reserved. Do not use.

R to R Gain (where Gain = 2^GAIN[3:0], plus an auto-scale option). This is used to

maximize the dynamic range of the algorithm.

0000 =

0001 =

0010 =

0011 =

1

2

4

8

1000 = 256

1001 = 512

1010 = 1024

D[19:16]

GAIN[3:0]

1111

1011 = 2048

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1100 = 4096

1101 = 8192

1110 = 16384

1111 = Auto-Scale (default)

In Auto-Scale mode, the initial gain is set to 64.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Table 31. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Functionality

(continued)

INDEX

NAME

DEFAULT

FUNCTION

ECG RTOR Detection Enable

0 = RTOR Detection disabled

D[15]

EN_RTOR

0

1 = RTOR Detection enabled if EN_ECG is also enabled.

R to R Peak Averaging Weight Factor

This sis the weighting factor for the current RTOR peak observation vs. past peak

observations when determining peak thresholds. Lower numbers weight current peaks

more heavily.

00 = 2

D[13:12]

D[11:8]

PAVG[1:0]

10

01 = 4

10 = 8 (default)

11 = 16

Peak_Average(n) =

[Peak(n) + (RTOR_PAVG-1) x Peak_Average(n-1)] / RTOR_PAVG.

R to R Peak Threshold Scaling Factor

PTSF[3:0]

HOFF[5:0]

0011

This is the fraction of the Peak Average value used in the Threshold computation.

Values of 1/16 to 16/16 are selected directly by (RTOR_PTSF[3:0]+1)/16, default is 4/16.

R to R Minimum Hold Oﬀ

This sets the absolute minimum interval used for the static portion of the Hold Oﬀ criteria.

Values of 0 to 63 are supported, default is 32

CNFG_

RTOR2

(0x1E)D

[21:16]

t

= HOFF[5:0] * t

RTOR

, where t

is ~8ms, as determined by

RTOR

HOLD_OFF_MIN

10_0000

FMSTR[1:0] in the CNFG_GEN register.

(representing approximately ¼ second).

The R to R Hold Oﬀ qualiﬁcation interval is

= MAX(t , t

t

) (see below).

Hold_Oﬀ

Hold_Oﬀ_Min Hold_Oﬀ_Dyn

R to R Interval Averaging Weight Factor

This is the weighting factor for the current RtoR interval observation vs. the past interval

observations when determining dynamic holdoﬀ criteria. Lower numbers weight current

intervals more heavily.

00 = 2

D[13:12]

RAVG[1:0]

10

01 = 4

10 = 8

(default)

11 = 16

Interval_Average(n) = [Interval(n) + (RAVG-1) x

Interval_Average(n-1)] / RAVG.

R to R Interval Hold Oﬀ Scaling Factor

This is the fraction of the RtoR average interval used for the dynamic portion of the holdoﬀ

criteria (t

).

HOLD_OFFDYN

D[10:8]

RHSF[2:0]

100

Values of 0/8 to 7/8 are selected directly by RTOR_RHSF[3:0]/8, default is 4/8.

If 000 (0/8) is selected, then no dynamic factor is used and the holdoﬀ criteria is

determined by HOFF[5:0] only (see above).

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

The write pointer is governed internally. To aide data

management and reduce µC overhead, the device

provides a user-programmable ECG FIFO Interrupt

Threshold (EFIT) governing the ECG Interrupt term (EINT).

This threshold can be programmed with values from 1 to

32, representing the number of unread ECG FIFO entries

required before the EINT term will be asserted, alerting

the µC that there is a significant amount of data in the

ECG FIFO ready for read back (see MNGR_INT (0x04)

for details).

FIFO Memory Description

The device provides FIFO memory for ECG information.

Single memory registers are also supported for heart rate

detection output data (RTOR). The operation of these

FIFO memories and registers is detailed in the following

sections.

Table 32 summarizes the method of access and data

structure within the FIFO memory.

ECG FIFO Memory (32 Words x 24 Bits)

If the write pointer ever traverses the entire FIFO array

and catches up to the read pointer (due to failure of the

µC to read/maintain FIFO data), a FIFO overflow will

occur and data will be corrupted. The EOVF STATUS

and tag bits will indicate this condition and the FIFO

should be cleared before continuing measurements using

either a SYNCH or FIFO_RST command—note overflow

events will result in the loss of samples and thus timing

information, so these conditions should not occur in well-

designed applications.

The ECG FIFO memory is a standard circular FIFO

consisting of 32 words, each with 24 bits of information.

The ECG FIFO is independently managed by internal

read and write pointers. The read pointer is updated in

response to the 32nd SCLK rising edge in a normal mode

read back transaction and on the (32+n x 24)th SCLK

rising edge(s) in a burst mode transaction. Once a FIFO

sample is marked as read, it cannot be accessed again.

Table 32. FIFO Memory Access and Data Structure Summary

CMD FIFO & MODE

DATA STRUCTURE (D [23:0])

O

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5 4 3 2 1 0

ETAG

[2:0]

PTAG

[2:0]

0x20

0x21

ECG Burst

ECG

ECG Sample Voltage Data [17:0]

ETAG

[2:0]

PTAG

[2:0]

ECG Sample Voltage Data [17:0]

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x25

RTOR

RTOR Interval Timing Data [13:0]

0

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

left justified two’s complement format. The remaining six

bits of data hold important data tagging information (see

details in Table 33).

ECG FIFO Data Structure

The data portion of the word contains the 18 Bit ECG voltage

information measured at the requested sample rate in

Table 33. ECG FIFO Data Tags (ETAG[2:0] = DO[5:3])

ETAG

[2:0]

DATA TIME

VALID VALID

MEANING

DETAILED DESCRIPTION

RECOMMENDED USER ACTION

Log sample into ECG record and increment

the time step.

Continue to gather data from the ECG FIFO.

000

Valid Sample

This is a valid FIFO sample.

Yes

No

Yes

This sample was taken while the ECG

channel was in a FAST recovery mode. Discard, note, or post-process this voltage

The voltage information is not valid, sample, but increment the time base.

but the sample represents a valid time Continue to gather data from the ECG FIFO.

step.

Fast Mode

Sample

001

010

Log sample into ECG record and increment

This is a valid FIFO sample, but this is

the time step.

Last Valid

Sample

(EOF)

the last sample currently available in

Yes

Suspend read back operations on the ECG

the FIFO (End of File indicator).

FIFO until more samples are available.

See above (ETAG=001), but in

addition, this is the last sample

currently available in the FIFO (End of Suspend read back operations on the ECG

Discard, note, or post-process this voltage

sample, but increment the time base.

Last Fast Mode

Sample

(EOF)

011

10x

110

No

--

Yes

--

File indicator).

FIFO until more samples are available.

Unused

Discard this sample, without incrementing

the time base.

Suspend read back operations on this FIFO

until more samples are available.

This is an invalid sample provided in

response to an SPI request to read an

empty FIFO.

FIFO Empty

(Exception)

No

Issue a FIFO_RST command to clear the

FIFO Overﬂow The FIFO has been allowed to overﬂow FIFOs or re-SYNCH if necessary.

111

No

(Exception)

– the data is corrupted.

Note the corresponding halt and resumption

in ECG/BIOZ time/voltage records.

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

ECG Data Tags (ETAG)

RTOR Interval Memory Register

(1 Word x 24 Bits)

The RTOR Interval (RTOR) memory register is a single

read-only register consisting of 14 bits of timing interval

information, left justified (and 8 unused bits, set to zero).

Three bits in the sample record are used as a ECG data

tag (ETAG[2:0] = DO[5:3]). This section outlines the

meaning of the various data tags used in the ECG FIFO

and recommended handling within the continuous ECG

record.

The RTOR register stores the time interval between the

last two R events, as identified by the RTOR detection

circuitry, which operates on the ECG output data. Each

LSB in the RTOR register is approximately equal to 8ms

(CNFG_GEN for exact figures). The resulting 14 bit

storage interval can thus be approximately 130 seconds

in length, again depending on device settings.

VALID: ETAG = 000 indicates the ECG data for this

sample represents both a valid voltage and time step in

the ECG record.

FAST: ETAG = 001 indicates the ECG data for this

sample was taken in the FAST settling mode and that the

voltage information in the sample should be treated as

transient and invalid. Note that while the voltage data is

invalid, samples of this type do represent valid time steps

in the ECG record.

Each time the RTOR detector identifies a new R event,

the RTOR register is updated, and the RRINT interrupt

term is asserted (see STATUS register for details).

VALID EOF: ETAG = 010 indicates the ECG data for this

sample represents both a valid voltage and time step in

the ECG record, and that this is the last sample currently

available in the ECG FIFO (End-of-File, EOF). The µC

should wait until further samples are available before

requesting more data from the ECG FIFO.

Users wishing to log heart rate based on RTOR register

data should set CLR_RRINT equals 01 in the MNGR_INT

register. This will clear the RRINT interrupt term after the

RTOR register has been read back, preparing the device

for identification of the next RTOR interval.

Users wishing to log heart rate based on the time elapsed

between RRINT assertions using the µC to keep track of

the time base (and ignoring the RTOR register data) have

two choices for interrupt management. If CLR_RRINT

equals 00 in the MNGR_INT register, the RRINT interrupt

term will clear after each STATUS register read back,

preparing the device for identification of the next RTOR

interval. If CLR_RRINT equals 10 in the MNGR_INT

register, the RRINT interrupt term will self-clear after each

one full ECG data cycle has passed, preparing the device

for identification of the next RTOR interval (this mode is

recommended only if using the INT2B as a dedicated

heart rate indicator).

FAST EOF: ETAG = 011 indicates the ECG data for this

sample was taken in the FAST settling mode and that the

voltage information in the sample should be treated as

transient and invalid. Note that while the voltage data is

invalid, samples of this type do represent valid time steps

in the ECG record. In addition, this is the last sample

currently available in the ECG FIFO (End-of-File, EOF).

The µC should wait until further samples are available

before requesting more data from the ECG FIFO.

EMPTY: ETAG = 110 is appended to any requested read

back data from an empty ECG FIFO. The presence

of this tag alerts the user that this FIFO data does not

represent a valid sample or time step. Note that if

handled properly by the µC, an occurrence of an empty

tag will not compromise the integrity of a continuous ECG

record – this tag only indicates that the read back request

was either premature or unnecessary.

If the RTOR detector reaches an overflow state after several

minutes without detection of an R event, the counter will

simply roll over, and the lack of the RRINT activity on the

dedicated INT2B line will inform the µC that no RTOR

activity was detected.

OVERFLOW: ETAG = 111 indicates that the ECG FIFO

has overflowed and that there are interruptions or missing

data in the sample records. The ECG Overflow (EOVF) bit

is also included in the STATUS register. A FIFO_RESET

is required to resolve this situation, effectively clearing

the FIFO so that valid sampling going forward is assured.

Depending on the application, it may also be necessary to

resynchronize the MAX30003 internal channel operations

to move forward with valid recordings, the SYNCH

command can perform this function while also resetting

the FIFO memories

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Typical Application Circuit

1kΩ

AVDD

DVDD

0VDD

ECGP

ENERGY

RATED

CSB

SDI

CSB

MOSI

SCLK

MISO

INTB

1kΩ

ECGN

SCLK

SDO

MCU

MAX30003

INTb

CAPP

INT2b

FCLK

CPLL

INT2B

FCLK

1µF

CAPN

VCM

VBG

VREF

1nF

10µF

0.1µF

10µF

0.1µF

10µF

1.0µF

10µF

Figure 11. Two-terminal, with Differential and Common-Mode Filtering Typical Operating Circuit

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Application Diagrams

Two Electrode Heart Rate Fitness

See Figure 12 for an example of a fitness monitoring configuration.

PCB

ELECTRODE MODEL

EXTERNAL EMI

FILTERS

Z_EL

ECGP

PHYSICAL

ELECTRODE

REPRESENTATION

ELECTRODE

POLARIZATION

VOLTAGE

MAX30003

1nF-50nF

±150mV

ECGN

50-200Ω

10kΩ-20MΩ

Figure 12. Two Electrode Heart Rate Monitoring for Fitness

Ordering Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PART

TEMP RANGE

0°C to +70°C

PIN-PACKAGE

28 TQFN-EP**

30 WLP

MAX30003CTI+

MAX30003CTI+T

MAX30003CWV+T

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

**EP = Exposed pad.

28-TQFN

30-WLP

T2855+8

21-0140

90-0028

Refer to

Application

Note 1891

Chip Information

PROCESS: CMOS

W302L2+1

21-100074

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MAX30003

Ultra-Low Power, Single-Channel Integrated

Biopotential (ECG, R-to-R Detection) AFE

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

6/16

Initial release

—

Updated Pin Description table, added part number to Ordering Information table, and

added additional Typical Operating Characteristics graphs

1

2

3

11/16

9/19

9/21

10, 47

19, 38

35

Updated Decimation Filter section and Tables 28 and 29

Updated Table 23

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is

assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that

may result from its use.Speciﬁcations subject to change without notice. No license is granted by implicationor

otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the

property of their respective owners.

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型号：	MAX30003WING
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	MAX30003 Biopotential AFE
文件：	总46页 (文件大小：2493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX30003WING [MAXIM]

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