MAX30004_技术文档

MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

General Description

Beneﬁts and Features

● Heart Rate Detection with Interrupt Feature

Eliminates the Need to Extract and Process the ECG

Data on the Microcontroller

The MAX30004 is a complete, biopotential, analog front-

end solution for wearable applications. It offers high

performance for clinical and fitness applications, with

ultra-low power for long battery life. The MAX30004 is a

single biopotential channel providing heart rate detection.

• Robust R-R Detection in High Motion Environment

at Extremely Low Power

● Clinical-Grade Biopotential AFE with High-Resolution

The biopotential channel has ESD protection, EMI filtering,

internal lead biasing, DC leads-off detection, ultra-low

power leads-on detection during standby mode. Soft power-

up sequencing ensures no large transients are injected

into the electrodes. The biopotential channel also has high

input impedance, low noise, high CMRR, programmable

gain, various low-pass and high-pass filter options, and

Data Converter

• 15.5 Bits Effective Resolution with 5µV

Noise

P-P

● Better Dry Starts Due to Much Improved Real World

CMRR and High Input Impedance

• Fully Differential Input Structure with CMRR > 100dB

● Offers Better Common-Mode to Differential Mode

Conversion Due to High Input Impedance

a

high resolution analog-to-digital converter. The

biopotential channel is DC coupled, can handle large

electrode voltage offsets, and has a fast recovery mode

to quickly recover from overdrive conditions, such as

defibrillation and electrosurgery.

• High Input Impedance > 500MΩ for Extremely Low

Common-to-Differential Mode Conversion

● Minimum Signal Attenuation at the Input During Dry

Start Due to High Electrode Impedance

The MAX30004 is available in a 28-pin TQFN and

30-bump wafer-level package (WLP), operating over the

0°C to +70°C commercial temperature range.

● High DC Offset Range of ±650mV (1.8V, typ) Allows

to Be Used with Wide Variety of Electrodes

● High AC Dynamic Range of 65mV

Will Help the

P-P

Applications

● Single Lead Wireless Patches for At-Home/

AFE Not Saturate in the Presence of Motion/Direct

Electrode Hits

In-Hospital Monitoring

● Chest Band Heart Rate Monitors for Fitness Applications

● Longer Battery Life Compared to Competing Solutions

• 85µW at 1.1V Supply Voltage

● Leads-On Interrupt Feature Keeps µC in Deep Sleep

Mode with RTC Off Until Valid Lead Condition is

Detected

Ordering Information appears at end of data sheet.

• Lead-On Detect Current: 0.7µA (typ)

● Conﬁgurable Interrupts Allows the µC Wake-Up Only on

Every Heart Beat Reducing the Overall System Power

● High-Speed SPI Interface

● Shutdown Current of 0.5µA (typ)

19-8732; Rev 0; 12/16

MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Functional Diagram

AVDD

DVDD

OVDD

MAX30004

BIOPOTENTIAL CHANNEL

CSB

SDI

AAF

INP

ESD, EMI,

14-BIT

INPUT MUX ,

DC LEAD

CHECK

INPUT

AMP

18-BIT

ΣΔ ADC

DECIMATION

FILTER

R-TO-R

DETECTOR

f_-3dB

=600Hz

PGA

INN

SCLK

SDO

SPI INTERFACE

AND

-40dB/dec

REGISTERS

FAST

SETTLING

INTB

CAPP

CAPN

INT2B

SUPPORT CIRCUITRY

COMMON -MODE

BUFFER

REFERENCE

BUFFER

f_CLK

FCLK

SEQUENCER

BANDGAP

BIASING

PLL

f_HFC

AGND

VCM

VBG

VREF

CPLL

DGND

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Absolute Maximum Ratings

AV

to AGND.....................................................-0.3V to +2.0V

Continuous Power Dissipation (T = +70°C)

A

DD

DV

AV

to DGND ....................................................-0.3V to +2.0V

to DV ......................................................-0.3V to +0.3V

DD

28-Pin TQFN (derate 34.5mW/°C above +70°C)...2758.6mW

30-Bump WLP (derate 24.3mW/°C

DD

OV

to DGND....................................................-0.3V to +3.6V

above +70°C).....................................................1945.5mW

Operating Temperature Range...............................0°C to +70°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -65°C to +150°C

Lead Temperature (Soldering, 10sec).............................+300°C

Soldering Temperature (reflow).......................................+260°C

DD

AGND to DGND ...................................................-0.3V to +0.3V

CSB, SCLK, SDI, FCLK to DGND .......................-0.3V to +3.6V

SDO, INTB, INT2B to

DGND.............-0.3V to the lower of (3.6V and OV

All other pins to

+ 0.3V)

DD

AGND ..............-0.3V to the lower of (2.0V and AV

+ 0.3V)

DD

Maximum Current into Any Pin.........................................±50mA

(Note 1)

Package Thermal Characteristics

TQFN

WLP

Junction-to-Ambient Thermal Resistance (θ ) ..........29°C/W

Junction-to-Ambient Thermal Resistance (θ ) ..........44°C/W

JA

Junction-to-Case Thermal Resistance (θ ).................2°C/W

JC

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Electrical Characteristics

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

-15

TYP

MAX

+15

UNITS

BIOPOTENTIAL CHANNEL

V

= +1.1V, THD < 0.3%

= +1.8V, THD < 0.3%

AVDD

AC Differential Input Range

mV

p-p

±32.5

±650

= +1.1V, shift from nominal gain < 2%

= +1.8V

-300

+300

DC Differential Input Range

Common Mode Input Range

mV

= +1.1V, from V

, shift from

MID

-150

+150

nominal gain < 2%

mV

dB

V

= +1.8V, from V

, shift from

AVDD

MID

±550

nominal gain < 2%

0W source impedance, f = 64Hz (Note 3)

115

77

105

Common Mode Rejection

Ratio

CMRR

(Note 4)

0.82

5.4

µV

RMS

BW = 0.05 - 150Hz, G

= 20x

CH

µV

p-p

Input Referred Noise

0.53

3.5

1.0

6.6

+1

RMS

BW = 0.05 - 40Hz, G

= 20x (Note 3)

CH

µV

p-p

Input Leakage Current

Input Impedance (INA)

T

= +25°C

-1

0.1

nA

A

Common-mode, DC

Differential, DC

45

GΩ

MΩ

1500

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

= +1.80V, V = 65mV

,

AVDD

IN

p-p

F

= 64Hz, G

= 20x,

0.025

IN

CH

electrode offset = ±300mV

= +1.1V, V = 30mV ,

p-p

Total Harmonic Distortion

THD

%

V

AVDD

IN

F

= 64Hz, G

= 20x,

0.3

IN

CH

electrode offset = ±300mV

Programmable, see Register Map

20 to

160

Gain Setting

Gain Error

G

V/V

%

CH

V

= +1.8V, G

= 20x,

AVDD

CH

-2.5

-4.5

+2.5

+4.5

INP = INN = VMID

V

= +1.1V, G

AVDD

CH

%

INP = INN = VMID

% of

FSR

Offset Error

(Note 5)

0.1

18

ADC Resolution

Bits

125 to

512

ADC Sample Rate

Programmable, see Register Map

FHP = 1/(2R x R x C ), C =

HPF

SPS

HPF

CAPP to CAPN Impedance

R

320

450

600

kΩ

HPF

capacitance between CAPP and CAPN

Fast recovery enabled (1.8V)

Fast recovery enabled (1.1V)

Fast recovery disabled

160

55

Analog High-Pass Filter Slew

Current

µA

0.09

Fast Settling Recovery Time

Digital Low Pass Filter

C

= 10µF

500

40

ms

Hz

HPF

DLPF[0:1] = 01

DLPF[0:1] = 10

DLPF[0:1] = 11

Linear phase

FIR ﬁlter.

100

150

0.5

Digital High Pass Filter

Power Supply Rejection

INPUT MUX

Phase-corrected 1st-order IIR ﬁlter. DHPF = 1

Hz

dB

Lead bias disabled, DC

107

110

PSRR

Lead bias disabled, f

= 64Hz

SW

DCLOFF_IMAG[2:0] = 001

DCLOFF_IMAG[2:0] = 010

DCLOFF_IMAG[2:0] = 011

DCLOFF_IMAG[2:0] = 100

DCLOFF_IMAG[2:0] = 101

5

10

Pullup/

pulldown

DC Lead Off Check

nA

20

50

100

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

SYMBOL

CONDITIONS

DCLOFF_VTH[1:0] = 11 (Note 6)

DCLOFF_VTH[1:0] = 10 (Note 7)

DCLOFF_VTH[1:0] = 01 (Note 8)

DCLOFF_VTH[1:0] = 00

MIN

TYP

- 0.50

MAX

UNITS

V

MID

- 0.45

- 0.40

- 0.30

+ 0.50

+ 0.45

+ 0.40

+ 0.30

DC Lead Off Comparator Low

Threshold

V

DCLOFF_VTH[1:0] = 11 (Note 6)

DCLOFF_VTH[1:0] = 10 (Note 7)

DCLOFF_VTH[1:0] = 01 (Note 8)

DCLOFF_VTH[1:0] = 00

V

DC Lead Off Comparator

High Threshold

V

RBIASV[1:0] = 00

50

Lead bias

enabled

RBIASV[1:0] = 10

Lead bias enabled

Lead Bias Impedance

Lead Bias Voltage

RBIASV[1:0] = 01

100

200

MΩ

V

/

AVDD

2.15

V

MID

INTERNAL REFERENCE/COMMON-MODE

V

Output Voltage

V

0.650

100

V

BG

V

Output Impedance

kΩ

External V

Capacitor

Compensation

BG

C

V

1

µF

VBG

V

Output Voltage

T

= +25°C

0.995

1.000

10

1.005

V

REF

A

Temperature Coefﬁcient

Buffer Line Regulation

Buffer Load

TC

= 0°C to +70°C

ppm/°C

µV/V

REF

A

330

I

= 0 to 100µA

25

µV/µA

LOAD

Regulation

External V

Capacitor

Compensation

REF

C

1

10

0.650

10

µF

V

REF

V

Output Voltage

V

CM

External V

Capacitor

Compensation

CM

C

1

µF

DIGITAL INPUTS (SDI, SCLK, CSB, FCLK)

0.7 ×

Input-Voltage High

Input-Voltage Low

Input Hysteresis

V

IH

V

OVDD

0.3 ×

V

IL

V

OVDD

0.05 ×

V

HYS

V

OVDD

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Electrical Characteristics (continued)

(V

= V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, f

= 32.768kHz, T = T

to T

, unless otherwise noted. Typical

MAX

DVDD

AVDD

OVDD

FCLK

A

MIN

values are at V

= V

= +1.8V, V = +2.5V, T = +25°C.) (Note 2)

OVDD A

DVDD

AVDD

PARAMETER

Input Capacitance

Input Current

DIGITAL OUTPUTS (SDO, INTB, INT2B)

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

pF

C

10

IN

I

-1

+1

µA

IN

V

OVDD

– 0.4

Output Voltage High

V

I

= 1mA

SOURCE

V

OH

Output Voltage Low

V

= 1mA

SINK

0.4

+1

V

OL

Three-State Leakage Current

-1

µA

Three-State Output

Capacitance

15

pF

POWER SUPPLY

Analog Supply Voltage

V

Connect V

to V

DVDD

1.1

2.0

V

AVDD

DVDD

Digital Supply Voltage

V

to V

1.1

2.0

3.6

V

DVDD

AVDD

Interface Supply Voltage

Power for I/O drivers only

1.65

OVDD

V

= V

= +1.1V

= +1.8V

= +2.0V

76

AVDD

DVDD

R-R

Operation

100

I

+

AVDD

I

Supply Current

µA

110

0.98

0.73

122

2.5

DVDD

T

= +70°C

= +25°C

A

ULP Lead

On Detect

V

= +1.65V, ADC at 512sps (Note 9)

= +3.6V, ADC at 512sps (Note 9)

0.2

0.6

OVDD

Interface Supply Current

Shutdown Current

I

µA

OVDD

1.6

V

2.0V

=

T = +70°C

0.79

0.51

AVDD

DVDD

A

I

+

SAVDD

=

I

SDVDD

T

= +25°C

2.5

1.1

A

I

V

= +3.6V, V

= V

= +2.0V

SOVDD

OVDD

AVDD

DVDD

ESD PROTECTION

IEC61000-4-2 Contact Discharge (Note 10)

IEC61000-4-2 Air-Gap Discharge (Note 10)

HMM

±8

±15

±8

INP, INN

kV

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Timing Characteristics

(V

V

= V

= +1.8V, V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DVDD

AVDD

OVDD

A

MIN

= +2.5V, T = +25°C.) (Notes 2, 3)

OVDD A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS

SCLK Frequency

f

t

0

12

MHz

ns

SCLK

CP

SCLK Period

83

15

SCLK Pulse Width High

SCLK Pulse Width Low

ns

CH

ns

CL

CSB Fall to SCLK Rise

Setup Time

t

To 1st SCLK rising edge (RE)

15

0

ns

CSS0

CSH0

CSH1

CSA

CSB Fall to SCLK Rise

Hold Time

Applies to inactive RE preceding 1st RE

Applies to 32nd RE, executed write

CSB Rise to SCLK Rise

Hold Time

10

15

Applies to 32nd RE, aborted write

sequence

CSB Rise to SCLK Rise

SCLK Rise to CSB Fall

t

Applies to 32nd RE

100

20

8

ns

CSF

CSPW

DS

CSB Pulse-Width High

SDI-to-SCLK Rise Setup Time

SDI to SCLK Rise Hold Time

8

DH

C

= 20pf

40

20

LOAD

SCLK Fall to SDO Transition

t

DOT

= 20pf, V

= V

≥ 1.8V,

LOAD

DVDD

AVDD

DVDD

ns

V

≥ 2.5V

SCLK Fall to SDO Hold

CSB Fall to SDO Fall

t

C

= 20pf

LOAD

2

ns

DOH

DOE

Enable time, C

= 20pf

30

LOAD

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Timing Characteristics (continued)

(V

V

= V

= +1.8V, V

= +1.1V to +2.0V, V

= +1.65V to +3.6V, T = T

to T

, unless otherwise noted. Typical values are at

MAX

DVDD

AVDD

OVDD

A

MIN

= +2.5V, T = +25°C.) (Notes 2, 3)

OVDD A

PARAMETER

SYMBOL

CONDITIONS

Disable time

MIN

TYP

MAX

UNITS

ns

CSB Rise to SDO Hi-Z

FCLK Frequency

t

f

t

35

DOZ

FCLK

FP

External reference clock

32.768

kHz

µs

FCLK Period

30.52

15.26

FCLK Pulse-Width High

FCLK Pulse-Width Low

50% duty cycle assumed

µs

FH

µs

FL

Note 2: Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are

A

guaranteed by design and characterization.

Note 3: Guaranteed by design and characterization. Not tested in production.

Note 4: One electrode drive with <10Ω source impedance, the other driven with 51kΩ in parallel with a 47nF per IEC60601-2-47.

Note 5: Inputs connected to 51kΩ in parallel with a 47nF to V

.

CM

Note 6: Use this setting only for V

Note 7: Use this setting only for V

Note 8: Use this setting only for V

= V

≥ 1.65V.

≥ 1.55V.

≥ 1.45V.

AVDD

DVDD

Note 9: f

= 4MHz, burst mode, EFIT = 8, C

= C

= 50pF.

SCLK

SDO

INTB

Note 10: ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.

SDI

A6

A5

t_DS

A4

A3

t_DH

A2

t_CP

A1

A0

R/WB D_IN23 D_IN22

D_IN1

D_IN0

A6'

SCLK

1

2

3

4

5

6

7

8

9

10

31

32

1'

t_CSA

t_CSH0

t_CH

t_CSH1

t_CSS0

t_CL

CSB

SDO

t_CSPW

Z

t_DOT

t_DOH

t_CSF

Z

D_O23

D_O22

D_O1

D_O0

t_DOZ

t_DOE

Figure 1a. SPI Timing Diagram

t_FP

FCLK

t_FH

t_FL

Figure 1b. FCLK Timing Diagram

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Typical Operating Characteristics

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

CHANNEL NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 20, LPF = 40Hz

CHANNEL NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 20, LPF = 150Hz

CHANNEL NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 160, LPF = 40Hz

toc01

toc02

toc03

0

-50

0

-50

0

-50

-100

-150

-200

-250

-100

-150

-200

-250

-100

-150

-200

-250

0

64

128

192

256

0

64

128

192

256

0

64

128

192

256

FREQUENCY (Hz)

CHANNEL INPUT-REFERRED NOISE vs.TIME

GAIN = 20, LPF = 40Hz

CHANNEL NOISE SPECTRUM vs. FREQUENCY

INPUTS SHORTED, GAIN = 160, LPF = 150Hz

(10 seconds)

toc05

toc04

4

3

0

-50

-100

-150

-200

-250

2

1

0

-1

-2

-3

-4

0

2

4

6

8

10

0

64

128

192

256

TIME (s)

FREQUENCY (Hz)

CHANNEL INPUT-REFERRED NOISE vs. TIME

GAIN = 20, LPF = 150Hz

CHANNEL INPUT-REFERRED NOISE vs. TIME

GAIN = 160, LPF = 40Hz

(10 seconds)

toc06

toc07

4

3

4

3

2

1

0

-1

-2

-3

-4

-1

-2

-3

-4

0

2

4

6

8

10

0

2

4

6

8

10

TIME (s)

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Typical Operating Characteristics

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

CHANNEL INPUT-REFERRED NOISE vs. TIME

GAIN = 160, LPF = 150Hz

DIFFERENTIAL INPUT RESISTANCE

vs. FREQUENCY

CHANNEL PSRR vs. FREQUENCY

(10 seconds)

toc08

toc09

toc10

4

3

1000

100

10

10000

1000

100

10

NO LEAD

BIAS

2

1

0

200MΩ

LEAD BIAS

50MΩ

LEAD

BIAS

-1

-2

-3

-4

100MΩ

LEAD BIAS

1

0

64

128

192

256

0

2

4

6

8

10

0

0.5

1

1.5

2

2.5

FREQUENCY (Hz)

TIME (s)

FREQUENCY (MHz)

DIFFERENTIAL INPUT RESISTANCE

vs. VOLTAGE

COMMON-MODE INPUT

RESISTANCE vs. FREQUENCY

toc11

toc12

10000

NO LEAD

BIAS

200MΩ

LEAD BIAS

200MΩ

LEAD BIAS

NO LEAD

BIAS

1000

100

10

1000

100

10

100MΩ

LEAD BIAS

50MΩ

LEAD

BIAS

100MΩ

LEAD BIAS

50MΩ

LEAD BIAS

1

0

64

128

FREQUENCY (Hz)

192

256

-500

-300

-100

100

300

500

V_INP-V_INN(mV)

COMMON-MODE INPUT

RESISTANCE vs. VOLTAGE

RESISTANCE vs. TEMPERATURE

toc13

toc14

10000000

1000000

100000

10000

1000

1000000.00

100000.00

10000.00

1000.00

100.00

NO LEAD

BIAS

NO LEAD

BIAS

200MΩ

LEAD BIAS

200MΩ

LEAD BIAS

100

10.00

100MΩ

50MΩ

LEAD BIAS

10

50MΩ

LEAD BIAS

100MΩ

LEAD BIAS

1.00

1

0

10

20

30

40

50

60

70

-400

-200

0

200

400

TEMPERATURE (°C)

V_CM-V_MID(mV)

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Typical Operating Characteristics

(V

= V

= +1.8V, V

= 2.5V, T = +25°C, unless otherwise noted.)

DVDD

AVDD

OVDD A

DIFFERENTIAL INPUT

RESISTANCE vs. TEMPERATURE

VREF vs. TEMPERATURE

toc15

toc16

10000.00

1000.00

100.00

10.00

1000.6

1000.5

1000.4

1000.3

1000.2

1000.1

1000

NO LEAD

BIAS

200MΩ

LEAD BIAS

100MΩ

LEAD BIAS

50MΩ

LEAD BIAS

999.9

999.8

999.7

999.6

1.00

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

AVDD AND DVDD SUPPLY CURRENT

(RtoR ENABLED) vs. TEMPERATURE

AVDD AND DVDD ULP CURRENT

vs. TEMPERATURE

toc18

toc17

1.2

1

120

110

100

90

2.0V

1.8V

2.0V

0.8

0.6

0.4

0.2

0

1.8V

1.5V

80

1.1V

70

1.1V

60

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

OVDD SHUTDOWN CURRENT

vs. TEMPERATURE

and AVDD (OVDD = 3.6V)

AVDD SHUTDOWN CURRENT

toc19

toc20

0.25

0.20

0.15

0.10

0.05

0.00

0.12

0.10

0.08

0.06

0.04

0.02

0.00

V_AVDD= 1.1V

2.0V

V_AVDD= 1.5V

V_AVDD= 1.8V

V_AVDD= 2.0V

1.8V

1.5V

1.1V

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

TEMPERATURE (°C)

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Pin Conﬁgurations

Pin Description

BUMP

WLP

NAME

FUNCTION

TQFN

1, 2, 4, 5, 24,

26

A1, A2, A3,

A4, B2, C2

I.C.

Internally Connected. Connect to AGND.

B3, B4, C3,

C4, D4

Analog Power and Reference Ground. Connect into the printed circuit board

ground plane.

3,8,28

AGND

6

7

A5

A6

INP

INN

Positive Input

Negative Input

Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (CHPF) between CAPP

and CAPN to form a 0.5Hz high-pass response in the channel.

9

B6

CAPP

Analog High-Pass Filter Input. Connect a 1μF X7R capacitor (CHPF) between CAPP

and CAPN to form a 0.5Hz high-pass response in the channel.

10

11

B5

C6

CAPN

CPLL

PLL Loop Filter Input. Connect 1nf COG cap between CPLL and AGND.

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Pin Description (continued)

BUMP

WLP

NAME

FUNCTION

TQFN

Digital Ground for Both Digital Core and I/O Pad Drivers. Recommended to connect

to AGND plane.

12

13

14

C5

D6

D5

DGND

DVDD

FCLK

Digital Core Supply Voltage. Connect to AVDD

External 32.768kHz Clock that Controls the Sampling of the Internal Sigma-Delta

Converters and Decimator.

15

16

E6

E5

CSB

Active-Low Chip-Select Input. Enables the serial interface.

SCLK

Serial Clock Input. Clocks data in and out of the serial interface when CSB is low.

Serial Data Input. SDI is sampled into the device on the rising edge of SCLK when

CSB is low.

17

E4

SDI

Serial Data Output. SDO will change state on the falling edge of SCLK when CSB

is low. SDO is three-stated when CSB is high.

18

19

20

E3

D3

E2

SDO

OVDD

INT2B

Logic Interface Supply Voltage

Interrupt 2 Output. INT2B is an active-low status output. It can be used to interrupt

an external device.

Interrupt Output. INTB is an active low status output. It can be used to interrupt an

external device.

21

22

23

D2

E1

D1

INTB

AVDD

VREF

Analog Core Supply Voltage. Connect to DVDD.

ADC Reference Buffer Output. Connect a 10μF X5R ceramic capacitor between

VREF and AGND.

Common Mode Buffer Output. Connect a 10μF X5R ceramic capacitor between

VCM and AGND.

25

C1

VCM

Bandgap Noise Filter Output. Connect a 1.0μF X7R ceramic capacitor between

VBG and AGND.

27

B1

—

VBG

—

EP

Exposed Paddle. Connect to AGND.

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

filtering, lead biasing, leads off checking, and ultra-low

power leads-on checking. The output of this analog channel

drives a high-resolution ADC.

Detailed Description

Biopotential Channel

Figure 2 illustrates the biopotential channel block diagram,

excluding the ADC. The channel comprises an input

MUX, a fast-recovering instrumentation amplifier, an anti-

alias filter, and a programmable gain amplifier. The MUX

includes several features such as ESD protection, EMI

Input MUX

The input MUX shown in Figure 3 contains integrated

ESD and EMI protection, DC leads off detect current

sources, lead-on detect, series isolation switches, and

lead biasing.

PCB

AAF

INP

ESD, EMI,

INPUT MUX ,

DC LEAD

CHECK

INPUT

AMP

PGA

INN

f

= 600Hz

-3dB

-40dB/dec

FAST

SETTLING

CAPP

CAPN

C

MAX30004

HPF

Figure 2. Channel Input Amplifier and PGA Excluding the ADC

MAX30004

ESD PROTECTION

AND

EMI FILTER

INPUT AND

POLARITY

SWITCHES

ULP LEAD-ON

CHECK

LEAD

BIAS

DC LEAD-OFF CHECK

V_THH

AV_DD

V_MID

50,

15MΩ

100,

200MΩ

5-100nA

V_THL

TO ECG

INA IN+

INP

AV_DD

5-100nA

R

AGND

5-100nA

3R

AGND

TO ECG

INA IN-

AGND

INN

V_THH

5-100nA

50,

100,

200MΩ

5MΩ

AGND

V_THL

AGND

V_MID

Figure 3. Input MUX

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

protects against false flags generated by the input amplifier

and input chopping. The comparator checks for a minimum

continuous violation (or threshold exceeded) of 115ms to

140ms depending on the setting of FMSTR[1:0] before

asserting any one of the LDOFF_* interrupt flags (Figure

4). See registers CNFG_GEN (0x10) and CNFG_MUX

0x14) for configuration settings and see Table 1 for

recommended values given electrode type and supply

voltage.

The ULP lead on detect operates by pulling INN low with a

pulldown resistance larger than 5mΩ and pulling INP high

with a pullup resistance larger than 15mΩ. A low-power

comparator determines if INP is pulled below a

predefined threshold that occurs when both electrodes

make contact with the body. When the impedance between

INP and INN is less than 20Ω, an interrupt LONINT is

asserted, alerting the µC to a leads-on condition.

EMI Filtering and ESD Protection

EMI filtering of the INP and INN inputs consists of a single

pole, low pass, differential, and common mode filter with

the pole located at approximately 2MHz. The INP and INN

inputs also have input clamps that protect the inputs from

ESD events.

● ±8kV using the Contact Discharge method specified

in IEC61000-4-2 ESD

● ±15kV using the Air Gap Discharge method specified

in IEC61000-4-2 ESD

● ±8kV HBM

● For IEC61000-4-2 ESD protection, use 1kΩ series

resistors on INP and INN that is rated to withstand

8kV surge voltages.

DC Leads-Off Detection and ULP

Leads-On Detection

The input MUX leads-off detect circuitry consists of

programmable sink/source DC current sources that allow

for DC leads-off detection, while the channel is powered

up in normal operation and an ultra-low-power (ULP)

leads-on detect while the channel is powered-down.

A 0nA/V

± 300mV selection is available allowing

MID

monitoring of the input compliance of the INA during non-

DC lead-off checks.

Lead Bias

The MAX30004 limits the INP and INN DC input common

The MAX30004 accomplishes DC leads-off detection by

applying a DC current to pull the input voltage up to above

mode range to V

±150mV. This range can be maintained

MID

either through external/internal lead-biasing.

V

MID

+ V

or down to below V - V . The current

MID TH

TH

sources have user selectable values of 0nA, 5nA, 10nA,

20nA, 50nA, and 100nA that allow coverage of dry and

wet electrode impedance ranges. Supported thresholds

Internal DC lead-biasing consists of 50MΩ, 100MΩ,

or 200MΩ selectable resistors to V

that drive the

MID

electrodes within the input common mode requirements

of the channel and can drive the connected body to the

proper common mode voltage level. See register CNFG_

GEN (0x10) to select a configuration.

are V

± 0.30V (recommended), V

± 0.40V, V

±

MID

0.45V, and V

± 0.50V. A threshold of 400mV, 450mV,

MID

and 500mV should only be used when V

≥ 1.45V,

AVDD

1.55V, and 1.65V, respectively. A dynamic comparator

V_DD

VTHH

V_MID

INP,N

VTHL

VSS

ABOVE

BELOW

THRESHOLD

>115ms

<115ms

INTB

LDOFF_*H

BITS

ASSERTED

Figure 4. Lead-Off Detect Behavior

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 1. Recommended Lead Bias (Rb), Current Source Values,

and Thresholds for Electrode Impedances

ELECTRODE IMPEDANCE

I

V

DC

100kΩ -

200kΩ

200kΩ -

400kΩ

400kΩ -

1MΩ

1MΩ -

2MΩ

2MΩ - 4

MΩ

4MΩ -

10MΩ

10MΩ -

20MΩ

TH

<100kΩ

All settings of R

b

I

= 10nA

V

= V

DC

TH MID

± 300mV, ±400mV

All settings

of R

b

All settings of R

All settings of V

V

= V

b

TH MID

= 20nA

±400mV,

±450mV,

±500mV

TH

All settings

of R

b

= V

All settings of R

b

I

= 50nA

V

DC

TH MID

All settings of V

TH

±450mV,

±500mV

All settings

of Rb

All settings of R

V

= V

b

TH MID

= 100nA

DC

All settings of V

±400mV,

±450mV,

±500mV

TH

provides the most motion artifact rejection, making it best

suited for heart rate monitoring. 0.5Hz and 0.05Hz can be

used for applications requiring moderate and no motion

artifact rejection respectively. The high-pass corner

frequency is calculated by the following equation:

Isolation Switches

The series switches in the MAX30004 isolate INP and

INN pins (subject) from the internal signal path. the series

switches are disabled by default. They must be enabled

to record R-to-R data.

1/(2π x R

x C

)

HPF

Gain Settings and Input Range

RHPF is specified in the Electrical Characteristics table.

The device’s biopotential channel contains an input

instrumentation amplifier that provides low-noise, fixed

20V/V gain amplification of the differential signal, rejects

differential DC voltage due to electrode polarization,

rejects common-mode interference primarily due to AC

mains interference, and provides high input impedance

to guarantee high CMRR even in the presence of severe

electrode impedance mismatch (see Figure 2). The differ-

ential DC rejection corner frequency is set by an external

Following the instrumentation amplifier is a 2-pole active

anti-aliasing filter with a 600Hz -3dB frequency that

provides57dBofattenuationathalfthemodulatorsampling

rate (approximately 16kHz) and a PGAwith programmable

gains of 1, 2, 4, and 8V/V for an overall gain of 20, 40, 80,

and 160V/V. The instrumentation amplifier and PGA are

chopped to minimize offset and 1/f noise. Gain settings are

configured through the CNFG_CH (0x15) register. The

useable common-mode range is V

±150mV, internal

MID

capacitor (C

) placed between pins CAPP and CAPN,

HPF

lead biasing can be used to meet this requirement. The

useable DC differential range is ±300mV to allow for

electrode polarization voltages on each electrode. The

refer to Table 2 for appropriate value selection. There are

three recommended options for the cutoff frequency: 5Hz,

0.5Hz, and 0.05Hz. Setting the cutoff frequency to 5Hz

input AC differential range is ±32.5mV or ±65mV

.

P-P

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

in the MNGR_DYN (0x05) register and accumulates the

time that the ADC output exceeds either the positive or

negative threshold. If the saturation counter exceeds

125ms, it triggers the fast settling mode (if enabled) and

resets. The saturation counter can also be reset prior to

triggering the fast settling mode if the ADC output falls

Table 2. Analog HPF Corner Frequency

Selection

C

HPF CORNER FREQUENCY

HPF

0.1µ

1.0µ

10µ

≤ 5Hz

≤ 0.5Hz

≤ 0.05Hz

below the threshold continuously for 125ms (t

). This

BLW

feature is designed to avoid false triggers due to the

QRS complex. Once triggered, fast settling mode will be

engaged for 500ms, see Figure 5.

Fast Recovery Mode

The input instrumentation amplifier has the ability to

rapidly recover from an excessive overdrive event such

as a defibrillation pulse, high-voltage external pacing,

and electro-surgery interference. There are two modes of

recovery that can be used: automatic or manual recovery.

The mode is programmed by the FAST[1:0] bits in the

MNGR_DYN (0x05) register.

In manual mode, a user algorithm running on the host

microcontroller or an external stimulus input will generate

the trigger to enter fast recovery mode. The host

microcontroller then enables the manual fast recovery

mode in the MNGR_DYN (0x05) register. The manual fast

recovery mode can be of a much shorter duration than

the automatic mode and allows for more rapid recovery.

One such example is recovery from external high-voltage

pacing signals in a few milliseconds to allow the observation

of a subsequent p-wave.

Automatic mode engages once the saturation counter

exceeds approximately 125ms (t

). The counter is

SAT

activated the first time the ADC output exceeds the

symmetrical threshold defined by the FAST_TH[5:0] bits

Figure 5. Automatic Fast Settling Behavior

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

WNDW[3:0] bits in the CNFG_RTOR (0x1D) register. The

R-to-R Detection

The MAX30004 contains built-in hardware to detect

R-to-R intervals using an adaptation of the Pan-Tompkins

detection delay (t

equation:

) is described by the following

R2R_DET

t

= 5,376 + 256 x WNDW in FMSTR clocks

1

R2R_DET

QRS detection algorithm . The timing resolution of the

where WNDW is an integer from 0 to 15 and the total

latency (t ) is the sum of the two delays and

R-R interval is approximately 8ms and depends on the

setting of FMSTR [1:0] in CNFG_GEN (0x10) register. See

Table 19 for the timing resolution of each setting.

R2R_DEL

summarized in the equation below:

= t + t = 3,370 + 5,376 +

R2R_DET

t

R2R_DEL

R2R_DEC

When an R event is identified, the RRINT status bit is

asserted and the RTOR_REG (0x25) register is updated

with the count seen since the last R event. Figure 6 illustrates

the R-R interval on a QRS complex. Refer to registers

CNFG_RTOR1 (0x1D) and CNFG_RTOR2 (0x1E) for

configuration details.

256 x WNDW in FMSTR clocks where WNDW

is an integer from 0 to 15.

Reference and Common Mode Buffer

The MAX30004 features internally generated reference

voltages. The bandgap output (V ) pin requires an

BG

external 1.0µF capacitor to AGND and the reference

The latency of the R-to-R value written to the RTOR

Interval Memory Register is the sum of the R-to-R

decimation delay and the R-to-R detection delay blocks.

The R-to-R decimation factor is fixed at 256 and the

output (V

) pin requires a 10µF external capacitor to

REF

AGND for compensation and noise filtering.

A common-mode buffer is provided to buffer 650mV

which is used to drive common mode voltages for internal

decimation delay (t

) is always 3,370 FMSTR

R2R_DEC

blocks. Use a 10µF external capacitor between V

AGND to provide compensation and noise filtering.

to

CM

clocks, as shown in Table 3.

The detection circuit consists of several digital filters

and signal processing delays. These depend on the

R-R INTERVAL

Figure 6. R-to-R Interval Illustration

Table 3. R-to-R Decimation Delay in ms and FMSTR CLK vs. Register Settings,

FCLK = 32.768Hz

DELAY IN R-TO-R DECIMATION

FMSTR

[1:0]

FMSTR FREQ

IN FCLKs

FMSTR

FREQ (Hz)

RTOR TIME

RESOLUTION (ms)

DECIMATION

IN FMSTR CLKs

IN ms

102.844

00

FCLK

32,768

256

7.8125

8.0

3370

01

10

11

FCLK x 625/640

FCLK x 640/656

32,000

105.313

105.415

32,000

8.0

31,968.78

8.0078

1

J. Pan and W.J. Tompkins, “A Real-Time QRS Detection Algorithm,” IEEE Trans. Biomed. Eng., vol. 32, pp. 230-236

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

command word (comprised of a seven bit address and a

Read/Write mode indicator (i.e., A[6:0] + R/W) followed

by a three-byte data word. The MAX30004 is compatible

with the CPOL = 0/CPHA = 0 and CPOL = 1/CPHA = 1

modes of operation.

Write mode operations will be executed on the 32nd SCLK

rising edge using the first four bytes of data available.

In write mode, any data supplied after the 32nd SCLK

rising edge will be ignored. Subsequent writes require CSB

to de-assert high and then assert low for the next write

command. In order to abort a command sequence, the

rise of CSB must precede the updating (32nd) rising-edge

Sample Synchronization Pulse

The MAX30004 offers a sample synchronization pulse

that allows the direct observation of the channel sample

instant for either synchronization between multiple devices

or as a monitoring feature during debug. When enabled

(EN_SAMP in either register EN_INT or EN_INT2), the

MAX30004 generates an interrupt either every sample

instant, or every second, fourth, or 16th sample instant,

based on the setting of SAMP_IT[1:0] in register MNGR_

INT. The sample instants are defined by the channel

ADC, and are not R-to-R samples. Therefore, the interval

between individual sample instants is dependent on

the channel data rate as defined by FMSTR[1:0] and

RATE[1:0]. The clear behavior of the sample synchroni-

zation pulse is affected by the CLR_SAMP bit in register

MNGR_INT. When this feature is used, it is recommended

to use a dedicated interrupt output for just the sample

synchronization pulse.

of SCLK, meeting the t

requirement.

CSA

Read mode operations will access the requested data

on the 8th SCLK rising edge, and present the MSB of

the requested data on the following SCLK falling edge,

allowing the µC to sample the data MSB on the 9th

SCLK rising edge. Configuration and status data are all

available via normal mode read back sequences. If more

than 32 SCLK rising edges are provided in a normal read

sequence then the excess edges will be ignored and the

device will read back zeros.

SPI Interface Description

32-Bit Read/Write Sequences

The MAX30004 interface is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

in Figure 1. Data is strobed into the MAX30004 on SCLK

rising edges. The device is programmed and accessed by

a 32 cycle SPI instruction framed by a CSB low interval.

The content of the SPI operation consists of a one byte

If accessing the STATUS register, all interrupt updates

will be made in response to the 30th SCLK rising edge,

allowing for internal synchronization operations to occur.

Figure 7. SPI Normal Mode Transaction Diagrams

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

STATUS (0x01) Register

Register Descriptions

STATUS is a read-only register that provides a compre-

hensive overview of the current status of the device. The

first two bytes indicate the state of all interrupt terms

(regardless of whether interrupts are enabled in registers

EN_INT (0x02) or EN_INT2 (0x03)). All interrupt terms

are active high. The last byte includes detailed status

information for conditions associated with the interrupt

terms.

NO_OP (0x00 and 0x7F) Registers

No Operation (NO_OP) registers are read-write registers

that have no internal effect on the device. If these

registers are read back, DOUT remains zero for the entire

SPI transaction. Any attempt to write to these registers is

ignored without impact to internal operation.

Table 4. STATUS (0x01) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

x

16 / 8 / 0

x

DCLOFF

x

FSTINT

x

INT

0x01

STATUS

R

x

LONINT

RRINT

SAMP

PLLINT

LDOFF_

PH

LDOFF_

PL

LDOFF_

NH

LDOFF_

NL

x

Table 5. Status (0x01) Register Meaning

INDEX

NAME

MEANING

Fast Recovery Mode. Issued when the Fast Recovery Mode is engaged

(either manually or automatically).

D[21]

FSTINT

Status and Interrupt Clear behavior is deﬁned by CLR_FAST, see MNGR_INT for details.

DC Lead-Off Detection Interrupt. Indicates that the MAX30004 has determined it is in leads off

condition (as selected in CNFG_GEN) for more than 115ms.

Remains active as long as the leads-off condition persists, then held until cleared by STATUS

read back (32nd SCLK).

D[20]

DCLOFFINT

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 5. Status (0x01) Register Meaning (continued)

INDEX

NAME

MEANING

Ultra-Low Power (ULP) Leads-On Detection Interrupt. Indicates that the MAX30004 has determined

it is in a leads-on condition (as selected in CNFG_GEN).

LONINT is asserted whenever EN_ULP_LON[1:0] in register CNFG_GEN is set to either 0b01 or

0b10 to indicate that the ULP leads on detection mode has been enabled. The STATUS register

has to be read back once after ULP leads-on detection mode has been activated to clear LONINT

and enable leads-on detection.

D[11]

LONINT

LONINT remains active while the leads-on condition persists, then held until cleared by STATUS read

back (32nd SCLK).

R-to-R Detector R Event Interrupt. Issued when the R-to-R detector has identiﬁed a new R event.

Clear behavior is deﬁned by CLR_RRINT[1:0]; see MNGR_INT for details.

D[10]

D[9]

RRINT

SAMP

Sample Synchronization Pulse. Issued on the ADC base-rate sampling instant, for use in assisting

µC monitoring and synchronizing other peripheral operations and data, generally recommended for use

as a dedicated interrupt.

Frequency is selected by SAMP_IT[1:0], see MNGR_INT for details.

Clear behavior is deﬁned by CLR_SAMP, see MNGR_INT for details.

PLL Unlocked Interrupt. Indicates that the PLL has not yet achieved or has lost its phase lock.

PLLINT will only be asserted when the PLL is powered up and active (Channel enabled).

Remains asserted while the PLL unlocked condition persists, then held until cleared by STATUS read

back (32nd SCLK).

D[8]

PLLINT

D[3]

D[2]

LDOFF_PH

LDOFF_PL

DC Lead Off Detection Detailed Status. Indicates that the MAX30004 has determined (as selected by

CNFG_GEN):

INP is above the high threshold (V

INN is above the high threshold (V

), INP is below the low threshold (V

),

THH

THL

), INN is below the low threshold (V

), respectively.

THH

THL

D[1]

D[0]

LDOFF_NH

LDOFF_NL

Remains active as long as the leads-off detection is active and the leads-off condition persists, then

held until cleared by STATUS read back (32nd SCLK). LDOFF_PH to LDOFF_NL are detailed status

bits that are asserted at the same time as DCLOFFINT.

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

INTB_TYPE[1:0] allows the user to select between a

CMOS or an open-drain NMOS mode INTB output. If

using open-drain mode, an option for an internal 125kΩ

pullup resistor is also offered.

EN_INT (0x02) and EN_INT2 (0x03) Registers

EN_INT and EN_INT2 are read/write registers that govern

the operation of the INTB output and INT2B output,

respectively. The first two bytes indicate which

interrupt input terms are included in the interrupt output OR

term (ex. a one in an EN_INT register indicates that the

corresponding input term is included in the INTB interrupt

output OR term). See the STATUS register for detailed

descriptions of the interrupt terms. The power-on reset

state of all EN_INT terms is 0 (ignored by INT).

All INTB and INT2B types are active-low (INTB low

indicates the device requires servicing by the µC);

however, the open-drain mode allows the INTB line to be

shared with other devices in a wired-or configuration.

In general, it is suggested that INT2B be used to

support specialized/dedicated interrupts of use in specific

applications, such as the self-clearing versions of SAMP

or RRINT.

EN_INT and EN_INT2 can also be used to mask persistent

interruptconditionsinordertoperformotherinterrupt-driven

operations until the persistent conditions are resolved.

Table 6. EN_INT (0x02) and EN_INT2 (0x03) Register Maps

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

EN_

FSTINT

EN_DCL

OFFINT

x

0x02

0x03

EN_INT

EN_INT2

R/W

EN_

LONINT

EN_

RRINT

EN_

SAMP

EN_

PLLINT

x

INTB_TYPE[1:0]

Table 7. EN_INT (0x02 and 0x03) Register Meaning

INDEX

NAME

DEFAULT

FUNCTION

EN_FSTINT

EN_DCLOFFINT

EN_LONINT

EN_RRINT

Interrupt Enables for interrupt terms in STATUS[23:8]

0 = Individual interrupt term is not included in the interrupt OR term

1 = Individual interrupt term is included in the interrupt OR term

D[23:20]

D[11:8]

0x0000

EN_SAMP

EN_PLLINT

INTB Port Type (EN_INT Selections)

00 = Disabled (Three-state)

11

01 = CMOS Driver

10 = Open-Drain NMOS Driver

11 = Open-Drain NMOS Driver with Internal 125kΩ Pullup Resistance

D[1:0]

INTB_TYPE[1:0]

INT2B Port Type (EN_INT2 Selections)

00 = Disabled (three-state)

01 = CMOS Driver

10 = Open-Drain nMOS Driver

11 = Open-Drain nMOS Driver with Internal 125kΩ Pullup Resistance

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

registercontainstheconfigurationbitssupportingthesample

synchronization pulse (SAMP) and RTOR heart rate

detection interrupt (RRINT).

MNGR_INT (0x04)

MNGR_INT is a read/write register that manages the

operation of the configurable interrupt bits. Finally, this

Table 8. MNGR_INT (0x04) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

x

MNGR_

INT

0x04

R/W

CLR_

FAST

CLR_

SAMP

x

CLR_RRINT[1:0]

x

SAMP_IT[1:0]

Table 9. MNGR_INT (0x04) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

FAST MODE Interrupt Clear Behavior:

0 = FSTINT remains active until the FAST mode is disengaged (manually or

automatically), then held until cleared by STATUS read back (32nd SCLK).

1 = FSTINT remains active until cleared by STATUS read back (32nd SCLK),

even if the MAX30004 remains in FAST recovery mode. Once cleared,

FSTINT will not be re-asserted until FAST mode is exited and re-entered,

either manually or automatically.

D[6]

CLR_FAST

0

RTOR R Detect Interrupt (RRINT) Clear Behavior:

00 = Clear RRINT on STATUS Register Read Back

01 = Clear RRINT on RTOR Register Read Back

10 = Self-Clear RRINT after one data rate cycle, approximately 2ms to 8ms

11 = Reserved. Do not use.

D[5:4]

D[2]

CLR_RRINT[1:0]

CLR_SAMP

00

1

Sample Synchronization Pulse (SAMP) Clear Behavior:

0 = Clear SAMP on STATUS Register Read Back (recommended for debug/

evaluation only).

1 = Self-clear SAMP after approximately one-fourth of one data rate cycle.

Sample Synchronization Pulse (SAMP) Frequency

00 = issued every sample instant

D[1:0]

SAMP_IT[1:0]

00

01 = issued every 2nd sample instant

10 = issued every 4th sample instant

11 = issued every 16th sample instant

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

MNGR_DYN (0x05)

SW_RST (0x08)

MNGR_DYN is a read/write register that manages

the settings of any general/dynamic modes within the

device. The Fast Recovery modes and thresholds are

managed here. Unlike many CNFG registers, changes

to dynamic modes do not require a RESTART operation.

SW_RST (Software Reset) is a write-only register/

command that resets the MAX30004 to its original default

conditions at the end of the SPI SW_RST transaction

(i.e. the 32nd SCLK rising edge). Execution occurs only

if DIN[23:0] = 0x000000. The effect of a SW_RST is

identical to power-cycling the device.

Table 10. MNGR_DYN (0x05) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

FAST[1:0] FAST_TH[5:0]

MNGR_

DYN

0x05

R/W

x

Table 11. MNGR_DYN (0x05) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Fast Recovery Mode Selection (High-Pass Filter Bypass):

00 = Normal Mode (Fast Recovery Mode Disabled)

01 = Manual Fast Recovery Mode Enable (remains active until disabled)

10 = Automatic Fast Recovery Mode Enable (Fast Recovery automatically

activated when/while outputs are saturated, using FAST_TH).

11 = Reserved. Do not use.

D[23:22]

FAST[1:0]

00

Automatic Fast Recovery Threshold:

If FAST[1:0] = 10 and the output of a measurement exceeds the symmetric

thresholds deﬁned by 2048*FAST_TH for more than 125ms, the Fast Recovery

mode will be automatically engaged and remain active for 500ms.

D[21:16]

FAST_TH[5:0]

0x3F

For example, the default value (FAST_TH = 0x3F) corresponds to an output upper

threshold of 0x1F800, and an output lower threshold of 0x20800.

Table 12. SW_RST (080x) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x08

SW_RST

R/W

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Likewise, anytime a change to CNFG_GEN or CNFG_CH

registers are made discontinuities in the RTOR record

may occur. The RESTART command provides a means to

restart operations cleanly following any such disturbances.

RESTART (0x09)

RESTART (Restart) is a write-only register/command that

begins new RTOR operations and recording, beginning on

the internal MSTR clock edge following the end of the

SPI RESTART transaction (i.e., the 32nd SCLK rising

edge). Execution occurs only if DIN[23:0] = 0x000000. In

addition to restarting the operations of any active R-to-R

circuitry, RESTART also resets and clears the DSP filters

(to midscale), allowing the user to effectively set the “Time

Zero” for the RTOR data. No configuration settings are

impacted. For best results, users should wait until the PLL

has achieved lock before restarting if the CNFG_GEN

settings have been altered.

RTOR_RST (0x0A)

RTOR_RST is a write-only register/command that begins a

new data recording by resetting the memories and resuming

the record with the next available data. Execution occurs only

if DIN[23:0] = 0x000000. Unlike the RESTART command,

the operations of any active data and R-to-R circuitry are not

impacted by RTOR_RST, so, therefore, no settling/recovery

transients apply.

Once the device is initially powered up, it needs to be

fully configured prior to launching recording operations.

Table 13. RESTART (0x09) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x09 RESTART R/W

Table 14. RTOR_RST (0x0A) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

D[23:16] = 0x00

D[15:8] = 0x00

D[7:0] = 0x00

0x0A RTOR_RST R/W

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

INFO (0x0F)

CNFG_GEN (0x10)

INFO is a read-only register that provides information

about the MAX30004. The first nibble contains an alternating

bit pattern to aide in interface verification. The second

nibble contains the revision ID. The third nibble includes

part ID information. The final 3 nibbles contain a serial

number for Maxim internal use—note that individual

units are not given unique serial numbers, and these bits

should not be used as serial numbers for end products,

though they may be useful during initial development

efforts.

CNFG_GEN is a read/write register which governs

general settings, most significantly the master clock rate

for all internal timing operations. Anytime a change to

CNFG_GEN is made, there may be discontinuities in

the data record may occur. The RESTART command

can be used to restore internal synchronization resulting

from configuration changes. Note when EN_CH is logic-

low, the device is in one of two ultra-low power modes

(determined by EN_ULP_LON).

Table 19 shows the data rates that can be realized with various

setting of FMSTR, along with RATE configuration bits available

in the CNFG_CH register.

Note: Due to internal initialization procedures, this

command will not read-back valid data if it is the first

command executed following either a power-cycle event,

or a SW_RST event.

Table 15. INFO (0x0F) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

0

x

1

X

x

0

x

1

0

x

REV_ID[3:0]

0x0F

INFO

R/W

x

Table 16. INFO (0x0F) Register Meaning

INDEX

NAME

MEANING

D[19:16]

REV_ID[3:0]

Revision ID

Table 17. CNFG_GEN (0x10) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

x

16 / 8 / 0

EN_ULP_LON[1:0]

FMSTR[1:0]

EN_DCLOFF[1:0]

EN_RBIAS[1:0]

EN_RTOR

IPOL

x

CNFG_

GEN

0x10

R/W

x

IMAG[2:0]

RBIASP

VTH[1:0]

RBIASV[1:0]

RBIASN

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 18. CNFG_GEN (0x10) Register Functionality

INDEX

NAME

DEFAULT FUNCTION

Ultra-Low Power Lead-On Detection Enable

00 = ULP Lead-On Detection disabled

01 = ULP Lead-On Detection enabled

10 = Reserved. Do not use.

D[23:22]

EN_ULP_LON

[1:0]

00

11 = Reserved. Do not use.

ULP mode is only active when the RTOR channel is powered down/disabled.

Master Clock Frequency. Selects the Master Clock Frequency (FMSTR), and Timing

Resolution (T

). These are generated from FCLK, which is always 32.768Khz.

RES

00 =

01 =

10 =

11 =

F

= 32768Hz,

= 32000Hz,

T

= 15.26µs (512Hz data progressions)

= 15.63µs (500Hz data progressions)

= 15.63µs (200Hz data progressions)

= 15.64µs (199.8049Hz data progressions)

MSTR

RES

D[21:20]

D[19]

FMSTR[1:0]

EN_CH

00

= 31968.78Hz, T

Channel Enable

0 = Channel disabled

1 = Channel enabled

0

Note: The channel must be enabled to allow R-to-R operation.

DC Lead-Off Detection Enable

00 = DC Lead-Off Detection disabled

01 = DCLOFF Detection applied to the INP/INN pins

10 = Reserved. Do not use.

11 = Reserved. Do not use.

DC Method, requires active selected channel, enables DCLOFF interrupt

and status bit behavior.

Uses current sources and comparator thresholds set below.

D[13:12]

D[11]

EN_DCLOFF

00

DC Lead-Off Current Polarity (if current sources are enabled/connected)

DCLOFF_

IPOL

0

0 = INP - Pullup

INN – Pulldown

1 = INP - Pulldown INN – Pullup

DC Lead-Off Current Magnitude Selection

000 = 0nA (Disable and Disconnect Current Sources)

001 = 5nA

010 = 10nA

011 = 20nA

100 = 50nA

DCLOFF_

IMAG[2:0]

D[10:8]

000

101 = 100nA

110 = Reserved. Do not use.

111 = Reserved. Do not use.

DC Lead-Off Voltage Threshold Selection

00 = V

01 = V

10 = V

11 = V

± 300mV

± 400mV

± 450mV

± 500mV

MID

DCLOFF_

VTH[1:0]

D[7:6]

D[5:4]

00

Enable and Select Resistive Lead Bias Mode

00 = Resistive Bias disabled

01 = Resistive Bias enabled if EN_CH is also enabled

10 = Reserved. Do not use.

EN_RBIAS[1:0]

11 = Reserved. Do not use.

If EN_CH is not asserted at the same time as prior to EN_RBIAS[1:0] being set to

01, then EN_RBIAS[1:0] will remain set to 00.

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 18. CNFG_GEN (0x10) Register Functionality (continued)

INDEX

NAME

DEFAULT FUNCTION

Resistive Bias Mode Value Selection

00 = R

01 = R

10 = R

= 50MΩ

= 100MΩ

= 200MΩ

BIAS

D[3:2]

RBIASV[1:0]

01

11 = Reserved. Do not use.

Enables Resistive Bias on Positive Input

D[1]

D[0]

RBIASP

RBIASN

0

0 = INP is not resistively connected to V

MID

1 = INP is connected to V

through a resistor (selected by RBIASV).

MID

Enables Resistive Bias on Negative Input

0 = INN is not resistively connected to V

MID

1 = INN is connected to V

through a resistor (selected by RBIASV).

MID

Table 19. Master Frequency Summary Table

DATA RATES & RELATED TIMING (RATE SELECTIONS)

CALIBRATION

TIMING

MASTER

FREQUENCY

CHANNEL

RTOR

FMSTR

[1:0]

RESOLUTION

(CAL_RES) (µs)

DATA

RATE (sps)

TIMING RESOLUTION

(RTOR_RES) (ms)

(f

) (Hz)

MSTR

00 = 512

01 = 256

10 = 128

00

01

32768

7.8125

8.000

30.52

31.25

00 = 500

01 = 250

10 = 125

32000

10

11

32000

10 = 200

8.000

8.008

31.25

31.28

31968.78

10 =199.8049

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

CNFG_MUX (0x14)

CNFG_CH (0x15)

CNFG_MUX is a read/write register which configures

the operation, settings, and functionality of the Input

Multiplexer.

CNFG_CH is a read/write register that configures the

operation, settings, and functionality of the Biopotential

channel. Anytime a change to CNFG_CH is made, there

may be discontinuities in the data record.

Table 20. CNFG_EMUX (0x14) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

POL

x

OPENP

OPENN

x

CNFG_

MUX

0x14

R/W

x

Table 21. CNFG_MUX (0x14) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Input Polarity Selection

0 = Non-Inverted

1 = Inverted

D[23]

POL

0

Open the INP Input Switch (most often used for testing and calibration studies)

0 = INP is internally connected to the AFE Channel

1 = INP is internally isolated from the AFE Channel

D[21]

D[20]

OPENP

OPENN

1

Open the INN Input Switch (most often used for testing and calibration studies)

0 = INN is internally connected to the AFE Channel

1 = INN is internally isolated from the AFE Channel

Table 22. CNFG_CH (0x15) Register Map

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

RATE[1:0]

DHPF

x

GAIN[1:0]

CNFG_

CH

0x15

R/W

x

DLPF[1:0]

x

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 23. CNFG_CH (0x15) Register Functionality

INDEX

NAME

DEFAULT

FUNCTION

Sample Data Rate (also dependent on F

selection, see CNFG_GEN Table 24):

MSTR

FMSTR = 00: f

00 = 512sps

01 = 256sps

10 = 128sps

= 32768Hz, t

= 15.26µs (512Hz data progressions)

MSTR

RES

11 = Reserved. Do not use.

FMSTR = 01: f

00 = 500sps

01 = 250sps

10 = 125sps

= 32000Hz, t

= 15.63µs (500Hz data progressions)

= 15.63µs (200Hz data progressions)

= 15.64µs (199.8Hz data progressions)

MSTR

11 = Reserved. Do not use.

D[23:22]

RATE[1:0]

10

FMSTR = 10: f = 32000Hz, t

MSTR

RES

00 = Reserved. Do not use.

01 = Reserved. Do not use.

10 = 200sps

11 = Reserved. Do not use.

FMSTR = 11: f

= 31968Hz, t

MSTR

00 = Reserved. Do not use.

01 = Reserved. Do not use.

10 = 199.8sps

11 = Reserved. Do not use.

Gain Setting

00 = 20V/V

01 = 40V/V

10 = 80V/V

11 = 160V/V

D[17:16]

GAIN[1:0]

00

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 23. CNFG_CH (0x15) Register Functionality (continued)

INDEX

NAME

DEFAULT

FUNCTION

Digital High-Pass Filter Cutoff Frequency

D[14]

DHPF

1

0 = Bypass (DC)

1 = 0.50Hz

Digital Low-Pass Filter Cutoff Frequency

00 = Bypass (Decimation only, no FIR ﬁlter applied)

01 = approximately 40Hz

10 = approximately 100Hz (Available for 512, 256, 500, and 250sps data Rate

selections only)

D[13:12]

DLPF[1:0]

01

11 = approximately 150Hz (Available for 512 and 500sps data rate selections only)

Note: See Table 24. If an unsupported DLPF setting is speciﬁed, the 40Hz setting

(DLPF[1:0] = 01) will be used internally; the CNFG_CH register will continue to hold

the value as written, but return the effective internal value when read back.

Table 24. Supported RATE and DLPF Options

RATE[1:0]

CNFG_GEN

DLPF[1:0]/DIGITAL LPF CUTOFF

SAMPLE RATE

FMSTR[1:0]

00

01 (Hz)

10 (Hz)

11 (Hz)

(sps)

00 = 512

01 = 256

10 = 128

00 = 500

01 = 250

10 = 125

10 = 200

10 = 199.8

Bypass

40.96

40.00

39.96

102.4

40.96

100.0

40.00

39.96

153.6

40.96

150.0

40.00

39.96

00 = 32768Hz

01 = 32000Hz

10 = 32000Hz

11 = 31968Hz

Note: Combinations shown in grey are unsupported and will be internally mapped to the default settings shown.

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

CNFG_RTOR1 and CNFG_RTOR2 (0x1D & 0x1E)

CNFG_RTOR is a two-part read/write register that configures the operation, settings, and function of the RTOR heart

rate detection block. The first register contains algorithmic voltage gain and threshold parameters, the second contains

algorithmic timing parameters.

RTOR Interval Memory Register (1 Word x 24 Bits)

The RTOR Interval (RTOR) memory register is a single read-only register consisting of 14 bits of timing interval information,

left justified (and 8 unused bits, set to zero).

The RTOR register stores the time interval between the last two R events, as identified by the RTOR detection circuitry, which

operates on the channel output data. Each LSB in the RTOR register is approximately equal to 8ms (CNFG_GEN for

exact figures). The resulting 14-bit storage interval can thus be approximately 130 seconds in length, again depending

on device settings.

Each time the RTOR detector identifies a new R event, the RTOR register is updated, and the RRINT interrupt term is

asserted (see STATUS (0x01) Register for details).

Users wishing to log heart rate based on RTOR register data should set CLR_RRINT equals 01 in the MNGR_INT

register. This will clear the RRINT interrupt term after the RTOR register has been read back, preparing the device for

identification of the next RTOR interval.

Users wishing to log heart rate based on the time elapsed between RRINT assertions using the µC to keep track of the

time base (and ignoring the RTOR register data) have two choices for interrupt management. If CLR_RRINT equals 00

in the MNGR_INT register, the RRINT interrupt term will clear after each STATUS register read back, preparing the device

for identification of the next RTOR interval. If CLR_RRINT equals 10 in the MNGR_INT register, the RRINT interrupt term

will self-clear after each one full data cycle has passed, preparing the device for identification of the next RTOR interval

(this mode is recommended only if using the INT2B as a dedicated heart rate indicator).

If the RTOR detector reaches an overflow state after several minutes without detection of an R event, the counter will

simply roll over, and the lack of the RRINT activity on the dedicated INT2B line will inform the µC that no RTOR activity

was detected.

Table 25. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Maps

REG

NAME

R/W

23 / 15 / 7 22 / 14 / 6 21 / 13 / 5 20 / 12 / 4 19 / 11 / 3 18 / 10 / 2

17 / 9 / 1

16 / 8 / 0

WNDW[3:0] GAIN[3:0]

CNFG_

RTOR1

EN_

RTOR

0x1D

R/W

x

PAVG[1:0]

RAVG[1:0]

PTSF[3:0]

x

HOFF[5:0]

CNFG_

RTOR2

0x1E

R/W

x

RHSF[2:0]

x

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 26. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Functionality

INDEX

NAME

DEFAULT FUNCTION

CNFG_RTOR1 (0x1D)

This is the width of the averaging window, which adjusts the algorithm sensitivity to

the width of the QRS complex.

R-to-R Window Averaging (Window Width = RTOR_WNDW[3:0]*8ms)

0000 =

0001 =

6

8

0010 = 10

0011 = 12

0100 = 14

0101 = 16

0110 = 18

0111 = 20

1000 = 22

1001 = 24

1010 = 26

1011 = 28

(default = 96ms)

D[23:20]

WNDW[3:0]

0011

1100 = Reserved. Do not use.

1101 = Reserved. Do not use.

1110 = Reserved. Do not use.

1111 = Reserved. Do not use.

R-to-R Gain (where Gain = 2^GAIN[3:0], plus an auto-scale option). This is used to

maximize the dynamic range of the algorithm.

0000 =

0001 =

0010 =

0011 =

1

2

4

8

1000 = 256

1001 = 512

1010 = 1024

1011 = 2048

D[19:16]

GAIN[3:0]

1111

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1100 = 4096

1101 = 8192

1110 = 16384

1111 = Auto-Scale (default)

In Auto-Scale mode, the initial gain is set to 64.

RTOR Detection Enable

D[15]

EN_RTOR

0

0 = RTOR Detection disabled

1 = RTOR Detection enabled if EN_CH is also enabled.

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│ 35

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Table 26. CNFG_RTOR and CNFG_RTOR2 (0x1D and 0x1E) Register Functionality

(continued)

INDEX

NAME

DEFAULT

FUNCTION

R-to-R Peak Averaging Weight Factor

This is the weighting factor for the current RTOR peak observation vs. past peak

observations when determining peak thresholds. Lower numbers weight current

peaks more heavily.

00 = 2

01 = 4

D[13:12]

PAVG[1:0]

10

10 = 8 (default)

11 = 16

Peak_Average(n) =

[Peak(n) + (RTOR_PAVG-1) x Peak_Average(n-1)]/RTOR_PAVG.

R-to-R Peak Threshold Scaling Factor

This is the fraction of the Peak Average value used in the Threshold computation.

Values of 1/16 to 16/16 are selected directly by (RTOR_PTSF[3:0]+1)/16,

default is 4/16.

D[11:8]

PTSF[3:0]

HOFF[5:0]

0011

R-to-R Minimum Hold Off

This sets the absolute minimum interval used for the static portion of the Hold Off

criteria.

CNFG_

RTOR2

(0x1E)D

[21:16]

Values of 0 to 63 are supported, default is 32

10_0000

t

= HOFF[5:0] * t

, where t

is ~8ms, as determined by

RTOR

HOLD_OFF_MIN

RTOR

FMSTR[1:0] in the CNFG_GEN register.

(representing approximately ¼ second).

The R-to-R Hold Off qualiﬁcation interval is

t

= MAX(t

, t

) (see below).

Hold_Off

Hold_Off_Min Hold_Off_Dyn

R-to-R Interval Averaging Weight Factor

This is the weighting factor for the current RtoR interval observation vs. the past

interval observations when determining dynamic holdoff criteria. Lower numbers

weight current intervals more heavily.

00 = 2

01 = 4

D[13:12]

RAVG[1:0]

10

10 = 8

(default)

11 = 16

Interval_Average(n) = [Interval(n) + (RAVG-1) x

Interval_Average(n-1)]/RAVG.

R-to-R Interval Hold Off Scaling Factor

This is the fraction of the RtoR average interval used for the dynamic portion of the

holdoff criteria (t

).

HOLD_OFFDYN

D[10:8]

RHSF[2:0]

100

Values of 0/8 to 7/8 are selected directly by RTOR_RHSF[3:0]/8, default is 4/8.

If 000 (0/8) is selected, then no dynamic factor is used and the holdoff criteria is

determined by HOFF[5:0] only (see above).

Maxim Integrated

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Typical Application Circuit

1kΩ

AVDD

DVDD

0VDD

INP

ENERGY

RATED

CSB

SDI

CSB

MOSI

SCLK

MISO

INTb

1kΩ

INN

SCLK

SDO

MCU

MAX30004

INTb

CAPP

INT2b

FCLK

CPLL

INT2b

FCLK

10µF

CAPN

VCM

VBG

100pF

10µF

0.1µF

10µF

0.1µF

VREF

10µF

1.0µF

10µF

Maxim Integrated

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Application Diagrams

Two Electrode Heart Rate Fitness

See Figure 8 for an example of a fitness monitoring configuration.

PCB

EXTERNAL EMI FILTERS

ELECTRODE MODEL

Z_EL

INP

1MΩ

2.2nF

CAPP

ELECTRODE

POLARIZATION

VOLTAGE

PHYSICAL

ELECTRODES

R_BODY

100-300Ω

10pF

100nF

MAX30004

1-50nF

2.2nF

CAPN

INN

50-200Ω

1MΩ

±150mV

10kΩ-20MΩ

Figure 8. Two Electrode Heart Rate Monitoring for Fitness

Ordering Information

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PART

TEMP RANGE

0°C to +70°C

PIN-PACKAGE

28 TQFN-EP**

30 WLP

MAX30004CTI+T*

MAX30004CWV+

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*Future product-contact factory for availability.

**EP = Exposed pad.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

LAND

PATTERN NO.

NO.

28 TQFN

T2855+8

21-0140

90-0028

Refer to

Application

Note 1891

30 WLP

W302L2+1

21-100074

Chip Information

PROCESS: CMOS

Maxim Integrated

│ 38

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MAX30004

Ultra-Low Power, Single-Channel Integrated

Biopotential (R-to-R Detection) AFE

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

12/16

Initial release

—

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2016 Maxim Integrated Products, Inc.

│ 39


型号：	MAX30004
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Ultra-Low Power, Single-Channel Integrated Biopotential (R-to-R Detection) AFE
文件：	总39页 (文件大小：3262K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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