MAX31341CETB+T [MAXIM]
Low-Current, Real-Time Clock with I2C Interface and Power Management;
| 型号： | MAX31341CETB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Current, Real-Time Clock with I2C Interface and Power Management |
| 文件： | 总30页 (文件大小：750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
General Description
Benefits and Features
● Increases Battery Life
The MAX31341B/MAX31341C low-current, real-time clock
(RTC) is a time-keeping device that provides nanoamperes
time-keeping current, extending battery life. The MAX31341B/
MAX31341C supports 6pF high-ESR crystals, which broaden
the pool of usable crystals for the devices. This device is
• 180nA Timekeeping Current
• Wide Range of External Crystals with CL = 6pF and
ESR up to 100kΩ for Minimal Current Draw
• Trickle Charger for External Super Capacitor or
Rechargeable Battery
2
accessed through an I C serial interface. The device features
one digital Schmitt trigger input and one programmable threshold
analog input. The device generates an interrupt output on a
falling or rising edge of the digital input (D1), or when the
analog input (AIN) voltage crosses a programmed threshold in
either direction. An integrated power-on reset function ensures
deterministic default register status upon power-up.
● Provides Flexible Configurability
• A Schmitt Trigger Input to Trigger Interrupt
• One Analog Input with Adjustable Threshold to
Trigger Interrupt
• Programmable Square-Wave Output for Clock
Monitoring
Other features include two time-of-day alarms, interrupt
outputs, a programmable square-wave output, a serial bus
timeout mechanism, and a 64-byte RAM for user data stor-
age. The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information. The date at the end
of the month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The clock
operates in 24-hour format. The MAX31341B/MAX31341C
also includes an input for synchronization. When a
reference clock (e.g., 32kHz, 50Hz/60Hz Power Line, GPS
1PPS) is present at the CLKIN pin and the enable exter-
nal clock input bit (ECLK) is set to 1, the MAX31341B/
MAX31341C RTC is frequency-locked to the external clock
and the clock accuracy is determined by the external source.
● Saves Board Space
• Integrated Load Capacitors for Crystal Oscillator
• 2mm x 1.5mm, 12-Bump WLP with 0.5mm Pitch
• 3mm x 3mm, 10-pin TDFN
● Value Add Features for Ease-of-Use
• +1.6V to +3.6V Operating Voltage Range
• Countdown Timer with Repeat and Pause Functions
• 64-Byte RAM for User Data Storage
● Integrated Protection
• Power-On Reset for Default Configuration
• Automatic Switchover to Backup Battery or Super
Capacitor on Power Fail
• Lockup-Free Operation with Bus Timeout
The device is available in a lead (Pb)-free/RoHS-
compliant, 12-pin, 2mm x 1.5mm WLP with 0.5mm pitch
and a 10-pin, 3mm x 3mm TDFN. The device supports the
-40°C to +85°C extended temperature range.
Typical Operating Circuit
V
CC
Applications
● Medical
V
CC
● Wearables
● Point-of-Sale (POS)
● Telematics
● Portable Instruments
● Portable Audio
SDA
SCL
X1
X2
AIN
D1
CONTROL
SYSTEM
MAX31341B/
MAX31341C
V
BACKUP
INTA/CLKIN
INTB/CLKOUT
GND
Ordering Information appears at end of data sheet.
19-100537; Rev 4; 3/20
MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to Ground -0.3V to +6V
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -55°C to +150°C
Soldering Temperature................................ See the IPC/JEDEC
J-STD-020A Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
12 WLP
PACKAGE CODE
W121A2+1
Outline Number
21-0009
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
49°C/W
N/A
JA
Junction to Case (θ
)
JC
10 TDFN
PACKAGE CODE
T1033-4
Outline Number
21-0137
90-0061
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
54°C/W
9°C/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
41°C/W
9°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Electrical Characteristics
(V
= +1.6V to +3.6V, typical values at V
= +3.0V, unless otherwise noted. Limits are 100% tested at T = +25°C. Note 1.)
CC
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Operating Voltage Range
Minimum Timekeeping Voltage
V
Full operation (Note 2)
(Note 2, Note 3)
1.6
3.6
V
V
CC
V
1.0
180
210
220
CCTMIN
V
V
V
= +1.6V (Note 3)
= +3.0V
330
370
390
CC
CC
CC
Timekeeping Current:
I
nA
CCT
CLKIN = GND or CLKIN = V
CC
= +3.6V
Data Retention Current (Oscillator
Stopped and I C Enabled)
I
5
3
nA
BATDR
2
Maximum Supply Power-Up
Slew Rate
T
V/µs
V/ms
VCCR
Maximum Supply Switchover
Slew Rate
T
Power-fail voltage = 2.2V
1.4
VCCF
BATTERY BACKUP AND ANALOG THRESHOLD (AIN)
Backup Supply Voltage
V
1.6
3.6
V
V
AIN
TH1
TH2
TH3
TH4
V
V
V
V
1.3
1.7
2.0
Programmable Power-Fail Voltage if
Comparator Threshold Voltage
Power Management mode is
2
enabled through I C
2.2
3.3
R1
R2
R3
Measured at V
Measured at V
Measured at V
= 0V
= 0V
= 0V
AIN
AIN
AIN
Trickle-Charge Current-Limiting
Resistance
6.4
kΩ
11.3
SCHMITT TRIGGER INPUT (D1)
V
V
V
V
= 3.0V
= 1.6V
= 3.0V
= 1.6V
1.65
0.9
0.9
0.6
2
V
CC
CC
CC
CC
Rising Input Threshold Voltage
V
T+
1.25
0.7
0.35
-0.1
Falling Input Threshold Voltage
V
V
T-
Input Leakage
I
LI
+0.1
µA
LOGIC INPUTS AND OUTPUTS
0.75 x
V
+
CC
0.3
V
V
= 1.6V (Note 1, Note 2)
= 3.0V (Note 1, Note 2)
CC
V
CC
Logic 1 Input
Logic 0 Input
V
V
V
IH
0.7 x
V
CC
0.3
+
CC
V
CC
0.3 x
V
(Note 1, 2)
-0.3
IL
V
CC
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Electrical Characteristics (continued)
(V
= +1.6V to +3.6V, typical values at V
= +3.0V, unless otherwise noted. Limits are 100% tested at T = +25°C. Note 1.)
CC
CC A
PARAMETER
SYMBOL
CONDITIONS
Input clock enabled
MIN
TYP
MAX
UNITS
I
-0.1
+0.1
µA
Input Leakage (SCL, CLKIN/INTA)
IL
Output Leakage (CLKIN/INTA,
CLKOUT/INTB)
I
Input clock disabled
-1.0
-1.0
2
+1.0
µA
mA
mA
O
Output Logic 1 V
= +1.0V
OH
I
V
V
≥ 1.6V
≥ 1.6V
OH
CC
CC
(CLKOUT/INTB)
Output Logic 0, V = +0.4V (SDA,
OL
CLKIN/INTA, CLKOUT/INTB)
I
OL
AC ELECTRICAL CHARACTERISTICS
SCL Clock Frequency
f
(Note 4)
(Note 5)
10
400
kHz
µs
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
BUF
Hold Time (Repeated) START
Condition
t
0.6
µs
HD:STA
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
LOW
t
HIGH
t
(Note 6, Note 7)
0.9
HD:DAT
Data Setup Time
t
V
= 3.0V (Note 8)
100
SU:DAT
CC
Setup Time for a Repeated,
START Condition
t
0.6
µs
ns
ns
ns
SU:STA
Minimum Rise Time of Both SDA
and SCL Signals
20 +
t
(Note 9)
(Note 9)
RMIN
0.1C
B
Maximum Rise Time of Both SDA
and SCL Signals
t
300
RMAX
Minimum Fall Time for Both SDA
and SCL Signals
20 +
t
FMIN
0.1C
B
Maximum Fall Time for Both SDA
and SCL Signals
t
300
ns
µs
pF
FMAX
Setup Time for STOP Condition
t
0.6
SU:STO
Maximum Capacitive Load for
Each Bus Line
C
(Note 9)
400
B
I/O Capacitance
C
(Note 10)
(Note 10)
(Note 11)
(Note 12)
10
37
30
pF
ns
I/O
SCL Spike Suppression
Oscillator Stop Flag (OSF) Delay
Timeout Interval
t
SP
t
100
35
ms
ms
OSF
t
25
TIMEOUT
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Electrical Characteristics – Crystal Parameters
(V
= +1.6V to +3.6V, typical values at V
= +3.0V, unless otherwise noted. Limits are 100% tested at T = +25°C. Note 1.)
CC
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
32.768
100
MAX
UNITS
kHz
kΩ
Nominal Frequency
f
O
Maximum Series Resistance
Load Capacitance
ESR
C
L
6
pF
Note 1: Limits at -40°C and +85°C are guaranteed by design; not production tested.
Note 2: Voltage referenced to ground.
2
Note 3: Specified with I C bus inactive. Oscillator operational. (INTCN = 1, ECLK = 0).
Note 4: The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is held
low for t
.
TIMEOUT
Note 5: After this period, the first clock pulse is generated.
Note 6: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
to bridge the undefined region of the falling edge of SCL.
of the SCL signal)
IHMIN
Note 7: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 8: A fast-mode device can be used in a standard-mode system, but the requirement t
≥ 250ns must then be met. This
SU:DAT
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
+ t
= 1000 + 250 = 1250ns
RMAX
SU:DAT
Note 9:
Note 10: Guaranteed by design; not 100% production tested.
Note 11: The parameter t is the period of time the oscillator must be stopped for the OSF flag to be set over V
C is the total capacitance of one bus line, including all connected devices, in pF.
B
range.
2
OSF
CC
Note 12: The MAX31341B/MAX31341C can detect any single SCL clock held low longer than t
. The device I C
TIMEOUTMIN
interface is in reset state and can receive a new START condition when SCL is held low for at least t
. Once
TIMEOUTMAX
the device detects this condition, the SDA output is released. The oscillator must be running for this function to work.
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Typical Operating Characteristics
V
= 3.6V; T = +25°C, unless noted otherwise (T = +25°C, unless otherwise noted.)
CC
A
A
ICC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
POWER SUPPLY CURRENT
vs. SCL FREQUENCY
toc01
toc02
400
350
300
250
200
150
100
50
100
VCC = +3.6V
90
80
70
60
50
40
30
20
10
0
VCC = +3.3V
TA = +85°C
TA = +25°C
VCC = +3.0V
VCC = +1.6V
TA = -40°C
2.1
0
1.6
2.6
3.1
3.6
50
150
250
350
450
SUPPLY VOLTAGE (V)
SCL FREQUENCY (kHz)
CLKOUT/INTB OUTPUT VOLTAGE LOW
CLKOUT/INTB OUTPUT VOLTAGE HIGH
vs. OUTPUT CURRENT
vs. OUTPUT CURRENT
toc03
toc04
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
VCC = +1.6V, TA = +25°C
VCC = +1.6V, TA = +25°C
0.8
0.6
0.4
0.2
0
0
1
2
3
4
-1.5
-1
-0.5
0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
CLKOUT/INTA OUTPUT VOLTAGE LOW
CLOCK ERROR
vs. TEMPERATURE
vs. OUTPUT CURRENT
toc05
toc06
0.6
0.5
0.4
0.3
0.2
0.1
0
60
40
VCC = +1.6V, TA = +25°C
VCC = +1.6V to 3.6V
Tested with ECS-.327-6-12-C-TR on EV
kit
20
0
-20
-40
-60
-80
-100
-120
-140
-40
-15
10
35
60
85
0
2
4
6
8
10
OUTPUT CURRENT (mA)
TEMPERATURE(°C)
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Pin Configuration
TOP VIEW
INTA/
TOP VIEW
X1
10
AIN
8
D1
6
CLKIN
V
CC
9
MAX31341B
7
1
2
3
4
+
A
MAX31341C
GND
SDA
AIN
VCC
SCL
D1
B
X2
INTB/CLKOUT GND
+
1
2
3
4
5
C
INTB/
CLKOUT
X2 GND SDA SCL
X1
INTA/CLK IN
12 WLP
N.C.
TDFN
3mm x 3mm x 0.75mm
Pin Description
PIN
NAME
FUNCTION
MAX31341B MAX31341C
A1, B4
A2
2
3
GND
SDA
Ground.
2
Serial-Data Input/Output. SDA is the input/output pin for the I C serial interface.
The SDA pin is open-drain and requires an external pullup resistor.
A3
A4
B1
4
6
1
SCL
D1
Serial-Clock Input. SCL is used to synchronize data movement on the serial interface.
Digital Input.
X2
Second Crystal Input for an External 32.768kHz Crystal with 6pF Load Capacitance.
Analog Input for Programmable Threshold Comparator; Backup Battery Input; and
Trickle Charger Output. Connect to GND when backup battery is not used.
B2
8
AIN
Square-Wave Clock or Active-Low Interrupt Output. This pin is used to output a
programmable square wave or an alarm interrupt signal. This is a CMOS push-pull output
and does not require an external pullup resistor. If not used, this pin can be left
unconnected. Refer to Table 2.
INTB,
CLK-
OUT
B3
5
C1
C2
10
9
X1
First Crystal Input for an External 32.768kHz Crystal with 6pF Load Capacitance.
Supply Voltage.
VCC
Clock Input/Active-Low Interrupt Output. This I/O pin is used to output an alarm interrupt
or accept an external clock input to drive the RTC counter. In the output mode, this is an
open drain and requires an external pullup resistor. If not used, connect this pin to ground.
Refer to Table 2.
INTA,
CLKIN
C3
C4
7
NC
Not connected.
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Functional Diagram
32.768kHz EXTERNAL CRYSTAL
X1
X2
DIV BY
1/4/8/32K
INTB/
CLKOUT
POWER
CONTROL
OSCILLATOR
V
CC
AND TRI CKLE
CHARGER
V
CC
AIN
GND
INTERNAL
POR
CLOCK,
INTA/
CLKIN
EXT
SYNC
CALENDAR,
AND ALARM
REGISTERS
MAX31341B/
MAX31341C
64-BYTE RAM
N
D1
CONTROL
LOGIC AND
REGISTERS
SCL
SDA
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
N
The MAX31341B/MAX31341C uses an external
32.768kHz crystal. The oscillator circuit does not require
any external resistors or capacitors to operate. The
device supports high-ESR crystals, which broadens
the pool of usable crystals for the device. It uses a 6pF
crystal, which decreases oscillator current draw. The
MAX31341B/MAX31341C also accepts an external clock
reference for synchronization. The external clock can be a
32.768kHz, 50Hz, 60Hz, or 1Hz source. When the enable
oscillator bit (OSCONZ) is set to 0, the MAX31341B/
MAX31341C uses the oscillator for timekeeping. If the
enable external clock input bit (ECLK) is set to 1, the
time base derived from the oscillator is compared to the
1Hz signal that is derived from the CLKIN signal. The
conditioned signal drives the RTC time and date counters.
When the external clock is lost or when the frequency
differs more than ±0.8% from the crystal frequency, the
LOS flag is asserted.
Detailed Description
Introduction
The MAX31341B/MAX31341C low-current, real-time
clock (RTC) is a timekeeping device that provides
nanoamperes timekeeping current, extending battery life.
The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for each month,
including corrections for leap year through 2199. The clock
operates in 24-hour format.
The MAX31341B/MAX31341C is accessed through an
2
I C serial interface. The device features one digital Schmitt
trigger input and one programmable threshold analog
input. The device generates an interrupt output on a
falling or rising edge of the digital input (D1) or when the
analog input (AIN) voltage crosses a programmed thresh-
oldineitherdirection.Anintegratedpower-onresetfunction
ensures deterministic default register status upon power-
up. Soft reset is required after a brown out or brief black-
out. Other features include two time-of-day alarms, two
interrupts, a programmable square-wave output, a count-
down timer, 64-byte RAM and a bus timeout mechanism
2
Address and data are transferred serially through an I C
serial interface.
2
thatresetstheI Cbusifitremainsinactiveforaminimumof
t
.
TIMEOUT
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
7 most significant bits (MSBs) sent by the master after a
START condition. The address is 0xD2 (left justified with
LSB set to 0). The eight bit is used to defined a write or
read operation.
Clock/Calendar
The time and calendar information are obtained by reading
2
the appropriate I C register(s) when Rd_RTC bit is set.
The time and calendar data are set or initialized by writing
the appropriate register followed by a SET_RTC bit of
Config_reg2 register transition from 0 to 1. The contents
of the time and calendar registers are in the binary-coded
decimal (BCD) format.
If a microcontroller connected to the MAX31341B/
2
MAX31341C resets during I C communications, it is
possible that the microcontroller and the MAX31341B/
MAX31341C could become unsynchronized. When the
2
microcontroller resets, the MAX31341B/MAX31341C I C
The century bit (bit 7 of the Month register) is toggled
when the Years register overflows from 99 to 00. The
day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must
be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result
in undefined operation. When reading or writing the time
and date registers, secondary buffers are used to prevent
errors when the internal registers update. When reading
the time and date registers, the secondary buffers are
interface can be placed into a known state by holding SCL
low for tTIMEOUT. Doing so limits the minimum frequency
2
at which the I C interface can be operated. If data is
being written to the device when the interface timeout is
exceeded, prior to the acknowledge, the incomplete byte
of data is not written.
Burst Mode
Burst read/write allows the controller to read/write multiple
consecutive bytes from a device. It is initiated in the same
manner as the byte read/write operation, but instead of
terminating the read/write cycle after the first data byte
is transferred, the controller can read/write to the whole
register array. In burst write operation, after the receipt of
each byte, the device responds with an acknowledge, and
the address is internally incremented by one. When the
address pointer reaches the end of the register address
list, it goes back to the first register address. In burst
read mode, the controller responds with an acknowledge,
indicating it is waiting for additional data. The device
continues to output data for each acknowledge received.
The controller terminates the read operation by not
responding with an acknowledge and issuing a STOP
condition.
2
synchronized to the internal registers on any I C START
and when the register pointer rolls over to zero. The time
information is read from these secondary registers, while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read.
2
I C Interface
2
The I C interface is guaranteed to operate when VCC is
2
between 1.6V and 3.6V. The I C interface is accessible
whenever VCC is at a valid level. To prevent invalid device
2
operation, the I C interface should not be accessed when
VCC is below +1.6V. The slave address is defined as the
2
Data Transfer on I C Serial Bus
SDA
t
BUF
t
F
t
SP
t
LOW
t
HD:STA
SCL
t
SU:STA
t
t
HIGH
HD:STA
t
R
t
SU:STO
t
t
SU:DAT
HD:DAT
REPEATED
START
STOP
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
ILMAX
IHMIN
2
Figure 1. I C Timing Diagram
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
RTC Startup Process
Clock Accuracy
Use the following procedure to enable RTC and set time.
When running from the internal oscillator, the accuracy of
the clock is dependent upon the accuracy of the crystal
and the accuracy of the match between the capacitive
load of the oscillator circuit and the capacitive load for
which the crystal was trimmed. Additional error is added
by crystal frequency drift caused by temperature shifts.
External circuit noise coupled into the oscillator circuit
can result in the clock running fast. Figure 2 shows
a typical PCB layout for isolation of the crystal and
oscillator from noise. Refer to Application Note 58:
Crystal Considerations with Maxim Real-Time Clocks
(RTCs) for detailed information.
1) Exit software reset and enable oscillator (SWRSTN = 1
and OSCONZ = 0) on register Config_reg1(00h)
2) Write RTC time for registers 0x06-0x0C
3) Write Set_RTC=1 on register Config_reg2(01h)
4) Wait 10ms.
5) Write Set_RTC=0 on register Config_reg2(01h)
Oscillator Circuit
The MAX31341B/MAX31341C uses an external
32.768kHz crystal. The oscillator circuit does not require
any external resistors or capacitors to operate. The
MAX31341B/MAX31341C includes integrated capaci-
tive loading for a 6pF CL crystal. See the Electrical
Characteristics table for the external crystal parameters.
After the oscillator is enabled, the startup time of the
oscillator circuit is usually less than 1 second when using
a crystal with the specified characteristics; however, an
additional 4 seconds are needed for the chip to reach
stable, low-current operation.
Minimizing the Clock Synchronization Delay
When external clock input is disabled (ECLK = 0), the
countdown chain is driven by internal high-speed clock.
The output of the countdown chain is the 1Hz clock that
drives the RTC logic. By default, Clk_sync_reg (58h) = 0x02
and the countdown chain is reset whenever the Set_RTC
transitions from 0 to 1. That means after Set_RTC becomes
1, RTC registers (06h – 0Ch) will transfer to internal RTC
counter and the next RTC update will happen 1 second
later with less than 10ms synchronization delay. If external
clock (50Hz/60Hz/32kHz) is used, set Clk_sync_reg = 0x01
to minimize the synchronization delay to less than 100ms.
If external 1Hz clock is used, set Clk_sync_reg = 0x00, the
maximum synchronization delay will be 1 second.
Layout Example
Figure 2. PCB Layout Example
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Trickle Charger mode, set D_MODE in Pwr_mgmt_reg
(56h) to 0x01. Refer to Table 1 for configuration details.
There is an ANA_IF interrupt flag status bit in the Int_
status_reg (05h) register that can be used as a power-fail
flag. In power management mode, the ANA_IF interrupt
flag is set when VCC falls below the analog threshold
voltage set through BREF in the Config_reg2 (01h) reg-
ister (or when analog threshold voltage is adjusted to
cross above VCC). When operating in comparator mode,
ANA_IF is set when it crosses the analog threshold voltage.
The analog threshold voltage can be configured to detect
a falling or rising edge trigger through the AIP bit in the
Int_polarity_config (02h) register.
CLK RESET
1Hz CLK
1s
SYNC-TIME DELAY
Set_RTC
t0
t0 + 1
(NEW TIME PROGRAMMED)
Figure 3. Clock Synchronization Delay
Trickle Charger
Comparator Mode
The trickler charger is for charging an external super
capacitor or a rechargeable battery. The maximum charg-
ing current can be calculated as follows:
When Comparator Mode is selected, the comparator com-
pares AIN voltage with the threshold that was configured in
BREF bit field of Config_reg2 register. When AIN goes
above or below (depending on AIP interrupt polarity bit)
the threshold ANA_IF flag will be set, and interrupt will be
asserted if ANA_IE bit in Int_en_reg register is 1. Refer to
Interrupt Modes to configure the interrupt output pin.
IMAX = (VCC – VD – VBAT)/R
Where VD is the diode voltage drop, VBAT is the voltage
of the battery being charged, and R is the resistance
selected in the charging path.
As the battery charges, the battery voltage increases
and the voltage across the charging path decreases.
Therefore, the charging current also decreases.
Power Management
The MAX31341B/MAX31341C has a power management
mode that monitors the supply voltage on VCC and
backup battery voltage connected to AIN and determines
which source is used as the internal power supply. In
power management mode, pin AIN should be connected
to the backup battery. To enter Power Management/
Interrupts Status and Output
When an interrupt is asserted, a corresponding status
bit in Int_status_reg (05h) becomes “1”, and an interrupt
output transitions from High to Low. The time registers
0x06-0x0C will update 2ms after the interrupt is asserted.
The interrupt status bit and output can be cleared by
Table 1. Power Management
D_MODE[1:0]
D_MAN_SEL
D_VBACK_SEL
MODE OF OPERATION
Comparator Mode
00
x
x
Power Management Auto and Trickle Charger
Supply Condition
Active Supply
V
CC
V
CC
V
CC
V
CC
< V , V
< AIN
> AIN
< AIN
> AIN
AIN
TH CC
01
0
x
< V , V
V
V
V
TH CC
CC
CC
CC
> V , V
TH CC
> V , V
TH CC
Power Management Manual and Trickle Charger
Active Supply = V
01
01
1
1
0
1
CC
Power Management Manual and Trickle Charger
Active Supply = AIN, for AIN > V
CC
10
11
x
x
x
x
Reserved (Do Not Use)
Reserved (Do Not Use)
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
R1
3kΩ
VCC
AIN
R2
6kΩ
R3
11kΩ
Pwr_mgmt_reg
D_MODE = 01
ON OR OFF
ON OR OFF
1 OF 3 SELECT
(56h)
TRICKLE CHARGER
CONFIGURATION
REGISTER (57h)
TRICKLE CHARGER
SELECT
DIODE
SELECT
RESISTOR
SELECT
RESISTOR
SELECT
BIT3
BIT2
BIT1
BIT0
Figure 4. Trickle Charger Block Diagram
reading the Int_status_reg. Refer to Table 2 for interrupt
configurations.
Countdown Timer
The MAX31341B/MAX31341C features a countdown
timer with a pause function. The timer can be configured
by writing into registers Timer_config (03h) and Timer_init
(15h). The Timer_init register should be loaded with the
initial value from which the timer would start counting
down. The Timer_config register allows these configura-
tion options:
Data Retention Mode
The MAX31341B/MAX31341C features a Data Retention
mode wherein the device shuts down its internal functional
2
blocks (including the oscillator) except the I C interface.
The device consumes 5nA (typical) in this mode. It retains
all the register and RAM contents, including the last valid
date and time values. The device can resume counting
from here when this mode is exited, and the oscillator is
enabled again. User data can be preserved in the RAM in
this mode as long as the backup supply is active.
● Select the frequency of the timer using the TFS[1:0] field.
● Start/stop the timer using the TE (Timer Enable) bit.
● Enable/disable the timer repeat function using the
TRPT bit. This function reloads and restarts the timer
with the same init value once it counts down to zero. In
repeat mode, the first timer interrupt indicates the timer
has started counting.
Procedure to enter Data Retention mode:
1) Write DATA_RETEN = 1 in Config_reg2 (01h).
2) Write OSCONZ = 1 in Config_reg1 (00h).
Procedure to exit Data Retention mode:
1) Write DATA_RETEN = 0 in Config_reg2 (01h).
2) Write OSCONZ = 0 in Config_reg1 (00h).
●
Pause/resume the countdown at any time when the timer
is enabled using the TPAUSE bit (explained below).
The timer can be programmed to assert the INTA or INTB
output (see Table 2) whenever it counts down to zero.
This can be enabled/disabled using the TIE bit in register
Int_en_reg (04h).
The TPAUSE bit is only valid when TE = 1. This bit must
be reset to 0 whenever TE is reset to 0.
Table 3 highlights the steps to be used for various use
cases involving TE and TPAUSE.
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Table 2. Interrupt Modes
Table 3. Countdown Timer Sequence
INTCN ECLK
CLKIN/INTA
CLKOUT/INTB
SEQUENCE TE TPAUSE
ACTION
Countdown timer is reset,
and ready for next countdown
operation. Timer_init can be
programmed in this state.
INTA: Alarm1, Alarm2,
Timer, Analog interrupt
(AIN), Digital interrupt (D1)
0
0
CLKOUT
Step1
Step2
0
1
0
0
0
1
1
0
CLKIN
CLKOUT
Countdown timer starts
counting down from the value
programmed in Timer_init
INTA: Alarm1, Timer,
Analog interrupt (AIN),
Digital interrupt (D1)
INTB: Alarm2
Countdown timer is paused and
is ready to start counting down
when TPAUSE is programmed
back to ‘0’. Contents of the
countdown timer are preserved
in this state.
INTB: Alarm1,
Alarm2, Timer,
Analog interrupt
(AIN), Digital
Step3a
(Optional)
1
1
1
1
CLKIN
interrupt (D1)
Countdown timer is brought
out of pause state and starts
counting down from the
paused value.
Step3b
If 3a is true
1
0
0
1
Not allowed
Typical use cases:
● Countdown timer without pause: Step 1 Step 2
Step 1, and so on.
● Countdown timer with pause: Step 1 Step 2
Step 3a Step 3b Step 1, and so on.
Register Map
ADDRESS
REGBLK
NAME
MSB
LSB
0x00
Config_reg1[7:0]
ECLK
–
INTCN
CLKSEL[1:0]
BREF[1:0]
OSCONZ
RS[1:0]
SWRSTN
DATA_RE-
TEN
I2C_TIME-
OUT_EN
0x01
Config_reg2[7:0]
Rd_RTC Set_RTC
–
–
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Int_polarity_config[7:0]
Timer_config[7:0]
Int_en_reg[7:0]
Int_status_reg[7:0]
Seconds[7:0]
Minutes[7:0]
Hours[7:0]
–
AIP
–
EIP1
–
–
–
–
–
–
–
–
TPAUSE
ANA_IE
TE
TRPT
TIE
TFS[1:0]
–
DOSF
OSF
EIE1
EIF1
A2IE
A2F
A1IE
A1F
LOS
ANA_IF
TIF
–
sec_10[2:0]
min_10[2:0]
seconds[3:0]
–
minutes[3:0]
hour[3:0]
–
Reserved
hr_10[1:0]
Day[7:0]
–
–
–
–
–
–
–
–
day[2:0]
Date[7:0]
date_10[1:0]
– month_10
date[3:0]
month[3:0]
year[3:0]
Month[7:0]
century
Year[7:0]
year_10[3:0]
sec_10[2:0]
min_10[2:0]
Alm1_sec[7:0]
Alm1_min[7:0]
A1M1
A1M2
seconds[3:0]
minutes[3:0]
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Register Map (continued)
ADDRESS
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
NAME
MSB
A1M3
A1M4
A2M2
A2M3
A2M4
LSB
Alm1_hrs[7:0]
Reserved
DY_DT
hr_10[1:0]
hour[3:0]
day_date[3:0]
minutes[3:0]
hour[3:0]
Alm1day_date[7:0]
Alm2_min[7:0]
date_10[1:0]
min_10[2:0]
Alm2_hrs[7:0]
Reserved
DY_DT
hr_10[1:0]
Alm2day_date[7:0]
Timer_Count[7:0]
Timer_Init[7:0]
date_10[1:0]
day_date[3:0]
Count[7:0]
Count[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Ram_Reg 0[7:0]
Ram_Reg 1[7:0]
Ram_Reg 2[7:0]
Ram_Reg 3[7:0]
Ram_Reg 4[7:0]
Ram_Reg 5[7:0]
Ram_Reg 6[7:0]
Ram_Reg 7[7:0]
Ram_Reg 8[7:0]
Ram_Reg 9[7:0]
Ram_Reg 10[7:0]
Ram_Reg 11[7:0]
Ram_Reg 12[7:0]
Ram_Reg 13[7:0]
Ram_Reg 14[7:0]
Ram_Reg 15[7:0]
Ram_Reg 16[7:0]
Ram_Reg 17[7:0]
Ram_Reg 18[7:0]
Ram_Reg 19[7:0]
Ram_Reg 20[7:0]
Ram_Reg 21[7:0]
Ram_Reg 22[7:0]
Ram_Reg 23[7:0]
Ram_Reg 24[7:0]
Ram_Reg 25[7:0]
Ram_Reg 26[7:0]
Ram_Reg 27[7:0]
Ram_Reg 28[7:0]
Ram_Reg 29[7:0]
Ram_Reg 30[7:0]
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Register Map (continued)
ADDRESS
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
NAME
MSB
LSB
Ram_Reg 31[7:0]
Ram_Reg 32[7:0]
Ram_Reg 33[7:0]
Ram_Reg 34[7:0]
Ram_Reg 35[7:0]
Ram_Reg 36[7:0]
Ram_Reg 37[7:0]
Ram_Reg 38[7:0]
Ram_Reg 39[7:0]
Ram_Reg 40[7:0]
Ram_Reg 41[7:0]
Ram_Reg 42[7:0]
Ram_Reg 43[7:0]
Ram_Reg 44[7:0]
Ram_Reg 45[7:0]
Ram_Reg 46[7:0]
Ram_Reg 47[7:0]
Ram_Reg 48[7:0]
Ram_Reg 49[7:0]
Ram_Reg 50[7:0]
Ram_Reg 51[7:0]
Ram_Reg 52[7:0]
Ram_Reg 53[7:0]
Ram_Reg 54[7:0]
Ram_Reg 55[7:0]
Ram_Reg 56[7:0]
Ram_Reg 57[7:0]
Ram_Reg 59[7:0]
Ram_Reg 58[7:0]
Ram_Reg 60[7:0]
Ram_Reg 61[7:0]
Ram_Reg 62[7:0]
Ram_Reg 63[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
D_
VBACK_
SEL
D_MAN_
SEL
0x56
Pwr_mgmt_reg[7:0]
–
–
–
–
D_MODE[1:0]
0x57
0x58
0x59
Trickle_reg[7:0]
Clock_sync_reg[7:0]
RevID_reg[7:0]
–
–
–
–
–
–
–
–
D_TRICKLE[3:0]
–
–
–
–
SYNC_DELAY[1:0]
REVID[3:0]
–
–
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Register Details
Config_reg1 (0x00)
Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
ECLK
0x0
INTCN
0x0
CLKSEL[1:0]
0x0
OSCONZ
0x1
RS[1:0]
0x3
SWRSTN
0x0
Access Type Write, Read Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
ECLK
BITS
DESCRIPTION
Enable external clock input
DECODE
0x0: Disable the external clock
0x1: Enable the external clock
7
0x0: Output is square wave
0x1: Output is interrupt
Interupt control bit. Selects INTB/CLKOUT pin
output function
INTCN
6
5:4
3
0x0: 1Hz
0x1: 50Hz
0x2: 60Hz
0x3: 32.768kHz
CLKSEL
OSCONZ
RS
Selects the CLKIN frequency
Oscillator is on when set to 0. Oscillator is off 0x0: Enable the oscillator
when set to 1.
0x1: Disable the oscillator
0x0: 1Hz
Square-wave output frequency selection on
CLKOUT pin
0x1: 4.098kHz
0x2: 8.192kHz
0x3: 32.768kHz
2:1
0
0x0: Resets the digital block
0x1: Device is not on reset mode
SWRSTN
Software reset
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Config_reg2 (0x1)
Configuration Register
BIT
Field
7
6
5
4
3
2
1
0
DATA_RE-
TEN
I2C_TIME-
OUT_EN
–
BREF[1:0]
Rd_RTC
0x1
Set_RTC
0x0
–
Reset
–
–
0x0
0x0
0x1
–
–
Access Type
Write, Read
Write, Read
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
DATA_RE-
TEN
0x0: Normal operation mode
0x1: Data retention mode
6
Sets the device into data retention mode.
0x0: 1.3V
0x1: 1.7V
0x2: 2.0V
0x3: 2.2V
BREF sets the analog comparator threshold
voltage.
BREF
5:4
3
2
I2C_TIME-
OUT_EN
0x0: Disables the I C timeout
0x1: Enables the I C timeout
2
I C timeout Enable
2
0x0: Reads previous programmed RTC value in
registers 06h-0Ch
0x1: Reads Current RTC value in registers 06h-
0Ch
Rd_RTC
Set_RTC
2
Read RTC
Set RTC
0 to 1 transition loads RTC registers (06h - 0Ch)
contents to countdown chain. See Detailed De-
scription.
1
Int_polarity_config (0x2)
Interrupt Polarity Configuration Register
BIT
Field
7
–
–
–
6
5
4
–
–
–
3
–
–
–
2
–
–
–
1
–
–
–
0
–
–
–
AIP
0x0
EIP1
0x0
Reset
Access Type
Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Analog interrupt will trigger on falling edge of
AIN input
0x1: Analog interrupt will trigger on rising edge
of AIN input
AIP
6
Analog interrupt polarity
0x0: External interrupt will trigger on falling edge of
D1 input
EIP1
5
External interrupt polarity for D1
0x1: External interrupt will trigger on rising edge
of D1 input
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Timer_config (0x3)
Countdown Timer Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
–
–
–
2
TRPT
1
0
TPAUSE
0x0
TE
0x0
TFS[1:0]
0x3
Reset
0X1
Access Type
Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Timer Pause. This field is valid only when
TE = 1. Reset TPAUSE when TE is reset to 0.
See Countdown Timer section.
0x0: Resume timer countdown from paused state
0x1: Pause timer
TPAUSE
5
0x0: Timer is reset. New timer countdown value
(Timer_Init) can be programmed in this state.
TE
4
Timer enable
Note: TPAUSE must be reset to 0 prior to setting TE to 1
0x1: Timer enabled countdown starts
0x0: Countdown timer will halt once it reaches zero
0x1: Countdown timer reloads the value from the
Timer_init register upon reaching zero and contin-
ues counting.
TRPT
TFS
2
Timer repeat mode
0x0: 1024Hz
0x1: 256Hz
0x2: 64Hz
0x3: 16Hz
1:0
Timer frequency selection
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Timer_config (0x3)
Countdown Timer Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
–
–
–
2
TRPT
1
0
TPAUSE
0x0
TE
0x0
TFS[1:0]
0x3
Reset
0X1
Access Type
Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Timer Pause. This field is valid only when
TE = 1. Reset TPAUSE when TE is reset to 0.
See Countdown Timer section.
0x0: Resume timer countdown from paused state
0x1: Pause timer
TPAUSE
5
0x0: Timer is reset. New timer countdown value
(Timer_Init) can be programmed in this state.
TE
4
Timer enable
Note: In this state, reset TPAUSE to 0
0x1: Timer enabled countdown starts
0x0: Countdown timer will halt once it reaches zero
0x1: Countdown timer reloads the value from the
Timer_init register upon reaching zero and contin-
ues counting.
TRPT
2
Timer repeat mode
0x0: 1024Hz
0x1: 256Hz
0x2: 64Hz
0x3: 16Hz
TFS
1:0
Timer frequency selection
Int_en_reg (0x4)
Interrupt Enable Register
BIT
Field
7
–
–
–
6
5
4
3
–
–
–
2
1
0
DOSF
0x0
ANA_IE
0x0
EIE1
0x0
TIE
0x0
A2IE
0x0
A1IE
0x0
Reset
Access Type
Write, Read Write, Read Write, Read
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: OSF indicates oscillator status
0x1: Disables the oscillator flag (OSF= 0)
DOSF
6
Disable Oscillator flag
0x0: Disabled
0x1: Enabled
ANA_IE
EIE1
TIE
5
4
2
1
0
Analog Interrupt enable
External Interrupt enable for D1
Timer interrupt enable
0x0: Disabled
0x1: Enabled
0x0: Disabled
0x1: Enabled
0x0: Disabled
0x1: Enabled
A2IE
A1IE
Alarm 2 interrupt enable
Alarm1 interrupt enable
0x0: Disabled
0x1: Enabled
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Int_status_reg (0x5)
Interrupt Status Register
BIT
Field
7
6
5
4
3
–
–
2
1
0
LOS
0x0
OSF
0x1
ANA_IF
0x0
EIF1
0x0
TIF
0x0
A2F
0x0
A1F
0X0
Reset
Read Clears Read Clears Read Clears Read Clears
Read Clears Read Clears Read Clears
All All All
Access Type
–
All
All
All
All
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Oscillator clock frequency is within 0.8% of
external clock frequency
0x1: Oscillator clock frequency differs more than
0.8% from the external clock frequency
Loss of signal. Valid only for external clock
modes (ECLK = 1)
LOS
7
0x0: Oscillator is running or when DOSF = 1
0x1: Oscillator has stopped
OSF
ANA_IF
EIF1
TIF
6
5
4
2
1
0
Oscillator stop flag
0x0: There is no external interrupt on AIN
0x1: There is/was an external interrupt on AIN
Analog interrupt flag/power-fail flag
External interrupt flag for D1
Timer interrupt flag
Alarm2 flag
0x0: There is no external interrupt on D1
0x1: There is/was an external interrupt on D1
0x0: Countdown timer is not zero
0x1: Countdown timer reached to zero
0x0: Alarm2 not triggered
0x1: Alarm2 triggered
A2F
0x0: Alarm1 not triggered
0x1: Alarm1 triggered
A1F
Alarm1 flag
Seconds (0x6)
Seconds Configuration Register
BIT
Field
7
–
–
–
6
5
4
3
2
1
0
sec_10[2:0]
0x0
seconds[3:0]
0x0
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
6:4
DESCRIPTION
sec_10
RTC seconds in multiples of 10
RTC seconds value
seconds
3:0
Maxim Integrated
│ 20
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Minutes (0x7)
Minutes Configuration Register
BIT
Field
7
–
–
–
6
5
4
3
2
1
0
min_10[2:0]
0x0
minutes[3:0]
0x0
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
6:4
DESCRIPTION
min_10
minutes
RTC minutes in multiples of 10
RTC minutes value
3:0
Hours (0x8)
Hours Configuration Register
BIT
Field
7
–
–
–
6
5
4
3
2
1
0
Reserved
0x0
hr_10[1:0]
hour[3:0]
Reset
0x0
0x0
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
Reserved
hr_10
BITS
6
DESCRIPTION
DECODE
User must enter 0
5:4
3:0
RTC hours in multiples of 10
RTC hours value
hour
Day (0x9)
Day Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
1
day[2:0]
0
Reset
0x1
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
day
2:0
RTC day of the week
Maxim Integrated
│ 21
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Date (0xA)
Date Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
4
3
2
1
0
date_10[1:0]
0x0
date[3:0]
0x1
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
5:4
DESCRIPTION
date_10
date
RTC date in multiples of 10
RTC date
3:0
Month (0xB)
Month Configuration Register
BIT
Field
Reset
7
6
–
–
–
5
–
–
–
4
3
2
1
0
century
0x0
month_10
0x0
month[3:0]
0x1
Access Type Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Year is in current century
0x1: Year is in next century
century
7
Century bit
month_10
month
4
RTC month in multiples of 10
RTC months
3:0
Year (0xC)
Year Configuration Register
BIT
Field
7
6
5
4
3
2
1
0
year_10[3:0]
0x0
year[3:0]
0x0
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
7:4
DESCRIPTION
year_10
year
RTC year multiples of 10
RTC years
3:0
Maxim Integrated
│ 22
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Alm1_sec (0xD)
Alarm 1 can be set by writing to registers 0Dh - 10h. See register map. The alarm can be programmed by the A1IE bit
in Int_en_reg (04h) register to activate the INTA/CLKIN output on an alarm match condition. A1M1, A1M2, A1M3, and
A1M4 are mask bits. When all the mask bits of each alarm are logic 0, an alarm only occurs when the values in the
timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers. The alarm can also
be programmed to repeat every second, minute, hour, day, or date. Table 4 shows the possible settings. Configurations
not listed in the table result in illogical operation. The DY_DT bit (bit 6 of the alarm day/date registers) control whether
the alarm value stored in bits 0-5 reflects the day of the week or the date of the month. If DY_DT is written to logic 0,
the alarm is the result of a match with date of the month. If DY_DT is written to logic 1, the alarm is the result of a match
with day of the week.
Table 4. Alarm 1 Settings
DY_DT
A1M4
A1M3
A1M2
A1M1
ALARM RATE
Once per sec
x
x
x
1
1
1
1
1
1
1
1
0
1
0
0
Sec match
Min and sec match
Hour, min, and sec
match
x
0
1
1
0
0
0
0
0
0
0
0
0
0
0
Date and Time
match
Day and Time
match
BIT
Field
Reset
7
6
5
4
3
2
1
0
A1M1
0x0
sec_10[2:0]
0x0
seconds[3:0]
0x0
Access Type Write, Read
Write, Read
Write, Read
BITFIELD
A1M1
BITS
7
DESCRIPTION
Alarm1 mask bit for seconds
sec_10
6:4
3:0
Alarm1 seconds in multiples of 10
Alarm1 seconds
seconds
Alm1_min (0xE)
Alarm1 Minutes Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
A1M2
0x0
min_10[2:0]
0x0
minutes[3:0]
0x0
Access Type Write, Read
Write, Read
Write, Read
BITFIELD
A1M2
BITS
7
DESCRIPTION
Alarm1 mask bit for minutes
min_10
6:4
3:0
Alarm1 minutes in multiples of 10
Alarm1 minutes
minutes
Maxim Integrated
│ 23
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Alm1_hrs (0xF)
Alarm1 Hours Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
A1M3
0x0
Reserved
0x0
hr_10[1:0]
hour[3:0]
0x0
0x0
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
A1M3
BITS
7
DESCRIPTION
Alarm1 mask bit for hours
DECODE
Reserved
hr_10
6
User must enter 0
5:4
3:0
Alarm1 hours in multiples of 10
Alarm1 hours
hour
Alm1day_date (0x10)
Alarm1 Day/Date Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
A1M4
0x0
DY_DT
0x0
date_10[1:0]
0x0
day_date[3:0]
0x0
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
A1M4
BITS
DESCRIPTION
DECODE
7
Alarm1 mask bit for day/date
0x0: Alarm when date match
0x1: Alarm when day match
DY_DT
6
Alarm1 day/date match
date_10
5:4
3:0
Alarm1 date in multiples of 10
Alarm1 day/date
day_date
Alm2_min (0x11)
Alarm 2 can be set by writing to registers 11h - 13h. See the Register Map. The alarm can be programmed by the A2IE
bit in Int_en_reg (04h) register to activate the INTB/CLKIN output on an alarm match condition. Bit 7 of each of the time-
of-day/ date alarm registers are mask bits. When all the mask bits of each alarm are logic 0, an alarm only occurs when
the values in the timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers.
The alarm can also be programmed to repeat every minute, hour, day, or date. Table 5 shows the possible settings.
Configurations not listed in the table result in illogical operation. The DY_DT bit (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0-5 reflects the day of the week or the date of the month. If DY_DT is
written to logic 0, the alarm is the result of a match with date of the month. If DY_DT is written to logic 1, the alarm is
the result of a match with day of the week.
Maxim Integrated
│ 24
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Table 5. Alarm 2 Settings
DY_DT
A2M4
A2M3
A2M1
ALARM RATE
Once per minute
x
x
x
1
1
1
1
1
0
1
0
0
Minute match
Hour and minute match
Date, hour, and minute
match
0
1
0
0
0
0
4
0
0
Day, hour, and minute
match
BIT
Field
Reset
7
6
5
3
2
1
0
A2M2
0x0
min_10[2:0]
0x0
minutes[3:0]
0x0
Access Type Write, Read
Write, Read
Write, Read
BITFIELD
A2M2
BITS
7
DESCRIPTION
Alarm2 mask bit for minutes
min_10
6:4
3:0
Alarm2 minutes in multiples of 10
Alarm2 minutes
minutes
Alm2_hrs (0x12)
Alarm2 Hours Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
A2M3
0x0
Reserved
0x0
hr_10[1:0]
hour[3:0]
0x0
0x0
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
A2M3
BITS
7
DESCRIPTION
Alarm2 mask bit for hours
DECODE
Reserved
hr_10
6
User must enter 0
5:4
3:0
Alarm2 hours in multiples of 10
Alarm2 hours
hour
Maxim Integrated
│ 25
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Alm2day_date (0x13)
Alarm2 Day/Date Configuration Register
BIT
Field
Reset
7
6
5
4
3
2
1
0
A2M4
0x0
DY_DT
0x0
date_10[1:0]
0x0
day_date[3:0]
0x0
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
A2M4
BITS
DESCRIPTION
DECODE
7
Alarm2 mask bit for day/date
0x0: Alarm when date match
0x1: Alarm when day match
DY_DT
6
Alarm2 day/date match
date_10
5:4
3:0
Alarm2 date in multiples of 10
Alarm2 day/date
day_date
Timer_Count (0x14)
Countdown Timer Value Register
BIT
Field
7
6
5
4
3
2
1
0
Count[7:0]
0x0
Reset
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
Count
7:0
Count down timer current count value
Timer_Init (0x15)
Countdown Timer Initialization Register
BIT
Field
7
6
5
4
3
2
1
0
Count[7:0]
0x0
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
Count down timer initial value. The timer is loaded with the contents of this
register when it reaches to zero in repeat mode
Count
7:0
Maxim Integrated
│ 26
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Ram_Reg (0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25,
0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55)
BIT
Field
7
6
5
4
3
2
1
0
Data[7:0]
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
Data
7:0
RAM data byte. Power-on Reset value is random
Pwr_mgmt_reg (0x56)
Power Management Configuration Register
BIT
Field
7
6
5
4
3
2
1
0
D_VBACK_
SEL
D_MAN_
SEL
–
–
–
–
D_MODE[1:0]
Reset
–
–
–
–
–
–
–
–
0x0
0x0
0x0
Access Type
Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
When this bit is 0, and D_MAN_SEL is 1, V
is used as power supply. When this bit is 1,
CC
D_VBACK_
SEL
0x0: Use V
0x1: Use V
as supply.
CC
as supply.
BACKUP
3
and D_MAN_SEL is 1, V
power supply.
is used as
BACKUP
Default low. When this bit is low, the RTC
determines which supply to use automati-
0x0: Device decides whether to use V
or
CC
V
as supply.
BACKUP
D_MAN_SEL
D_MODE
2
cally. When this bit is high, user can manually
select whether to use V or V as
0x1: User decides whether to use V
or V
BACKUP
CC
CC
BACKUP
as supply by setting D_VBACK_SEL bit.
supply via D_VBACK_SEL.
0x0: Comparator Mode
0x1: Power Management/Trickle Charger Mode
0x2: Reserved
Sets the mode of the comparator to comparator
mode or power management/trickle charger
mode.
1:0
0x3: Reserved
Maxim Integrated
│ 27
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Trickle_reg (0x57)
Trickle Charger Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
2
1
0
D_TRICKLE[3:0]
0x0
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No Connect
0x1: No Connect
0x2: No Connect
0x3: No Connect
0x4: No Connect
0x5: No Connect
0x6: No Connect
0x7: No Connect
0x8: 3kΩ in series with a Schottky diode.
0x9: No Connect
D_TRICKLE
3:0
Sets the charging path for trickle charger.
0xA: 6kΩ in series with a Schottky diode.
0xB: 11kΩ in series with a Schottky diode.
0xC: 3kΩ in series with a diode in series with a
Schottky diode.
0xD: No Connect
0xE: 6kΩ in series with a diode in series with a
Schottky diode.
0xF: 11kΩ in series with a diode in series with a
Schottky diode.
Clock_sync_reg (0x58)
Clock Synchronization Configuration Register
BIT
Field
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
–
–
–
1
0
SYNC_DELAY[1:0]
0b10
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Synchronization delay setting for
external 1Hz clock (ECLK = 1, CLKSEL
= 0) mode. Delay is less than 1s.
0x1: Synchronization delay setting
for external 50Hz/60Hz/32kHz clock
(ECLK = 1, CLKSEL = 1/2/3) mode.
Delay is less than 100ms.
0x2: Synchronization delay setting for
internal oscillator mode (OSCONZ = 0,
ECLK = 0). Delay is less than 10ms.
0x3: Reserved
Synchronization delay is the time it
takes for the internal countdown chain
to reset after the rising edge of Set_
RTC. See the Minimizing the Clock
Synchronization Delay section for
further details. To minimize the delay,
select the appropriate setting based
on the clock configuration.
SYNC_DELAY
1:0
Maxim Integrated
│ 28
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
RevID_reg (0x59)
Revision Identification Register
BIT
Field
7
6
5
4
3
–
–
–
2
–
–
–
1
–
–
–
0
–
–
–
REVID[3:0]
0x1
Reset
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
REVID
7:4
Revision ID
Ordering Information
PART NUMBER
MAX31341BEWC+T
MAX31341CETB+T
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
12 WLP
10 TDFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape-and-reel.
Maxim Integrated
│ 29
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MAX31341B/
MAX31341C
Low-Current, Real-Time Clock with
I2C Interface and Power Management
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
2
3
4
4/19
5/19
8/19
1/20
3/20
Initial release
—
10–12
9
Updated Layout Example, Table 1, and Countdown Timer section
2
Updated I C Interface section
Added MAX31341C part number to data sheet
1–30
29
Updated Ordering Information
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2020 Maxim Integrated Products, Inc.
│ 30
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