MAX3391EEBC-T [MAXIM]
【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP; ± 15kV ESD保护， 1μA ， 16Mbps的，双/四通道，低电压电平转换器，UCSP封装
| 型号： | MAX3391EEBC-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP |
| 文件： | 总25页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2328; Rev 3; 9/03
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
General Description
Features
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
±±15k EꢀSD-proeꢁoed ꢂeꢃeꢂ opanꢄꢂaorpꢄ -prꢃvde ohe ꢂeꢃeꢂ
ꢄhvfovng neꢁeꢄꢄapy or aꢂꢂrw daoa opanꢄfep vn a muꢂovꢃrꢂoage
o Guaranteed Data Rate Options
230kbps
8Mbps (+1.2V ≤ V ≤ V
≤ +5.5V)
L
CC
ꢄyꢄoem. Exoepnaꢂꢂy a--ꢂved ꢃrꢂoageꢄ, k
and k , ꢄeo ohe
L
CC
10Mbps (+1.2V ≤ V ≤ V
≤ +3.3V)
L
CC
CC
ꢂrgvꢁ ꢂeꢃeꢂꢄ rn evohep ꢄvde rf ohe deꢃvꢁe. A ꢂrwDꢃrꢂoage
16Mbps (+1.8V ≤ V ≤ V
≤ +2.5V and +2.5V ≤
L
ꢂrgvꢁ ꢄvgnaꢂ -peꢄeno rn ohe k ꢄvde rf ohe deꢃvꢁe a--eapꢄ
L
V ≤ V
≤ +3.3V)
L
CC
aꢄ a hvghDꢃrꢂoage ꢂrgvꢁ ꢄvgnaꢂ rn ohe k
ꢄvde rf ohe
CC
o Bidirectional Level Translation
(MAX3372E/MAX3373E and
MAX3377E/MAX3378E)
deꢃvꢁe, and ꢃvꢁeDꢃepꢄa. The MAX3374E/MAX3371E/
MAX3376E/MAX3379E and MAX3390E–MAX3393E unvdvD
peꢁovrnaꢂ ꢂeꢃeꢂ opanꢄꢂaorpꢄ ꢂeꢃeꢂ ꢄhvfo daoa vn rne dvpeꢁovrn
(k → k
rp k
→ k ) rn any ꢄvngꢂe daoa ꢂvne. The
L
CC
CC L
o Operation Down to +1.2V on V
L
MAX3372E/MAX3373E and MAX3377E/MAX3378E bvdvD
peꢁovrnaꢂ ꢂeꢃeꢂ opanꢄꢂaorpꢄ uovꢂvze a opanꢄmvꢄꢄvrnDgaoeD
baꢄed deꢄvgn (Fvgupe 2) or aꢂꢂrw daoa opanꢄꢂaovrn vn evohep
o
15kV EꢀD ꢁrotection on ꢂ/O V
Lines
CC
o Ultra-Low 1µA ꢀupply Current in Three-ꢀtate
Output Mode
o Low-Quiescent Current (130µA typ)
o UCꢀꢁ, ꢀOT, and TꢀꢀOꢁ ꢁackages
o Thermal ꢀhort-Circuit ꢁrotection
dvpeꢁovrn (k ↔ k ) rn any ꢄvngꢂe daoa ꢂvne. The
L
CC
MAX3372E–MAX3379E and MAX3390E–MAX3393E
aꢁꢁe-o k fprm +±.2k or +1.1k and k fprm +±.61k or
L
CC
+1.1k, ma5vng ohem vdeaꢂ frp daoa opanꢄfep beoween ꢂrwD
ꢃrꢂoage AꢀICꢄ/PLSꢄ and hvghep ꢃrꢂoage ꢄyꢄoemꢄ.
Aꢂꢂ deꢃvꢁeꢄ vn ohe MAX3372E–MAX3379E, MAX3390E–
MAX3393E famvꢂy feaoupe a ohpeeDꢄoaoe ruo-uo mrde ohao
peduꢁeꢄ ꢄu--ꢂy ꢁuppeno or ꢂeꢄꢄ ohan ±µA, ohepmaꢂ ꢄhrpoD
Ordering Information
ꢁꢂN-
ꢁACKAGE
ꢁART NUMBER
TEMꢁ RANGE
ꢁvpꢁuvo -proeꢁovrn, and ±±15k EꢀS -proeꢁovrn rn ohe k
CC
ꢄvde frp gpeaoep -proeꢁovrn vn a--ꢂvꢁaovrnꢄ ohao pruoe ꢄvgD
naꢂꢄ exoepnaꢂꢂy. The MAX3372E/MAX3377E r-epaoe ao a
guapanoeed daoa paoe rf 2305b-ꢄ. ꢀꢂewDpaoe ꢂvmvovng
peduꢁeꢄ EMI emvꢄꢄvrnꢄ vn aꢂꢂ 2305b-ꢄ deꢃvꢁeꢄ. The
MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E r-epaoe ao a guapanoeed daoa paoe
rf 8Mb-ꢄ rꢃep ohe enovpe ꢄ-eꢁvfved r-epaovng ꢃrꢂoage
pange. Wvohvn ꢄ-eꢁvfvꢁ ꢃrꢂoage drmavnꢄ, hvghep daoa paoeꢄ
ape -rꢄꢄvbꢂe. (ꢀee Timing Characteristics.)
MAX3372EEKA-T
-40°C to +85°C
8 SOT23-8
Ordering Information continued at end of data sheet.
Selector Guide appears at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
I2C is a trademark of Phillips Corp.
MICROWIRE is a trademark of National Semiconductor Corp.
The MAX3372E–MAX3376E ape duaꢂ ꢂeꢃeꢂ ꢄhvfoepꢄ
aꢃavꢂabꢂe vn 3 x 3 UCꢀP™ and 8D-vn ꢀOT23D8 -aꢁ5D
ageꢄ. The MAX3377E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E ape quad ꢂeꢃeꢂ ꢄhvfoepꢄ aꢃavꢂD
abꢂe vn 3 x 4 UCꢀP and ±4D-vn TꢀꢀOP -aꢁ5ageꢄ.
-in Configurations
________________________Applications
ꢀPI™, MICROWIRE™, and I2C™ Leꢃeꢂ
Tpanꢄꢂaovrn
LrwDkrꢂoage AꢀIC Leꢃeꢂ Tpanꢄꢂaovrn
ꢀmapo Capd Readepꢄ
I/O V
2
1
2
3
4
8
7
6
5
I/O V 1
CC
CC
GND
V
CC
MAX3372E/
MAX3373E
V
L
THREE-STATE
I/O V 1
CeꢂꢂDPhrne Cpadꢂeꢄ
I/O V 2
L
L
Prpoabꢂe POꢀ ꢀyꢄoemꢄ
Prpoabꢂe Crmmunvꢁaovrn Seꢃvꢁeꢄ
LrwDCrꢄo ꢀepvaꢂ Inoepfaꢁeꢄ
Ceꢂꢂ Phrneꢄ
ꢀOT23-8
TOꢁ VꢂEW
GPꢀ
Pin Configurations continued at end of data sheet.
Teꢂeꢁrmmunvꢁaovrnꢄ Equv-meno
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
ABꢀOLUTE MAXꢂMUM RATꢂNGꢀ
All Voltages Referenced to GND
Continuous Power Dissipation (T = +70°C)
A
V
I/O V
...........................................................................-0.3V to +6V
8-Pin SOT23 (derate 8.9mW/°C above +70°C)...........714mW
3 x 3 UCSP (derate 4.7mW/°C above +70°C) ............379mW
3 x 4 UCSP (derate 6.5mW/°C above +70°C) ............579mW
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ........727mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
......................................................-0.3V to (V
+ 0.3V)
CC_
CC
I/O V ...........................................................-0.3V to (V + 0.3V)
THREE-STATE...............................................-0.3V to (V + 0.3V)
Short-Circuit Duration I/O V , I/O V
Short-Circuit Duration I/O V or I/O V
L_
L
L
to GND...........Continuous
L
CC
to GND
L
CC
Driven from 40mA Source
(except MAX3372E and MAX3377E) .....................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRꢂCAL CHARACTERꢂꢀTꢂCꢀ
(V
= +1.65V to +5.5V, V = +1.2V to (V
+ 0.3V), GND = 0, I/O V and I/O V
unconnected, T = T
to T
, unless other-
MAX
CC
L
CC
L_
CC_
A
MIN
wise noted. Typical values are at V
= +3.3V, V = +1.8V, T = +25°C.) (Notes 1, 2)
A
L
CC
ꢁARAMETER
ꢀYMBOL
CONDꢂTꢂONꢀ
MꢂN
TYꢁ
MAX
UNꢂTꢀ
ꢁOWER ꢀUꢁꢁLꢂEꢀ
V Supply Range
V
1.2
5.5
5.50
300
100
V
L
L
V
Supply Range
V
1.65
V
CC
CC
Supply Current from V
I
130
16
µA
µA
CC
L
QVCC
Supply Current from V
I
QVL
V
Three-State Output Mode
CC
I
I
T
T
= +25°C, THREE-STATE = GND
= +25°C, THREE-STATE = GND
0.03
0.03
1
1
µA
µA
THREE-STATE-VCC
A
A
Supply Current
V Three-State Output Mode
L
Supply Current
I
THREE-STATE-VL
Three-State Output Mode
Leakage Current
I/O V and I/O V
T
T
= +25°C, THREE-STATE = GND
= +25°C
0.02
0.02
1
1
µA
µA
THREE-STATE-LKG
A
A
L_
CC_
THREE - S TATE Pin Input Leakage
EꢀD ꢁROTECTꢂON
IEC 1000-4-2 Air-Gap Discharge
IEC 1000-4-2 Contact Discharge
Human Body Model
8
8
I/O V
(Note 3)
kV
CC
15
LOGꢂC-LEVEL THREꢀHOLDꢀ (MAX3372E/MAX3377E)
I/O V Input Voltage High
V
V - 0.2
L
V
V
L_
IHL
I/O V Input Voltage Low
V
0.15
L_
ILL
2
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
ELECTRꢂCAL CHARACTERꢂꢀTꢂCꢀ (continued)
(V
= +1.65V to +5.5V, V = +1.2V to (V
+ 0.3V), GND = 0, I/O V and I/O V
unconnected, T = T
to T
, unless other-
MAX
CC
L
CC
L_
CC_
A
MIN
wise noted. Typical values are at V
= +3.3V, V = +1.8V, T = +25°C.) (Notes 1, 2)
CC
A
L
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
V - 0.4
CC
MAX
UNITS
I/O V
I/O V
Input Voltage High
Input Voltage Low
V
V
V
CC_
IHC
V
0.15
CC_
ILC
I/O V source current = 20µA,
L_
✕
I/O V Output Voltage High
V
0.67
0.67
V
V
V
V
V
V
V
L_
OHL
L
I/O V
> V
- 0.4V
CC
CC_
I/O V sink current = 20µA,
L_
I/O V Output Voltage Low
V
0.4
0.4
L_
OLL
I/O V
< 0.15V
CC_
I/O V
source current = 20µA,
CC_
✕
I/O V
Output Voltage High
Output Voltage Low
V
OHC
V
CC_
CC_
CC
I/O V > V - 0.2V
L _
L
I/O V
sink current = 20µA,
CC_
I/O V
V
OLC
I/O V < 0.15V
L_
THREE-STATE Input Voltage
High
V
V - 0.2
L
IL-THREE-STATE
IL-THREE-STATE
THREE-STATE Input Voltage
Low
V
0.15
LOGIC-LEVEL THRESHOLDS (MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E)
I/O V Input Voltage High V - 0.2
V
V
V
V
V
L_
IHL
L
I/O V Input Voltage Low
V
0.15
0.15
L_
ILL
I/O V
Input Voltage High
Input Voltage Low
V
V - 0.4
CC
CC_
CC_
IHC
I/O V
V
ILC
I/O V source current = 20µA,
L_
✕
I/O V Output Voltage High
V
0.67
0.67
V
V
V
V
V
V
V
L_
OHL
L
I/O V
≥ V
- 0.4V
CC
CC_
I/O V sink current = 1mA,
L_
I/O V Output Voltage Low
V
0.4
0.4
L_
OLL
I/O V
≤ 0.15V
CC_
I/O V
source current = 20µA,
CC_
✕
I/O V
Output Voltage High
Output Voltage Low
V
OHC
V
CC_
CC_
CC
I/O V ≥ V - 0.2V
L_
L
I/O V
sink current = 1mA,
CC_
I/O V
V
OLC
I/O V ≤ 0.15V
L_
THREE-STATE Input Voltage
High
V
V - 0.2
L
IH-THREE-STATE
THREE-STATE Input Voltage
Low
V
0.15
IL-THREE-STATE
_______________________________________________________________________________________
3
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
TIMING CHARACTERISTICS
(V
= +1.65V to +5.5V, V = +1.2V to (V
+ 0.3V), GND = 0, R
= 1MΩ, I/O test signal of Figure 1, T = T
to T
, unless
MAX
CC
L
CC
LOAD
A
A
MIN
otherwise noted. Typical values are at V
= +3.3V, V = +1.8V, T = +25°C, unless otherwise noted.) (Notes 1, 2)
CC
L
PARAMETER
SYMBOL
= 50pF)
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3372E/MAX3377E (C
LOAD
I/O V _ Rise Time (Note 4)
t
1100
1000
600
ns
ns
ns
ns
CC
RVCC
I/O V _ Fall Time (Note 5)
t
CC
FVCC
I/O V _ Rise Time (Note 4)
t
RVL
L
I/O V _ Fall Time (Note 5)
L
t
1100
FVL
I/O
I/O
Driving I/O V _
1.6
1.6
500
VL-VCC
VCC-VL
SKEW
L
Propagation Delay
µs
Driving I/O V
_
CC
Channel-to-Channel Skew
Maximum Data Rate
t
Each translator equally loaded
C = 25pF
ns
230
kbps
L
MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E (C
= 15pF, Driver Output Impedance ≤ 50Ω)
LOAD
+1.2V ≤ V ≤ V
≤ +5.5V
L
CC
7
170
6
25
400
37
I/O V _ Rise Time (Note 4)
t
ns
ns
ns
ns
CC
RVCC
Open-drain driving
Open-drain driving
Open-drain driving
Open-drain driving
I/O V _ Fall Time (Note 5)
t
CC
FVCC
20
8
50
30
I/O V _ Rise Time (Note 4)
t
RVL
L
180
3
400
30
I/O V _ Fall Time (Note 5)
L
t
LFV
30
5
60
30
I/O
I/O
Driving I/O V _
L
VL-VCC
VCC-VL
SKEW
Open-drain driving
Open-drain driving
Open-drain driving
210
4
1000
30
Propagation Delay
ns
ns
Driving I/O V _
CC
190
1000
20
Each translator
equally loaded
Channel-to-Channel Skew
Maximum Data Rate
t
50
8
Mbps
kbps
Open-drain driving
500
4
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
TIMING CHARACTERISTICS (continued)
(V
= +1.65V to +5.5V, V = +1.2V to (V
+ 0.3V), GND = 0, R
= 1MΩ, I/O test signal of Figure 1, T = T
to T
, unless
MAX
CC
L
CC
LOAD
A
A
MIN
otherwise noted. Typical values are at V
= +3.3V, V = +1.8V, T = +25°C, unless otherwise noted.) (Notes 1, 2)
CC
L
PARAMETER
+1.2V ≤ V ≤ V ≤ +3.3V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
L
CC
I/O V _ Rise Time (Note 4)
t
25
30
30
30
20
20
10
ns
ns
ns
ns
CC
RVCC
I/O V _ Fall Time (Note 5)
t
CC
FVCC
I/O V _ Rise Time (Note 4)
t
RVL
L
I/O V _ Fall Time (Note 5)
L
t
FVL
I/O
I/O
Driving I/O V _
L
VL-VCC
VCC-VL
SKEW
Propagation Delay
ns
Driving I/O V
_
CC
Each translator equally loaded
Channel-to-Channel Skew
Maximum Data Rate
t
ns
10
Mbps
+2.5V ≤ V ≤ V
≤ +3.3V
L
CC
I/O V _ Rise Time (Note 4)
t
15
15
15
15
15
15
10
ns
ns
ns
ns
CC
RVCC
I/O V _ Fall Time (Note 5)
t
CC
FVCC
I/O V _ Rise Time (Note 4)
t
RVL
L
I/O V _ Fall Time (Note 5)
L
t
FVL
I/O
I/O
Driving I/O V _
L
VL-VCC
VCC-VL
SKEW
Propagation Delay
ns
Driving I/O V
_
CC
Channel-to-Channel Skew
Maximum Data Rate
t
Each translator equally loaded
ns
16
Mbps
+1.8V ≤ V ≤ V
≤ +2.5V
L
CC
I/O V _ Rise Time (Note 4)
t
15
15
15
15
15
15
10
ns
ns
ns
ns
CC
RVCC
I/O V _ Fall Time (Note 5)
t
CC
FVCC
I/O V _ Rise Time (Note 4)
t
RVL
L
I/O V _ Fall Time (Note 5)
L
t
FVL
I/O
I/O
Driving I/O V _
L
VL-VCC
VCC-VL
SKEW
Propagation Delay
ns
Driving I/O V
_
CC
Channel-to-Channel Skew
Maximum Data Rate
t
Each translator equally loaded
ns
16
Mbps
Note 1: All units are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design
A
and not production tested.
Note 2: For normal operation, ensure V < (V
+ 0.3V). During power-up, V > (V
+ 0.3V) will not damage the device.
L
CC
L
CC
Note 3: To ensure maximum ESD protection, place a 1µF capacitor between V
and GND. See Applications Circuits.
CC
Note 4: 10% to 90%
Note 5: 90% to 10%
_______________________________________________________________________________________
5
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Typical Operating Characteristics
(R = 1MΩ, T = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
L
A
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
V
SUPPLY CURRENT vs. SUPPLY VOLTAGE
V SUPPLY CURRENT vs. SUPPLY VOLTAGE
L
V SUPPLY CURRENT vs. TEMPERATURE
L
CC
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
L
CC
L
L
CC
L
CC CC
L
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
500kbps, OPEN-DRAIN, C = 15pF
LOAD
8Mbps, C
= 15pF
LOAD
8Mbps, C
= 15pF
LOAD
500kbps, OPEN-DRAIN, C
= 15pF
8Mbps, C
= 15pF
LOAD
LOAD
500kbps, OPEN-DRAIN, C
= 15pF
LOAD
230kbps, C
= 50pF
LOAD
230kbps, C
= 50pF
LOAD
230kbps, C
= 50pF
60
LOAD
0
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
(V)
1.65 2.20 2.75 3.30 3.85 4.40 4.95 5.50
(V)
-40
-15
10
35
85
V
V
TEMPERATURE (°C)
CC
CC
V
SUPPLY CURRENT vs. TEMPERATURE
V SUPPLY CURRENT vs. CAPACITIVE LOAD
V
SUPPLY CURRENT vs. CAPACITIVE LOAD
CC
CC
L
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
CC CC
L
L
CC
L
L CC L
1600
1400
1200
1000
800
600
400
200
0
350
300
250
200
150
100
50
2500
8Mbps
2000
1500
1000
500
0
8Mbps, C
= 15pF
LOAD
8Mbps
500kbps, OPEN-DRAIN, C
230kbps, C
= 15pF
LOAD
500kbps, OPEN-DRAIN
500kbps, OPEN-DRAIN
230kbps
= 50pF
LOAD
230kbps
85
0
-40
-15
10
35
60
85
10
25
40
55
70
100
10
25
40
55
70
85
100
TEMPERATURE (°C)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
L
CC
L
L
CC
L
L
CC
L
2500
2000
1500
1000
500
18
16
14
12
10
8
250
t
LH
200
150
100
50
t
LH
t
LH
DATA RATE = 500kbps,
OPEN-DRAIN
t
HL
6
DATA RATE = 230kbps
t
HL
4
DATA RATE = 8Mbps
2
t
HL
0
0
0
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
6
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Typical Operating Characteristics (continued)
(R = 1MΩ, T = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
L
A
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
L
CC
L
L
CC
L
L
CC
L
700
600
500
400
300
200
100
0
15
12
9
300
250
200
150
100
50
DATA RATE = 8Mbps
t
PLH
t
PHL
t
PHL
DATA RATE = 500kbps,
OPEN-DRAIN
t
PLH
6
DATA RATE = 230kbps
3
t
PHL
t
PLH
0
0
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +2.5V, V = +1.8V)
(DRIVING I/O V , V = +2.5V, V = +1.8V)
(DRIVING I/O V , V = +2.5V, V = +1.8V)
L
CC
L
L
CC
L
CC CC L
2500
2000
1500
1000
500
14
300
250
200
150
100
50
DATA RATE = 8Mbps
t
LH
12
10
8
t
LH
t
LH
DATA RATE = 500kbps,
OPEN-DRAIN
6
t
HL
DATA RATE = 230kbps
4
t
HL
2
t
HL
0
0
0
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
(DRIVING I/O V , V = +3.3V, V = +1.8V)
CC CC
L
CC CC
L
CC CC L
2500
2000
1500
1000
500
12
10
8
300
250
200
150
100
50
DATA RATE = 8Mbps
DATA RATE = 230kbps
t
LH
t
HL
t
LH
DATA RATE = 500kbps,
OPEN-DRAIN
6
4
t
HL
t
2
HL
t
LH
0
0
0
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
_______________________________________________________________________________________
7
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Typical Operating Characteristics (continued)
(R = 1MΩ, T = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
L
A
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
PROPAGATION DELAY vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +3.3V, V = +1.8V)
CC CC
L
CC CC
L
CC CC
L
6
5
4
3
2
1
0
300
250
200
150
100
50
700
600
500
400
300
200
100
0
DATA RATE = 8Mbps
DATA RATE = 230kbps
t
PLH
t
PHL
t
PHL
DATA RATE = 500kbps,
OPEN-DRAIN
t
PLH
t
PHL
t
PHL
0
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
10 15 20 25 30 35 40 45 50
CAPACITIVE LOAD (pF)
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
RISE/FALL TIME vs. CAPACITIVE LOAD
(DRIVING I/O V , V = +2.5V, V = +1.8V)
(DRIVING I/O V , V = +2.5V, V = +1.8V)
(DRIVING I/O V , V = +2.5V, V = +1.8V)
CC CC
L
CC CC
L
CC CC L
2500
2000
1500
1000
500
12
10
8
350
300
250
200
150
100
50
DATA RATE = 8Mbps
DATA RATE = 230kbps
t
t
HL
LH
DATA RATE = 500kbps,
OPEN-DRAIN
6
t
LH
4
t
t
HL
HL
2
t
LH
0
0
0
20 30 40 50 60 70 80 90 100
CAPACITIVE LOAD (pF)
10
20
30
40
50
10
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
RAIL-TO-RAIL DRIVING
RAIL-TO-RAIL DRIVING
(DRIVING I/O V , V = +3.3V, V = +1.8V,
(DRIVING I/O V , V = +3.3V, V = +1.8V,
L
CC
L
L
CC
L
C = 50pF, DATA RATE = 230kbps)
L
C = 15pF, DATA RATE = 8Mbps)
L
I/O V
1V/div
2V/div
I/O V
1V/div
2V/div
L_
L_
I/O V
I/O V
CC_
CC_
200ns/div
1µs/div
8
_______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Typical Operating Characteristics (continued)
(R = 1MΩ, T = +25°C, unless otherwise noted. All 230kbps TOCs apply to MAX3372E/MAX3377E only. All 8Mbps and 500kbps
L
A
TOCs apply to MAX3373E–MAX3376E/MAX3378E/MAX3379E and MAX3390E–MAX3393E only.)
OPEN-DRAIN DRIVING
EXITING THREE-STATE OUTPUT MODE
(DRIVING I/O V , V = +3.3V, V = +1.8V,
L
CC
L
(V = +3.3V, V = +1.8V, C = 50pF)
C = 15pF, DATA RATE = 500kbps)
CC
L
L
L
MAX3372E toc28
2V/div
1V/div
I/O V
CC_
I/O V
1V/div
2V/div
L_
I/O V
L_
I/O V
CC_
1V/div
THREE-STATE
2µs/div
200ns/div
-in Description
PIN
NAME
I/O V 1
FUNCTION
3 x 4
UCSP
3 x 3
UCSP
TSSOP
SOT23-8
A1
A2
A3
A4
B1
B2
2
3
5
4
C2
C3
—
Input/Output 1. Referenced to V . (Note 6)
L
L
I/O V 2
Input/Output 2. Referenced to V . (Note 6)
L
L
4
—
—
7
I/O V 3
Input/Output 3. Referenced to V . (Note 6)
L
L
5
—
I/O V 4
Input/Output 4. Referenced to V . (Note 6)
L
L
14
1
A1
C1
V
V
Input Voltage +1.65V ≤ V
≤ +5.5V.
CC
CC
CC
3
V
Logic Input Voltage +1.2V ≤ V ≤ (V
+ 0.3V)
L
L
CC
Three-State Output Mode Enable. Pull THREE-STATE low
to place device in three-state output mode. I/O V and
I/O V are high impedance in three-state output mode.
L_
CC_
THREE-
STATE
B3
8
6
B1
NOTE: Logic referenced to V (for logic thresholds see
L
Electrical Characteristics).
B4
C1
C2
C3
C4
—
7
13
12
11
10
6, 9
2
8
B3
A2
A3
—
GND
Ground
I/O V
I/O V
I/O V
I/O V
1
2
3
4
Input/Output 1. Referenced to V . (Note 6)
CC
CC
CC
CC
CC
1
Input/Output 2. Referenced to V . (Note 6)
CC
—
—
—
Input/Output 3. Referenced to V . (Note 6)
CC
—
Input/Output 4. Referenced to V . (Note 6)
CC
B2
N.C.
No Connection. Not internally connected.
Note 6: For unidirectional devices (MAX3374E/MAX3375E/MAX3376E/MAX3379E and MAX3390E–MAX3393E) see Pin
Configurations for input/output configurations.
_______________________________________________________________________________________
9
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
All devices in the MAX3372E–MAX3379E, MAX3390E–
Detailed Description
MAX3393E family feature a three-state output mode that
The MAX3372E–MAX3379E and MAX3390E–MAX3393E
reduces supply current to less than 1µA, thermal short-
ESD-protected level translators provide the level shifting
circuit protection, and 15kV ESD protection on the V
CC
necessary to allow data transfer in a multivoltage system.
side for greater protection in applications that route sig-
nals externally. The MAX3372E/MAX3377E operate at a
guaranteed data rate of 230kbps. Slew-rate limiting
reduces EMI emissions in all 230kbps devices. The
MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E operate at a guaranteed data rate
of 8Mbps over the entire specified operating voltage
range. Within specific voltage domains, higher data rates
are possible. (See Timing Characteristics.)
Externally applied voltages, V and V , set the logic lev-
CC
L
els on either side of the device. A low-voltage logic signal
present on the V side of the device appears as a high-
L
voltage logic signal on the V
side of the device, and
CC
vice-versa. The MAX3374E/MAX3375E/MAX3376E/
MAX3379E and MAX3390E–MAX3393E unidirectional
level translators level shift data in one direction (V
→
L
V
or V
→ V ) on any single data line. The
CC
CC L
MAX3372E/MAX3373E and MAX3377E/MAX3378E bidi-
rectional level translators utilize a transmission-gate-
based design (see Figure 2) to allow data translation in
Level Translation
For proper operation ensure that +1.65V ≤ V
≤ +5.5V,
CC
either direction (V ↔ V ) on any single data line. The
L
CC
+1.2V ≤ V ≤ +5.5V, and V ≤ (V + 0.3V). During
L
L
CC
MAX3372E–MAX3379E and MAX3390E–MAX3393E
power-up sequencing, V ≥ (V + 0.3V) will not damage
L
CC
accept V from +1.2V to +5.5V and V from +1.65V to
L
CC
the device. During power-supply sequencing, when V
CC
+5.5V, making them ideal for data transfer between low-
is floating and V is powering up, a current may be
L
voltage ASICs/PLDs and higher voltage systems.
sourced, yet the device will not latch up. The speed-up
V
V
V
L
V
CC
L
CC
V
V
CC
V
V
CC
L
L
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
DATA
DATA
I/O V
_
I/O V
_
I/O V _
L
CC
I/O V _
L
CC
C
R
LOAD
GND
GND
LOAD
R
C
LOAD
LOAD
I/O V _
L
,
I/O V
_
CC
,
(t
RISE
FALL
(t
RISE
FALL
t
< 10ns)
t
< 10ns)
t
t
PD-VCC-LH
PD-VCC-HL
t
t
PD-VL-LH
PD-VL-HL
I/O V
_
CC
I/O V _
L
t
t
RVCC
FVCC
t
t
RVL
FVL
Figure 1b. Rail-to-Rail Driving I/O V
Figure 1a. Rail-to-Rail Driving I/O V
CC
L
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
10 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
circuitry limits the maximum data rate for devices in the
MAX3372E–MAX3379E, MAX3390E–MAX3393E family to
16Mbps. The maximum data rate also depends heavily
on the load capacitance (see Typical Operating
Characteristics), output impedance of the driver, and the
operational voltage range (see Timing Characteristics).
put mode. Connect THREE-STATE to V (logic high) for
L
normal operation. Activating the three-state output mode
disconnects the internal 10kΩ pullup resistors on the I/O
V
and I/O V lines. This forces the I/O lines to a high-
L
CC
impedance state, and decreases the supply current to
less than 1µA. The high-impedance I/O lines in three-
state output mode allow for use in a multidrop network.
When in three-state output mode, do not allow the voltage
ꢀpeedꢁUp Circuitry
The MAX3373E–MAX3376E/MAX3378E/MAX3379E and
MAX3390E–MAX3393E feature a one-shot generator that
decreases the rise time of the output. When triggered,
MOSFETs PU1 and PU2 turn on for a short time to pull up
at I/O V to exceed (V + 0.3V), or the voltage at I/O
L_
L
V
CC_
to exceed (V + 0.3V).
CC
Thermal ꢀhortꢁCircuit -rotection
I/O V and I/O V
to their respective supplies (see
Thermal overload detection protects the MAX3372E–
MAX3379E and MAX3390E–MAX3393E from short-circuit
fault conditions. In the event of a short-circuit fault, when
L_
CC_
Figure 2b). This greatly reduces the rise time and propa-
gation delay for the low-to-high transition. The scope
photo of Rail-to-Rail Driving for 8Mbps Operation in the
Typical Operating Characteristics shows the speed-up
circuitry in operation.
the junction temperature (T ) reaches +152°C, a thermal
J
sensor signals the three-state output mode logic to force
the device into three-state output mode. When T has
J
cooled to +142°C, normal operation resumes.
Threeꢁꢀtate Output Mode
Pull THREE-STATE low to place the MAX3372E–
MAX3379E and MAX3390E–MAX3393E in three-state out-
V
V
L
CC
V
V
L
CC
V
V
CC
L
V
V
CC
L
MAX3373E–MAX3376E,
MAX3378E/MAX3379E
MAX3372E–MAX3379E
AND MAX3390E–MAX3393E
AND MAX3390E–MAX3393E
DATA
DATA
I/O V
I/O V
CC_
L_
I/O V
I/O V
CC_
L_
C
LOAD
C
LOAD
GND
R
LOAD
GND
R
LOAD
I/O V
CC_
I/O V
L_
t
t
PD-VCC-HL
PD-VL-HL
t
t
PD-VL-LH
PD-VCC-LH
I/O V
I/O V
L_
CC_
t
t
t
RVL
t
FVL
RVCC
FVCC
Figure 1c. Open-Drain Driving I/O V
Figure 1d. Open-Drain Driving I/O V
L
CC
______________________________________________________________________________________ 11
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
V
V
CC
L
P
P
GATE
BIAS
I/O V
I/O V
CC
L
N
Figure 2a. Functional Diagram, MAX3372E/MAX3377E (1I/O line)
V
V
L
CC
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
PU1
PU2
GATE
BIAS
I/O V
L_
I/O V
CC_
N
Figure 2b. Functional Diagram, MAX3373E/MAX3378E (1I/O line)
12 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX3372E–
MAX3379E and MAX3390E–MAX3393E help to design
equipment that meets Level 3 of IEC 1000-4-2, without
the need for additional ESD-protection components.
±±15k EꢀD -rotection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O V
lines have extra protection against static
CC
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, three-state out-
put mode, and powered down. After an ESD event,
Maxim’s E versions keep working without latchup,
whereas competing products can latch and must be
powered down to remove latchup.
The major difference between tests done using the
Human Body Model and IEC 1000-4-2 is higher peak cur-
rent in IEC 1000-4-2, because series resistance is lower
in the IEC 1000-4-2 model. Hence, the ESD withstand
voltage measured to IEC 1000-4-2 is generally lower than
that measured using the Human Body Model. Figure 4a
shows the IEC 1000-4-2 model, and Figure 4b shows the
current waveform for the 8kV, IEC 1000-4-2, Level 4,
ESD contact-discharge test.
ESD protection can be tested in various ways. The I/O
V
lines of this product family are characterized for
CC
protection to the following limits:
The air-gap test involves approaching the device with a
charged probe. The contact-discharge method connects
the probe to the device before the probe is energized.
1) 15kV using the Human Body Model
2) 8kV using the Contact Discharge method specified
in IEC 1000-4-2
3) 10kV using IEC 1000-4-2’s Air-Gap Discharge
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. Of course, all pins require this protec-
tion during manufacturing, not just inputs and outputs.
Therefore, after PC board assembly, the Machine
Model is less relevant to I/O ports.
method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 3a shows the Human Body Model and Figure 3b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩ resistor.
R
1MΩ
R 1500Ω
D
C
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
100pF
STORAGE
CAPACITOR
36.8%
SOURCE
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 3a. Human Body ESD Test Model
Figure 3b. Human Body Current Waveform
______________________________________________________________________________________ 13
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
I
100%
90%
R
C
50MΩ to 100MΩ
R 330Ω
D
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
10%
t
t = 0.7ns to 1ns
r
30ns
60ns
Figure 4a. IEC 1000-4-2 ESD Test Model
Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform
ASIC and an I2C device. A typical application involves
interfacing a low-voltage microprocessor to a 3V or 5V
D/A converter, such as the MAX517.
Applications Information
-owerꢁꢀupply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass V and V
to ground with a 0.1µF
CC
-ushꢁ-ull vs. OpenꢁDrain Driving
All devices in the MAX3372E–MAX3379E and
MAX3390E–MAX3393E family may be driven in a push-
pull configuration. The MAX3373E–MAX3376E/
MAX3378E/MAX3379E and MAX3390E–MAX3393E
L
capacitor. See Typical Operating Circuit. To ensure full
15kV ESD protection, bypass V to ground with a
CC
1µF capacitor. Place all capacitors as close to the
power-supply inputs as possible.
include internal 10kΩ resistors that pull up I/O V and
L_
2
I C Level Translation
I/O V
to their respective power supplies, allowing
CC_
The MAX3373E–MAX3376E, MAX3378E/MAX3379E
and MAX3390E–MAX3393E level-shift the data present
on the I/O lines between +1.2V and +5.5V, making
them ideal for level translation between a low-voltage
operation of the I/O lines with open-drain devices. See
Timing Characteristics for maximum data rates when
using open-drain drivers.
Typical Operating Circuit
+1.8V
+3.3V
1µF
0.1µF
0.1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3378E–MAX3383E
I/O V I/O V
DATA
DATA
L_
CC_
14 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Applications Circuits
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3372E/MAX3373E
I/O V
I/O V
I/O V
I/O V
CC1
CC2
L1
L2
DATA
DATA
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3374E
O V
O V
I V
I V
CC1
L1
L2
DATA
DATA
CC2
______________________________________________________________________________________ 15
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3375E
O V
I V
L1
CC1
CC2
DATA
DATA
I V
O V
L2
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3376E
I V
O V
O V
CC1
CC2
L1
L2
DATA
DATA
I V
16 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3377E/MAX3378E
I/O V
I/O V
CC1
L1
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
L2
L3
L4
CC2
CC3
CC4
DATA
DATA
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3379E
O V
I V
I V
I V
I V
CC1
L1
L2
L3
L4
O V
O V
O V
CC2
CC3
CC4
DATA
DATA
______________________________________________________________________________________ 17
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3390E
I V
O V
I V
L1
L1
O V
O V
O V
CC2
CC3
CC4
L2
DATA
DATA
I V
I V
L3
L4
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3391E
I V
O V
O V
CC1
CC2
CC3
CC4
L1
L2
I V
O V
O V
DATA
DATA
I V
L3
I V
L4
18 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Applications Circuits (continued)
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3392E
I V
O V
O V
CC1
CC2
L1
L2
L3
I V
I V
O V
DATA
DATA
O V
I V
CC3
CC4
L4
+1.8V
+3.3V
0.1µF
0.1µF
1µF
V
V
CC
L
THREE-STATE
+1.8V
SYSTEM
+3.3V
SYSTEM
CONTROLLER
MAX3393E
I V
CC1
I V
CC2
I V
CC3
I V
CC4
O V
O V
L1
L2
DATA
DATA
O V
L3
I V
L4
______________________________________________________________________________________ 19
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
ꢀelector Guide
Ordering Information (continued)
PIN-
PACKAGE
LEVEL
TRANS-
LATION
PART NUMBER
TEMP RANGE
Tx/
Rx†
DATA
RATE
TOP
MARK
PART NUMBER
✕
MAX3372EEBL-T
MAX3373EEKA-T
MAX3373EEBL-T
MAX3374EEKA-T
MAX3374EEBL-T
MAX3375EEKA-T
MAX3375EEBL-T
MAX3376EEKA-T
MAX3376EEBL-T
MAX3377EEUD
MAX3377EEBC-T
MAX3378EEUD
MAX3378EEBC-T
MAX3379EEUD*
MAX3379EEBC-T*
MAX3390EEUD*
MAX3390EEBC-T*
MAX3391EEUD*
MAX3391EEBC-T*
MAX3392EEUD*
MAX3392EEBC-T*
MAX3393EEUD*
MAX3393EEBC-T*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
3
3 UCSP
8 SOT23-8
MAX3372EEKA-T
MAX3372EEBL-T
MAX3373EEKA-T
MAX3373EEBL-T
MAX3374EEKA-T
MAX3374EEBL-T
MAX3375EEKA-T
MAX3375EEBL-T
MAX3376EEKA-T
MAX3376EEBL-T
MAX3377EEUD
MAX3377EEBC-T
MAX3378EEUD
MAX3378EEBC-T
MAX3379EEUD
MAX3379EEBC-T
MAX3390EEUD
MAX3390EEBC-T
MAX3391EEUD
MAX3391EEBC-T
MAX3392EEUD
MAX3392EEBC-T
MAX3393EEUD
MAX3393EEBC-T
ꢀ Bi
ꢀ Bi
ꢀ Bi
ꢀ Bi
Uni
2/2
2/2
2/2
2/2
2/0
2/0
1/1
1/1
0/2
0/2
4/4
4/4
4/4
4/4
4/0
4/0
3/1
3/1
2/2
2/2
1/3
1/3
0/4
0/4
AAKO
AAR
AAKS
AAZ
AALH
ABA
AALI
ABB
AALG
AAV
—
230kbps
8Mbps*
230kbps
✕
3
3 UCSP
8 SOT23-8
✕
3
3 UCSP
8 SOT23-8
✕
3
3 UCSP
Uni
8 SOT23-8
Uni
✕
3
3 UCSP
Uni
14 TSSOP
Uni
✕
3
4 UCSP
Uni
14 TSSOP
ꢀ Bi
ꢀ Bi
ꢀ Bi
ꢀ Bi
Uni
✕
3
4 UCSP
AAX
—
14 TSSOP
✕
3
4 UCSP
AAY
—
14 TSSOP
✕
3
4 UCSP
Uni
AAZ
—
14 TSSOP
Uni
✕
3
4 UCSP
Uni
ABA
—
8Mbps*
14 TSSOP
Uni
✕
3
4 UCSP
Uni
ABB
—
14 TSSOP
Uni
✕
3
4 UCSP
Uni
ABC
—
Uni
*Future product—contact factory for availability.
Uni
ABD
†Tx = V → V , Rx = VCC → V
L
CC
L
*Higher data rates are possible (see Timing Characteristics).
20 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
-in Configurations (continued)
A
B
C
V
I/O V
2
1
2
3
4
8
7
6
5
I/O V 1
CC
CC
1
2
3
V
THREE-STATE
N.C.
CC
L
GND
V
CC
MAX3372E/
MAX3373E
V
L
THREE-STATE
I/O V 1
I/O V
I/O V
1
2
I/O V 1
L
CC
I/O V 2
L
L
GND
I/O V 2
L
CC
SOT23-8
TOP VIEW
3 x 3 UCSP
A
B
C
O V
2
1
2
3
4
8
7
6
5
O V 1
CC
CC
1
V
V
L
THREE-STATE
N.C.
CC
GND
V
CC
MAX3374E
2
3
V
L
THREE-STATE
I V 1
O V
O V
1
I V 1
L
CC
I V 2
L
L
GND
3 x 3 UCSP
B
I V 2
L
2
CC
SOT23-8
TOP VIEW
A
C
O V
2
1
2
3
4
8
7
6
5
I V 1
CC
CC
1
V
V
L
THREE-STATE
N.C.
CC
GND
V
CC
MAX3375E
2
3
V
L
THREE-STATE
O V 1
O V
1
I V 1
L
CC
I V 2
L
L
GND
O V 2
L
I V
CC
2
SOT23-8
TOP VIEW
3 x 3 UCSP
A
B
C
I V
2
1
2
3
4
8
7
6
5
I V 1
CC
CC
1
2
3
V
V
L
THREE-STATE
N.C.
CC
GND
V
CC
MAX3376E
V
L
THREE-STATE
O V 1
I V
I V
1
O V 1
L
CC
O V 2
L
L
GND
O V 2
L
2
CC
SOT23-8
TOP VIEW
3 x 3 UCSP
______________________________________________________________________________________ 21
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
-in Configurations (continued)
A
B
C
V
1
2
3
4
5
6
7
14
V
CC
L
1
2
3
4
IO V 1
13 I/0 V
12 I/0 V
11 I/0 V
10 I/0 V
1
2
3
4
I/O V 1
L
V
I/O V
I/O V
1
2
L
CC
CC
CC
CC
CC
CC
CC
MAX3377E/
MAX3378E
IO V 2
L
IO V 3
L
I/O V 2
L
V
L
O V 4
L
I/O V 3
L
THREE-STATE I/O V
3
4
N.C.
GND
9
8
N.C.
THREE-STATE
CC
CC
I/O V 4
L
GND
I/O V
TSSOP-14
3 x 4 UCSP
A
B
C
V
1
2
3
4
5
6
7
14
V
CC
L
1
2
3
4
I V 1
L
V
O V
O V
1
I V 1
L
13 O V
12 O V
11 O V
10 O V
1
CC
CC
CC
MAX3379E
I V 2
L
2
3
4
CC
CC
CC
I V 2
L
V
L
2
I V 3
L
CC
I V 4
L
I V 3
L
THREE-STATE O V
3
4
CC
CC
N.C.
GND
9
8
N.C.
THREE-STATE
I V 4
L
GND
O V
TSSOP-14
3 x 4 UCSP
A
B
C
V
1
2
3
4
5
6
7
14
V
CC
L
1
O V 1
L
V
I V
1
O V 1
L
13 I V 1
CC
CC
CC
MAX3390E
I V 2
L
12 O V
11 O V
10 O V
2
CC
CC
CC
2
3
4
I V 3
L
3
4
I V 2
L
V
O V
2
L
CC
I V 4
L
I V 3
L
THREE-STATE O V
3
4
N.C.
GND
9
8
N.C.
THREE-STATE
CC
CC
I V 4
L
GND
O V
TSSOP-14
3 x 4 UCSP
22 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
-in Configurations (continued)
A
B
C
V
1
2
3
4
5
6
7
14 V
CC
L
1
2
3
4
O V 1
L
V
I V
1
2
O V 1
L
13 I V
12 I V
11 I V
10 I V
1
2
3
4
CC
CC
CC
CC
CC
CC
CC
MAX3391E
O V 2
L
I V 3
L
O V 2
L
V
I V
L
I V 4
L
I V 3
L
THREE-STATE O V
3
N.C.
GND
9
8
N.C.
THREE-STATE
CC
CC
I V 4
L
GND
O V
4
TSSOP-14
3 x 4 UCSP
A
B
C
V
1
2
3
4
5
6
7
14
V
CC
L
1
2
3
4
O V 1
L
V
I V
I V
1
O V 1
L
13 I V
12 I V
11 I V
1
2
3
CC
CC
CC
CC
CC
MAX3392E
O V 2
L
O V 2
L
V
L
2
3
O V 3
L
CC
CC
I V 4
L
10 O V 4
CC
O V 3
L
THREE-STATE I V
N.C.
GND
9
8
N.C.
THREE-STATE
I V 4
L
GND
O V 4
CC
TSSOP-14
3 x 4 UCSP
A
B
C
V
1
2
3
4
5
6
7
14
V
CC
L
1
2
3
4
O V 1
L
13 I V
12 I V
11 I V
10 I V
1
2
3
4
O V 1
L
V
I V
I V
1
CC
CC
CC
CC
CC
CC
CC
MAX3393E
O V 2
L
O V 3
L
O V 2
L
V
L
2
O V 4
L
O V 3
L
N.C.
GND
9
8
N.C.
THREE-STATE
THREE-STATE I V
3
4
CC
CC
O V 4
L
GND
I V
TSSOP-14
3 x 4 UCSP
______________________________________________________________________________________ 23
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
Chip Information
TRANSISTOR COUNT: MAX3372E–MAX3376E: 189
MAX3377E–MAX3379E,
MAX3390E–MAX3393E: 295
PROCESS: BiCMOS
-ac5age Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
SEE DETAIL "A"
SYMBOL
MIN
MAX
e
b
A
0.90
0.00
0.90
0.28
0.09
2.80
2.60
1.50
0.30
1.45
0.15
1.30
0.45
0.20
3.00
3.00
1.75
0.60
C
L
A1
A2
b
C
D
E
C
C
L
E1
L
E
E1
L
0.25 BSC.
L2
e
PIN 1
I.D. DOT
(SEE NOTE 6)
0.65 BSC.
1.95 REF.
e1
0
0
8
e1
D
C
C
L
L2
A2
A
GAUGE PLANE
A1
SEATING PLANE
C
0
L
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF
HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.
DETAIL "A"
3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.
4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.
5. COPLANARITY 4 MILS. MAX.
6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1.
PROPRIETARY INFORMATION
TITLE:
7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD
BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.
8. MEETS JEDEC MO178.
PACKAGE OUTLINE, SOT-23, 8L BODY
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0078
D
1
24 ______________________________________________________________________________________
±±15k EꢀDꢁ-rotected, ±µA, ±6Mbps, Dual/Quad
Lowꢁkoltage Level Translators in UCꢀ-
-ac5age Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated -roducts, ±20 ꢀan Gabriel Drive, ꢀunnyvale, CA 94086 408ꢁ737ꢁ7600 ____________________ 25
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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