MAX3680EAI [MAXIM]
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs; + 3.3V ， 622Mbps的， SDH / SONET 1 ： 8解串器与TTL输出
| 型号： | MAX3680EAI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs |
| 文件： | 总8页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1210; Rev 0; 3/97
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
MAX3680
_________________Ge n e ra l De s c rip t io n
______________________________Fe a t u re s
♦ Single +3.3V Supply
The MAX3680 d e s e ria lize r is id e a l for c onve rting
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial-clock and data inputs, and delivers TTL clock
and data outputs. It also provides a TTL synchroniza-
tion input that enables data realignment and reframing.
♦ 622Mbps Serial to 77Mbps Parallel Conversion
♦ 165mW Power
♦ Synchronization Input for Data Realignment and
Reframing
The MAX3680 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 28-pin SSOP
package.
♦ Differential 3.3V PECL Clock and Data Inputs
♦ TTL Data Outputs and Synchronization Input
__________________________Ap p lic a t io n s
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
________________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
PIN-PACKAGE
MAX3680EAI
-40°C to +85°C
28 SSOP
Digital Cross Connects
Pin Configuration appears at end of data sheet.
___________________________________________________________________Typ ic a l Op e ra t in g Circ u it
V
CC
= +3.3V
V
CC
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
V
= +3.3V
CC
V
CC
= +3.3V
MAX3680
130Ω
130Ω
SD+
SD-
PHOTODIODE
MAX3664
MAX3675
OVERHEAD
TERMINATION
82Ω
82Ω
DATA
AND
CLOCK
RECOVERY
LIMITING
AMP
PREAMP
100Ω
V
CC
= +3.3V
130Ω
130Ω
SCLK+
SCLK-
82Ω
82Ω
PCLK
SYNC
GND
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
0
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
...........................................................................-0.5V to 5V
Continuous Power Dissipation (T = +85°C)
SSOP (derate 9.52mW/°C above +85°C) ......................619mW
A
V
CC
PECL Inputs (SD+/-, SCLK+/-).................-0.5V to (V + 0.5V)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
TTL Input (SYNC) .....................................-0.5V to (V + 0.5V)
CC
TTL Outputs (PCLK, PD_).........................-0.5V to (V + 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX3680
DC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +3.3V, T = +25°C.)
CC
A
CC
A
PARAMETER
SYMBOL
CONDITIONS
TTL outputs = high
MIN
TYP
MAX
UNITS
Supply Current
I
CC
25
50
90
mA
PECL INPUTS (SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
V
V
- 1.16
V - 0.88
CC
V
V
IH
CC
V
IL
V
CC
- 1.81
V
- 1.48
CC
Input High Current
Input Low Current
I
V
= V
IH(MAX)
-10
10
10
µA
µA
IH
IN
I
V
IN
= V
IL(MAX)
-10
IL
TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
2.0
V
V
IH
V
IL
0.8
10
10
I
IH
V
= V
IH(MAX)
-10
-10
2.4
0
µA
µA
V
IN
I
IL
V
= V
IN IL(MAX)
V
OH
Output sourcing = 400µA
Output sinking = 400µA
V
CC
V
OL
0.44
V
AC ELECTRICAL CHARACTERISTICS
(V = +3.0V to +3.6V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
622
800
50
TYP
MAX
UNITS
MHz
ps
Maximum Serial Clock Frequency
Serial Data Setup Time
f
SCLK
t
SU
Serial Data Hold Time
t
H
ps
Parallel Clock to Data Output Delay
t
V
CC
= 3.3V, C = 18pF
-200
500
1300
ps
L
CLK-Q
Note 1: AC characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
MAX3680
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +3.0V to +3.6V, unless otherwise noted.)
CC
MAXIMUM SERIAL-CLOCK FREQUENCY
vs. TEMPERATURE
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
1.3
1.2
400
360
1.1
1.0
320
280
0.9
0.8
240
200
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
400
340
70
60
50
V
CC
= 3.6V
V
CC
= 3.3V
280
220
40
30
V
CC
= 3.0V
20
10
0
160
100
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1, 2, 5, 8,
14, 18, 25
V
CC
+3.3V Supply Voltage
3
4
6
7
SD+
SD-
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
MAX3680
SCLK+
SCLK-
Inverting PECL Serial Clock Input
9, 11, 12, 16,
20, 23, 27
GND
Ground
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data align-
ment by dropping one bit in the serial input data stream.
10
13
SYNC
PCLK
TTL Parallel Clock Output
15, 17, 19, 21,
22, 24, 26, 28
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relation-
ship between serial-data-bit position and output-data-bit assignment.
PD0–PD7
_______________De t a ile d De s c rip t io n
The MAX3680 deserializer uses an 8-bit shift register,
8-bit parallel output register, 3-bit counter, PECL input
b uffe rs , a nd TTL inp ut/outp ut b uffe rs to c onve rt
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data (Figure 1).
PD7
TTL
TTL
TTL
TTL
TTL
SD+
SD-
PD6
PD5
PD4
PD3
PECL
PECL
8-BIT
SHIFT
REGISTER
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by eight, causing the out-
put register to latch every eight bits of incoming serial
data.
SCLK+
SCLK-
8-BIT
PARALLEL
OUTPUT
REGISTER
PD2
PD1
The s ync hroniza tion inp ut (SYNC) is us e d for d a ta
realignment and reframing. When the SYNC signal is
p uls e d hig h for a t le a s t two SCLK c yc le s , PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
TTL
TTL
MAX3680
PD0
TTL
TTL
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
3-BIT
COUNTER
PCLK
SYNC
TTL
Figure 1. Functional Diagram
_______________________________________________________________________________________
4
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
MAX3680
SCLK*
SD*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17 D18
PCLK
D8-
D0
D1
D2
D3
D4
D5
D6
D7
PD7
PD6
D8
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D9
D10
D11
D12
D13
D14
D15
PD5
PD4
PD3
PD2
PD1
PD0
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2a. Functional Timing Diagram—Normal Operation
_______________________________________________________________________________________
5
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
SCLK*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17 D18
SD*
SYNC
MAX3680
PCLK
D8-
D1
D2
D3
D4
D5
D6
D7
D8
D9
PD7
PD6
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D10
D11
D12
D13
D14
D15
D16
PD5
PD4
PD3
PD2
PD1
PD0
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2b. Functional Timing Diagram—SYNC Operation
t
= 1 / f
SCLK
SCLK
SCLK*
t
SU
t
H
SD*
PCLK
t
CLK-Q
PD0–PD7
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
6
_______________________________________________________________________________________
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
MAX3680
P ECL In p u t s
The s e ria l d a ta a nd c loc k PECL inp uts (SD+, SD-,
SCLK+, SCLK-) require 50Ω termination to (V - 2V)
when interfacing with a PECL source (see Alternative
PECL Input Termination).
THEVENIN-EQUIVALENT TERMINATION
CC
+3.3V
130Ω
130Ω
MAX3680
Z = 50Ω
O
__________Ap p lic a t io n s In fo rm a t io n
Alt e rn a t ive P ECL In p u t Te rm in a t io n
Fig ure 4 s hows a lte rna tive PECL inp ut-te rmina tion
methods. Use Thevenin-equivalent termination when a
PECL
INPUTS
Z = 50Ω
O
(V
- 2V) termination voltage is not available. If AC
CC
82Ω
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
82Ω
La yo u t Te c h n iq u e s
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3680 data inputs.
ECL AC-COUPLING TERMINATION
+3.3V
1.6k
1.6k
Z = 50Ω
O
MAX3680
50Ω
PECL
INPUTS
__________________P in Co n fig u ra t io n
-2V
-2V
Z = 50Ω
O
TOP VIEW
50Ω
2.7k
2.7k
28
27
26
25
24
V
PD7
GND
PD6
1
2
CC
V
CC
Figure 4. Alternative PECL Input Termination
SD+
SD-
3
V
CC
4
PD5
V
CC
5
MAX3680
SCLK+
SCLK-
23 GND
6
___________________Ch ip In fo rm a t io n
PD4
PD3
7
22
21
V
CC
8
TRANSISTOR COUNT: 1346
GND
SYNC
GND
9
20 GND
PD2
19
18
10
11
V
CC
GND 12
17 PD1
16
13
14
PCLK
GND
V
CC
15 PD0
SSOP
_______________________________________________________________________________________
7
+3 .3 V, 6 2 2 Mb p s , S DH/S ONET
1 :8 De s e ria lize r w it h TTL Ou t p u t s
________________________________________________________P a c k a g e In fo rm a t io n
MAX3680
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
___________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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