MAX3755CCM [MAXIM]
Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater; 双率，在1Gbps / 2Gbps光纤通道四端口旁路集成电路与中继器
| 型号： | MAX3755CCM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater |
| 文件： | 总13页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2098; Rev 1; 1/02
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
General Description
Features
The MAX3754/MAX3755 quad-port bypass circuits
(PBCs) are designed for use in Fibre Channel Arbitrated
Loop applications. Each consists of four serially con-
nected port bypass circuits and a repeater that provides
clock and data recovery. The quad-PBC allows connec-
tion of up to four Fibre Channel L-ports; each can be
enabled or bypassed by individual logic inputs. To
reduce the external parts count, all signal inputs and
outputs have internal termination resistors. The
MAX3754/MAX3755 comply with Fibre Channel jitter tol-
erance requirements and can recover data signals with
up to 0.7 unit intervals (UIs) of high-frequency jitter.
These devices operate from a single +3.3V supply.
o Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate
Operation
o Meets Fibre Channel Jitter Tolerance
o 1400mV Typical Differential Output Swing
o 3.0V to 3.6V Operation
o No Reference Clock Required
o Frequency Lock Indication
o 1W Power Consumption (MAX3754) at +3.3V
o 150Ω or 100Ω Differential L-Port Impedance
Available
Pin Configuration
Applications
1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel
Fibre Channel Data Storage Systems
Storage Area Networks
Fibre Channel Hubs
GND
LIN1-
LIN1+
GND
1
2
3
4
5
6
7
8
9
36 GND
35 LOUT4+
34 LOUT4-
33 GND
32 LIN4+
31 LIN4-
30 GND
29 GND
28 OUT-
27 OUT+
26 GND
25 LOCK
LOUT1-
LOUT1+
GND
MAX3754
MAX3755
Typical Operating Circuit appears at end of data sheet.
GND
IN-
IN+ 10
GND 11
CLKEN 12
TQFP-EP*
*EXPOSED PAD MUST BE CONNECTED TO GROUND
Ordering Information
DIFFERENTIAL LIN
DIFFERENTIAL IN
AND OUT
AND LOUT
PART
TEMP RANGE
PIN-PACKAGE
TERMINATION
TERMINATION
MAX3754CCM
MAX3755CCM
0°C to +70°C
0°C to +70°C
48 TQFP-EP
48 TQFP-EP
150Ω
100Ω
100Ω
100Ω
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
ABSOLUTE MAXIMUM RATINGS
CC
V
...........................................................................-0.5V to +5V
Current into LOCK...............................................-1mA to +10mA
Current into OUT , LOUT1 , LOUT2 ,
LOUT3 , LOUT4 .......................................................... 22mA
Voltage at OUT , LOUT1 , LOUT2 ,
Continuous Power Dissipation (T = +70°C)
A
48-Pin TQFP-EP (derate 30.0mW/°C above +70°C)...........2W
Operating Junction Temperature Range...........-55°C to +150°C
Operating Temperature Range .........................-55°C to +110°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
LOUT3 , LOUT4 .....................(V
- 1.65V) to (V
+ 0.5V)
+ 0.5V)
+ 0.5V)
CC
CC
CC
CC
Voltage at IN , LIN1 , LIN2 , LIN3 ,
LIN4 ......................................................-0.5V to (V
Voltage at CLKEN, CF+, CF-, CDREN, RATESEL,
SEL_, LOCK............................................-0.5V to (V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, C = 0.047µF, T = 0°C to +70°C, unless otherwise noted.
CC
F
A
Typical values are at V
= +3.3V, T = +25°C.)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
245
285
308
349
MAX
285
UNITS
MAX3754
MAX3755
MAX3754
MAX3755
CDREN = GND
334
Supply Current (Note 1)
mA
362
CDREN = V
CC
411
1.0625Gbps operation, RATESEL = GND
2.125Gbps operation, RATESEL = V
-100
-100
200
+100
+100
2200
Input Data Rate Range
ppm
CC
Differential Input Voltage Swing
mV
P-P
V
0.45
-
CC
Input Common-Mode Voltage
V
Differential Output Voltage
Swing
R
= R
1000
1400
1800
mV
LOAD
SOURCE
P-P
MAX3754
MAX3755
MAX3754
MAX3755
118
78
150
100
150
100
182
122
182
122
Differential L-Port Input
Resistance
Ω
118
78
Differential L-Port Output
Resistance
Ω
Ω
Ω
Differential Input Resistance at
IN
78
78
100
100
122
Differential Output Resistance at
OUT
122
0.8
TTL Low Input Voltage
TTL High Input Voltage
TTL Input Current
V
V
2
0 ≤ TTL input voltages ≤ V
-50
50
µA
V
CC
LOCK Output Low Voltage
LOCK Output High Voltage
Differential Voltage across CF
I
I
= +1mA (sinking)
0.4
OL
= -100µA (sourcing)
2.4
V
OH
V
V
CC
3
IN to OUT , SEL_ = GND, CDREN = V
LIN(n) to LOUT(n+1) , LIN4 to OUT
CC
Data Propagation Delay
ns
1
2
_______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, C = 0.047µF, T = 0°C to +70°C, unless otherwise noted.
CC
F
A
Typical values are at V
= +3.3V, T = +25°C.)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Channel Select Delay to Data
Valid
SEL(n) to LOUT(n+1) , SEL4 to OUT
9
ns
Data Transition Time
20% to 80%
65
110
100
40
160
ps
10Hz ≤ f < 100Hz
100Hz ≤ f < 1MHz
1MHz ≤ f < 2.5GHz
Supply Noise Tolerance (Note 2)
mV
P-P
10
CDR Lock Time
530
µs
(Note 3)
OPERATION AT 2.125Gbps
Pattern = K28.7, CDREN = GND (Note 4)
Pattern = K28.7, CDREN = V
1.6
4.1
3
Random Jitter at OUT ,
L-Port Outputs
ps
RMS
CC
Pattern = CRPAT, CDREN = V
(Notes 5, 6)
CC
Pattern = K28.5+, CDREN = GND (Note 7)
29
60
Deterministic Jitter at OUT ,
L-Port Outputs
Pattern = K28.5+, CDREN = V
CC
19
28
50
ps
P-P
Pattern = RPAT, CDREN = V
Pattern = RPAT, CDREN = V
(Notes 6, 8, 9)
(Notes 6, 8, 9)
50
CC
CC
Total Jitter at OUT , LOUT_
105
ps
P-P
f = 85kHz sine wave
f = 1.27MHz sine wave
f = 10MHz sine wave
1.5
0.1
0.1
0.4
Sinusoidal Component of Jitter
-12
Pattern = CJTPAT
(Notes 6, 10)
UI
Tolerance (BER = 10
)
Deterministic Jitter Tolerance
CJTPAT (Note 10)
UI
UI
Total High-Frequency Jitter
Tolerance
Pattern = CJTPAT (Notes 6, 10, 11)
0.7
Jitter Transfer Bandwidth
Jitter Transfer Peaking
6
10
MHz
dB
(Note 12)
0.05
(Note 3)
OPERATION AT 1.0625Gbps
Pattern = K28.7, CDREN = GND (Note 4)
1.7
5.4
3.8
27
Random Jitter at OUT ,
L-Port Outputs
ps
RMS
Pattern = K28.7, CDREN = V
CC
Pattern = CRPAT, CDREN = V
(Notes 5, 6)
CC
Pattern = K28.5+, CDREN = GND (Note 7)
60
50
Deterministic Jitter at OUT ,
L-Port Outputs
ps
P-P
Pattern = K28.5+, CDREN = V
CC
19
Pattern = RPAT, CDREN = V
(Notes 6, 8, 9)
(Notes 6, 8, 9)
37
75
CC
CC
Total Jitter at OUT , LOUT_
Pattern = RPAT, CDREN = V
135
ps
P-P
f = 42.5kHz sine wave
f = 635kHz sine wave
f = 5MHz sine wave
1.5
0.1
0.1
Sinusoidal Component of Jitter
-12
Pattern = CJTPAT
(Notes 6, 10)
UI
Tolerance (BER = 10
)
_______________________________________________________________________________________
3
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, C = 0.047µF, T = 0°C to +70°C, unless otherwise noted.
CC
F
A
Typical values are at V
= +3.3V, T = +25°C.)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Deterministic Jitter Tolerance
CJTPAT (Note 10)
0.4
UI
Total High-Frequency Jitter
Tolerance
Pattern = CJTPAT (Notes 6, 10, 11)
(Note 12)
0.7
UI
Jitter Transfer Bandwidth
Jitter Transfer Peaking
3
5
MHz
dB
0.05
Note 1: Includes output currents.
Note 2: Meets jitter output specifications with noise applied.
Note 3: AC characteristics are guaranteed by design and characterization.
Note 4: K28.7 Pattern: 00 1111 1000
Note 5: Compliant Random Pattern in hex (CRPAT):
Pattern Sequence:
Repetitions:
3E AA 2A AA AA
3E AA A6 A5 A9
6
1
86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65
72 31 9A 95 AB
16
1
C1 6A AA 9A A6
1
-12
Note 6: Parameter measured with 0.40UI deterministic and 0.20UI random jitter (BER = 10
) applied to the input. All ports are
bypassed, SEL_ = TTL low. Jitter is in compliance with the inter-enclosure, Fibre Channel jitter tolerance (at compliance
point α ) and jitter output (at compliance point α ) specifications (FC-PI rev 10.0). Output jitter is specified as an output
R
T
total given a non-zero jitter input.
Note 7: K28.5 Pattern: 00 1111 1010 11 0000 0101
Note 8: Random Pattern in Hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65
Note 9: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 ✕ (bit-rate) by a
4th-order Bessel-Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the bit error rate
-12
exceeds 10 . TJ can be estimated as TJ = DJ + (14 ✕ RJ). DJ is deterministic jitter. RJ is one sigma distribution (RMS) of
random jitter.
Note 10:Compliant Jitter Tolerance Pattern in Hex (CJTPAT):
Pattern Sequence:
3E AA 2A AA AA
3E AA A6 A5 A9
Repetitions:
6
1
87 1E 38 71 E3
87 1E 38 70 BC 78 F4 AA AA AA
AA AA AA AA AA
AA A1 55 55 E3 87 1E 38 71 E1
AB 9C 96 86 E6
41
1
12
1
1
C1 6A AA 9A A6
1
Note 11:Parameter measured with 0.1UI sinusoidal jitter at 10MHz for 2.125Gbps data rate, or 5MHz for 1.0625Gbps.
Note 12:Simulation shows peaking of 0.01dBm max. Characterization results limited by test equipment.
4
_______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Typical Operating Characteristics
(V
= +3.3V, C = 0.047µF, T = +25°C, unless otherwise noted.)
F A
CC
OUTPUT EYE DIAGRAM AT OUT
(1.0625Gbps CRPAT, CDR ENABLED)
OUTPUT EYE DIAGRAM AT OUT
(2.125Gbps CRPAT, CDR ENABLED)
SUPPLY CURRENT vs. TEMPERTURE
(MAX3754)
340
320
300
280
260
240
220
200
CDR ENABLED
INPUT =
INPUT =
200mV/
div
400mV
200mV/
div
400mV
P-P
DJ = 0.4UI
RJ = 0.2UI
P-P
DJ = 0.4UI
RJ = 0.2UI
CDR DISABLED
100ps/div
200ps/div
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
OUTPUT JITTER BATHTUB PLOT
(2.125Gbps)
OUTPUT JITTER BATHTUB PLOT
(1.0625Gbps)
1
1
-1
-1
10
10
10
10
10
10
10
10
10
10
2.125Gbps CRPAT AT INPUT
(DJ = 0.4UI, RJ = 0.2UI)
-2
-2
-3
-4
-5
-6
-7
-8
-9
10
-3
10
-4
10
1.0625Gbps CRPAT AT INPUT
(DJ = 0.4UI, RJ = 0.2UI)
-5
10
-6
10
-7
10
-8
10
-9
10
-10
-10
-11
-12
10
10
10
10
-11
10
-12
10
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
DATA SAMPLING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
DATA SAMPLING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
JITTER TOLERANCE
1.0625Gbps
JITTER TOLERANCE
2.125Gbps
10
1
10
1
CJTPAT
DJ = 0.4UI
RJ = 0.2UI
CJTPAT
DJ = 0.4UI
RJ = 0.2UI
FIBRE CHANNEL
MASK
FIBRE CHANNEL
MASK
0.1
0.1
0.01
0.01
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
_______________________________________________________________________________________
5
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Pin Description
PIN
NAME
DESCRIPTION
1, 4, 7, 8, 11, 26, 29, 30,
33, 36, 39, 42, 43, 46
GND
Electrical Ground
2
LIN1-
LIN1+
Inverted Data Input for L-Port 1
Noninverted Data Input for L-Port 1
Inverted Data Output for L-Port 1
3
5
LOUT1-
6
LOUT1+ Noninverted Data Output for L-Port 1
9
IN-
IN+
Inverted Data Input
10
Noninverted Data Input
12
CLKEN
Clock Enable. A TTL high level enables clock output at L-Port 1.
Supply Voltage
13, 16, 21, 24
V
CC
14
15
17
CF+
CF-
CDR Filter Capacitor Positive Connection. C = 0.047µF.
F
CDR Filter Capacitor Negative Connection. C = 0.047µF.
F
SEL1
Select 1. A TTL low on SEL1 selects data from IN. TTL high on SEL1 selects data from LIN1.
Select 2. A TTL low on SEL2 selects data from the previous port bypass circuit. A TTL high
on SEL2 selects data from LIN2.
18
19
20
22
23
25
SEL2
SEL3
Select 3. A TTL low on SEL3 selects data from the previous port bypass circuit. A TTL high
on SEL3 selects data from LIN3.
Select 4. A TTL low on SEL4 selects data from the previous port bypass circuit. A TTL high
on SEL4 selects data from LIN4.
SEL4
CDR Enable Input (TTL). A high input enables the CDR for data recovery. A low input
disables the CDR (no data recovery).
CDREN
RATESEL
LOCK
Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps
operation.
Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequency-
locked. The output of the LOCK pin may chatter when large jitter is applied to the input.
27
28
31
32
34
35
37
38
40
41
44
45
47
48
OUT+
OUT-
Noninverted Data Output
Inverted Data Output
LIN4-
Inverted Data Input for L-Port 4
Noninverted Data Input for L-Port 4
Inverted Data Output for L-Port 4
LIN4+
LOUT4-
LOUT4+ Noninverted Data Output for L-Port 4
LIN3-
LIN3+
Inverted Data Input for L-Port 3
Noninverted Data Input for L-Port 3
Inverted Data Output for L-Port 3
LOUT3-
LOUT3+ Noninverted Data Output for L-Port 3
LIN2-
LIN2+
Inverted Data Input for L-Port 2
Noninverted Data Input for L-Port 2
Inverted Data Output for L-Port 2
LOUT2-
LOUT2+ Noninverted Data Output for L-Port 2
Exposed The exposed pad must be soldered to the circuit board ground for proper thermal
EP
Pad
performance.
6
_______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
0.047µF
CF+
CF-
RATESEL
LOCK
Q
D
IN+
IN-
PHASE/FREQ
DETECTOR
LOOP
FILTER
100Ω
VCO
1
0
CDREN
CLKEN
÷2
1
0
0
1
0
1
0
1
0
1
0
1
OUT+
OUT-
100Ω
OPTIONAL
100Ω OR 150Ω TERMINATION
FOR LOUT AND LIN
Figure 1. MAX3754/MAX3755 Functional Diagram
The input buffer drives the CDR circuit, as well as one
input of a 2:1 multiplexer. A TTL high on CDREN
enables the CDR and connects the CDR data output to
the port bypass circuits. The recovered clock signal is
available for test purposes at LOUT1 when CLKEN is
asserted high. A TTL low on CDREN disables the CDR
and connects the output of the input buffer directly to
the port bypass circuits. A RATESEL pin is included to
switch the CDR between data rates. The VCO output
has a divide-by-2 block that is switched into the PLL
when RATESEL is TTL low for 1.0625Gbps operation
(see Figure 1).
Detailed Description
The MAX3754/MAX3755 quad port bypass circuits
(PBCs) consist of an input buffer, a rate-selectable
clock and data recovery (CDR) circuit (for optional jitter
attenuation), four serially connected port bypass cir-
cuits, and an output buffer (Figure 1). The circuit
design is optimized for both 1.0625Gbps and
2.125Gbps operation at 3.3V.
Input Buffer
The input buffer provides line termination and level con-
version. It accepts a differential input voltage of 200mV
to 2200mV at IN . Internal resistors terminate the inputs
to 100Ω differentially eliminating the need for external
resistors.
Phase and Frequency Detector
The frequency difference between the VCO clock and
the received data is derived by sampling the in-phase
and quadrature VCO outputs on the edges of the input
data signal. The frequency detector drives the VCO
until the frequency difference is reduced to zero. Once
frequency acquisition is complete, the phase detector
produces a voltage proportional to the phase differ-
ence between the incoming data and the internal clock.
The PLL drives this error voltage to zero, aligning the
recovered clock to the center of the incoming eye.
Clock and Data Recovery
The purpose of the CDR is to improve jitter transfer per-
formance by attenuating jitter that may be present in
the input data. The CDR can recover 1.0625Gpbs or
2.125Gbps data signals that are corrupted by up to
-12
0.7UI of high-frequency jitter (BER = 10
). When jitter
attenuation is not needed, the CDR may be disabled in
order to save power.
_______________________________________________________________________________________
7
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Loop Filter, VCO, and Latch
Output Buffer
The output signal of the last PBC drives the differential
high-power output buffer. The output buffer drives the
output port (OUT ). Internal resistors terminate each
The phase detector and frequency detector outputs are
summed into a loop filter. An external capacitor
(between CF+ and CF-) is required to set the PLL
damping factor. The fully integrated VCO contains an
internal current reference and filter circuitry to minimize
output with 50Ω to V
(100Ω differentially), eliminating
CC
the need for external termination resistors. The output
buffer produces a differential peak-to-peak output volt-
age of 1V to 1.8V when driving a differential load.
the influence of V
noise. The VCO creates a clock
CC
output with frequency proportional to the control volt-
age applied by the loop filter. Data recovery is accom-
plished by using the recovered clock signal to latch the
incoming data to the CML output buffers, significantly
reducing output jitter.
Applications Information
The MAX3754/MAX3755 quad-PBC is designed for
hard-disk array applications using the Fibre Channel
Arbitrated Loop network protocol. In applications where
data storage reliability is critical, it may be desirable to
create a disk array where the data is stored redundant-
ly on more than one physical drive.
LOCK Output
An active high LOCK output monitor derived from the
frequency detector indicates that the PLL is frequency
locked onto the input data. Without input data, the
LOCK signal may settle at TTL High or TTL Low. The
use of a low-pass RC filter is recommended to reduce
the effects of chatter that could be caused by a high
input jitter content.
The Fibre Channel Arbitrated Loop protocol enables
multiple physical drives to be connected in a loop
topology. Each physical drive is connected to the Fibre
Channel loop through an L-port that may be individually
addressed and controlled to create an array of logical
drives. Data is transmitted over the loop as an encoded
serial bit stream. Using the Fibre Channel Arbitrated
Loop protocol, the configuration of the disk array can
be rearranged under software control to achieve
desired objectives (such as data reliability or fast
access).
RATESEL Input
The RATESEL input is used to select between input
data rates of 2.125Gbps and 1.0625Gbps. This func-
tion allows the repeater to sample data at the correct
data rate by selecting an optional a divide-by-2 net-
work. RATESEL selects between the VCO tuned fre-
quency and half that frequency, allowing maximum
jitter tolerance at both data rates. The loop bandwidth
of the repeater scales with the selected frequency; i.e.,
the loop-bandwidth at an input rate of 1.0625Gbps is
half that at the input rate of 2.125Gbps.
The port bypass circuit allows any L-port to be enabled
(connected to the loop) or bypassed (disconnected
from the loop) while the loop is operating. This enables
hot swapping of physical drives (inserting or removing
physical drives while the loop is operating) so that dri-
ves may be replaced with minimal disruption to the disk
array system. Figure 2 shows a disk array.
Port Bypass Circuits
The output of the 2:1 input multiplexer drives a cascad-
ed series of four PBCs. Each PBC consists of a differ-
ential output buffer, a differential input buffer, and a 2:1
multiplexer. The multiplexer select input (SEL_) controls
whether a port is included in the loop. A TTL low on a
multiplexer select pin routes the data signal from the
previous stage to the multiplexer output (port bypass
mode). A TTL high on the multiplexer select pin routes
the data signal from the input buffer to the multiplexer
output (port enable mode). The output of the last PBC
drives the output buffer.
Filter Capacitor Requirements
The MAX3754/MAX3755 phase lock loop’s (PLL) filter
capacitor is required to be supplied in a port bypass
design. This capacitor sets the damping factor of the
device. It also determines how fast the PLL can acquire
initial lock. This device is specified and tested with the
recommended filter capacitor value of 0.047µF that lim-
its transfer peaking.
Input/Output Structures
Figures 3 and 4 show models for the MAX3754/
MAX3755 inputs and outputs, modeling package para-
sitics, and ESD diodes.
The MAX3754 has 150Ω differential termination on the
inputs and 75Ω single-ended terminations to V
on
CC
the outputs (see Input/Output Structures for specifics)
of the L-ports to match Fibre Channel Arbitrated Loop
specifications. The MAX3755 is terminated with 100Ω
and 50Ω, respectively. Testing a MAX3754 using stan-
dard 50Ω test equipment requires an impedance
matching network
Cascading Port Bypass Circuits
Two or more MAX3754/MAX3755 quad-PBCs can be
cascaded by directly connecting the OUT pins of one
8
_______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
MAX377x
Figure 2. Disk Array Implemented with Port Bypass Circuits
_______________________________________________________________________________________
9
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
PACKAGE
PARASITICS
V
CC
DIE
ESD
STRUCTURES
1.2kΩ
2.2nH
0.4pF
0.2pF
0.2pF
2.2nH
0.4pF
50Ω
*(75Ω)
50Ω
*(75Ω)
V
- 0.45V
CC
*MAX3754 LIN_ INPUTS
Figure 3. MAX3754/MAX3755 Input Structure
PACKAGE
PARASITICS
DIE
V
CC
quad-PBC to the IN pins of the next quad-PBC. See
Typical Operating Circuit.
ESD
STRUCTURES
50Ω
*(75Ω)
50Ω
*(75Ω)
Layout Considerations
For best performance, carefully lay out the PC board
using high-frequency techniques. Filter voltage sup-
plies, keep ground connections short with multiple vias
where possible. Use controlled impedance transmis-
sion lines to interface with the MAX3754/MAX3755
high-speed inputs and outputs. Power-supply decou-
2.2nH
OUT+
OUT-
0.4pF
2.2nH
0.4pF
0.2pF
0.2pF
pling capacitors should be placed very close to V
CC
pins. Isolate the input signals from the output signals as
much as possible.
*MAX3754 LOUT_ OUTPUTS
Figure 4. MAX3754/MAX3755 Output Structure
10 ______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Typical Operating Circuit
DISK
DRIVE
DISK
DRIVE
DISK
DRIVE
DISK
DRIVE
L_PORT n
L_PORT n+1
L_PORT n+4
L_PORT n+5
IN OUT SEL
IN OUT SEL
IN OUT SEL
IN OUT SEL
V
CC
V
CC
V
V
CC
CC
V
CDREN
V
CDREN
CC
CC
GND
IN+
LOCK
OUT+
GND
IN+
LOCK
OUT+
Z = 50Ω
0
MAX3754
MAX3755
MAX3754
MAX3755
IN-
OUT-
IN-
OUT-
Z = 50Ω
0
CF+
CF-
CLKEN
RATESEL
CF+
CF-
CLKEN
RATESEL
C
C
F
F
0.047µF
0.047µF
IN OUT SEL
IN OUT SEL
IN OUT SEL
IN OUT SEL
L_PORT n+2
L_PORT n+3
L_PORT n+6
L_PORT n+7
DISK
DRIVE
DISK
DRIVE
DISK
DRIVE
DISK
DRIVE
NOTE: ALL HIGH-SPEED INPUTS AND OUTPUTS (IN , OUT , LIN , AND LOUT ) SHOULD BE CONNECTED USING CONTROLLED-
IMPEDANCE TRANSMISSION LINES. AC-COUPLING MAY ALSO BE REQUIRED. ALL CAPACITORS ARE 0.1µF UNLESS OTHERWISE INDICATED.
FIGURE SHOWS 1.0625Gbps OPERATION. FOR 2.125Gbps OPERATION, CONNECT RATESEL TO V
.
CC
______________________________________________________________________________________ 11
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
12 ______________________________________________________________________________________
Dual-Rate, 1Gbps/2Gbps Fibre Channel
Quad-Port Bypass ICs with Repeater
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明