MAX3780 [MAXIM]
Quad 2.5Gbps Cable Transceiver ; 四2.5Gbps的电缆收发器
| 型号： | MAX3780 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad 2.5Gbps Cable Transceiver
|
| 文件： | 总19页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2247; Rev 0; 10/01
Quad 2.5Gbps Cable Transceiver
General Description
Features
The MAX3780 cable transceiver provides a bidirectional
interface of four 2.5Gbps channels over low-cost copper
cable or external fiber-optic interface. The transmitter
section accepts eight channels of input at 1.25Gbps. An
integrated 4-bit FIFO allows retiming of the transmit data
to a clean local reference clock. The channels are multi-
plexed (2:1) into four outputs operating at 2.5Gbps. Pre-
emphasis and equalization provide compensation for
losses in low-cost cables up to 3m. The receiver recov-
ers the clock and demultiplexes (1:2) the 2.5Gbps chan-
nels into eight 1.25Gbps outputs. Fully integrated
phase-locked loops and delay-locked loops recover
clock and data from the serial data inputs.
o Quad 2:1 Channel Serialization
o Quad 1:2 Channel Deserialization
o 3m Link Distance with Low-Cost Copper Cable
o Better than 10-16 BER Performance
o 10Gbps Aggregate Parallel Interface
o System Loopback
o 1.25Gbps LVDS Synchronous Interface
o 2.5Gbps CML Serial Cable Interface
o PLL Lock Detect Signal
The transceiver IC is available in a compact 100-pin
TQFP package with exposed-ground pad and con-
sumes 2.2W.
o Selectable Cable Pre-Emphasis
o Fixed Receive Equalization
Applications
Ordering Information
Gigabit Ethernet Cable Backplane Concentration
PART
TEMP. RANGE
PIN-PACKAGE
System Interconnects Using Low-Cost Copper
Cable
MAX3780CCQ
0°C to +70°C
100 TQFP-EP*
*Exposed pad
System Interconnects Using Parallel Optics
Typical Operating Circuit
0.1µF
CMOS ASIC
625MHz
TCLK
8B/10B
CODING
TDAT[1:8]
8
1.25Gbps
LVDS
8B/10B
TX[1:4]
DECODING
MAX3780
CABLE TRANSCEIVER
625MHz
8
RCLK
RECEIVER
DESKEW
RDAT[1:8]
CHANNEL
IDENTITY
+3.3V
2.5Gbps CML
10kΩ
LOCK
RESET
LOOPEN
TRIEN
EQ1
RX[1:4]
EQ2
GND
VCC6 VCC5 TXFIL
REFCLK
RXFIL VCC1 VCC2
VCC3
VCC4
125MHz
REFERENCE
CLOCK
0.1µF
50Ω
0.1µF
PECL
BUFFER
50Ω
+3.3V
SUPPLY FILTER NETWORK
VCC6 - 2V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad 2.5Gbps Cable Transceiver
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V 1, V 2, V 3, V 4,
TTL Input or Output Voltage.......................-0.5V to (V
PECL Input Voltage ....................................-0.5V to (V
TMPSENS, TXFIL, RXFIL Voltage ...............-0.5V to (V
+ 0.5V)
+ 0.5V)
+ 0.5V)
CC
CC
CC
CC
CC
CC
CC
V
CC
5, V 6, VCCTEMP) ....................................-0.5V to +4.0V
CC
Continuous CML Output Current ......................-10mA to +25mA
Momentary CML Output Voltage
Operating Ambient Temperature Range ................0°C to +70°C
Operating Junction Temperature Range..............0°C to +150°C
Storage Ambient Temperature Range...............-55C° to +100°C
(duration < 1 minute, +25°C).......................0V to (V
CML Input Voltage......................................-0.5V to (V
LVDS Input and Output Voltage.................-0.5V to (V
+ 0.5V)
+ 0.5V)
+ 0.5V)
CC
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, T = 0°C to +70°C, unless otherwise
CC
A
noted. Typical values are at V
= +3.3V and T = +25°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
Referenced to GND
MIN
3.0
0
TYP
3.3
25
MAX
3.6
UNITS
V
Supply Voltage
V
CC
Operating Ambient Temperature
Power Dissipation
T
70
°C
A
1.6
533
2.2
665
3.3
W
Supply Current
I
916
mA
CC
TTL INPUTS AND OUTPUTS
TTL Input High Voltage
TTL Input Low Voltage
TTL Input High Current
TTL Input Low Current
TTL Output High Voltage
TTL Output Low Voltage
PECL INPUTS
V
2.0
2.4
V
V
IH
V
0.8
IL
I
V
V
= 2.0V
= 0V
-250
-500
µA
µA
V
IH
IH
IL
I
IL
V
Open collector, R
= 10kΩ
OH
LOAD
V
R
= 10kΩ
LOAD
0.4
V
OL
PECL Input High Voltage
PECL Input Low Voltage
PECL Input Current
Referenced to V
Referenced to V
6
6
-1165
-1810
-10
-880
-1475
+10
mV
mV
µA
CC
CC
CML INPUTS (Note 1, Figure 5)
Total differential signal required to achieve
error rate
Differential Input Voltage Range
200
800
mVp-p
V
Single-Ended Input Voltage
Range
Single-ended range of a differential input
signal
V
-
V
+
CC
CC
0.5
0.2
Common-Mode Voltage
Input Impedance
Inputs open or AC-coupled
Differential
V
V
CC
R
85
100
115
800
Ω
IN
CML OUTPUTS (Note 1, Figure 4)
0m channel, EQ1 = 1, EQ2 = 1
0.5m channel, EQ1 = 1, EQ2 = 1
1m channel, EQ1 = 1, EQ2 = 0
3m channel, EQ1 = 0, EQ2 = 1
400
600
540
500
400
Differential Output Voltage
(Measured at the End of the
Channel)
mVp-p
(Note 3)
2
_______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, T = 0°C to +70°C, unless otherwise
CC
A
noted. Typical values are at V
= +3.3V and T = +25°C.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.3
-
CC
Output Common-Mode Voltage
V
Differential Output Impedance
LVDS INPUTS
R
85
100
115
Ω
OUT
Input Voltage Range
V
|V
|V
| < 925mV
| < 925mV
0
2000
500
mV
mV
Ω
I
GPD
Differential Input Voltage
Differential Input Impedance
Input Common-Mode Current
LVDS OUTPUTS (Note 2)
Output High Voltage
|V
ID
|
150
85
GPD
R
100
-80
115
IN
V
= 1.2V, inputs tied together
-200
µA
OS
V
1.475
400
25
V
V
OH
Output Low Voltage
V
0.925
250
OL
Differential Output Voltage
|V
OD
|
mV
Change in Magnitude of
Differential Output Voltage for
Complementary States
∆|V
|
mV
V
OD
Output Offset Voltage
V
1.125
1.275
25
OS
Change in Magnitude of Output
Offset Voltage for
∆|V
|
mV
OS
Complementary States
Differential Output Impedance
Short-Circuit Current
R
80
5
100
10
120
40
Ω
OD
Short to supply or ground
mA
kΩ
Impedance When Disabled
TRIEN = 0
Note 1: CML differential signal amplitudes are specified as the total signal across the load (V+ - V-).
Note 2: LVDS output signal amplitudes are specified according to IEEE 1596.3-1996.
Note 3: Differential output voltage is production tested for all EQ1 and EQ2 settings. Typical values are the differential peak-to-peak
eye opening at the end of the cable.
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, T = 0°C to +70°C, REFCLK =
CC
A
125MHz, unless otherwise noted. Typical values are at V
= +3.3V and T = +25°C.) (Note 4)
CC
A
PARAMETER
TRANSMITTER PARAMETERS
TCLK Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
625
4.5
MHz
ns
Transmitter Latency
LVDS INPUTS
From TDAT to TX
Accumulated Phase Error at
TCLK
Relative to REFCLK
±±.ꢀ
ns
_______________________________________________________________________________________
3
Quad 2.5Gbps Cable Transceiver
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω 1ꢀ, CML differential load = 100Ω 1ꢀ, T = 0°C to +70°C, REFCLK =
CC
A
125MHz, unless otherwise noted. Typical values are at V
= +3.3V and T = +25°C.) (Note 4)
CC
A
PARAMETER
Setup Time
SYMBOL
CONDITIONS
MIN
1±±
1±±
TYP
MAX
UNITS
ps
t
Figure 1
SU
Hold Time
t
Figure 1
ps
H
CML OUTPUTS
Deterministic Jitter
(Note 5)
15
22
25
66
ps
ps
p-p
Wideband jitter with ±1 pattern
(Note 7)
Random Jitter
Edge Speed
p-p
2±% to ꢀ±%, measured at transmitter output,
(EQ1 = 1, EQ2 = 1)
t , t
r
14±
ps
f
RECEIVER PARAMETERS
Clock Frequency
625
525
4.3
25
MHz
µs
PLL Lock Time
After valid data applied
From RX to RDAT
(Note 7)
Receiver Latency
ns
Jitter Generation
66
ps
p-p
LVDS OUTPUTS
Clock Duty-Cycle Distortion
T
Variation of 5±% crossing from ideal time
-32
+32
5±
ps
PW
Measured with K2ꢀ.5 pattern at RDAT_
outputs
Deterministic Jitter
15
ps
p-p
Edge Speed
t , t
2±% to ꢀ±%
Figure 2
16±
4±±
25±
532
ps
ps
r
f
Clock-to-Data Delay
CML INPUTS
τ
26ꢀ
22±
CLK-Q
High-Frequency Jitter Tolerance
(Note 6)
3±±
ps
p-p
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Deterministic jitter (DJ) and differential output signal measured with K28.5 at TX_ pins.
Note 6: High-frequency jitter comprised of 164ps
of deterministic jitter, 1.6ps
random jitter, and the remaining as 5MHz sinu-
p-p
RMS
soidal jitter.
Note 7: Peak-to-peak random jitter is 16.4 ✕ RMS jitter for a jitter probability of 10-16
.
RCLK
τ
CLK-Q
τ
CLK-Q
RDAT_
t
= 100ps
H
300mV
MINIMUM INPUT
1000mVp-p
MAXIMUM
INPUT
Figure 2. Definition of Clock-to-Q Delay
t
= 100ps
SU
CENTER OF RISING OR
FALLING CLOCK EDGE
Figure 1. LVDS Receiver Input Eye Mask
4
_______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
TRANSMITTER JITTER TRANSFER
(REFCLK TO TX_)
RECEIVER JITTER TRANSFER
(RX4 TO RCLK)
TMPSENS VOLTAGE VS. TEMPERATURE
450
5
0
10
0
430
410
390
370
350
330
310
290
270
250
-5
-10
-15
-20
-10
-20
-30
-25
-30
-40
-50
-35
-40
10
1
10
100
1000
10,000
0
25
50
75
100
125
150
1
1000
FREQUENCY (kHz)
10,000
100
FREQUENCY (kHz)
JUNCTION TEMPERATURE (°C)
R TO T VCO PULLING
TRANSMITTER POWER-SUPPLY REJECTION
X
X
RECEIVER POWER-SUPPLY REJECTION
2.0
1.5
40
35
30
25
20
15
10
5
0.5
0.4
0.3
1.0
0.5
0.2
0.1
0
0
0
0
50
100
150
200
250
1
10
100
1000
1
10
100
1000
10,000
VCO FREQUENCY DIFFERENCE (ppm)
POWER-SUPPLY NOISE FREQUENCY (kHz)
FREQUENCY (kHz)
CML INPUT RETURN LOSS
CML OUTPUT RETURN LOSS
T TO R VCO PULLING
X
X
0
-5
3.5
0
-5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
-15
-20
-25
-30
-10
-15
-20
-25
5000
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
0
50
100
150
200
250
FREQUENCY (MHz)
FREQUENCY (MHz)
VCO FREQUENCY DIFFERENCE (ppm)
_______________________________________________________________________________________
5
Quad 2.5Gbps Cable Transceiver
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
EYE DIAGRAM AFTER 3m CABLE
RX4 JITTER TOLERANCE VS.
INPUT AMPLITUDE
RX4 JITTER TOLERANCE
UNCOMPENSATED (EQ1 = 1, EQ2 = 1)
MAX3780 toc12
100
0.45
INPUT = 80mVp-p 210 - 1
PRBS WITH 0.4UI OF
DETERMINISTIC JITTER
PATTERN = 27 - 1 PRBS
0.40
0.35
10
INPUT = 2 - 1 PRBS WITH
10
1
0.30
0.25
ADDITIONAL 0.4UI OF
DETERMINISTIC JITTER
64mV/
div
0.20
0.15
0.10
0.05
0
0.1
10
100
1000
10,000
10
100
1000
70ps/div
JITTER FREQUENCY (kHz)
DIFFERENTIAL INPUT AMPLITUDE (mVp-p)
EYE DIAGRAM AFTER 3m CABLE
COMPENSATED (EQ1 = 0, EQ2 = 1)
EYE DIAGRAM AFTER 0.5m CABLE
EYE DIAGRAM AFTER 1.0m CABLE
(EQ1 = 1, EQ2 = 0)
(EQ1 = 1, EQ2 = 1)
MAX3780 toc13
MAX3780 toc15
MAX3780 toc14
PATTERN = 27 - 1 PRBS
PATTERN = 27 - 1 PRBS
PATTERN = 27 - 1 PRBS
64mV/
div
64mV/
div
64mV/
div
70ps/div
70ps/div
70ps/div
6
_______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Pin Description
PIN
NAME
GND
FUNCTION
1, 12, 25, 26, 2ꢀ, 31,
45, 5±, 51, 55, 63, 71,
75, 76, ꢀ±, 1±±
Supply Ground
2, 11, 24
VCC1
+3.3V Supply for Receiver, LVDS Data and Clock Outputs, and Digital Receiver Functions
Positive Parallel-Data Outputs, LVDS
3, 5, 7, 9, 13, 15, 17,
19
RDAT1+ to
RDATꢀ+
4, 6, ꢀ, 1±, 14, 16, 1ꢀ,
2±
RDAT1- to
RDATꢀ-
Negative Parallel-Data Outputs, LVDS
Positive 625MHz Recovered Clock, LVDS. Parallel-data outputs are clocked on both the
rising and falling edge of the clock.
21
22
RCLK+
RCLK-
Negative 625MHz Recovered Clock, LVDS. Parallel-data outputs are clocked on both the
rising and falling edge of the clock.
Three-State Enable, TTL Input. Setting TRIEN low forces the LVDS outputs into a high-
impedance state and the LOCK pin to a logical ‘1’. CML outputs are not affected by
TRIEN. Internally pulled high through 15kΩ.
23
27
TRIEN
Lock Status Indicator, TTL Output. This output goes high when the transmit PLL, receiver
PLL, and receiver DLLs are in lock. Because this output is open-collector TTL, it requires
LOCK
an external 1±kΩ pullup resistor to V . The LOCK pins from multiple MAX37ꢀ±s can be
CC
connected in parallel to form a single LOCK signal.
29
3±
RXFIL
VCC2
VCC3
Receiver Loop Filter Connection. Connect a ±.1µF capacitor between RXFIL and VCC2.
+3.3V Supply for Receiver VCO, Analog Receiver Functions, and External Loop Filter
Connection
32, 35, 3ꢀ, 41, 44
33, 36, 39, 42
+3.3V Supply for CML Inputs
RX4- to
RX1-
Negative Serial Input, CML
RX4+ to
RX1+
34, 37, 4±, 43
46, 79, 99
Positive Serial Input, CML
VCC6
+3.3V Supply for LVDS Inputs, FIFO, Multiplexer, and PECL REFCLK Input
Loopback Enable, TTL input. Force low to enable system loopback. Internally pulled high
through 15kΩ.
47
4ꢀ
LOOPEN
+3.3V Supply for TMPSENS. Connect to ground to disable the temperature-sensing
circuit.
VCCTEMP
Junction Temperature Sensor. Analog output corresponding to the junction temperature
of the die. Leave open for normal use.
49
52
53
TMPSENS
PTPIN
Reserved for Maxim Use. Connect to ground for normal operation.
Transmit Equalizer Control Input #2, TTL. Refer to Table 1 for setting transmitter
precompensation. Internally pulled high.
EQ2
Transmit Equalizer Control Input #1, TTL. Refer to Table 1 for setting transmitter
precompensation. Internally pulled high.
54
EQ1
56, 59, 62, 64, 67, 7±
VCC4
+3.3V Supply for CML Outputs
_______________________________________________________________________________________
7
Quad 2.5Gbps Cable Transceiver
Pin Description (continued)
PIN
NAME
FUNCTION
TX4- to
TX1-
57, 60, 65, 68
Negative Serial Output, CML
Positive Serial Output, CML
TX4+ to
TX1+
58, 61, 66, 69
Reset Input, TTL. Connect low for >80ns to reset FIFO and receiver components.
Internally pulled high through 15kΩ.
72
73
74
RESET
TXFIL
VCC5
Transmitter Loop Filter Connection. Connect a 0.1µF capacitor between TXFIL and VCC5.
+3.3V Supply for Transmitter VCO, Analog Transmitter Functions, and External Loop
Filter Connection
77
78
81
82
REFCLK+
REFCLK-
TCLK+
Positive Reference Clock Input, PECL
Negative Reference Clock Input, PECL
Positive Clock Input for Transmitter Input Data, LVDS
Negative Clock Input for Transmitter Input Data, LVDS
TCLK-
83, 85, 87, 89, 91, 93,
95, 97
TDAT1+ to
TDAT8+
Positive Parallel Data Inputs, LVDS
Negative Parallel Data Inputs, LVDS
84, 86, 88, 90, 92, 94,
96, 98
TDAT1- to
TDAT8-
go into a high-impedance state when TRIEN is forced
Detailed Description
low. This simplifies system checks by allowing vectors
to be forced on the LVDS outputs. The LVDS outputs
also have short-circuit protection in case of shorts to
VCC or GND.
The MAX3780 cable transceiver uses four 2:1 muxes
and four 1:2 demuxes to simplify backplane routing.
The serial transceiver interface can either be a fiber
module or up to 3m of low-cost, twisted-pair copper
cable. This bidirectional interface provides low-voltage
differential signaling (LVDS) interfaces at the 1.25Gbps
parallel inputs and outputs. The serial data inputs and
outputs utilize current-mode logic (CML) structures. An
integrated PLL recovers the clock from the incoming
serial data, as well as retimes the received data.
PLL Clock Multiplier
The PLL clock multiplier uses the 125MHz reference
clock to synthesize 1.25GHz and 2.5GHz clocks used to
synchronize the transmitter functions. The reference clock
is also used to aid frequency acquisition in the receiver.
The 125MHz input signal at REFCLK requires a duty
cycle between 40ꢀ and 60ꢀ. To achieve proper jitter
performance and BER benchmarks, it is critical to use a
high-quality, low-jitter reference clock. See the Reference
Clock Requirements table for more information.
The serial interface uses both precompensation as well
as equalization to allow high-speed transmission
through up to 3m of copper cable while maintaining a
BER < 10-16. The compensation/equalization circuits
are optimized for short cables, 0.5m cables, 1m cables,
or 3m cables. TTL inputs are provided to select the
amount of precompensation.
Bit-Interleaved Multiplexer/Demultiplexer
The MAX3780 uses bit interleaving to multiplex the par-
allel data and bit deinterleaving to demultiplex the seri-
al data. After serial transmission, the channel
assignment of the parallel outputs is random for each
serial channel. In other words, there is a 50ꢀ chance
that RDAT1 = TDAT1 and RDAT2 = TDAT2 and a 50ꢀ
chance that RDAT1 = TDAT2 and RDAT2 = TDAT1.
Because the MAX3780 does not perform channel
assignment, other circuitry must handle this task.
LVDS Inputs and Outputs
The MAX3780 parallel interface includes eight differen-
tial data inputs at 1.25Gbps, one half-rate differential
clock input at 625MHz, eight differential data outputs at
1.25Gbps, and one half-rate differential clock output at
625MHz. All parallel inputs and outputs are LVDS com-
patible to minimize power dissipation, speed transition
time, and improve noise immunity. The LVDS outputs
8
_______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
TXFIL
REFCLK+
REFCLK-
TX_LOCK
(INTERNAL)
625MHz DDR
CLOCK
REFCLK
(INTERNAL)
PLL CLOCK
MULTIPLIER
TCLK+
TCLK-
MAX3780
CABLE TRANSCEIVER
2.5GHz
1.25GHz
FIFO
TDAT1+
TDAT1-
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
TX1+
TX1-
D
D
D
D
Q
Q
Q
Q
PRECOMP
TDAT2+
TDAT2-
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
TDAT3+
TDAT3-
TX2+
TX2-
LVDS
INPUTS
PRECOMP
PRECOMP
PRECOMP
TDAT4+
TDAT4-
CML
OUTPUTS
TDAT5+
TDAT5-
TX3+
TX3-
TDAT6+
TDAT6-
TDAT7+
TDAT7-
TX4+
TX4-
TDAT8+
TDAT8-
EQ2
EQ1
RESET
TRIEN
LOOPEN
RDAT1+
RDAT1-
Q
Q
D
D
0
1
DLL
PHASE
Q
Q
Q
Q
D
D
D
D
RX1+
RX1-
RECOVERY
EQ
EQ
EQ
RDAT2+
RDAT2-
RDAT3+
RDAT3-
Q
Q
D
D
0
1
DLL
PHASE
RECOVERY
RX2+
RX2-
RDAT4+
RDAT4-
CML
INPUTS
RDAT5+
RDAT5-
LVDS
Q
Q
D
D
0
1
OUTPUTS
DLL
PHASE
RECOVERY
RX3+
RX3-
RDAT6+
RDAT6-
RDAT7+
RDAT7-
Q
Q
D
D
0
1
RX4+
RX4-
EQ
K
RDAT8+
RDAT8-
2.5GHz
RCLK+
RCLK-
RXFIL
DIVIDE
BY 2
PLL CLOCK RECOVERY
REFCLK
1.25GHz
TMPSENS
VCCTEMP
TX_LOCK
1
0
RX_LOCK
LOCK
1
Figure 3. Functional Diagram
_______________________________________________________________________________________
9
Quad 2.5Gbps Cable Transceiver
ment, and the DLLs only serve as adjustable delay
lines to allow for different channels to have different
(static) phase relationships.
Table 1. Setting the CML Output
Precompensation
RECOMMENDED PRECOMPENSATION
CML Outputs with Precompensation
The serial outputs of the MAX3780 (TX1–TX4) are CML
compatible. These outputs offer the best combination
of low power dissipation, performance, and external
component count. AC-coupling capacitors should
always be used to provide immunity to common-mode
voltage mismatches. The CML output structure is
shown in Figure 4. For more information, refer to the
applications note HFAN 01.0 Introduction to LVDS,
PECL, and CML. Table 1 gives the amount of compen-
sation for different EQ1 and EQ2 settings.
EQ1
EQ2
CHANNEL
VALUE
Extended Range
3m Cable
30ꢀ
20ꢀ
10ꢀ
0
0
1
0
1
0
1m Cable
0.5m Cable or
Fiber Module
Off
1
1
VCC
The CML data outputs have adjustable precompensa-
tion to compensate for cable and PC board trace loss-
es. The cable and PC board traces have skin-effect
and dielectric losses that attenuate high frequencies
more than low frequencies. The precompensation FIR
filter does the inverse. It attenuates low frequencies
and boosts high frequencies. If precompensation is
chosen to match the channel attenuation, the data at
the end of the cable will be equalized.
50Ω
50Ω
TX_+
TX_-
CML Inputs with Equalization
The CML input structure, shown in Figure 5, provides
low power dissipation and excellent performance. The
CML inputs have integrated 50Ω termination resistors,
reducing the external component count required for
interfacing.
The CML inputs of the MAX3780 (RX1–RX4) provide
equalization to further compensate for cable losses.
The equalization circuit will typically add about 2dB of
boost at 2GHz.
GND
Figure 4. Simplified CML Output Structure
Lock Detection
The LOCK output indicates the state of both the trans-
mitter and receiver PLLs. For lock detect to be asserted
high, both the transmitter and receiver internal-lock
indicators must be high for 394µs. The internal lock sig-
nals go high once frequency lock has been achieved.
For LOCK to be asserted low, either the transmitter or
receiver internal-lock indicators must be low for a mini-
mum of 1053µs. LOCK is also asserted low when
RESET is forced low. LOCK will stay low for a minimum
of 394µs. For the lock detector to function properly,
there must be data transitions at the RX4 input and a
valid reference clock input. Note: The LOCK output is
not an accurate indicator of signal presence at the
receiver inputs. With no data input, the LOCK output
can be high, low, or toggling.
PLL Clock Recovery
The phase-locked loop recovers a synchronous clock
signal from the incoming serial data on RX4. This
recovered clock is then used to retime all four channels
of incoming serial data before demultiplexing. Phase
alignment on channels RX1, RX2, and RX3 is achieved
by using delay-locked loops. The typical loop band-
width of the PLL clock recovery circuit is 1.5MHz.
Delay-Locked Loop (DLL) Phase Recovery
The delay-locked loops in the RX1, RX2, and RX3
receive path are used to phase align the incoming data
to the clock generated by the PLL. Because all serial
channels originate from the same source and travel
down the same cable, it is assumed that the low-fre-
quency jitter on channel 4 is common to all channels.
This allows the PLL to maintain frequency/phase align-
10 ______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Temperature Sensor
To aid in evaluation of thermal performance, a tempera-
ture sensor is incorporated into the MAX3780. The tem-
VCC
perature sensor may be powered on or off regardless
of the state of the rest of the chip. The VCCTEMP pin
2kΩ
provides supply voltage for the temperature sensor cir-
cuit. The TMPSENS output is designed to output a volt-
age proportional to the die junction temperature (1mV
per Kelvin). The temperature of the die can be estimat-
ed as:
MAX3780
50Ω
50Ω
RX_+
RX_-
1°C
T(°C) ≈ V
(mV)×
−273°C
TEMPSENS
mV
Applications Information
BER Calculation
Digital transmission systems will always, given enough
time, have errors. This is due to the random nature of
both voltage noise and timing noise, or jitter. In today’s
high performance digital transmission systems, we
often try to measure bit error ratios (BERs) of fewer than
1 error every 10,000,000,000 bits (BER<10-10).
Measuring such low error rates can prove to be prob-
lematic, since even at high data rates, the testing time
required to obtain statistically significant results
becomes impractical. (For more information, refer to
HFTA-05.0 Statistical Confidence Levels for Calculating
Error Probability.)
GND
Figure 5. CML Input Structure
VCC
The MAX3780 serial interface operates at 2.5Gbps and
is designed to operate with a BER better than 10-16 (1
error every 10,000,000,000,000,000 bits). This will give,
on average, one error every 46 days on each 2.5Gbps
channel. It is practically impossible to directly test such
a low BER. For this reason, we turn to mathematics to
ensure that this incredible BER is met.
R
=
LOAD
10kΩ
MAX3780
100Ω
LOCK
The thermal noise in the MAX3780 serial channel is low
(<1mV
in the CML receiver). The dominant voltage
RMS
noise in the serial channel is due to crosstalk. The
remaining impairments are various types of timing jitter
due to clock nonidealities and data-dependant jitter. In
this section, all calculations will be done in the time
domain (similar to the draft technical report by ANSI
T11.2, Project 1230, Fibre Channel—Methodologies for
Jitter Specification) where timing jitter is applied direct-
ly and voltage noise is converted into an equivalent tim-
ing jitter. The equation relating timing jitter to error rate
is below:
Figure 6. LOCK Output Structure
RESET Input
Approximately 10ms or longer after power-up, the
RESET input should be asserted low. RESET must be
held low for a minimum of four reference clock cycles
for it to be properly asserted. RESET is used to reset
the lock state, FIFO clock logic, and delay-lock loops.
2
1UI= ΣDJ
+ α × ΣRJ
RMS
p−p
______________________________________________________________________________________ 11
Quad 2.5Gbps Cable Transceiver
Table 2. Summary of Jitter Parameters Contributing to the BER Calculation
DETERMINISTIC COMPONENTS
RANDOM COMPONENTS
TYPICAL WORST-CASE
(mUI (mUI
PARAMETER
TYPICAL
(mUIp-p)
WORST-CASE
(mUIp-p)
)
)
RMS
RMS
Reference Clock—Random
0.19
0.38
Reference Clock—Deterministic
Transmitter—Random
5
10
3.25
10
Transmitter—Oscillator Pulling
Transmitter—Supply Noise
Transmitter—Output Stage
Channel—Cable Losses
8.75
2.5
23.75
7.5
37.5
50
62.5
112.5
56
Channel—Crosstalk
28
Channel—Mismatched Load
Receiver—VCO Phase Noise
Receiver—Input-Referred Noise
Receiver—Sampling Offset
Receiver—Oscillator Pulling
Receiver—Supply Noise
12.5
25
3.75
1.25
10
2.5
187.5
7.5
387.5
15
6.25
345.5
18.75
718.5
TOTALS =
5.12
14.37
TYPICAL
127.8
~0
WORST-CASE
19.6
ALPHA =
BER =
-23
5.7 ✕ 10
Deterministic jitter and receiver sampling offset effec-
tively reduce the amount of time that the receiver can
sample without error. Errors occur at a rate determined
by α:
6-sigma margin. Many of the worst-case components
are uncorrelated variables that are taken to their indi-
vidual 6-sigma limits.
In summary, the predicted worst-case BER = 10-20. A
typical channel will operate error free.
1− ΣDJ
p−p
α =
All transmitter and channel jitter components are com-
pared to the jitter tolerance of the receiver by translat-
ing the components to equivalent phase error in the
receiver. Low-frequency jitter components are tracked
by the receive PLL, and therefore contribute little to the
phase error. High-frequency jitter components (beyond
the loop bandwidth of the receiver) are not tracked by
the receiver PLL and therefore directly translate to
phase error. The phase error transfer function is essen-
tially equivalent to the inverse of the jitter tolerance ver-
sus frequency with the high-frequency portion
normalized to unity.
2
ΣRJ
RMS
An α >16.4 corresponds to a BER < 10-16. Refer to
Maxim applications note HFAN-4.0.2 Converting
Between RMS and Peak-to-Peak Jitter at a Specified
BER.
For a discussion of deterministic jitter and random jitter
and the characteristics of each, refer to Maxim applica-
tions note HFAN-4.0.3 Jitter in Digital Communication
Systems, Part 1.
Table 2 shows the deterministic and random compo-
nents used in the BER calculation for the MAX3780.
Typical and worst-case numbers are presented. The
worst-case estimate represents a BER with greater than
12 ______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Reference Clock—Random
A maximum random jitter of 15ps for frequencies
less than 5kHz is stated as a requirement for the refer-
ence clock in the Reference Clock Requirements sec-
tion. Translating this to the phase error of the receiver
3) Output Stage
RMS
Finite bandwidth and pulse-width distortion in the
serial transmitter can cause deterministic jitter in the
serial data stream. Characterization and simulation
results tell us the deterministic jitter is typically
gives 75fs
(0.19mUI
) typical and 150fs
RMS RMS
RMS
) worst-case.
15ps
(37.5mUIp-p) and 25ps
(62.5mUIp-p)
p-p
p-p
worst-case.
(0.38mUI
RMS
Reference Clock—Deterministic
A maximum deterministic jitter of 20ps for frequen-
Channel—Deterministic
p-p
1) Cable Losses
cies greater than 5kHz is stated as a requirement for the
reference clock in the Reference Clock Requirements
section. Combining the low-pass jitter transfer of the
transmitter and the high-pass phase error transfer of the
receiver results in a bandpass transfer function. For
design margin, it is assumed that this deterministic jitter
is within the bandpass frequency range. The typical
The frequency-dependent skin-effect and dielectric
losses in the cable (and PC board traces) will cause
data-dependent jitter (also known as intersymbol
interference). Adjustable transmit precompensation
and fixed receiver boost is used to reduce the
cable-induced jitter. However, there will always be
some uncompensated jitter due to the cable and PC
board trace losses. Characterization and simulation
results tell us the deterministic jitter is typically
deterministic component is 2ps
(5mUIp-p) and the
p-p
(10mUIp-p).
worst-case entry is 4ps
p-p
20ps
(50mUIp-p) and 45ps
(112.5mUIp-p)
p-p
Transmitter—Random
p-p
worst-case.
This is the random jitter that results from the transmitter
VCO phase noise and is an AC parameter guaranteed
in the AC Electrical Characteristics table. Typical mea-
2) Crosstalk
The MAX3780 channel requirements allow for
crosstalk of up to 5ꢀ to be present at the RX inputs.
This is a peak-to-peak voltage measurement which
refers to 5ꢀ of the transmitter amplitude.
Characterization and simulation results tell us the
deterministic jitter due to crosstalk is typically
sured numbers are 1.3ps
(3.3mUI
RMS
) and the
RMS
RMS
worst-case specification is 4.0ps
(10mUI
).
RMS
Transmitter—Deterministic
1) Oscillator Pulling
The transmitter and receiver integrated LC oscilla-
tors when running at small frequency differences will
beat with each other at a rate equivalent to the fre-
quency difference between the oscillators. Typical
Operating Characteristic plot RX to TX VCO
PULLING shows the typical transmitter jitter versus
frequency difference. When referred to the phase
error transfer, the deterministic jitter is typically
11.2ps
(28mUIp-p) and 22.4ps
(56mUIp-p)
p-p
p-p
worst-case.
3) Mismatched Load Jitter
Incorrect impedances in PC board traces, connec-
tors, cables, and terminations can cause reflections
that can, in turn, cause deterministic jitter. These
effects are more pronounced on short cables (less
attenuation of the reflection) where timing margins
are highest. While measurements already account
for mistermination effects, we have allocated an
additional fixed budget for jitter induced by reflec-
tions. Characterization and simulation results tell us
the deterministic jitter due to load mismatch is typi-
3.5ps
(8.75mUIp-p) and 9.5ps
(23.75mUIp-p)
p-p
p-p
worst-case.
2) Supply Noise
Noise on the power supply will modulate the transmit
PLL output according to the typical transfer curve
shown in the Typical Operating Characteristic plot
TRANSMITTER POWER-SUPPLY REJECTION.
Combining this transfer function with the phase error
transfer of the receiver results in a band-pass char-
acteristic. At the peak of this band pass, the typical
transfer is 100fs/mV and the worst-case transfer is
300fs/mV. Making the worst-case assumption that all
the supply noise is at this peak with a value of 10mV
cally 5ps
(12.5mUIp-p) and 10ps
(25mUIp-p)
p-p
worst-case.
p-p
Receiver—Random
1) VCO Phase Noise
This is the random jitter that results from the receiver
VCO phase noise and is an AC parameter guaran-
teed in the AC Electrical Characteristics table. Typical
results in typically 1ps
(2.5mUIp-p) and worst-
p-p
measured numbers are 1.5ps
(3.75mUI
RMS
) and
RMS
RMS
RMS
(10mUI
case 3ps
(7.5mUIp-p).
p-p
the worst-case specification is 4ps
).
______________________________________________________________________________________ 13
Quad 2.5Gbps Cable Transceiver
2) Input-Referred Noise
terminate these outputs to ground. The parallel data
LVDS inputs (TCLK+, TCLK-, TDAT_+, TDAT_-) are
internally terminated with 100Ω differential input resis-
tance and therefore do not require external termination.
All electronic circuits generate random noise. The
input-referred noise voltage of the CML RX inputs is
< 0.5mV
. This will contribute <1ps
jitter. In
RMS
RMS
the BER calculation, it is assumed the jitter is typical-
ly 0.5ps (1.25mUI and 1ps
The LVDS inputs must be biased for proper operation.
DC-coupling LVDS outputs and inputs together pro-
vides sufficient biasing. When interfacing to laboratory
test equipment, AC-coupling cannot be used. A signal
source with DC offset must be used.
)
RMS
) worst-case.
RMS
RMS
(2.5mUI
RMS
Receiver—Deterministic
1) Sampling Offset
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground connec-
tions short, and use multiple vias where possible. Use
controlled-impedance 50Ω transmission lines to interface
with the MAX3780 high-speed inputs and outputs.
The peak-to-peak sampling offset in the receiver is
equal to 1UI minus the jitter tolerance minus the ran-
dom jitter of the receiver. Removal of the random jit-
ter is necessary since receiver VCO Phase Noise in
Table 2 accounts for this. For simplicity, the random
jitter portion will be assumed to be the typical mea-
sured value of 25ps
(62.5mUIp-p). Using the
Place power-supply decoupling as close to V
as
CC
p-p
numbers from the AC parameter electrical table, the
typical sampling offset is calculated to be
187.5mUIp-p and the worst-case is 387.5mUIp-p.
possible. To reduce feedthrough, take care to isolate
the input signals from the output signals.
Exposed-Pad (EP) Package
The exposed-pad 100-pin TQFP-EP incorporates fea-
tures that provide a very low thermal resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3780 and must be soldered to the circuit
board for proper thermal and electrical performance.
2) Oscillator Pulling
The transmitter and receiver integrated LC oscilla-
tors, when running at small frequency differences,
will beat with each other at a rate equivalent to the
frequency difference between the oscillators.
Typical Operating Characteristic plot TX to RX VCO
PULLING shows the typical receiver jitter versus fre-
quency difference. Typically the receiver oscillator
pulling jitter is 3ps
(7.5mUIp-p) and worst-case is
p-p
6ps
(15.0mUIp-p).
p-p
3) Supply Noise
Noise on the power supply will modulate the receive
PLL sampling point according to the typical transfer
curve shown in Typical Operating Characteristic plot
RECEIVER POWER-SUPPLY REJECTION. Using a
typical transfer of 250fs/mV and a worst-case trans-
fer of 750fs/mV with 10mV of supply noise results in
2.5ps
(6.25mUIp-p) and 7.5ps
(18.75mUIp-p)
p-p
p-p
respectively.
Low-Voltage Differential Signal (LVDS)
Inputs/Outputs
The MAX3780 has LVDS inputs and outputs for inter-
facing with high-speed digital circuitry. All LVDS inputs
and outputs are compatible with the IEEE-1596.3 LVDS
specification. This technology uses 250mV to 400mV
differential low-voltage amplitudes to achieve fast tran-
sition times, minimize power dissipation, and improve
noise immunity. For proper operation, the parallel clock
and data LVDS outputs (RCLK+, RCLK-, RDAT_+,
RDAT_-) require 100Ω differential DC terminations
between the inverting and noninverting outputs. Do not
14 ______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Channel Requirements
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
100
5.0
MAX
UNITS
Impedance
Differential
f = 1GHz, 3m channel
Ω
4.0
1.5
1.0
6.0
3.2
2.6
Through Loss at 1GHz
(S12, S21) f = 1GHz, 1m channel
f = 1GHz, 0.5m channel
(S12, S21)
2.4
dB
dB
ꢀ
1.7
Wideband Through Loss
Return Loss at 1GHz
Wideband Return Loss
See Figures 7–9
-12
(S11, S22)
(S11, S22)
See Figure 10
ꢀ of signal at aggressor. Near-end and far-end
aggressors driven with 100ps (20ꢀ to 80ꢀ)
Channel Crosstalk
5
edges. End of channel terminated with 100Ω.
Reference Clock Requirements
PARAMETER
REFCLK Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ppm
%
125
REFCLK Frequency Tolerance
REFCLK Duty Cycle
-100
40
+100
60
240
15
ps
p-p
f < 5kHz (jitter assumed Gaussian)
ps
RMS
REFCLK Jitter
f > 5kHz (jitter is assumed deterministic,
caused by power-supply noise and buffer
jitter)
20
ps
p-p
Parallel Fiber Module Requirements
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
120
UNITS
Ω
Differential Input Impedance
Transmitter Input Sensitivity
R
80
100
IN
300
mVp-p
Deterministic and random jitter, peak-to-
Total Jitter Generation
80
ps
p-p
peak, (DJ + 16.4 × RJ
)
RMS
Receiver Data Output Amplitude
Differential Output Impedance
Channel-to-Channel Crosstalk
Differential
300
80
800
120
5
mVp-p
R
100
Ω
OUT
ꢀ
______________________________________________________________________________________ 15
Quad 2.5Gbps Cable Transceiver
0.5m CHANNEL LOSS
1m CHANNEL LOSS
0
-1.00
-2.00
-3.00
-4.00
-5.00
-6.00
-7.00
-8.00
-9.00
-10.00
0
-1.00
-2.00
UPPER MASK
NOMINAL
UPPER MASK
-3.00
-4.00
NOMINAL
-5.00
-6.00
-7.00
LOWER MASK
LOWER MASK
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
Figure 7. 0.5m Channel Loss Mask
Figure 8. 1.0m Channel Loss Mask
3m CHANNEL LOSS
RETURN LOSS MASK
0
-2.00
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-4.00
-6.00
UPPER MASK
NOMINAL
-8.00
-10.00
-12.00
-14.00
-16.00
-18.00
LOWER MASK
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
Figure 9. 3.0m Channel Loss Mask
Figure 10. Channel Input Return Loss Mask
16 ______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Pin Configuration
TOP VIEW
1
2
3
4
5
6
7
8
9
75
74
73
72
71
70
69
GND
GND
VCC1
VCC5
TXFIL
RESET
GND
RDAT1+
RDAT1-
RDAT2+
RDAT2-
RDAT3+
RDAT3-
RDAT4+
VCC4
TX1+
TX1-
68
67
66
65
64
63
62
VCC4
TX2+
TX2-
10
11
RDAT4-
VCC1
MAX3780
CABLE TRANSCEIVER
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCC4
GND
GND
RDAT5+
RDAT5-
RDAT6+
RDAT6-
RDAT7+
RDAT7-
RDAT8+
RDAT8-
RCLK+
RCLK-
TRIEN
VCC4
61 TX3+
60
59
58
57
56
55
54
53
52
51
TX3-
VCC4
TX4+
TX4-
VCC4
GND
EQ1
EQ2
PTPIN
GND
VCC1
GND
TQFP - EP*
*EXPOSED PAD MUST BE CONNECTED TO GROUND
Chip Information
TRANSISTOR COUNT: 15,270
PROCESS: Bipolar
______________________________________________________________________________________ 17
Quad 2.5Gbps Cable Transceiver
Package Information
18 ______________________________________________________________________________________
Quad 2.5Gbps Cable Transceiver
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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