MAX3804ETE#G16 [MAXIM]
Telecom Circuit, 1-Func, Bipolar, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220, TQFN-16;
| 型号： | MAX3804ETE#G16 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telecom Circuit, 1-Func, Bipolar, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220, TQFN-16 电信 电信集成电路 |
| 文件： | 总9页 (文件大小：1526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2713; Rev 1; 11/03
12.5Gbps Settable Receive Equalizer
General Description
Features
The MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter-
symbol interference. The MAX3804 can extend the practi-
cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal-
ization for 10.7Gbps signals is typically 24psP-P on the
maximum path length.
ꢀ Compensates Up to 30in (0.75m) of 6-mil FR-4
Transmission Line Loss
ꢀ 115mW Operating Power
ꢀ Up to 12.5Gbps Data Rate
ꢀ Compatible with 8B10B, 64B66B, and PRBS Data
ꢀ Less than 30psP-P Residual Jitter After
Equalization
ꢀ 3-Bit Equalization Level Select Input
ꢀ 3mm x 3mm Thin QFN Package
ꢀ DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O
ꢀ -40°C to +85°C Operation
The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm ✕ 3mm package affords optimal placement and
routing flexibility. It has separate V
connections for
CC
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso-
lated supplies, providing independent DC-coupled inter-
facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con-
trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per-
formance over a wide range of data rates and formats.
ꢀ +3.3V Core Supply Voltage
Ordering Information
PIN-
PACKAGE
PACKAGE
CODE
PART
TEMP RANGE
16 Thin QFN
(3mm x 3mm)
MAX3804ETE
-40°C to +85°C
T1633F-3
Applications
OC-192 and 10Gb Ethernet Switches and Routers
OC-192 and 10Gb Ethernet Serial Modules
High-Speed Signal Distribution
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
+1.8V
+2.5V
+3.3V
V
CC
V
CC
10Gbps
SERDES
V
V
V
CC2
CC1
CC
30in OF FR-4 STRIPLINE OR
MICROSTRIP TRANSMISSION LINE
10Gbps
SERIAL OPTICAL
MODULE
MAX3804
SDO+
SDO-
SDI+
SDI-
SDO+
SDO-
SDI+
SDI-
IN
EQ1 EQ2 EQ3 GND
+3.3V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12.5Gbps Settable Receive Equalizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ............................................-0.5V to +4.0V
Continuous Power Dissipation (T = +85°C)
A
CC
CML Supply Voltage (V
Current at Serial Output (SDO+, SDO-)............................ 25mA
Input Voltage (SDI+, SDI-, EQ1,
, V
) ............-0.5V to (V
+ 0.5V)
16-Lead Thin QFN-EP (derate 17.5mW/ C
CC1 CC2
CC
above +85°C) ........................................................1398mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
EQ2, EQ3) ..............................................-0.5V to (V
+ 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= V
= +1.65V to +3.6V, T = -40°C to +85°C. Typical values are at V
= V
= V = +3.3V,
CC2
CC
CC1
CC2
A
CC
CC1
and T = +25°C, unless otherwise noted.)
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
50
UNITS
mA
I
35
CC
CML Input Differential
V
AC-coupled or DC-coupled (Note 1)
DC-coupled
400
1200
mVP-P
IN
V
V
CC1
+ 0.1
CC1
CML Input Common Mode
V
- 0.4
CML Input Termination
CML Input Return Loss
CML Output Differential
CML Output Impedance
CML Output Transition Time
Single ended
Up to 5GHz
42.5
50
10
57.5
dB
V
400
500
50
600
57.5
35
mVP-P
OUT
Single ended
42.5
t , t
R
20% to 80% (Notes 2, 6)
At 10.7Gbps (Notes 3, 4, 5, 6)
At 12.5Gbps (Notes 3, 4, 5, 6)
ps
F
24
17
30
Residual Jitter Output
(Total RJ, PWD, and PDJ)
psP-P
30
LVTTL Input Current
LVTTL Input Low
LVTTL Input High
I
, I
-30
2.0
+30
0.8
µA
V
IH IL
V
IL
V
V
IH
Note 1: Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z = 100 , 6-mil
0
microstrip in FR-4,
= 4.5, and tan
= 0.02, V = (SDI+ - SDI-).
r
IN
Note 2: Measured with 0000011111 pattern at 12.5Gbps.
Note 3: Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-
sion line) and equalizer output. Total residual jitter is DJ
Note 4: Measured at 10.7Gbps using a pattern of 100 ones, 2 PRBS, 100 zeros, 2 PRBS, and at 12.5Gbps using a K28.5 pattern.
+ 14.2 x RJ
.
P-P
RMS
7
7
Deterministic jitter at the input is from frequency-dependent, media-induced loss only.
Note 5: V = 400mV
to 1200mV , input path is 0 to 30in, 6-mil microstrip in FR-4, = 4.5, and tan
= 0.02.
IN
P-P
P-P
r
Note 6: Guaranteed by design and characterization.
2
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
RESIDUAL JITTER
vs. INPUT AMPLITUDE
RESIDUAL JITTER
vs. FR-4 PATH LENGTH
SUPPLY CURRENT vs. TEMPERATURE
85
70
55
40
25
10
35
30
25
20
15
10
5
35
30
25
20
15
10
5
30in OF FR-4
400mV
P-P
V
= V
= V = 3.3V
CC1 CC2
CC
TRANSMISSION LINE
INPUT AMPLITUDE
7
2 PRBS WITH 100
7
2 PRBS WITH 100
CIDs AT 9.953Gbps
CIDs AT 9.953Gbps
K28.5 AT 12.5Gbps
K28.5 AT 12.5Gbps
RESIDUAL JITTER
RESIDUAL JITTER
= DJ + 14.2RJ
RMS
= DJ + 14.2RJ
P-P
RMS
P-P
0
0
-40
-15
10
35
60
85
400
600
800
1000
1200
3
9
15
21
27
TEMPERATURE ( C)
INPUT AMPLITUDE (mV
)
P-P
FR-4 PATH LENGTH (in)
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4
(27PRBS WITH 100 CIDs AT 10.7Gbps)
EQUALIZER OUTPUT EYE AFTER 18in OF FR-4
(K28.5 AT 12.5Gbps)
RESIDUAL JITTER
vs. EQUALIZATION SETTING
35
31
27
23
19
15
RESIDUAL JITTER
DJ + 14.2RJ
P-P
RMS
18in
24in
30in
60mV/
div
60mV/
div
6in
400mV , FR-4,
P-P
7
2 PRBS WITH 100
12in
3in
CIDs AT 10.7Gbps
16ps/div
16ps/div
000 001 010 011 100 101 110 111
EQUALIZATION SETTING (EQ3, EQ2, EQ1)
_______________________________________________________________________________________
3
12.5Gbps Settable Receive Equalizer
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
EQUALIZER INPUT EYE AFTER 30in OF FR-4
(27PRBS WITH 100 CIDs AT 10.7Gbps)
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(27PRBS WITH 100 CIDs AT 10.7Gbps)
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(K28.5 AT 12.5Gbps)
60mV/
div
60mV/
div
60mV/
div
16ps/div
16ps/div
16ps/div
EQUALIZER OUTPUT EYE AFTER 24ft
OF RG-188/U COAXIAL CABLE, SINGLE ENDED
(27PRBS WITH 100 CIDs, 9.953Gbps)
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(27PRBS WITH 100 CIDs AT 3.2Gbps)
60mV/
div
60mV/
div
60ps/div
20ps/div
4
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Pin Description
PIN
NAME
FUNCTION
CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be
AC-coupled.
1, 4
V
CC1
2
SDI+
SDI-
EQ1
EQ2
EQ3
GND
Positive Serial Data Input, CML
3
5
Negative Serial Data Input, CML
Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1.
Equalizer Boost Control Logic Input, LVTTL. See Table 1.
Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1.
Supply Ground
6
7
8, 16
CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be
AC-coupled.
9, 12
V
CC2
10
11
SDO-
SDO+
N.C.
Negative Serial Data Output, CML
Positive Serial Data Output, CML
No Connection. Leave unconnected.
+3.3V Core Supply Voltage
13, 14
15
V
CC
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the Package and Layout Considerations section).
EP
Exposed Pad
CML Input and Output Buffers
Detailed Description
General Theory of Operation
The MAX3804 input and output CML buffers are termi-
nated with 50 to V
and V
, respectively. The
CC2
CC1
The MAX3804’s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (V ), input (V
), and output (V
) circuit-
CC2
CC
CC1
ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.
Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50 termination.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
_______________________________________________________________________________________
5
12.5Gbps Settable Receive Equalizer
V
V
CC2
CC1
FLAT-
RESPONSE
AMPLIFIER
VARIABLE
ATTENUATOR
50
50
50
50
SDO+
SDO-
SDI+
SDI-
LIMITING
AMP
CML
CML
BOOST-
RESPONSE
AMPLIFIER
VARIABLE
ATTENUATOR
MAX3804
EQ1
EQ2
EQ3
DIGITAL-
TO-ANALOG
CONVERTER
Figure 1. Functional Diagram
Applications Information
Equalizer Boost Level Control
The MAX3804 equalizer is intended for use at the
receive end of an FR-4 PC board transmission line,
typically up to 30in of differential 6-mil stripline or
microstrip. It is specifically designed to mitigate
intersymbol interference caused by the frequency-
dependent path loss of FR-4 transmission lines. It can
also be used with a variety of other transmission-line
materials and geometries, including coaxial cable,
or PC board paths that include well-engineered
connectors. Table 1 shows the relationship between
nominal 6-mil FR-4 transmission line length and
equalization setting.
V
V
CC
CC2
50
50
SDO+
SDO-
ESD
DIODES
MAX3804
Supply Voltage Connections
The CML input and output supplies (V
, V
) can
need
CC1 CC2
and V
be connected to +1.8V to +3.3V. V
CC1
CC2
not be connected to the same supply voltage; however,
the core supply (V ) must be connected to +3.3V.
CC
Package and Layout Considerations
The MAX3804 is packaged in a 3mm x 3mm plastic-
encapsulated 16-lead thin QFN package. The package
has an exposed pad that provides thermal and
electrical connectivity to the IC and must be soldered
to a high-frequency ground. Use good layout tech-
niques for the SDI and SDO PC board transmission
lines, and configure the trace geometry near the IC
Figure 2. Simplified Output Structure
package to minimize impedance discontinuities.
Power-supply decoupling capacitors should be as
close as possible to the IC.
6
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Pin Configuration
Table 1. Nominal 6-mil FR-4 Transmission
Line Length and Equalization Settings
NOMINAL 6-mil FR-4
MICROSTRIP LENGTH (in)
EQ3
EQ2
EQ1
V
1
2
3
4
12
V
CC2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
CC1
SDI+
SDI-
11 SDO+
10 SDO-
6
MAX3804
10
14
18
22
26
30
V
9
V
CC2
CC1
Thin QFN*
(3mm x 3mm)
*THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT
BOARD GROUND FOR PROPER THERMAL AND
ELECTRICAL PERFORMANCE.
Chip Information
TRANSISTOR COUNT: 1007
PROCESS: SiGe bipolar
_______________________________________________________________________________________
7
12.5Gbps Settable Receive Equalizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
b
0.10 M
C
A
B
D
D2/2
D/2
E/2
E2/2
- A -
(NE - 1)
X e
C
E2
E
L
L
- B -
k
e
C
L
(ND - 1)
X e
C
L
C
L
0.10
C
0.08
C
A
A2
A1
L
L
e
e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0136
C
2
8
_______________________________________________________________________________________
12.5Gbps Settable Receive Equalizer
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0136
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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