MAX3841ETG+ [MAXIM]

12.5Gbps CML 2 × 2 Crosspoint Switch; 12.5Gbps的慢性粒细胞白血病2 × 2交叉点开关


型号：	MAX3841ETG+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	12.5Gbps CML 2 × 2 Crosspoint Switch 12.5Gbps的慢性粒细胞白血病2 × 2交叉点开关开关
文件：	总7页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-2905; Rev 1; 3/09

12.5Gbps CML 2 × 2 Crosspoint Switch

MAX3841

General Description

Features

The MAX3841 is a low-power, 12.5Gbps 2 × 2 cross-

point switch IC for high-speed serial data loopback,

redundancy, and switching applications. The MAX3841

current-mode logic (CML) inputs and outputs have iso-

♦ Up to 12.5Gbps Operation

♦ Less Than 10ps Deterministic Jitter

P-P

♦ Less Than 0.7ps

Random Jitter

RMS

lated V

connections to enable DC-coupled interfaces

♦ 1.8V, 2.5V, and 3.3V DC-Coupled CML I/O

♦ Independent Output Power-Down

♦ 4mm × 4mm Thin QFN Package

♦ -40°C to +85°C Operation

to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal

paths and Maxim’s second-generation SiGe technology

provide optimum signal integrity, minimizing jitter,

crosstalk, and signal skew. The MAX3841 is ideal for

serial OC-192 and 10GbE optical module, line card,

switch fabric, and similar applications.

♦ +3.3V Core Supply

The MAX3841 has 150mV

sensitivity, and 500mV

minimum differential input

P-P

nominal differential output

♦ 215mW Power Consumption (Excluding

P-P

swing. Unused outputs can be powered down individu-

ally to conserve power. In addition to functioning as a 2

× 2 switch, the MAX3841 can be configured as a 2:1

multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841

is available in a 4mm × 4mm 24-pin thin QFN package,

and consumes only 215mW with both outputs enabled.

Termination Currents)

Ordering Information

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

24 Thin QFN-EP*

MAX3841ETG

MAX3841ETG+

Applications

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

OC-192, 10GbE Switch/Line Cards

OC-192, 10GbE Optical Modules

System Redundancy/Self Test

Clock Fanout

Pin Configuration appears at end of data sheet.

Typical Application Circuit

1.8V

2.5V

3.3V

1.8V

10Gbps

3.3V

2.5V

CDR/SERDES

VCC1OUT

OUT1+

VCC2IN

ASIC

SDI+

SDI-

IN2+

IN2-

SDO+

SDO-

SDI+

SDI-

10Gbps

SERIAL

OPTICAL

MODULE

OUT1-

IN1+

MAX3841

OUT2+

OUT2-

SDO+

SDO-

IN1-

2.5V

1.8V

VCC1IN

VCC2OUT

SEL1 SEL2 ENO1 ENO2 GND

LOOPBACK

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim's website at www.maxim-ic.com.

12.5Gbps CML 2 × 2 Crosspoint Switch

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V ..............................................-0.5V to +4.0V

Continuous Power Dissipation (T = +85°C)

CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V

Continuous Output Current (OUT1 , OUT2 )................... 25mA

CML Input Voltage (IN1 , IN2 )...........-0.5V to (VCC_IN + 0.5V)

LVCMOS Input Voltage (SEL1, SEL2,

24-Pin Thin QFN (derate 20.8mW/°C

above +85°C).............................................................1352mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ENO1, ENO2) .........................................-0.5V to (V

+ 0.5V)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

MAX3841

ELECTRICAL CHARACTERISTICS

= +3.0V to +3.6V, VCC_IN = +1.71V to V , VCC_OUT = +1.71V to V , T = -40°C to +85°C. Typical values are at V

+3.3V, VCC_IN = VCC_OUT = 1.8V, T = +25°C, unless otherwise noted.)

PARAMETER

Core Supply Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Excluding CML termination currents

(Note 1)

Data Rate

12.5

Gbps

CML Input Differential

CML Input Common Mode

CML Input Termination

CML Input Return Loss

CML Output Differential

CML Output Termination

CML Output Transition Time

Deterministic Jitter

AC-coupled or DC-coupled (Note 2)

DC-coupled

150

1200

VCC_IN

57.5

P-P

VCC_IN - 0.3

Single ended

42.5

ꢀ

Up to 10GHz

500

(Note 2)

400

600

57.5

P-P

OUT

Single ended

42.5

ꢀ

t , t

20% to 80% (Notes 1, 3)

(Notes 1, 4)

P-P

Random Jitter

= 150mV

(Notes 1, 5)

0.3

0.7

140

RMS

P-P

Propagation Delay

Any input to output (Note 1)

(Note 1)

100

μA

Channel-to-Channel Skew

Output Duty-Cycle Skew

LVCMOS Input Current

LVCMOS Input High Voltage

LVCMOS Input Low Voltage

50% input duty cycle (Notes 1, 3)

, I

-10

1.7

+10

IH IL

0.7

Note 1: Guaranteed by design and characterization.

Note 2: Differential swing is defined as V = (IN_+) - (IN_-) and V

= (OUT_+) - (OUT_-). See Figure 1.

OUT

Note 3: Measured using a 0000011111 pattern at 12.5Gbps, and V = 400mV

differential.

P-P

Note 4: Measured at 9.953Gbps using a pattern of 100 ones, 2 - 1 PRBS, 100 zeros, 2 - 1 PRBS, and at 12.5Gbps using a ±±28.5

pattern. VCC_IN = VCC_OUT = 1.8V, and V = 400mV

differential.

P-P

Note 5: Refer to Application Note 1181: HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope.

_______________________________________________________________________________________

12.5Gbps CML 2 × 2 Crosspoint Switch

MAX3841

Typical Operating Characteristics

= 3.3V, VCC_IN, VCC_OUT = 1.8V, V = 500mV , T = +25°C, unless otherwise noted.)

IN P-P A

CORE SUPPLY CURRENT vs. TEMPERATURE

(EXCLUDES CML I/O CURRENTS)

SUPPLY CURRENT vs. TEMPERATURE

(CORE PLUS CML I/O CURRENTS)

OUTPUT EYE DIAGRAM

(12.5Gbps, 2²³- 1 PRBS)

MAX3841 toc03

140

130

120

110

100

130

120

110

100

2 OUTPUTS ENABLE

1 OUTPUT ENABLE

0 OUTPUTS ENABLE

1 OUTPUT ENABLE

0 OUTPUTS ENABLE

60mV/div

2 OUTPUTS ENABLE

CML INPUTS AND OUTPUTS AC-COUPLED

-40

-15

-40

-15

14ps/div

TEMPERATURE (°C)

OUTPUT EYE DIAGRAM

(10.7Gbps, 2²³- 1 PRBS)

OUTPUT EYE DIAGRAM

(6.25Gbps, 2²³- 1 PRBS)

OUTPUT EYE DIAGRAM

(622Mbps, 2²³- 1 PRBS)

MAX3841 toc06

MAX3841 toc04

MAX3841 toc05

60mV/div

16ps/div

28ps/div

270ps/div

DETERMINISTIC JITTER

vs. TEMPERATURE

DIFFERENTIAL OUTPUT SWING

vs. TEMPERATURE

PROPAGATION DELAY

MAX3841 toc09

550

540

530

520

510

500

490

480

470

460

450

2⁷- 1 PRBS + 100CIDs

AT 10.7Gbps

IN1

OUT1

K28.5 AT 12.5Gbps

-40

-15

-40

-15

100ps/div

TEMPERATURE (°C)

_______________________________________________________________________________________

12.5Gbps CML 2 × 2 Crosspoint Switch

Pin Description

1, 12

2, 5

NAME

FUNCTION

+3.3V Core Supply Voltage

VCC1IN

IN1+

Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V.

Positive Serial Data Input 1, CML

IN1-

Negative Serial Data Input 1, CML

SEL1

SEL2

VCC2IN

IN2+

Output 1 Select, LVCMOS Input. See Table 1.

Output 2 Select, LVCMOS Input. See Table 1.

Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V.

Positive Serial Data Input 2, CML

MAX3841

8, 11

IN2-

Negative Serial Data Input 2, CML

13, 24

14, 17

GND

Supply Ground

VCC1OUT Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V.

OUT1-

OUT1+

ENO1

Negative Serial Data Output 1, CML

Positive Serial Data Output 1, CML

Output 1 Enable, LVCMOS Input. See Table 1.

Output 2 Enable, LVCMOS Input. See Table 1.

ENO2

20, 23

VCC2OUT Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V.

OUT2-

Negative Serial Data Output 2, CML

Positive Serial Data Output 2, CML

OUT2+

Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and

electrical performance.

—

The CML inputs accept serial NRZ data with differential

Detailed Description

amplitude from 150mV

to 1200mV

(see Figure 2).

P-P

The MAX3841 contains a pair of CML inputs that drive

two 2:1 multiplexers, with separate select inputs SEL1

and SEL2, providing a 2 × 2 crosspoint data path. The

outputs of the multiplexers each drive a high-perfor-

mance CML output that can be disabled (powered

down) using the ENO1/ENO2 inputs. All of the data

paths are fully differential to minimize jitter, crosstalk,

and signal skew. See Figure 1 for the functional diagram.

The CML outputs provide 500mV

swing, resulting in low power consumption.

nominal differential

P-P

IN1

IN2

CML

OUT1

CML

ENO1

SEL1

CML Input and Output Buffers

The MAX3841 input and output buffers are terminated

with 50Ω to independent supply lines, and are also com-

patible with 100Ω differential terminations. (See Figures 3

and 4.) Separate power-supply connections are provided

for the core, input buffers, and output buffers to allow DC-

coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the

CML inputs and outputs can be AC-coupled.

CML

OUT2

ENO2

SEL2

MAX3841

Figure 1. Functional Diagram

_______________________________________________________________________________________

12.5Gbps CML 2 × 2 Crosspoint Switch

MAX3841

Table 1. Output Controls

V-

75mV

MIN

ENO1

ENO2

SEL1

SEL2

OUT1

IN2

OUT2

IN1

600mV

MAX

IN2

V+

IN1

IN2

Disabled Disabled

150mV

MIN

(V+) - (V-)

1200mV

MAX

Applications Information

Select and Enable Controls

The MAX3841 provides two LVCMOS-compatible

select inputs, SEL1 and SEL2. Either data input can be

connected to either or both data outputs. The MAX3841

provides two LVCMOS-compatible enable inputs,

ENO1 and ENO2, so each output can be disabled

independently. The MAX3841 can also be used as a

1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using

the LVCMOS control inputs accordingly (see Table 1).

Figure 2. Definition of Differential Voltage Swing

VCC_IN

50Ω

Power-Supply Connections

Each of the input and output power-supply connections

(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-

dent and need not be connected to the same voltage.

The input and output supplies can be connected to

IN_+

IN_-

1.8V, 2.5V, or 3.3V, but the core supply (V ) must be

MAX3841

connected to 3.3V for proper operation.

Input and Output Interfaces

The MAX3841 inputs and outputs can be AC-coupled

or DC-coupled according to the application. If an input

or output is not used it should be terminated with 50Ω

to the correct input or output supply voltage. For more

information about interfacing with logic families, refer to

Application Note 291: HFAN-01.0: Introduction to

LVDS, PECL, and CML.

Figure 3. Equivalent CML Input Circuit

VCC_OUT

50Ω

Package and Layout Considerations

The MAX3841 is packaged in a 4mm × 4mm 24-pin thin

QFN with exposed pad. The exposed pad provides

thermal and electrical connectivity to the IC and must

be soldered to a high-frequency ground plane. Use

multiple vias to connect the exposed pad underneath

the package to the PC board ground plane.

OUT_+

OUT_-

Use good layout techniques for the 10Gbps PC board

transmission lines, and configure the layout near the IC to

minimize impedance discontinuities. Power-supply

decoupling capacitors should be located as close as

possible to the IC.

MAX3841

Figure 4. Equivalent CML Output Circuit

_______________________________________________________________________________________

12.5Gbps CML 2 × 2 Crosspoint Switch

Pin Configuration

Chip Information

TRANSISTOR COUNT: 950

PROCESS: SiGe BiCMOS

TOP VIEW

Package Information

24 23 22 21 20 19

For the latest package outline information and land patterns, go

ENO1

to www.maxim-ic.com/packages.

VCC1IN

IN1+

VCC1OUT

OUT1+

OUT1-

MAX3841

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

24 TQFN-EP

T2444-3

21-0139

MAX3841

IN1-

VCC1IN

SEL1

VCC1OUT

GND

*EP

10 11 12

THIN QFN

*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE

SOLDERED TO GROUND FOR PROPER THERMAL AND

ELECTRICAL OPERATION.

_______________________________________________________________________________________

12.5Gbps CML 2 × 2 Crosspoint Switch

MAX3841

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

8/03

Initial release.

—

Added a lead-free package to the Ordering Information table.

3/09

Changed the package code from T2444-1 to T2444-3 and replaced the package

outline drawings with the Package Information table.

1, 6

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7

Maxim is a registered trademark of Maxim Integrated Products, Inc.

MAX3841ETG+ [MAXIM]

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