MAX3886ETN+ [MAXIM]
ATM/SONET/SDH Support Circuit, 1-Func, BICMOS, 8 X 8 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220, TQFN-56;
| 型号： | MAX3886ETN+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ATM/SONET/SDH Support Circuit, 1-Func, BICMOS, 8 X 8 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220, TQFN-56 ATM 异步传输模式 电信 信息通信管理 电信集成电路 |
| 文件： | 总17页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3103; Rev 0; 12/07
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
General Description
Features
The MAX3886 2.488Gbps/1.244Gbps/622Mbps CDR
with SerDes (serializer/deserializer) is designed specifi-
cally for low-cost optical network terminal (ONT) appli-
cations in Gigabit passive optical network (GPON) and
broadband passive optical network (BPON) fiber-to-
the-home (FTTH) systems. It provides G.984- and
G.983-compliant clock and data recovery (CDR) for the
continuous downstream data signal, with an integrated
4-bit SerDes that has LVDS parallel interfaces and CML
serial interfaces.
♦ 2.488Gbps, 1.244Gbps, and 622Mbps Clock and
Data Recovery
♦ Meets G.984 and G.983 Jitter Requirements
♦ 4-Bit Serializer and 4-Bit Deserializer with
Loop-Timed Serialization
♦ CML Serial I/O, LVDS Parallel I/O
♦ Integrated Reference Oscillator Uses 19.44MHz
SMD Crystal
The SerDes uses the recovered downstream clock for
upstream serialization (loopback clock), providing opti-
mum PON operation. The CDR frequency reference
can be provided by a low-cost 19.44MHz SMD-type
crystal or external LVCMOS source, and excellent jitter
tolerance supports applications requiring FEC. An inte-
grated burst-enable signal path also simplifies high-
performance upstream burst timing.
♦ Integrated Upstream Burst-Enable Signal Path
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
56 TQFN
(8mm x 8mm)
This 3.3V IC is housed in a 8mm x 8mm, 56-lead thin
QFN package and operates from -40°C to +85°C.
MAX3886ETN+ -40°C to +85°C
T5688-2
+Denotes a lead-free package.
Applications
Pin Configuration appears at end of data sheet.
BPON/GPON Optical Network Terminal (ONT)
Typical Application Circuit
+3.3V
+3.3V
0.27μF
+3.3V
V
CC
CFIL
V
CC
RFCK1
MVCO
MDDR
MSYM
VOICE
19.4400MHz
MAX3747/
MAX3748
LIM AMP
SLIC
MAC IC
RFCK2
SDI
MAX3886
2.488G
PCKO
PCLK (311MHz)
GPON
CDR/SERDES
1490nm
PDO[3:0]
PDI[3:0]
PCKI
PDATA (622Mbps)
PDATA (311Mbps)
PCLK (311MHz)
BURST ENABLE
DATA
PON
1.244G
MAX3643/
MAX3656
LD DRIVER
SDO
10/100
ETHERNET
1310nm
BiDi
TRIPLEXER
BENO
BENI
GND LOCK FRST FERR
1550nm
870MHz VIDEO
MAX3654
VIDEO TIA
GPON OPTICAL NETWORK TERMINAL (ONT)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V ).................................-0.3V to +4.0V
LVCMOS Output Voltage Range
CC
CML Input Voltage Range (SDI )...............-0.3V to (V
CML Output Current (SDO , BENO )............................... 22mA
LVDS Input Voltage Range
+ 0.3V)
(LOCK, FERR) ........................................-0.3V to (V
Voltage Range at CFIL, RFCK1,
RFCK2, TP1, TP2, TP3, TP4 ...................-0.3V to (V
+ 0.3V)
+ 0.3V)
CC
CC
CC
Continuous Power Dissipation (T = +70°C)
(PCKI , PDI[3:0] , BENI )......................-0.3V to (V
LVDS Output Voltage Range
(RCKO , PDO[3:0] , PCKO )................-0.3V to (V
LVCMOS Input Voltage Range
(MSYM, MDDR, FRST)............................-0.3V to (V
Three-State Input Voltage Range
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
A
CC
CC
CC
CC
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX386
(MVCO)...................................................-0.3V to (V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
Operating Temperature
Power-Supply Voltage
SYMBOL
CONDITIONS
MIN
-40
3.0
TYP
MAX
+85
3.6
UNITS
T
A
°C
V
CC
V
Downstream/Upstream
Data Rates
See Table 2
19.4400
Gbps
MHz
ppm
Reference Frequency
Internal or external oscillator
Includes aging, temperature, and other
contributors
Crystal Accuracy
±250
Crystal ESR
Fundamental type, AT-strip cut
10
40
60
ꢀ
Crystal Drive
100
μW
pF
Crystal Load Capacitance
On-chip parallel capacitance
18
Reference Clock Input Duty
Cycle
When driven by an LVCMOS clock source
60
%
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted. LVDS outputs
CC A
CC
A
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
Supply Current
CDR/DESERIALIZER SPECIFICATIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
240
310
mA
CC
MVCO = 1
2488.32
1244.16
622.08
> 100
0.7
Serial Input Data Rate
Rate
Mbps
Bits
MVCO = open
MVCO = 0
-10
CDR CID Immunity
BER ꢁ 10 (Note 2)
-10
CDR Sinusoidal Jitter Tolerance
SDI to SDO Jitter Transfer
f > f
BER ꢁ 10 (Note 3)
0.3
UI
P-P
C
(Notes 4, 5)
0.1
dB
2
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted. LVDS outputs
CC
A
CC A
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDI to SDO Jitter Transfer
Bandwidth
(Notes 3, 4)
(Note 6)
f
C
MHz
Parallel Clock Output Random
Jitter
< 0.5
mUI
RMS
Parallel-Output Clock to Data
Time
t
Figure 1
-80
45
+80
300
55
ps
CK-Q
Parallel Clock and Data-Output
Rise/Fall Time
t , t
20% to 80%
ps
r
f
Parallel-Clock Output Duty
Cycle
%
MHz
ps
Parallel-Clock Output Frequency
See Table 2
Parallel-Data Output
Channel-to-Channel Skew
100
CDR Acquisition Time
(After Startup)
2
ms
Reference-Output Clock
Frequency
See Table 2
MHz
SERIALIZER SPECIFICATIONS
Parallel-Input Clock Frequency
Serial-Output Data Rate
See Table 2
See Table 2
MHz
Mbps
ps
Parallel-Data Input-Setup Time
Parallel-Data Input-Hold Time
t
t
Figure 1
Figure 1
170
300
SU
ps
HD
Serial-Data Output Rise/Fall
Time
t , t
r
20% to 80%
(Notes 5, 6)
(Notes 2, 5)
160
4
ps
f
Serial-Data Output Random Jitter
mUI
RMS
Serial-Data Output
Deterministic Jitter
47
mUI
P-P
Burst Enable to Serial Data
MSB Time
t
Figure 2
-50
+50
ps
B-MSB
Minimum Pulse Width of
FIFO Reset
UI is PCKO period
UI is PCKO period
4
UI
UI
Tolerated Drift Between PCKI
and PCKO After FIFO Reset
±1
I/O SPECIFICATIONS
CML Differential Input Voltage
V
200
1600
mV
P-P
IN
CML Input Common-Mode
Range
V
1.49
-
V
1.32
-
V
CC
-
CC
CC
V
V
/4
IN
_______________________________________________________________________________________
3
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted. LVDS outputs
CC
A
CC A
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mV
CML Differential Output
640
800
1000
P-P
CML Differential Output
Resistance
80
100
100
120
ꢂ
MAX386
LVDS Input Voltage Range
0
2400
mV
mV
LVDS Differential Input Range
(Note 5)
Figure 3
±100
±600
LVDS Differential Input
Resistance
80
120
ꢂ
LVDS Output Voltage High
LVDS Output Voltage Low
LVDS Output Differential Voltage
LVDS Output Offset Voltage
1475
mV
mV
mV
mV
mV
mV
925
250
V
V
400
1275
25
OD
V
= (V
+ V )/2, Figure 3
OUT-
1125
OS
OS
OUT+
LVDS Output Change in V
LVDS Output Change in V
|ꢀV
|ꢀV
|
|
Between “0” and “1”
Between “0” and “1”
OD
OS
OD
25
OS
LVDS Differential Output
Resistance
80
100
140
0.8
ꢂ
LVCMOS Input Voltage Low
LVCMOS Input Voltage High
LVCMOS Input Current
V
V
V
IL
V
2.0
-10
-50
IH
V
= V or V = ground
+10
+50
0.2
μA
μA
V
IH
CC
IL
Three-State Input Current
LVCMOS Output Voltage Low
MVCO input, V = V or V = ground
IH CC IL
V
I
= 100μA
OL
OL
V
0.2
-
CC
LVCMOS Output Voltage High
V
I
= -100μA
V
OH
OH
Note 1: With a 19.4400MHz SMD AT-strip crystal at RFCK1 and RFCK2.
7
7
Note 2: Pattern is 16 x 2 - 1 PRBS, 100 CIDs, 16 x 2 - 1 PRBS inverted, 100 CIDs inverted.
Note 3: For 622Mbps operation, f = 500kHz.
C
For 1.244Gbps operation, f = 1MHz.
C
For 2.488Gbps operation, f = 2MHz.
C
Note 4: Jitter transfer from SDI to SDO, with parallel side looped back. Defined as:
⎡
⎢
⎤
⎥
jitter onupstream signalUI
downstreambit rate
upstreambit rate
Jitter transfer =
×
jitter ondownstream signalUI
⎢
⎥
⎣
⎦
Note 5: Guaranteed by design and characterization.
Note 6: For 2.488Gbps operation, measurement bandwidth = 8kHz to 20MHz.
For 1.244Gbps operation, measurement bandwidth = 4kHz to 10MHz.
For 622Mbps operation, measurement bandwidth = 2kHz to 5MHz.
For 155Mbps operation, measurement bandwidth = 0.5kHz to 1.3MHz.
4
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
1UI
SDO
PDI1
PDI0
PDI3
PDI2
PDI1
PDO_
PCKO
(MDDR = 0)
BENO
t
t
B-MSB MIN
B-MSB MAX
PCKO
(MDDR = 1)
Figure 2. Burst-Enable Timing
t
t
CK-Q MAX
CK-Q MIN
1UI
PDI_
PCKI
t
SU
t
HD
Figure 1. Parallel Interface Timing Diagrams
LVDS
R = 100Ω
L
V
OD
V
V
OUT-
V
OD
V
OS
SINGLE- ENDED OUTPUT
V
OUT+
+V
OD
V
= V
- V
DIFFERENTIAL OUTPUT
0V
OD(P-P)
OUT+ OUT-
-V
OD
Figure 3. Definition of LVDS Output Levels
_______________________________________________________________________________________
5
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
Typical Operating Characteristics
(V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
1.244Gbps SERIAL DATA OUTPUT
622Mbps PARALLEL DATA AND CLOCK
622Mbps PARALLEL DATA AND CLOCK
(MVCO = 1, MSYM = 0)
OUTPUT (MVCO = 1, MDDR = 0)
OUTPUT (MVCO = 1, MDDR = 1)
MAX3886 toc01
MAX3886 toc02
MAX3886 toc03
MAX386
120ps/div
500ps/div
500ps/div
2.488Gbps JITTER TOLERANCE
1.244Gbps JITTER TOLERANCE
622Mbps JITTER TOLERANCE
100
100
100
10
TOLERANCE EXCEEDS TEST
EQUIPMENT GENERATION LIMIT
TOLERANCE EXCEEDS TEST
EQUIPMENT GENERATION LIMIT
TOLERANCE EXCEEDS TEST
EQUIPMENT GENERATION LIMIT
10
10
1
1
0.1
1
0.1
0.01
0.1
0.01
G.984 MASK
G.983MASK
G.984 MASK
0.01
10k
100k
1M
10M
10k
100k
1M
10M
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
SDI TO SDO JITTER TRANSFER
(SDI = 2.488Gbps)
SDI TO SDO JITTER TRANSFER
(SDI = 1.244Gbps)
SDI TO SDO JITTER TRANSFER
(SDI = 622Mbps)
1
0
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
G.984 MASK
G.984 MASK
G.983MASK
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
6
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
PARALLEL CLOCK OUTPUT RANDOM
JITTER vs. TEMPERATURE
SDO RANDOM JITTER vs. TEMPERATURE
(ASYMMETRIC, MSYM = 0)
SDO RANDOM JITTER vs. TEMPERATURE
(SYMMETRIC, MSYM = 1)
4.0
1.0
0.9
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
SDO=1.244Gbps
BW = 4kHz TO 10MHz
SDI = 2.488Gbps
BW = 8kHz TO 20MHz
SDO=2.488Gbps
BW = 8kHz TO 20MHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
SDO=622Mbps
BW=2kHzTO5MHz
SDO=1.244Gbps
BW = 4kHz TO 10MHz
SDI = 1.244Gbps
BW = 4kHz TO 10MHz
SDO= 155Mbps
BW= 0.5kHz TO 1.3MHz
SDI = 622Mbps
BW = 2kHz TO 5MHz
SDO= 622Mbps
BW = 2kHz TO 5MHz
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
NAME
GND
TP1
FUNCTION
1, 14, 15,
29, 42, 43,
56
Supply Ground
2
Test Pin, Reserved. Connect to GND for normal operation.
+3.3V Supply Voltage
3, 6, 12, 28,
46, 53
V
CC
4
SDI+
SDI-
Positive Serial Data Input, CML or LVPECL
Negative Serial Data Input, CML or LVPECL
Negative Burst-Enable Output, CML
Positive Burst-Enable Output, CML
5
7
BENO-
BENO+
TP2
8
9
Test Pin, Reserved. Connect to V for normal operation.
CC
10
11
13
16
17
18
19
20
21
22
SDO-
SDO+
TP3
Negative Serial Data Output, CML
Positive Serial Data Output, CML
Test Pin, Reserved. Connect to GND for normal operation.
Positive Parallel Clock Input, LVDS
PCKI+
PCKI-
PDI3+
PDI3-
PDI2+
PDI2-
PDI1+
Negative Parallel Clock Input, LVDS
Positive Parallel Data Input 3, LVDS, MSB (First Serial Bit Out)
Negative Parallel Data Input 3, LVDS, MSB (First Serial Bit Out)
Positive Parallel Data Input 2, LVDS
Negative Parallel Data Input 2, LVDS
Positive Parallel Data Input 1, LVDS
_______________________________________________________________________________________
7
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
Pin Description (continued)
PIN
23
24
25
26
27
30
31
32
33
34
35
36
37
38
39
NAME
PDI1-
FUNCTION
Negative Parallel Data Input 1, LVDS
PDI0+
PDI0-
Positive Parallel Data Input 0, LVDS, LSB (Last Serial Bit Out)
Negative Parallel Data Input 0, LVDS, LSB (Last Serial Bit Out)
Positive Burst Enable Input, LVDS
BENI+
BENI-
Negative Burst Enable Input, LVDS
MAX386
RCKO+
RCKO-
PDO3+
PDO3-
PDO2+
PDO2-
PDO1+
PDO1-
PDO0+
PDO0-
Positive Parallel Rate Reference Clock Output, LVDS
Negative Parallel Rate Reference Clock Output, LVDS
Positive Parallel Data Output 3, LVDS, MSB (First Serial Bit In)
Negative Parallel Data Output 3, LVDS, MSB (First Serial Bit In)
Positive Parallel Data Output 2, LVDS
Negative Parallel Data Output 2, LVDS
Positive Parallel Data Output 1, LVDS
Negative Parallel Data Output 1, LVDS
Positive Parallel Data Output 0, LVDS, LSB (Last Serial Bit In)
Negative Parallel Data Output 0, LVDS, LSB (Last Serial Bit In)
Positive Parallel Clock Output, LVDS; Rate/4 or Rate/8, depending on value of MDDR pin. See
Figure 1 for timing diagram.
40
41
PCKO+
PCKO-
Negative Parallel Clock Output, LVDS; Rate/4 or Rate/8, depending on value of MDDR pin. See
Figure 1 for timing diagram.
FIFO Error Output, LVCMOS. A high output indicates when the FIFO read and write clocks attempt to
access the same register. Normally connected to MAC IC.
44
45
FERR
FRST
FIFO Reset Input, LVCMOS. A high input resets the FIFO. Normally connected to MAC IC.
Reference Clock Crystal Input. A 19.4400MHz crystal must be connected between RFCK1 and
RFCK2; or a 19.4400MHz LVCMOS clock source (capable of driving up to 10pF load) can be
connected through a 10pF ±10% series capacitor to RFCK1, RFCK2 unconnected.
47
RFCK2
48
49
RFCK1
MDDR
Reference Clock Crystal Input. See Pin 47.
Dual Data Rate Select Input, LVCMOS. A high input selects dual data rate (DDR) parallel clock
output. See Figure 1 for timing diagram.
Symmetric Select Input, LVCMOS. A high input selects symmetric operation, a low input selects
asymmetric operation. See Table 2.
50
51
52
MSYM
MVCO
LOCK
VCO Rate Select Input, Three-State. See Table 2.
PLL Lock Detector Output, LVCMOS. A high output indicates the PLL is in lock, this output can
chatter when no valid input signal is present.
PLL Filter Capacitor Connection. Connect a 0.27μF ceramic capacitor (±10%, 10V, X7R-type)
between pin 54 and pin 53.
54
CFIL
55
—
TP4
EP
Test Pin, Reserved. Connect to V for normal operation.
CC
Exposed Paddle. Connect to thermal and electrical ground.
8
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
2.488Gbps). An external filter capacitor, connected
Detailed Description
between CFIL and V
sets the damping factor of the
CC
The MAX3886 CDR/SerDes provides 2.488Gbps/
1.244Gbps/622Mbps clock and data recovery, plus 1:4
deserializer for continuous downstream data and 1:4
serializer for burst upstream data (Figure 4).
Specifically designed for GPON and BPON ONT appli-
cations, the serializer uses the recovered downstream
clock to serialize the upstream serial data (loop-timed
serialization). The upstream rate can be configured to
be either equal to the downstream rate (symmetric
operation) or a submultiple of the downstream rate
(asymmetric operation). A low-cost 19.4400MHz SMD-
type crystal or external LVCMOS source serves as the
CDR frequency reference, providing robust frequency
acquisition and lock detection.
PLL. All jitter specifications are based on an external
0.27µF capacitor. Modifying the value of CFIL changes
jitter peaking, acquisition time, and loop stability but not
loop bandwidth.
PLL Reference Clock Oscillator
An integrated oscillator provides a reference clock sig-
nal for robust CDR acquisition and lock detection. This
oscillator requires a 19.4400MHz crystal connected
between RFCK1 and RFCK2, or an external LVCMOS
19.4400MHz clock source can be used. See the
Applications Information section for important informa-
tion about crystal selection and how to connect an
external clock source.
A parallel rate reference clock output, derived from the
recovered downstream signal, is provided for use by
the MAC layer IC, and an integrated FIFO is provided
to deal with phase variation between the serializer and
MAC layer IC. Once the FIFO has been initialized, the
serializer tolerates up to one parallel UI phase differ-
ence between the read and write clocks. The FIFO cir-
cuitry includes an error output that indicates when the
FIFO attempts to read and write from the same location.
An integrated burst-enable signal path also includes
the FIFO to simplify upstream burst timing.
Deserializer and Parallel Output
The downstream data is deserialized, producing four
parallel LVDS outputs, PDO[3:0] . The first serial data
bit received on the SDI input is the most significant bit
(MSB), which is routed to the parallel output PDO3. The
LVDS parallel output clock, PCKO, can be configured
for either full rate or half rate operation, as shown in the
timing diagrams of Figure 1. The PCKO rate is con-
trolled using the LVCMOS MDDR input. Set the MDDR
pin to logic high to clock out parallel data on each
edge of the PCKO clock.
The deserializer parallel output clock can optionally be
configured for dual data rate (DDR) operation. The
high-speed CML-format serial-data interfaces are com-
patible with Maxim burst-mode laser drivers and both
CML and LVPECL limiting amplifiers. The parallel data
interfaces are LVDS format for compatibility with FPGAs
or ASICs.
Parallel Input, FIFO, and Serializer
Parallel data presented at the four LVDS data inputs
PDI[3:0] is latched into the input register using the
LVDS parallel input clock PCKI and clocked out of the
ONT SerDes using the recovered serial clock. The par-
allel data bit PDI3 is the MSB and the first bit out of the
serial SDO output. For GPON and BPON ONT applica-
tions, the clock multiplier unit (CMU) frequency synthe-
sizer normally incorporated in SONET serializers is
eliminated, improving PON performance. Asymmetric
operation is configured using the LVCMOS MSYM input
(see Table 2). The parallel clock is also output on the
LVDS RCKO pins for use, if needed, by the MAC layer.
Serial Input Clock/Data Recovery
Clock and data recovery is provided by a phase-locked
loop (PLL) with selectable 2.488GHz/1.244GHz/
622MHz operation. The operating frequency is con-
trolled by the three-state MVCO input. A phase detector
and filter generate error voltage proportional to the
phase difference between the internal VCO and the
input data, and feedback in the PLL drives the error
voltage to zero, aligning the recovered clock to the
center of the input data for retiming.
The serializer’s 4-bit-long FIFO accommodates phase
variation between RCKO and PCKI. PCKI provides the
FIFO write clock and the internal RCKO is the read
clock (loading the 4:1 serializer); this arrangement
allows the phase relationship between these two clocks
to vary 1UI. In the event that valid read and write
clocks attempt to access the same FIFO address, this
error condition is indicated on the LVCMOS FERR out-
put. To initiate the FIFO or clear an error condition, the
LVCMOS FRST input must be asserted high for at least
4UI while valid clocks are present.
A frequency detector assists the PLL to “pull in” to the
serial data and generates the lock indicator signal on
the LOCK pin. When no valid input signal is present,
the LOCK output can oscillate (chatter) as the PLL
hunts for the input signal.
The PLL VCO and integrated loop filter implement a
second-order transfer function, with loop bandwidth
dependent on the VCO rate selected (e.g., 1.5MHz for
_______________________________________________________________________________________
9
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
CFIL
PDO3+
D
Q
Q
Q
Q
LVDS
LVDS
LVDS
LVDS
LVDS
PDO3-
PDO2+
SDI+
SDI-
CML
PD
LPF
VCO
CLK
3
PDO2-
PDO1+
4-BIT SERIAL
TO PARALLEL
CDR PLL
LOCK
CMOS
PDO1-
PDO0+
FREQ
DETECT
RFCK1
RFCK2
OSC
CLK/4
DIV 2
PDO0-
PCKO+
1
MVCO
CMOS
0
PCKO-
MDDR
1
CMOS
DIV 2,
DIV 4
0
CMOS
MSYM
PCKI+
DIV 4
RCKO+
RCKO-
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
PCKI-
PDI3+
CLK
RD
WR
CLK
D
D
D
PDI3-
PDI2+
PDI2-
PDI1+
CLK
SDO+
SDO-
CML
Q
D
Q
5 x 4 FIFO
REGISTER
4-BIT
PARALLEL
TO SERIAL
PDI1-
PDI0+
D
PDI0-
BENI+
CLK
BENO+
BENO-
CML
Q
D
BENI-
FERR
CMOS
CMOS
FRST
MAX3886
Figure 4. Functional Diagram
10 ______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
At power-up, the CDR takes approximately 50ms (if
valid NRZ data is present) for initial acquisition while
the internal reference oscillator, the PLL, and the fre-
quency detector reach their operating conditions.
During this startup period, the LOCK status output may
provide false indication of a lock condition. Once the
PLL and frequency detector are initialized, the nominal
time for reacquisition of an NRZ input is 2ms.
Burst-Enable Signal Processing
To minimize PON overhead, it is important that the laser
driver burst-enable (BEN) signal correspond accurately
with the beginning of the serial data burst. This is sup-
ported in the MAX3886 by the BENI LVDS input and
associated signal path. The LVDS burst-enable signal
from the MAC layer IC is passed through the same FIFO
as the parallel data and output on the BENO CML out-
put, which ensures that the laser driver’s burst enable
matches the beginning of the associated serial MSB. If
FRST or FERR are high, the BENO output is forced low
to prevent the laser driver from transmitting erroneous
data. The parallel data setup and hold timing require-
ments also apply to the burst-enable signal.
When valid NRZ input data is not present, the lock
detector may produce a chattering LOCK indicator out-
put while the PLL searches for the input frequency. If
needed, an external digital filter can be used to mask
this chattering.
Table 1. Lock Detector Output
Lock Detector Output
The lock detector operates by comparing a divided-
down version of the VCO output to the reference clock.
The LOCK output pin indicates lock (high) when the fre-
quency difference between the reference clock and the
CDR VCO is less than 250ppm, within the “pullin” range
of the PLL. The LOCK output indicates out-of-lock (low)
when the frequency difference between the reference
clock and the CDR VCO becomes more than 500ppm.
When valid input data is present, this provides a stable
lock indication.
CDR INPUT
Valid NRZ data
No CDR input
LOCK OUTPUT
1
0/1 (chatter)
Control Input Summary
Table 2 summarizes the clock and data rates as con-
trolled by MVCO, MSYM, and MDDR.
Table 2. Clock and Data Rate Controls
Rx
Tx
MVCO
MSYM
MDDR
SDI RATE PDO RATE
PCKO
(MHz)
SDO RATE PDI RATE
PCKI
(MHz)
RCKO
(MHz)
(Mbps)
(Mbps)
(Mbps)
(Mbps)
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
622
622
155
155
155
155
311
311
311
311
622
622
622
622
155
78
155
155
39
39
39
0
39
39
39
0
0
622
155
78
622
155
155
155
155
311
311
311
311
622
622
155
155
155
155
311
311
311
311
622
622
155
155
155
155
311
311
311
311
622
622
622
622
Open
Open
Open
Open
1
1244
1244
1244
1244
2488
2488
2488
2488
311
155
311
155
622
311
622
311
622
622
1244
1244
1244
1244
2488
2488
1
1
1
______________________________________________________________________________________ 11
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
Applications Information
V
CC
Interfacing to the CDR/SerDes
The MAX3886 has CML, LVDS, and LVCMOS inputs
and outputs. The high-speed CML (LVPECL-compati-
V
CC
V
CC
16kΩ
ble) inputs, SDI , are biased to V
- 1.3V with an on-
CC
5kΩ
5kΩ
chip high-impedance network (Figure 5). Figures 6 and
7 provide examples of DC-coupled and AC-coupled
termination networks that can be used to connect the
limiting amplifier outputs (CML or LVPECL) to the SDI
inputs. The two high-speed CML outputs, SDO and
SDI+
MAX386
V
CC
BENO , have internal 50Ω back terminations to V
CC
(Figure 8) and should be terminated with 50Ω to V
or
CC
100Ω differential at the laser driver inputs (Figure 9).
The burst SDO and BENO outputs must be DC-coupled
to the laser driver for proper operation. SDO can be
AC-coupled if a continuous serial signal is provided
between bursts (with gating provided by the laser dri-
ver BEN input).
SDI-
24kΩ
MAX3886
The LVDS outputs (PDO[3:0] , PCKO , RCKO )
require 100Ω differential termination for proper opera-
tion. The LVDS inputs (PDI[3:0] , PCKI ) are internally
terminated with 100Ω differential resistance, eliminating
the need for external termination when connected to an
LVDS output (Figure 10).
Figure 5. CML (LVPECL-Compatible) Input
outputs (LOCK, FERR) are given in Figure 11, Figure 12,
and Figure 13. For more information on interfacing to
Maxim’s high-speed I/O circuits, refer to Application
Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
Equivalent circuits for the three-state input (MVCO),
LVCMOS inputs (MSYM, MDDR, FRST), and LVCMOS
DC-COUPLED
LIMITING AMPLIFIER
CML
Z = 50Ω
0
SDI+
100Ω
MAX3886
Z = 50Ω
0
SDI-
AC-COUPLED
LIMITING AMPLIFIER
CML
0.1μF
Z = 50Ω
SDI+
SDI-
0
100Ω
MAX3886
0.1μF
Z = 50Ω
0
Figure 6. Interface to Limiting Amplifier (CML Outputs)
12 ______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
V
CC
DC-COUPLED
130Ω
130Ω
LIMITING AMPLIFIER
LVPECL
Z = 50Ω
0
SDI+
SDI-
MAX3886
Z = 50Ω
0
82Ω
82Ω
AC-COUPLED
LIMITING AMPLIFIER
LVPECL
0.1μF
Z = 50Ω
SDI+
SDI-
0
100Ω
MAX3886
0.1μF
143Ω
Z = 50Ω
0
143Ω
Figure 7. Interface to Limiting Amplifier (LVPECL Outputs)
V
CC
MAX3886
50Ω
50Ω
SDO+/BENO+
SDO-/BENO-
Figure 8. CML Outputs
______________________________________________________________________________________ 13
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
Z = 50Ω
SDO+
SDO-
IN+
IN-
0
CML
100Ω
Z = 50Ω
0
MAX386
MAX3886
MAX3656/MAX3643
CDR/SerDes
BURST-MODE
LASER DRIVER
Z = 50Ω
BENO+
BENO-
BEN+
BEN-
0
CML
100Ω
Z = 50Ω
0
Figure 9. Interface to Laser Driver
MAC IC
MAX3886
Z = 50Ω
0
LVDS
LVDS
100Ω
100Ω
Z = 50Ω
0
Z = 50Ω
0
LVDS
LVDS
100Ω
100Ω
Z = 50Ω
0
Figure 10. LVDS Interface
14 ______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
FIFO Control Signals
A valid input at FRST is required to initialize the FIFO
V
CC
V
CC
after the relationship between PCKO or RCKO and PCKI
has stabilized prior to operating the serializer, or after the
FERR output has indicated that the FIFO has overflowed
or underflowed due to the phase difference between
PCKO or RCKO and PCKI exceeding its capacity. The
MAC IC provides the control signal for FRST. FERR
should not be directly connected to FRST.
P
MVCO
N
If the PCKI signal is interrupted between bursts, the
FIFO must be reset before the beginning of each burst
while valid clocks are present. If a continuous PCKI sig-
nal is provided between bursts, the FIFO maintains the
correct FIFO counter values as long as the phase rela-
tionship does not change.
MAX3886
Reference Clock Oscillator
The integrated reference oscillator requires a parallel
resonant 19.4400MHz AT-strip cut crystal connected
between pins RFCK1 and RFCK2. It has 18pF nominal
(15pF to 21pF) of on-chip crystal load capacitance; any
frequency error due to mismatch to the rated crystal
load capacitance must be included in the budget for
the difference between reference clock frequency and
input data rate. Take care that the wiring capacitances
at the nodes RFCK1 and RFCK2 are controlled (typical-
ly no more than 2pF) to ensure proper operation.
Figure 11. Three-State Input (MVCO)
V
CC
V
CC
P
MSYM
MDDR
FRST
N
To drive the reference clock with an external
19.4400MHz LVCMOS clock source, connect it to
RFCK1 through a 10pF 10ꢀ series capacitor and
leave RFCK2 open. The LVCMOS clock source must be
capable of driving a 10pF load.
MAX3886
To ensure proper acquisition, the maximum difference
between the downstream data rate (divided down to
19.4400MHz) and 19.4400MHz clock should be
500ppm, including 57ppm required by the CDR itself.
Table 3 shows a typical budget.
Figure 12. LVCMOS Inputs
V
CC
V
CC
Table 3. Typical Frequency Budget
P
ꢀf
( ppm)
DESCRIPTION
Downstream Data Rate
Crystal Load Capacitance
NOTES
LOCK
FERR
50
G.983, G.984
e.g., 21ppm/pF ꢀ
from 18pF
N
63
Crystal Tolerance
Crystal Temperature Stability
Crystal Aging
75
100
50
MAX3886
CDR Operation
57
Total is less than
500ppm
Total
395
Figure 13. LVCMOS Outputs
______________________________________________________________________________________ 15
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
The 56-pin TQFN package features an exposed pad
(EP) that provides a low resistance thermal path for
heat removal from the IC and must be connected to the
circuit board ground plane for proper operation. The EP
also provides essential electrical ground connectivity.
Power Supply and Ground Connection
The MAX3886 has six V connection pads, and instal-
CC
lation of a bypass capacitor at each V
pad is recom-
CC
mended. All six V
connections should be driven from
CC
the same source to eliminate the possibility of indepen-
dent power-supply sequencing. Pin 53 provides current
directly to the internal VCO stage; excessive supply
noise at this node can result in increased jitter.
MAX386
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
GND
FERR
FRST
V
CC
43
44
45
46
BENI-
BENI+
PDI0-
PDI0+
PDI1-
PDI1+
PDI2-
PDI2+
PDI3-
PDI3+
V
CC
RFCK2 47
RFCK1 48
MDDR 49
MSYM 50
MVCO 51
LOCK 52
MAX3886
V
53
CC
CFIL 54
TP4 55
GND 56
17 PCKI-
16 PCKI+
15 GND
EP*
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14
THIN QFN
(8mm × 8mm × 0.8mm)
* THE EXPOSED PAD OF THE THIN QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER
THERMAL AND ELECTRICAL OPERATION.
16 ______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX386
Chip Information
Package Information
(For the latest package outline information, go to
TRANSISTOR COUNT: 10,684
www.maxim-ic.com/packages.)
PROCESS: SiGe BiCMOS
PACKAGE TYPE
DOCUMENT NO.
21-0135
56 Thin QFN
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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