MAX38909ATD+ [MAXIM]
2A High-Performance nMOS LDO Linear Regulator;
| 型号： | MAX38909ATD+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2A High-Performance nMOS LDO Linear Regulator |
| 文件： | 总20页 (文件大小：1175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX38909
2A High-Performance
nMOS LDO Linear Regulator
General Description
Benefits and Features
The MAX38909 is a fast transient response, high PSRR
nMOS linear regulator that delivers up to 2A of load cur-
rent.
● Delivers Flexible Operating Range
• 0.9V to 5.5V Input Voltage Range
• 2.7V to 20V BIAS Voltage Range
• 0.6V to 5.0V Programmable Output Voltage
• 2A Maximum Output Current
The regulator supports a wide input supply range from
0.9V to 5.5V, and BIAS voltage range from 2.7V to 20V to
provide wider supply options in a variety of applications.
±1% output accuracy is maintained over line, load, and
temperature variations, requiring only 300mV of input-to-
output headroom at full load for a good PSRR. The output
voltage can be adjusted to accommodate customers that
desire to specify a single LDO in the BOM for multiple volt-
age rails.
• 27mV Dropout at 2A Load Current
• 1.6mA Operating BIAS Supply Current
● Reduces Noise and Improves Accuracy
• ±1% DC Accuracy Over Load, Line, and
Temperature
• 15mV 2A Load Transient Excursion
• 52dB IN PSRR at 10kHz at 300mV Input-to-Output
Headroom
The output voltage on the MAX38909 is programmed to a
value in the range of 0.6V to 5.0V by using two external
feedback resistors.
● Enables Ease-of-Use and Robust Protection
• Stable with 10μF (Minimum) Output Capacitance
• Programmable Soft-Start Rate
The LDO is fully protected from damage by internal circuit-
ry that provides programmable inrush current limiting, out-
put overcurrent limiting, reverse-current limiting, and ther-
mal overload protection.
• Overcurrent and Overtemperature Protection
• Output-to-Input Reverse Current Protection
• Power-OK Status Pin
● Reduces Size, Improves Reliability
• 14-Pin (3mm x 3mm) TDFN and 5 x 3 Bump,
0.4mm Pitch WLP Packages
The MAX38909 is offered in 14-pin, 3mm x 3mm TDFN
and 5 x 3 bump, 0.4mm pitch WLP packages.
• -40°C to +125°C Operating Temperature
Applications
● FPGAs and DSPs
● Medical, Audio, and Instrumentation
● Server Microcontrollers
● Portable Cameras
● PLCs
Ordering Information appears at end of data sheet.
● Base Stations
19-100950; Rev 1; 11/20
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Typical Application Circuit
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
(1.3V TO 5.5V)
(1.0V/UP TO 2A)
C3
22µF
R3
C1
C2
100kΩ
MAX38909
22µF
47nF
GND
EN
BYP
POK
FB
ENABLE
POK
R2
10kΩ
BIAS
(2.7V TO 20V)
BIAS
EP
C4
R1
15kΩ
1µF
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Maxim Integrated | 2
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
14 TDFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 TDFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power OK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Active Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input and Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Maxim Integrated | 3
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
LIST OF FIGURES
Figure 1. Typical POK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. Typical IN UVLO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. Startup into Dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Maxim Integrated | 4
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
LIST OF TABLES
Table 1. Recommended Feedback Resistor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Maxim Integrated | 5
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Absolute Maximum Ratings
IN, FB, OUT, BYP, POK to GND.............................. -0.3V to +6V
WLP (derate 16.2mW/°C, T = +70°C).......................1312mW
A
BIAS to GND .......................................................... -0.3V to +22V
Operating Junction Temperature Range.............-40°C to +125°C
Maximum Junction Temperature ......................................+150°C
Storage Temperature Range ..............................-65°C to +150°C
Lead Temperature (soldering, 10s)...................................+300°C
EN to GND..................................................-0.3V to V
+ 0.3V
BIAS
Output Short-Circuit Duration ..................................... Continuous
Continuous Power Dissipation (T = +70°C)
A
TDFN (derate 24.4mW/°C, T = +70°C)..................1951.2mW
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
14 TDFN
Package Code
T1433+2C
21-0137
90-0063
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
54°C/W
8°C/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
41°C/W
8°C/W
JA
Junction to Case (θ
)
JC
WLP
Package Code
Outline Number
N151C2+1
21-100372
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
61.65°C/W
N/A
Junction to Case (θJC)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
Electrical Characteristics
(V = 1.5V, V
IN
= 1.0V, V
= 10V, T = -40°C to +125°C, C = 22μF, C
= 22μF, C
= 1nF, unless noted otherwise.)
BYP
OUT
BIAS
J
IN
OUT
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Guaranteed by output accuracy,
Input Voltage Range
V
IN
0.9
5.5
V
V
OUT
< V - V
IN DO
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Maxim Integrated | 6
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Electrical Characteristics (continued)
(V = 1.5V, V
IN
= 1.0V, V
= 10V, T = -40°C to +125°C, C = 22μF, C
= 22μF, C
= 1nF, unless noted otherwise.)
BYP
OUT
BIAS
J
IN
OUT
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bias Voltage Range
V
2.7
20
V
BIAS
Input Undervoltage
Lockout
V
V
V
rising, 60mV hysteresis
0.35
0.45
2.55
0.55
V
IN_UVLO
IN
Bias Undervoltage
Lockout
V
rising, 100mV hysteresis
2.45
0.6
10
2.65
5.0
V
V
BIAS_UVLO
BIAS
Output Voltage Range
Output Capacitance
Input Supply Current
V
Guaranteed by output accuracy
OUT
OUT
Effective capacitance required for stability
and proper operation
C
22
μF
μA
I
V
= 3.6V, V
= 5.0V, I = 0mA
OUT
70.5
0.001
1
150
1
Q
EN
EN
BIAS
T = +25°C
J
Input Shutdown Current
I
V
= 0V
μA
SD
T = +125°C
J
V
V
V
= 3.3V, V
= 3.3V, V
= 0V
= 5.0V, I
= 0mA
1.5
4
4
EN
BIAS
BIAS
OUT
OUT
I
mA
μA
BIAS
Bias Supply Current
= 5.0V, I
= 2A
1.6
EN
I
0.75
BIAS_SD
EN
I
from 10mA to 2A, V from V
+
OUT
OUT
IN
Feedback Voltage
Accuracy
0.3V to 5.5V, V
> 2.7V, V
from 0.6V to
OUT
from
BIAS
BIAS
V
FB
0.594
0.6
0.606
V
V
OUT
+ 2V to 20V, V
5.0V
Load Regulation
Load Transient
I
I
from 0.1mA to 2A, C
= 47nF
BYP
0.05
15
%
OUT
= 20mA to 2A and 2A to 20mA, di/dt
OUT
mV
= 1A/μs, C
= 3 x 10μF, C
= 47nF
BYP
OUT
V
1A, C
from V
+ 0.3V to 5.5V, I
=
OUT
IN
OUT
Line Regulation
Line Transient
0.04
4.5
%/V
mV
= 47nF
BYP
V
IN
= 1.0V to 1.2V to 1.0V, 10V/ms V
IN
slew rate, I
= 2A, V
= 0.8V, C
OUT
OUT
BYP
= 47nF
V
TDFN
= 5.0V,
BIAS
36
27
50
43
44
36
36
27
2.8
80
80
V
V
= 5.0V, WLP
= 3.3V,
I
= 2A,
BIAS
OUT
V
= 1.2V
= 2.5V
OUT_NOM
BIAS
100
100
TDFN
V
= 3.3V, WLP
= 5.0V,
Dropout Voltage (Note
2)
BIAS
BIAS
V
DO
mV
V
I
= 2A,
OUT
TDFN
V
OUT_NOM
V
V
= 5.0V, WLP
= 12V,
BIAS
BIAS
I
= 2A,
OUT
TDFN
V
= 5.0V
OUT_NOM
V
BIAS
= 12V, WLP
V
V
= 0.9 x V
= 300mV
, V
-
OUTS/OUT
OUT_NOM IN
Current Limit
I
2.2
3.4
A
LIM
OUT
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Maxim Integrated | 7
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Electrical Characteristics (continued)
(V = 1.5V, V
IN
= 1.0V, V
= 10V, T = -40°C to +125°C, C = 22μF, C
= 22μF, C
= 1nF, unless noted otherwise.)
BYP
OUT
BIAS
J
IN
OUT
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
μV
I
= 0.5A, 10Hz
OUT
Output Noise
to 100kHz, V
=
C
BYP
= 47nF
21.2
OUT
RMS
1.2V
V
- V
= 1A, C
= 0.3V, f = 1kHz
OUT
59
52
IN
I
=
OUT
OUT
f = 10kHz
4 x 10μF, C
=
BYP
IN Power Supply
Rejection Ratio
PSRR
PSRR
47nF, V
>
=
dB
dB
BIAS
2.7V, V
BIAS
f = 100kHz
42
V
OUT
+ 2V, T =
A
+25°C
V
IN
- V
= 0.3V, f = 1kHz
OUT
90
78
I
= 1A, C
=
OUT
OUT
f = 10kHz
BIAS Supply Rejection
Ratio
4 x 10μF, C
47nF, V
=
BYP
=
BIAS
f = 100kHz
69
V
OUT
+ 5V, T =
A
+25°C
Regulator remains stable; guaranteed by
design
BYP Capacitor Range
BYP Soft-Start Current
C
0.001
0.1
μF
μA
BYP
I
From BYP to GND during startup
EN rising
50
1.0
BYP
V
1.6
+1
IH
EN Input Threshold
V
V
EN falling
0.4
-1
0.9
IL
V
EN
from 0V to
T
A
= +25°C
+0.001
EN Input Leakage
Current
I
5.5V, V
8V to 20V
from
μA
EN_LK
BIAS
T = +125°C
J
0.01
V
V
rising
falling
88
-1
91
88
94
V
when POK
OUT
OUT
POK Threshold
%
mV
μA
switches
OUT
POK Voltage, Low
POK Leakage Current
V
I
= 1mA
10
100
+1
OL
POK
T
A
= +25°C
+0.001
0.01
I
V
POK
= 5.5V
POK_LK
T = +125°C
J
IN Reverse-Current
Threshold
V
= 1.2V, V
= 10V
700
165
150
mA
°C
OUT
BIAS
TJ when output
turns on/off
T rising
J
Thermal Shutdown
Threshold
T when output
J
turns on/off
T falling
J
Note 1: Limits over the specified operating temperature and supply voltage range are guaranteed by design and characterization, and
production tested at room temperature only.
Note 2: Dropout voltage is defined as (V - V
) when V
is 95% of its nominal value.
OUT
IN
OUT
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Maxim Integrated | 8
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Typical Operating Characteristics
(V = 1.5V, V
IN
= 12V, V
= 1.0V, C = 22μF, C
= 22μF, C
= 47nF, C = 1μF, T = +25°C, unless otherwise noted)
BIAS A
BIAS
OUT
IN
OUT
BYP
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Maxim Integrated | 9
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Typical Operating Characteristics (continued)
(V = 1.5V, V
IN
= 12V, V
= 1.0V, C = 22μF, C
= 22μF, C
= 47nF, C = 1μF, T = +25°C, unless otherwise noted)
BIAS A
BIAS
OUT
IN
OUT
BYP
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Maxim Integrated | 10
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Typical Operating Characteristics (continued)
(V = 1.5V, V
IN
= 12V, V
= 1.0V, C = 22μF, C
= 22μF, C
= 47nF, C = 1μF, T = +25°C, unless otherwise noted)
BIAS A
BIAS
OUT
IN
OUT
BYP
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Maxim Integrated | 11
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Pin Configurations
14 TDFN
TOP VIEW
14 13 12 11 10
9
8
MAX38909
EP*
+
1
2
3
4
5
6
7
TDFN-EP
3mm x 3mm
*EP = EXPOSED PAD
WLP
TOP VIEW
MAX38909
3
1
2
4
5
+
EN
POK
FB
IN
IN
IN
BIAS
GND
BYP
A
B
C
GND
OUT
GND
OUT
GND
OUT
5 x 3, 0.4mm PITCH
Pin Description
PIN
NAME
FUNCTION
14 TDFN
WLP
Regulator Supply Input. Connect to a voltage between 0.9V and 5.5V and bypass
with a 22μF ceramic capacitor from IN to GND.
1–4
A1–A3
IN
Bias Supply Input. Connect to a voltage between 2.7V and 20V and bypass with a
5
A4
BIAS
1μF capacitor from BIAS to GND. BIAS must be 2.0V or more above the V
target.
OUT
Enable. Connect this pin to a logic signal to enable (V
high) or disable (V
EN
EN
6
7
A5
EN
low) the regulator output. Connect to BIAS to keep the output enabled whenever a
valid supply voltage is present.
Regulator Ground. Bring IN and OUT bypass capacitor GND connections to this
pin for best performance.
B1–B4
GND
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Maxim Integrated | 12
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Pin Description (continued)
PIN
NAME
FUNCTION
14 TDFN
WLP
Power-On Reset Output. Connect a pullup resistor from this pin to a supply to
create a reset signal that goes high after the regulator output has reached its
regulation target voltage.
8
B5
POK
Output Voltage Feedback Input. Connect resistor divider across OUT and GND
with the center connected to this pin to set any output voltage between 0.6V and
5.0V.
9
10
C5
C4
FB
BYP
OUT
EP
Bypass Capacitor Input. Connect a 0.001μF to 0.1μF capacitor between OUT and
BYP to reduce output noise.
Regulator Output. Sources up to 2A at the output regulation voltage. Bypass this
pin with 22μF ceramic capacitor to GND. It is pulled low with a 70Ω resistance
when the regulator is disabled.
11–14
—
C1–C3
—
Exposed Pad (TDFN Only). Connect the exposed pad to a ground plane with low
thermal resistance to ambient to provide best heat sinking.
Functional Diagram
BIAS
BIAS
IN
THERMAL
PROTECTION
REVERSE-
CURRENT
PROTECTION
CONTROL
EN
CURRENT
LIMIT
OUT
ACTIVE
DISCHARGE
BYP
BYP
EA
REF
0.6V
POK
MAX38909
POK THRESHOLD
GND
FB
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Maxim Integrated | 13
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Detailed Description
The MAX38909 is a fast transient, high PSRR linear regulator that delivers up to 2A of load current. The regulator
supports a wide input supply (0.9V to 5.5V) and BIAS (2.7V to 20V) voltage ranges, making it suitable for variety of
applications. The output voltage regulation accuracy of ±1% is maintained across load, line, and temperature variations,
requiring only 300mV of input-to-output headroom at full load for good PSRR. The output voltage can be adjusted to
accommodate customers that desire to specify a single LDO in the BOM for multiple voltage rails.
The output voltage is programmed to a value in the range of 0.6V to 5.0V by using two external feedback resistors.
The LDO is fully protected from damage by internal circuitry that provides programmable inrush current limiting, output
overcurrent limiting, reverse current-limiting, and thermal overload protection.
Enable
The MAX38909 includes an enable pin (EN). The enable signal is an active-high digital signal that enables the device
when its voltage passes the rising threshold (V ≥ V (EN)) and disables the device when its voltage is below the falling
EN
IH
threshold (V
≤ V (EN)). While in the shutdown (V
= 0V), the MAX38909 consumes 1nA of current from the input
EN
IL
EN
supply. If a separate shutdown signal is not available, connect EN to BIAS. When EN is driven by a host its bias current
will vary with the BIAS supply level. See the Typical Operating Characteristics for more information.
Bypass
The capacitor connected from BYP to OUT filters noise at the reference, feedback resistors and regulator input stage. It
provides a high-speed feedback path for improved transient response. A 10nF capacitor rolls off noise at around 32Hz.
The slew rate of the output voltage during startup is also determined by the BYP capacitor. The MAX38909 features
programmable, monotonic, soft-start set by this capacitor. Its use is highly recommended to minimize inrush current into
the output capacitor. A 10nF capacitor sets the slew rate to 5V/ms. This startup rate results in a 110mA slew current
drawn from the input at startup to charge 22μF output capacitance.
The BYP capacitor value can be adjusted from 1nF to 100nF to change the startup slew rate according to the following
formula:
Startup slew rate = 5V/ms x 10nF/C
BYP
where C
is in nF.
BYP
This slew rate applies until V
reaches 75% of the target after which the V
slew rate is reduced.
OUT
OUT
Also, note that being a low-frequency filter node, BYP is sensitive to leakage. BYP leakage currents above 10nA cause
measurable inaccuracy at the output and should be avoided.
Power OK
The power-OK (POK) function monitors the voltage at the feedback pin to indicate the output voltage is in regulation. Its
operation versus the output voltage is shown in Figure 1.
The POK pin is open-drain and requires a pullup resistor to an external supply to properly report the device regulation
status to other devices so it can be used for sequencing. Check if the external pullup supply voltage results in a valid
logic levels for the receiving device or devices.
The range of the pullup resistance is between 10kΩ and 100kΩ. Its lower limit comes from a pulldown strength of the
POK transistor while the higher limit is determined by maximum leakage current at the POK pin.
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Maxim Integrated | 14
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
POK RISING THRESHOLD
POK FALLING THRESHOLD
V
OUT
POK
STARTUP
A
B
C
D
E
SHUTDOWN
Figure 1. Typical POK Operation
The POK operation versus the output voltage is shown in the Figure 1 above. Different operating regions are:
A: The device is in regulation.
B: V
sags, but does not reach the POK falling threshold.
OUT
C: The device is in regulation.
D: V sags low enough to cross the POK falling threshold. The POK is driven low until V
recovers above the POK
OUT
OUT
rising threshold.
E: The device is in regulation.
Protection
The MAX38909 is fully protected from an output short-circuit by a current-limiting and thermal overload protection circuit.
If the output is shorted to GND, the output current is limited to 2.8A (typ). Under these conditions, the device quickly
heats up. When the junction temperature reaches +165°C, a thermal limit circuit shuts the output device off. Once the
device cools to 150°C, the output turns back on to reestablish regulation. If the fault persists, the output current cycles
on and off as the junction temperature slews between +150°C and +165°C. Continuously operating in the fault conditions
or above +125°C junction temperature is not recommended since long-term reliability might be reduced. In dropout, the
current limit triggers at 4A (typ). Once the limit is triggered, the device limits the current to 2.8A (typ).
The thermal protection can also be triggered when the device is exposed to excessive heat in the system causing the die
temperature to reach undesired levels.
The MAX38909 provides the reverse-current protection when the output voltage is higher than the input. If extra output
capacitance is used at the output, a power-down transient at the input would normally cause a large reverse-current
through a conventional regulator. The MAX38909 include a reverse-voltage detector that trips when IN drops 6.5mV
below OUT shutting off the regulator and opening the body diode connection preventing any reverse current. The reverse
current is a current that flows through the body diode of the pass element and is undesired due to its impact on power
www.maximintegrated.com
Maxim Integrated | 15
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
dissipation and long-term reliability especially at higher current levels. The conditions where the reverse current can be
flowing back to IN are:
• If the device has a large C
and the input supply collapses quickly; OUT has little or no-load current,
OUT
• The output is biased when the input supply is not established, or
• The output is biased above the input supply.
The MAX38909 blocks reverse currents that exceed about 0.7A by opening a switch in series with the pass device body
diode.
Undervoltage Lockout (UVLO)
The MAX38909 undervoltage lockout (UVLO) circuits respond quickly to glitches on IN or BIAS and attempts to disable
the output of the device if either of these rails collapse. The local input capacitance prevents transient brownouts in most
applications.
UVLO RISING THRESHOLD
UVLO FALLING THRESHOLD
V
IN
V
OUT
STARTUP
A
B
C
IN REGULATION
SHUTDOWN
Figure 2. Typical IN UVLO Operation
The Figure 2 above reflects UVLO operation. The different operation regions are:
STARTUP: The device begins the soft-start once the input voltage crosses its UVLO rising threshold providing the BIAS
voltage is already above its UVLO rising threshold and the device is enabled (V
> V ).
IH
EN
A: The device is in regulation.
B: An input supply brownout condition where V can sag below UVLO rising threshold but not below the falling threshold.
IN
The device is enabled. Note the output sags once the device is in dropout.
C: An input supply brownout condition where V sags below UVLO falling threshold. The device is disabled when V
IN
IN
crosses its UVLO falling threshold. V
drops due to load current. The regulator gets enabled again once V recovers
OUT
IN
to the UVLO rising threshold. Note the output starts to sag once the device is in dropout.
SHUTDOWN: The output voltage starts to ramp down once the device gets into dropout. It is disabled when the input
www.maximintegrated.com
Maxim Integrated | 16
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
voltage drops below its UVLO falling threshold.
During V power-up, the MAX38909 begins V
soft-start after V crosses the V UVLO rising threshold. This
IN IN
IN
OUT
assures proper V
ramp up and transition to regulation. V
soft-start rate should be kept as or slower than the
OUT
OUT
V
V
slew rate to avoid entering the dropout. In some situations, V transients can place the regulator into dropout. As
starts climbing again and the device comes out of the dropout, the output can overshoot, as shown in Figure 3. This
IN
IN
IN
condition is avoided by using an enable signal or by increasing the soft-start time with larger C
.
BYP
V
V
IN
V
= V
+ V
OUT_NOM DO
IN
OUT
V
IN REGULATION
OUT
DROPOUT
= V - V
DO
V
OUT
IN
TIME
Figure 3. Startup into Dropout
Active Discharge
When EN is low or BIAS supply is below its falling UVLO threshold, the MAX38909 connects a 70Ω resistor from V
to GND in order to discharge the output capacitance.
OUT
Voltage Selection
The MAX38909 use external feedback resistors to set the output regulation voltage. The output voltage can be set from
0.6V to 5.0V. Set the bottom feedback resistor R1 to less than 100kΩ to minimize FB input bias current error. Calculate
the value of the top feedback resistor R2 as follows:
R2 = R1 x (V
/V - 1)
OUT FB
where V is the feedback regulation voltage of 0.6V.
FB
To set the output to 1.0V, for example, R2 should be:
R2 = 15kΩ x (1.0V/0.6V - 1) = 10kΩ
R1 of 15kΩ is recommended to optimize noise performance.
Values of the resistor divider and its tolerance will have a direct impact to V
accuracy. 1% resistors or better are
OUT
recommended. Table 1 shows recommended values for the feedback resistors.
www.maximintegrated.com
Maxim Integrated | 17
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Table 1. Recommended Feedback Resistor Values
TARGETED OUTPUT
VOLTAGE (V)
TOP FEEDBACK RESISTOR
VALUES (kΩ)
BOTTOM FEEDBACK RESISTOR
CALCULATED OUTPUT
VOLTAGE (V)
VALUES (kΩ)
0.8
0.9
1.0
1.2
1.5
1.8
2.5
2.7
3.0
3.3
3.6
4.5
5.0
4.99
7.50
10.0
15.0
22.6
30.1
47.5
52.3
59.0
68.1
75.0
97.6
110.0
15.0
0.799
0.900
1.0
15.0
15.0
15.0
1.2
15.0
1.504
1.804
2.5
15.0
15.0
15.0
2.692
3.008
3.324
3.6
14.7
15.0
15.0
15.0
4.504
5.0
15.0
www.maximintegrated.com
Maxim Integrated | 18
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Applications Information
Input and Output Capacitors
The MAX38909 is designed to have stable operation using low equivalent series resistance (ESR) ceramic capacitors at
the input, output, and bypass pin. Multilayer ceramic capacitors (MLCC) with X7R dialectic are commonly used for these
types of applications and are recommended due to their relatively stable capacitance across temperature. Nevertheless,
amount of equivalent capacitance depends on operating DC voltage, AC voltage ripple, temperature, etc. Therefore, the
capacitor data sheet needs to be properly examined.
The MAX38909 is designed and characterized for operation with X7R ceramic capacitors of 22µF or greater (10μF
or greater of effective capacitance) both at the input and output. Place these capacitors as close as possible to the
respective input and output pins to minimize trace parasitics.
A combination of multiple output capacitors in parallel boosts the high-frequency PSRR.
Thermal Design
To optimize the MAX38909 performance, special consideration is given to the device power dissipation and PCB thermal
design. Power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. It can
be calculated by following equation:
Loss (W) = (V – V
) x I
LOAD
IN
OUT
The optimal power dissipation can be achieved by carefully choosing input voltage for a given output target rail voltage.
The main thermal conduction path for the device is through the exposed pad of the package. As a result, the thermal
pad must be soldered to a copper pad area under the device. Thermal plated vias must be placed inside the thermal
PCB pad to transfer heat to different GND layers in the system. The vias should be capped to minimize solder voids. The
maximum power dissipation is determined by using thermal resistance from the device junction to ambient keeping the
maximum junction temperature below +125°C. Thermal properties of the package are given in the Package Information
section.
The first order power dissipation estimate for the 3.3V IN and 2.5V OUT with load current of 500mA condition is:
Loss (W) = (V – V
) x I
= (3.3V – 2.5V) x 0.5A = 0.4W
LOAD
IN
OUT
Assuming the MAX38909ATD+ is used, this power dissipation raises the junction temperature to:
T = (PD x θ ) + 25°C = (0.4W x 41°C/W) + 25°C = 41.4°C
J
JA
Ordering Information
TEMPERATURE
PART NUMBER
MAX38909ATD+
MAX38909ANL+
PIN-PACKAGE
FEATURE
RANGE
2A LDO, enable input, externally adjustable output, low
noise bypass
-40°C to +125°C
14 TDFN, 3mm x 3mm
15 WLP, 5 x 3, 0.4mm
pitch
2A LDO, enable input, externally adjustable output, low
noise bypass
-40°C to +125°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
www.maximintegrated.com
Maxim Integrated | 19
MAX38909
2A High-Performance
nMOS LDO Linear Regulator
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
11/20
11/20
0
1
Release for market intro
—
Updated Ordering Information table
19
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc.
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