MAX3945ETE+ [MAXIM]
Clock Recovery Circuit, 1-Func, CMOS, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-16;
| 型号： | MAX3945ETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Clock Recovery Circuit, 1-Func, CMOS, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-16 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总24页 (文件大小：1988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5144; Rev 0; 2/10
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
General Description
Features
S 130mW Power Dissipation Enables < 1W SFP+
The MAX3945 is a +3.3V, multirate, low-power limiting
amplifier optimized for Fibre Channel and Ethernet trans-
mission systems at data rates up to 11.3Gbps. The high-
sensitivity limiting amplifier limits the signal generated by
a transimpedance amplifier into a CML-level differential
output signal. All differential inputs and outputs (I/O) are
optimally back terminated for 50Itransmission line PCB
design. The MAX3945’s dual-path limiting amplifier has
programmable filtering to optimize sensitivity for differ-
ent data rates and to suppress relaxation oscillations
that could occur in some optical systems. The MAX3945
incorporates two loss-of-signal (LOS) circuits and a pro-
grammable time mask for the LOS output.
Modules
S Enables Single-Module Design Compliance
with 1000BASE-SX/LX and 10GBASE-SR/LR
Specifications
S -25.3dBm Optical Sensitivity at 1.25Gbps Using a
10.32Gbps ROSA
S Selectable 1GHz/2.1GHz/2.5GHz/3GHz Input Filters
at RATE_SEL = 0 Setting
S Supports SFF-8431 SFP+ MSA and SFF-8472
Digital Diagnostic
S Total Power Dissipation of 130mW at 3.3V Power
A 3-wire digital interface reduces the pin count and
enables control of LOS threshold, LOS polarity, LOS
mode, CML output level, input offset correction, receive
(Rx) polarity, Rx input filter, and Rx deemphasis without
the need for external components.
Supply with RSSI Monitor-Based LOS
S Total Power Dissipation of 154mW at 3.3V Power
Supply with Rx Input-Based LOS
S 4mV
P-P
Input Sensitivity at 11.3Gbps
S 4ps
S 4ps
S 5ps
DJ at 11.3Gbps with RATE_SEL = 1
DJ at 8.5Gbps with RATE_SEL = 1
DJ at 4.25Gbps with RATE_SEL = 0,
P-P
P-P
P-P
The MAX3945 is packaged in a 3mm x 3mm, 16-pin
TQFN package.
Applications
1x/2x/4x/8x SFF/SFP/SFP+ MSA Fibre-Channel
Optical Transceiver
BW1 = 1, BW0 = 1
S 9.0ps
DJ at 1.25Gbps with RATE_SEL = 0,
P-P
BW1 = 0, BW0 = 0
10GBASE-SR/LR SFP+ Optical Transceiver
10G PON ONU
S 26ps Rise and Fall Time with RATE_SEL = 1
S 52ps Rise and Fall Time with RATE_SEL = 0
Ordering Information
S CML Output with Level Adjustment and Squelch
Mode
PART
TEMP RANGE
PIN-PACKAGE
S Programmable CML Output Deemphasis
S CML Output Polarity Select
MAX3945ETE+
-40NC to +85NC
16 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
S LOS Polarity Select
S Programmable Masking Time for the LOS Output
S LOS Assert/Deassert Level Adjustment
Typical Application Circuit appears at end of data sheet.
S Choice of Rx Input-Based LOS or RSSI Monitor-
Based LOS
S 3-Wire Digital Interface Compatible with Maxim’s
SFP+ Family of Products
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
CC
V
.......................................................................-0.3V to +4.0V
Current Out of ROUT+, ROUT- ..........................................40mA
Voltage Range at SDA, SCL, CSEL,
Continuous Power Dissipation (T = +70NC)
A
LOS, CAZ, RPMIN................................. -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
16-Pin TQFN (derate 14.7mW/NC above +70NC).........1.176W
Operating Junction Temperature Range ......... -55NC to +150NC
Storage Temperature Range............................ -65NC to +160NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
CC
CC
Voltage Range at ROUT+, ROUT-........(V
- 2V) to (V
CC
Voltage Range at RIN+, RIN-........(V
- 1.7V) to (V
CC
CC
Current Range Into LOS...................................... -1mA to +5mA
Current Range Into SDA ..................................... -1mA to +1mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100Iload, C
= 0.1FF, T = -40NC to +85NC. Registers
CAZ A
are set to default values, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC, unless otherwise noted.)
A
CC
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
46.6
39.4
MAX
UNITS
Includes the CML output current,
= 400mV , RXDE_EN = 0,
P-P
LOS1_EN = 1, LOS2_EN = 0
V
62
DIFF_ROUT
Power-Supply Current
I
mA
V
CC
Includes the CML output current,
V
= 400mV , RXDE_EN = 0,
52.5
DIFF_ROUT
P-P
LOS1_EN = 0, LOS2_EN = 1
Power-Supply Voltage
Power-Supply Noise
V
2.85
3.63
100
10
CC
f < 10MHz
mV
P-P
10MHz < f < 20MHz
GENERAL
Input Data Rate
1.06
14.1
10.32
11.3
10E-12
2.75
Gbps
Input/Output SNR
BER
POWER-ON RESET (POR)
POR Deassert Threshold
POR Assert Threshold
INPUT SPECIFICATIONS
2.55
2.45
V
V
2.3
75
Differential Input Resistance
RIN+/RIN-
R
100
4
125
8
I
IN_DIFF
RATE_SEL = 1, input transition time 25ps,
10.32Gbps, PRBS23-1 pattern
Input Sensitivity
(Note 1)
V
mV
P-P
INMIN
RATE_SEL = 0, input transition time 260ps,
1.25Gbps, K28.5 pattern
1
2
Input Overload
V
1.2
V
P-P
INMAX
DUT is powered on, f P 5GHz
10
7
SDD11
SCC11
dB
dB
nA
DUT is powered on, f P 16GHz
Input Return Loss
DUT is powered on, 1GHz < f P 5GHz
DUT is powered on, 1GHz < f P 16GHz
LOS1_EN = 0 and LOS2_EN = 1,
13
5
RPMIN Input-Current High
I
50
IH
V
= 2V
RPMIN
2
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100Iload, C
= 0.1FF, T = -40NC to +85NC. Registers
CAZ A
are set to default values, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
External RPMIN Filter Capacitor
OUTPUT SPECIFICATIONS
100
pF
Differential Output Resistance
ROUT+/ROUT-
R
75
100
125
I
OUTDIFF
DUT is powered on, f P 5GHz
13
7
SDD22
SCC22
DUT is powered on, f P 16GHz
Output Return Loss
dB
DUT is powered on, 1GHz < f P 5GHz
DUT is powered on, 1GHz < f P 16GHz
10
6
5mV
PV P1200mV , RATE_SEL = 0,
IN P-P
P-P
595
595
800
800
400
1005
1005
SET_CML[7:0] = 169d (decimal)
Differential Output-Voltage High
mV
mV
P-P
10mV PV P1200mV, RATE_SEL = 1,
SET_CML[7:0] = 181d
10mV P V P 1200mV
P-P,
P-P
IN
Differential Output-Voltage
Medium
P-P
IN
300
60
515
255
15
P-P
RATE_SEL = 1, SET_CML[7:0] = 91d
SET_CML DAC Range
Decimal
mV
Differential Output Signal When
Squelched (Note 1)
Outputs AC-coupled, SET_CML[7:0] =
181d, at 8.5Gbps, SQ_EN = 1
6
P-P
60mV
P V P 400mV
at 10.32Gbps,
P-P
IN
P-P
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 25ps,
pattern 11110000
= 400mV
,
DIFF_ROUT
P-P
26
35
90
Data Output Transition Time
(20% to 80%) (Note 1)
t /t
R F
ps
10mV
P V P 1200mV
at 1.25Gbps,
P-P
IN
P-P
RATE_SEL = 0, V
= 800mV
,
52
DIFF_ROUT
P-P
input transition time 260ps, pattern 11110000
TRANSFER CHARACTERISTICS
10mV
P V P 1200mV
at 8.5Gbps,
P-P
IN
P-P
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
= 400mV
,
4
4
4
8
9
9
DIFF_ROUT
P-P
60mV
P V P 400mV
at 10.32Gbps,
P-P
IN
P-P
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
= 400mV
,
DIFF_ROUT
P-P
60mV
P V P 400mV
at 11.3Gbps,
P-P
IN
P-P
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
= 400mV
,
DIFF_ROUT
P-P
Deterministic Jitter
(Notes 1, 2)
DJ
ps
P-P
10mV P V P 1200mV at 1.25Gbps,
P-P
IN
P-P
RATE_SEL = 0, BW1 = 0, BW0 = 0,
= 800mV , input transition
9
5
30
10
V
DIFF_ROUT
P-P
time 260ps
10mV P V P 1200mV at 4.25Gbps,
P-P
P-P
IN
RATE_SEL = 0, BW1 = 1, BW0 = 1,
= 800mV , input transition
V
DIFF_ROUT
P-P
time 28ps
_______________________________________________________________________________________
3
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100Iload, C
= 0.1FF, T = -40NC to +85NC. Registers
CAZ A
are set to default values, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input = 60mV
at 10.32Gbps
P-P
,
Random Jitter
(Note 1)
RATE_SEL = 1, RXDE_EN = 0, input transi-
tion time 28ps, pattern 11110000,
RJ
0.28
0.51
ps
RMS
V
= 800mV
P-P
DIFF_ROUT
RATE_SEL = 0, C
RATE_SEL = 1, C
= 0.1FF
= 0.1FF
2
Low-Frequency Cutoff
(Simulated Value)
CAZ
kHz
0.7
1.0
2.1
2.5
3.0
9
CAZ
RATE_SEL = 0, BW1 = 0, BW0 = 0
RATE_SEL = 0, BW1 = 0, BW0 = 1
RATE_SEL = 0, BW1 = 1, BW0 = 0
RATE_SEL = 0, BW1 = 1, BW0 = 1
RATE_SEL = 1
Small-Signal Bandwidth
(Simulated Value)
f
GHz
3dB
Rx INPUT-BASED LOS SPECIFICATIONS (LOS1_EN = 1 and LOS2_EN = 0) (Note 1)
LOS Assert Sensitivity Range
SET_LOS DAC Range
LOS Hysteresis
(Note 3)
14
7
77
63
mV
P-P
Decimal
dB
10log(V
/V
)
1.25
2.3
8
2.1
20
DEASSERT ASSERT
LOS Assert/Deassert Time
Low Assert Level
(Note 4)
80
14
Fs
11
SET_LOS[5:0] = 7d (Note 3)
SET_LOS[5:0] = 32d (Note 3)
SET_LOS[5:0] = 63d (Note 3)
mV
mV
mV
P-P
P-P
P-P
Low Deassert Level
Medium Assert Level
Medium Deassert Level
High Assert Level
14
39
65
77
127
18
22
49
58
82
95
96
112
182
High Deassert Level
158
LOS Output Masking Time
Range
SET_LOSTIMER[6:0] = 0d for minimum and
SET_LOSTIMER[6:0] = 127d for maximum
0
2920
50
Fs
LOS Output Masking DAC
Resolution
SET_LOSTIMER[6:0] = 1d to 127d
23
35
Fs
RSSI MONITOR-BASED LOS SPECIFICATIONS (LOS1_EN = 0 and LOS2_EN = 1) (Note 1)
LOS Assert Sensitivity Range
SET_LOS DAC Range
LOS Hysteresis
(Note 5)
8.3
4
90
63
mV
Decimal
dB
10log(V
/V
)
1.25
2.3
5.1
9.0
45
2.1
20
DEASSERT ASSERT
LOS Assert/Deassert Time
Low Assert Level
(Note 4)
80
8.3
12.7
55
Fs
6.7
10.8
50
SET_LOS[5:0] = 4d (Note 5)
SET_LOS[5:0] = 32d (Note 5)
SET_LOS[5:0] = 63d (Note 5)
mV
mV
mV
Fs
Low Deassert Level
Medium Assert Level
Medium Deassert Level
High Assert Level
77
85
92
90
98
106
180
High Deassert Level
153
167
LOS Output Masking Time
Range
SET_LOSTIMER[6:0] = 0d for minimum and
SET_LOSTIMER[6:0] = 127d for maximum
0
2920
50
LOS Output Masking DAC
Resolution
SET_LOSTIMER[6:0] = 1d to 127d
23
35
Fs
4
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100Iload, C
= 0.1FF, T = -40NC to +85NC. Registers
CAZ A
are set to default values, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1192
828
MAX
UNITS
OUTPUT LEVEL VOLTAGE DAC (SET_CML)
100I differential resistive load,
RXDE_EN = 0
Full-Scale Voltage
V
FS
mV
mV
P-P
P-P
100I differential resistive load,
RATE_SEL = 1, RXDE_EN = 1, RXDE1 = 1,
RXDE0 = 1 (maximum deemphasis)
100I differential resistive load,
4.5
RXDE_EN = 0
Resolution
100I differential resistive load,
RATE_SEL = 1, RXDE_EN = 1, RXDE1 = 1,
RXDE0 = 1 (maximum deemphasis)
3.3
Integral Nonlinearity
INL
SET_CML[7:0] > 60d
Q0.9
LSB
LOS THRESHOLD VOLTAGE DAC (SET_LOS)
LOS1_EN = 1, LOS2_EN = 0
LOS1_EN = 0, LOS2_EN = 1
LOS1_EN = 1, LOS2_EN = 0
LOS1_EN = 0, LOS2_EN = 1
SET_LOS[5:0] > 3d
96
98
mV
P-P
Full-Scale Voltage
Resolution
V
FS
mV
1.52
1.56
Q0.7
mV
P-P
mV
Integral Nonlinearity
INL
LSB
CONTROL I/O SPECIFICATIONS
V
-
CC
0.5
LOS Output High Voltage
LOS Output Low Voltage
V
R
R
= 4.7kI to 10kI to V
= 4.7kI to 10kI to V
V
CC
V
V
OH
LOS
LOS
CC
V
0
0.4
OL
CC
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.0
V
V
V
V
IH
CC
V
0.8
IL
V
I
0.082
HYST
V
= 0V or V , internal pullup or
CC
IN
Input Leakage Current
85
FA
IL,IH
pulldown (75kI typ)
V
-
CC
0.5
Output High Voltage
Output Low Voltage
V
External pullup of 4.7kI to V
External pullup of 4.7kI to V
V
V
V
OH
CC
CC
V
0
0.4
OL
CC
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 5)
SCL Clock Frequency
SCL Pulse-Width High
SCL Pulse-Width Low
SDA Setup Time
f
0
400
1000
kHz
ns
SCL
t
500
500
CH
t
ns
CL
DS
DH
t
100
100
ns
SDA Hold Time
t
ns
SCL Rise to SDA Propagation
Time
t
5
ns
ns
D
CSEL Pulse-Width Low
t
500
CSW
_______________________________________________________________________________________
5
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100Iload, C
= 0.1FF, T = -40NC to +85NC. Registers
CAZ A
are set to default values, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CSEL Leading Time Before the
First SCL Edge
t
500
ns
L
T
CSEL Trailing Time After the Last
SCL Edge
t
500
ns
Total bus capacitance on one line with
SDA, SCL External Load
C
B
20
pF
4.7kI to V
CC
Note 1: Guaranteed by design and characterization, T = -40NC to +95NC.
A
Note 2: Deterministic jitter is measured with a repeating K28.5 pattern [00111110101100000101] for 1.25Gbps to 8.5Gbps data.
At 10.32Gbps and 11.3Gbps, a repeating K28.5 plus 59 0s and K28.5 plus 59 1s pattern is used. Deterministic jitter is
defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 3: LOS1_EN = 1, data rates of 1.25Gbps to 8.5Gbps with K28.5 pattern, and 6.4GHz input filter. For data rates of 10.32Gbps
to 11.3Gbps, the input filter is 12.5GHz and the pattern is PRBS23-1.
Note 4: Measurement includes an input AC-coupling capacitor of 100nF and C
is switched between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty
a) Signal_OFF = 0
of 100nF. The signal at the RIN or RPMIN input
CAZ
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload
Signal_OFF = 0
Signal_ON = 1.2V
P-P
max_deassert_level and min_assert_level are measured for one SET_LOS setting
Note 5: LOS1_EN = 0, LOS2_EN = 1, DC voltage applied to the RPMIN input.
6
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Typical Operating Characteristics
(V
CC
= 3.3V, T = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
A
is static during measurements.)
RECEIVE OUTPUT FROM OPTICAL SYSTEM,
10.32Gbps, OPTICAL INPUT -10dBm,
RECEIVE OUTPUT FROM OPTICAL SYSTEM,
10.32Gbps, OPTICAL INPUT -15dBm,
RECEIVE OUTPUT FROM OPTICAL SYSTEM,
10.32Gbps, OPTICAL INPUT -20dBm,
RXDE1 = 1, RXDE0 = 0
RXDE1 = 1, RXDE0 = 0
RXDE1 = 1, RXDE0 = 0
MAX3945 toc01
MAX3945 toc02
MAX3945 toc03
K28.5 PATTERN AT 1.25Gbps,
SET_CML[7:0] = 169d,
K28.5 PATTERN AT 4.25Gbps,
SET_CML[7:0] = 169d,
RATE_SEL = 0, BW0 = 0, BW1 = 0
RATE_SEL = 0, BW0 = 1, BW1 = 1
OPTICAL BER CURVES (NEC NR3312)
MAX3945 toc05
MAX3945 toc06
1.00E-01
10.3Gbps, PRBS31, RATE_SEL = 1
8.5Gbps, PRBS9, RATE_SEL = 1
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
4.5Gbps, PRBS9, RATE_SEL = 1
4.5Gbps, PRBS9, RATE_SEL = 0,
BW1 = 1, BW0 = 1
1.25Gbps, PRBS9, RATE_SEL = 0,
BW1 = 1, BW0 = 1
1.25Gbps, PRBS9, RATE_SEL = 0, BW1 = 0, BW0 = 0
200ps/div
50ps/div
-27
-26
-25
-24
-23
-22
-21
AVERAGE POWER dBm (Er~12dB)
K28.5 PATTERN AT 10.3Gbps,
SET_CML[7:0] = 148d,
K28.5 PATTERN AT 11.3Gbps,
SET_CML[7:0] = 148d,
K28.5 PATTERN AT 8.5Gbps, SET_CML[7:0] = 148d,
RATE_SEL = 1, RXDE_EN = 0
RATE_SEL = 1, RXDE_EN = 0
RATE_SEL = 1, RXDE_EN = 0
MAX3945 toc07
MAX3945 toc08
MAX3945 toc09
20ps/div
18ps/div
18ps/div
_______________________________________________________________________________________
7
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
A
is static during measurements.)
DEEMPHASIS VALUE
vs. SET_CML DAC SETTING
(RATE_SEL = 1)
DIFFERENTIAL OUTPUT SIGNAL LEVEL
Rx INPUT-BASED LOS THRESHOLD vs. DAC
CODE (LOS1_EN = 1 AND LOS2_EN = 0)
vs. SET_CML DAC SETTING
1200
1100
1000
900
160
140
120
100
80
RXDE1 = 1, RXDE0 = 1
6
4
2
0
RXDE_EN = 0
DEASSERT
RXDE1 = 1, RXDE0 = 0
RXDE1 = 0, RXDE0 = 1
RXDE1 = 0, RXDE0 = 0
RXDE1 = 0, RXDE0 = 1
800
RXDE1 = 0,
RXDE0 = 0
RXDE1 = 1,
RXDE0 = 0
700
60
ASSERT
600
40
RXDE1 = 1,
RXDE0 = 1
500
20
RXDE_EN = 0
400
0
50
100
150
200
250
300
50
100
150
200
250
0
10
20
30
40
50
60
70
SET_CML DAC SETTING
SET_CML DAC SETTING
SET_LOS[5:0] DAC CODE
DETERMINISTIC JITTER vs. INPUT AMPLITUDE AT 1.25Gbps
RSSI MONITOR-BASED LOS THRESHOLDS
(LOS1_EN = 0 AND LOS2_EN = 1)
(K28.5 PATTERN, 933MHz INPUT FILTER)
LOS MASKING TIME vs. DAC SETTING
25
180
160
140
120
100
80
5000
4000
3000
2000
1000
0
RATE_SEL = 0, BW1 = 0, BW2 = 0
20
15
10
5
DEASSERT
60
ASSERT
40
20
0
0
200
400
600
800 1000 1200
0
10
20
30
40
50
60
70
0
20
40
60
80
100 120
SIGNAL AMPLITUDE (mV
)
SET_LOS[5:0] DAC CODE
SET_LOSTIMER[6:0] DAC CODE
P-P
DETERMINISTIC JITTER AT 10.32Gbps
(PRBS7 PATTERN WITH 100 CIDs, RATE_SEL = 1)
DETERMINISTIC JITTER vs. DATA RATE
(INPUT = 100mV
POWER-SUPPLY CURRENT vs. TEMPERATURE
)
(SET_CML[7:0] = 91d)
P-P
10
25
20
15
10
5
80
K28.5 PATTERN, RATE_SEL = 1
9
8
7
6
5
4
3
2
1
0
70
60
LOS2_EN = 0 AND LOS1_EN = 1
50
DJ WITH 100mV NOISE
P-P
ON POWER SUPPLY
40
LOS2_EN = 1 AND LOS1_EN = 0
30
DJ WITH NO NOISE ON POWER SUPPLY
0
20
0
200
400
600
800 1000 1200
0
3
6
9
12
-40 -20
0
20
40
60
80 100
INPUT SIGNAL AMPLITUDE (mV
)
DATA RATE (Gbps)
TEMPERATURE (°C)
P-P
8
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
A
is static during measurements.)
INPUT RETURN GAIN (SDD11)
(INPUT POWER OF 0dBm, ENABLED)
OUTPUT RETURN GAIN (SDD22)
(INPUT POWER OF 0dBm, ENABLED)
INPUT COMMON-MODE RETURN GAIN (SCC11)
(INPUT POWER OF 0dBm, ENABLED)
0
0
-10
-20
-30
-40
0
-10
-20
-30
-40
-10
-20
-30
-40
0
1
10
100
0
1
10
100
1
10
100
FREQUENCY (GHz)
FREQUENCY (GHz)
FREQUENCY (GHz)
OUTPUT COMMON-MODE RETURN GAIN (SCC22)
TRANSIENT RESPONSE (10.3Gbps,
10 ONES 10 ZEROS PATTERN, SET_CML[7:0] = 92d)
0.25
(INPUT POWER OF 0dBm, ENABLED)
0
0.20
0.15
-10
-20
-30
-40
0.10
0.05
0
A = 1.39dB, RXDE1 = 0, RXDE0 = 0
B = 2.12dB, RXDE1 = 0, RXDE0 = 1
C = 3.27dB, RXDE1 = 1, RXDE0 = 0
D = 4.37dB, RXDE1 = 1, RXDE0 = 1
-0.05
-0.10
-0.15
-0.20
-0.25
A
C
B
D
0
200
400
600
800
1000
1
10
100
TIME (ps)
FREQUENCY (GHz)
ELECTRICAL EYE DIAGRAM AFTER 6in OF FR4
AND 72in OF CABLE WITH NO DEEMPHASIS (11.3Gbps K28.5,
ELECTRICAL EYE DIAGRAM AFTER 6in OF FR4
AND 72in OF CABLE WITH DEEMPHASIS (11.3Gbps K28.5, RATE_SEL = 1,
RATE_SEL = 1, SET_CML[7:0] = 160d, RXDE_EN = 0)
SET_CML[7:0] = 160d, RXDE_EN = 1, RXDE0 = 1, RXDE1 = 1)
MAX3945 toc24
MAX3945 toc25
20ps/div
20ps/div
_______________________________________________________________________________________
9
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Pin Configuration
TOP VIEW
12
11
10
9
V
V
13
8
7
6
5
CCR
CCR
RIN- 14
RIN+ 15
ROUT-
ROUT+
MAX3945
*EP
V
V
16
CCR
CCR
+
1
2
3
4
THIN QFN
(3mm × 3mm)
*THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Pin Description
PIN
1
NAME
FUNCTION
Offset-Correction Loop Capacitor. A capacitor connected between this pin and the adjacent V pin sets
EE
the time constant of the offset-correction loop. The offset correction can be disabled through the digital
interface by setting bit AZ_EN=0 and by connecting this pin to ground.
CAZ
2, 3
V
Ground for Limiting Amplifier
EE
Loss-of-Signal Output. This output is an open-drain output. LOS is asserted when the level of the input
signal drops below the preset threshold set by SET_LOS[5:0]. LOS is deasserted when the signal level
is above the threshold. The polarity of the LOS output can be inverted by setting LOS_POL = 0. The LOS
circuitry can be disabled by setting LOS1_EN = 0 and LOS2_EN = 0. See Table 8.
4
LOS
5, 8, 13,
16
Power Supply. Provides supply voltage to the limiting amplifier. All pins must be connected to the supply
voltage.
V
CCR
6
7
9
ROUT+
ROUT-
SCL
Noninverted Output, CML. Back terminated for 50I load.
Inverted Output, CML. Back terminated for 50I load.
Serial-Clock Input, TTL/CMOS. This pin has a 75kI internal pulldown.
Serial-Data Bidirectional I/O. TTL/CMOS input and open-drain output. This pin has a 75kI internal pul-
lup, but it requires an external 4.7kI pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
10
SDA
Chip-Select Input, TTL/CMOS. Internally pulled down by a 75kI resistor. CSEL = 1 starts an SPI cycle,
while CSEL = 0 ends the SPI cycle and resets the control state machine.
11
CSEL
12
14
15
—
RPMIN
RIN-
RIN+
EP
High-Impedance Receive Power-Monitor Input. Connect to ground when not used.
Inverted Data Input, CML, with 50I Termination
Noninverted Data Input, CML, with 50I Termination
Exposed Pad. Must be soldered to circuit ground.
10 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
bandwidth for a given data rate. Table 1 summarizes
Detailed Description
the RATE_SEL, BW1, and BW0 control bit functions. The
high data-rate mode (RATE_SEL = 1) is recommended
for operation up to 11.3Gbps.
The MAX3945 is designed to operate from 1.0625Gbps
to 11.3Gbps. It consists of a dual-path limiter, offset-
correction circuitry, CML output stage, and LOS circuitry.
The characteristics of the MAX3945 can be controlled
through the on-chip 3-wire interface. The registers that
control the part’s functionality are RXCTRL1, RXCTRL2,
RXSTAT, SET_CML, SET_LOS, MODECTRL, and SET_
LOSTIMER. The MAX3945 provides integrated DACs to
allow the use of low-cost controller ICs. Figure 1 shows
simplified input and output structures.
The polarity of ROUT+/ROUT- relative to RIN+/RIN- is
programmed by the RX_POL bit, as shown in Table 2.
Offset-Correction Circuitry
The offset-correction circuitry is provided to remove
PWD caused by intrinsic offset voltages within the dif-
ferential amplifier stages. An external 0.1FF capacitor
connected between the CAZ pin and ground sets the
offset-correction loop cutoff frequency to approximately
2kHz when RATE_SEL = 0 and to approximately 0.7kHz
when RATE_SEL = 1. The offset-correction loop can be
disabled using the AZ_EN bit, as shown in Table 3.
Dual-Path Limiter
The limiting amplifier features a low data-rate path
(1.0625Gbps to 4.25Gbps) and a high data-rate path
(up to 11.3Gbps), allowing for overall system optimiza-
tion. Figure 2 shows the functional diagram. Data path
selection is controlled by the RATE_SEL bit. The low
data-rate path further features a programmable filter
that provides optimization for 1.0625Gbps, 1.25Gbps,
2.125Gbps, and 4.25Gbps operation. It is important to
tailor the bandwidth of the first stages to get the best
receive sensitivity and to reduce the maximum receive
CML Output Stage
CML Output Enable and Squelch
The CML output stage is optimized for differential 100I
loads. The output stage is controlled by a combination of
the RX_EN and SQ_EN bits and the internal LOS status.
See Table 4.
Table 1. Rate Select and Bandwidth Control
RXCTRL1[3:1]
OPERATION MODE DESCRIPTION
DATA RATE
(Gbps)
FILTER BANDWIDTH
(MHz)
RISE/FALL TIME
(ps)
BW1
BW0
RATE_SEL
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
1.0625 to 1.25
2.125
1000
2100
2500
3000
9000
52
52
52
52
26
2.125
4.25
11.3
Table 2. Signal Polarity Control
Table 3. Offset-Correction Enable/Disable
Control
RX_POL
OPERATION MODE DESCRIPTION
0
1
Inversed polarity of the differential signal path
Normal polarity of the differential signal path
AZ_EN
OPERATION MODE DESCRIPTION
0
1
Autozero loop is disabled
Autozero loop is enabled
Table 4. CML Output Stage Operation Modes
RX_EN
SQ_EN
LOS STATUS
OPERATION MODE DESCRIPTION
CML output disabled
0
1
1
1
X
0
1
1
X
X
0
1
CML output enabled
CML output enabled
CML output disabled
______________________________________________________________________________________ 11
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
V
V
CCR
CCR
DEEMPHASIS
CONTROL
50Ω
50Ω
ROUT+
ROUT-
RIN+
50Ω
50Ω
V
- 1V
CCR
RIN-
V
CCD
V
EER
V
EER
V
CCD
75kΩ
LOS
SDA
376Ω
CLAMP
SCL, CSEL
75kΩ
V
EET
V
V
EER
EER
V
CCR
2kΩ
2kΩ
COMPARATOR
RPMIN
2pF
DAC
Figure 1. Simplified Input/Output Structures
12 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
V
CCR
CAZ
V
CCR
R
R
OUT
MAX3945
OUT
ROUT+
ROUT-
DIGITAL OFFSET CORRECTION
RXDE1
RXDE0
DEEMPHASIS
AZ_EN
V
CCR
- 1V
LPF
4G
1
1
0
R
IN
R
IN
RIN+
RIN-
0
10G
MX
RX_POL
LOSS OF SIGNAL
BW1 BW0
RATE_SEL
RX_EN
SQ_EN
OUTPUT
CTRL LOGIC
RPMIN
LOS
V
CCR
LOS_POL
LOS2/1_EN
R
PULL
6b DAC SET_LOS
CONTROL
LOGIC
SDA
SCL
3-WIRE
INTERFACE
7b DAC SET_LOSTIMER
8b DAC SET_CML
INTERNAL
REGISTER
CSEL
R
R
PULL
PULL
V
EE
Figure 2. Functional Diagram
CML Output Deemphasis
Programmable CML Output Amplitude
The CML output stage is optimized for differential 100I
transmission lines on a standard FR4 board. The RXDE1
and RXDE0 bits add programmable analog output
deemphasis to compensate for FR4 board losses and
SFP connector losses. Table 5 describes the deempha-
sis control settings.
The 8-bit SET_CML register controls the amplitude of the
CML output stage. The maximum programmable output
level depends on the operational mode of the MAX3945.
These output levels (which assume an ideal 100I dif-
ferential load) and their corresponding control bits are
described in Table 6. Table 7 shows the output DAC
resolution dependency.
______________________________________________________________________________________ 13
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 5. Output Signal Deemphasis Control
RXCTRL2[1]
RXCTRL1[7:6]
OPERATION MODE DESCRIPTION
MODE
DEEMPHASIS
(dB)
RXDE_EN
RXDE1
RXDE0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Deemphasis block is disabled
0
Deemphasis block is enabled Level 1
Deemphasis block is enabled Level 2
Deemphasis block is enabled Level 3
Deemphasis block is enabled Level 4
0.3
1.1
2.1
4.3
Table 6. CML Output Amplitude Range (Typical)
OUTPUT
AMPLITUDE
RXCTRL1[1]
RXCTRL2[1]
RXCTRL1[7:6]
MODE
RATE_SEL
RXDE_EN
RXDE1 RXDE0
(mV
)
P-P
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
Low data-rate path
400 to 1192
400 to 1147
400 to 1041
400 to 987
400 to 908
400 to 828
High data-rate path
High data-rate path with deemphasis
High data-rate path with deemphasis
High data-rate path with deemphasis
High data-rate path with deemphasis
Table 7. CML Output DAC Resolution (Typical)
RXCTRL1[1]
RXCTRL2[1]
RXCTRL1[7:6]
RXDE1 RXDE0
RESOLUTION
MODE
(mV )
P-P
RATE_SEL
RXDE_EN
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
Low data-rate path
4.5
High data-rate path
4.5
4.1
3.9
3.6
3.3
High data-rate path with deemphasis
High data-rate path with deemphasis
High data-rate path with deemphasis
High data-rate path with deemphasis
14 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 8. LOS Control
LOS2_EN
LOS1_EN
OPERATION MODE DESCRIPTION
LOS circuitry is disabled and powered down
0
X
1
0
1
0
LOS circuitry is enabled and Rx input amplitude is detected
LOS circuitry is enabled and RPMIN input amplitude is detected
LOS Circuitry
The LOS circuitry has two operational modes controlled
by the LOS1_EN and LOS2_EN bits (see Table 8). In the
first mode, the LOS block detects the differential ampli-
tude of the input signal and compares it against a preset
threshold controlled by the 6-bit SET_LOS register. In
the second mode, the LOS block compares the voltage
at the RPMIN pin to a preset threshold also controlled by
the 6-bit SET_LOS register. The second mode enables
low-power LOS detection based on average photodiode
current.
50mV/div
2mV/div
The LOS assert threshold is approximately 1.5mV
x
P-P
400µs/div
SET_LOS[5:0]. The LOS deassert level is approximately
1.6 times the assert level to avoid LOS chatter. LOS
polarity, squelch, and LOS masking time are unaffected
by the selection of LOS1_EN or LOS2_EN.
Figure 3. LOS Response to a Short Burst of Input Signal
Programmable LOS Output Masking Time
This feature masks false input signals that can occur
after a loss-of-light event in a fiber optic link. These false
input signals, caused by some transimpedance amplifier
implementations, can corrupt the LOS output and cause
system-level link diagnostic errors.
50mV/div
The LOS output masking time can be programmed from 0
to 4500Fs in 35Fs steps using the 7-bit SET_LOSTIMER[6:0]
register. The output mask timer is initiated on the first
transition of the LOS signal and prevents any further
changes in the LOS output signal until the end of the
programmed LOS timing period. The LOS output mask-
ing time should be carefully chosen to extend beyond
any expected input glitch. Figure 3 shows the LOS signal
changing after approximately 800Fs to a change in the
input signal where the LOS output masking time function
is not used. Figure 4 shows masking of the LOS signal
by the LOS output masking time function to a change in
the input signal.
2mV/div
400µs/div
Figure 4. LOS Response to a Short Burst of Input Signal (Any
changes in LOS are masked until the end of the LOS masking
period.)
______________________________________________________________________________________ 15
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 9. Digital Communication Word Structure
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Address
RWN
Data that is written or read.
Table 10. Register Descriptions and Addresses
ADDRESS
H0x00
H0x01
H0x02
H0x03
H0x04
H0x0E
H0x12
NAME
RXCTRL1
FUNCTION
Receiver Control Register 1
Receiver Control Register 2
Receiver Status Register
RXCTRL2
RXSTAT
SET_CML
SET_LOS
CML Output Level Setting Register
LOS Threshold Assert Level Setting Register
General Control Register
MODECTRL
SET_LOSTIMER
LOS Timer Setting Register
line at falling edge of the clock. The master closes the
transmission by setting CSEL to 0. Figure 5 shows the
interface timing, and Table 11 defines the various timing
parameters.
3-Wire Digital Communication
General
The MAX3945 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL has been set to
1. All data transfers are most significant bit (MSB) first.
Read Mode (RWN = 1)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at falling edge of the clock. The SDA line is released after
the RWN bit has been transmitted. The slave outputs 8
bits of data (MSB first) at rising edge of the clock. The
master closes the transmission by setting CSEL to 0.
Figure 5 shows the interface timing.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
MAX3945. The RWN bit determines if the cycle is read
or write. See Table 9.
Mode Control
Normal mode allows read-only instruction for all registers
except MODECTRL. Normal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the RXSTAT register. To enter
setup mode, the MODECTRL register (address = H0x0E)
must be set to H0x12. After the MODECTRL register has
been set to H0x12, the next operation is unrestricted.
The setup mode is automatically exited after the next
operation is finished. This sequence must be repeated if
further unrestricted settings are necessary.
Register Addresses
The MAX3945 contains seven registers available for pro-
gramming. Table 10 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
16 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
WRITE MODE
CSEL
SCL
t
L
t
T
t
t
CH CL
0
1
2
3
4
5
6
7
8
9
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
t
DS
SDA
A6
A5
A4
A3
A2
A1
A0
RWN
D7
D6
t
DH
READ MODE
CSEL
SCL
t
L
t
T
t
t
CH CL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
t
D
DS
SDA
A6
A5
A4
A3
A2
A1
A0
RWN
D7
D6
D5
D4
D3
D2
D1
D0
t
DH
Figure 5. Timing for the 3-Wire Digital Interface
Table 11. Interface Timing Parameters
SYMBOL
DEFINITION
t
CSEL leading time before the first SCL edge
SCL pulse-width high
L
t
CH
t
SCL pulse-width low
CL
t
SCL rise to SDA propagation time
SDA setup time
D
t
DS
DH
t
SDA hold time
t
CSEL trailing time after last SCL edge
T
Register Descriptions
Receiver Control Register 1 (RXCTRL1)
Bit #
7
RXDE1
0
6
RXDE0
0
5
X*
1
4
SOFTRES
0
3
BW1
1
2
BW0
1
1
RATE_SEL
1
0
X*
1
ADDRESS
Name
H0x00
Default Value
*Do not change default setting.
Bits 7 and 6: RXDE[1:0]. These 2 bits are used to control deemphasis of the output waveform. See Table 5 for the bit
settings and corresponding deemphasis levels.
Bit 4: SOFTRES. When this bit is set to 1 during a 3-wire interface write operation, all registers are set to the default
state when CSEL goes low.
Bits 3 and 2: BW[1:0]. When RATE_SEL = 0, these 2 bits control the bandwidth of the limiting amplifier. See Table 1 for
the settings and corresponding filter selection.
Bit 1: RATE_SEL. RATE_SEL selects between the low bandwidth data path (1.0625Gbps to 4.25Gbps) and the high
bandwidth data path (4.25Gbps to 11.3Gbps). When RATE_SEL is set to 1, the high bandwidth path is chosen. When
RATE_SEL is set to 0, the low bandwidth path is chosen.
______________________________________________________________________________________ 17
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Receiver Control Register 2 (RXCTRL2)
Bit #
7
6
5
4
RX_POL
1
3
SQ_EN
0
2
RX_EN
1
1
RXDE_EN
0
0
AZ_EN
1
ADDRESS
Name
LOS2_EN LOS1_EN LOS_POL
H0x01
Default Value
0
1
1
Bit 7: LOS2_EN. Enables or disables the RSSI monitor-based LOS circuitry, in combination with the LOS1_EN bit. The
below table shows when the RSSI monitor-based LOS is disabled and enabled.
LOS2_EN
LOS1_EN
RX_EN
Rx INPUT-BASED LOS
Disabled and powered down
Enabled
RSSI MONITOR-BASED LOS
Disabled and powered down
Disabled and powered down
Disabled and powered down
Disabled and powered down
Enabled
0
0
X
1
1
1
0
1
1
1
0
0
X
1
0
1
0
1
Disabled and powered down
Enabled
Disabled and powered down
Disabled and powered down
Enabled
Bit 6: LOS1_EN. Controls the Rx input-based LOS circuitry. When RX_EN is set to 0, the LOS detector is also disabled.
0 = disabled
1 = enabled
Bit 5: LOS_POL. Controls the polarity of the LOS pin.
0 = inverse
1 = normal
Bit 4: RX_POL. Controls the polarity of the CML output.
0 = inverse
1 = normal
Bit 3: SQ_EN. When SQ_EN = 1, the CML output is squelched when LOS is asserted.
0 = disabled
1 = enabled
Bit 2: RX_EN. Enables or disables the receive circuitry.
0 = disabled
1 = enabled
Bit 1: RXDE_EN. Enables or disables the deemphasis on the CML output.
0 = disabled
1 = enabled
Bit 0: AZ_EN. Enables or disables the autozero circuitry.
0 = disabled
1 = enabled
18 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Receiver Status Register (RXSTAT)
1
0
Bit #
7
6
5
4
3
2
ADDRESS
(STICKY) (STICKY)
Name
X
X
X
X
X
X
X
X
X
X
X
X
POR_2d
X
LOS_2d
X
H0x02
Default Value
Bit 1: POR_2d. When the V
supply voltage is below 2.3V, the POR circuitry sets POR_2d high. When the supply
CC
voltage is above 2.75V, the POR circuitry deasserts, but the POR_2d bit remains high until it is read.
Bit 0: LOS_2d. Copy of the LOS status. This is a sticky bit, which means that it is cleared on a read. The first 0-to-1
transition is latched until the bit is read by the master or POR occurs.
CML Output Level Setting Register (SET_CML)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
SET_CML[7]
(MSB)
SET_CML[0]
(LSB)
Name
SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1]
H0x03
Default Value
0
1
0
1
1
1
0
0
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set up to 255 for maximum CML
output amplitude. See Table 13 for equations to determine CML output level vs. SET_CML.
LOS Threshold Assert Level Setting Register (SET_LOS)
Bit #
7
X
X
6
X
X
5
4
3
2
1
0
ADDRESS
SET_LOS[5]
(MSB)
SET_LOS[0]
(LSB)
Name
SET_LOS[4] SET_LOS[3] SET_LOS[2] SET_LOS[1]
H0x04
Default Value
0
0
1
1
0
0
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the
Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code for both the Rx input-based
LOS and the RSSI monitor-based LOS.
______________________________________________________________________________________ 19
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
General Control Register (MODECTRL)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
MODECTRL[7]
(MSB)
MODECTRL[0]
(LSB)
MODECTRL[6] MODECTRL[5] MODECTRL[4] MODECTRL[3] MODECTRL[2] MODECTRL[1]
Name
H0x0E
Default
Value
0
0
0
0
0
0
0
0
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The setup
mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation.
LOS Timer Setting Register (SET_LOSTIMER)
Bit #
7
X
X
6
5
4
3
2
1
0
ADDRESS
SET_
LOSTIMER[6]
(MSB)
SET_
LOSTIMER[0]
(LSB)
SET_
SET_
SET_
SET_
SET_
Name
LOSTIMER[5] LOSTIMER[4] LOSTIMER[3] LOSTIMER[2] LOSTIMER[1]
H0x12
Default Value
0
0
0
0
0
0
0
Bits 6 to 0: SET_LOSTIMER[6:0]. The SET_LOSTIMER register is a 7-bit register that can be set from 0 to 127. See
the Typical Operating Characteristics section for a typical timer period vs. DAC code.
Table 12. Register Map
REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL SETUP
BIT NUMBER/
TYPE
DEFAULT
VALUE
BIT NAME
RXDE1
NOTES
MODE
MODE
Rx deemphasis
MSB control with
RXDE_EN = 1
R
RW
7
6
0
0
Rx deemphasis
LSB control with
RXDE_EN = 1
R
RW
RXDE0
R
R
RW
RW
5
4
X
1
0
Must be set to 1
Soft reset control
bit
SOFTRES
Receiver
Control
Register 1
Address =
H0x00
Input bandwidth
control with
RATE_SEL = 0:
00: 1GHz
01: 2.1GHz
10: 2.5GHz
11: 3GHz
RXCTRL1
R
R
RW
RW
3
2
BW1
BW0
1
1
Rate-select con-
trol
0: 1G/4G mode
1: fast mode
R
R
RW
RW
1
0
RATE_SEL
X
1
1
Must be set to 1
20 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 12. Register Map (continued)
REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL SETUP
BIT NUMBER/
TYPE
DEFAULT
VALUE
BIT NAME
NOTES
MODE
MODE
RSSI monitor-
based LOS
R
RW
7
6
LOS2_EN
0
1
0: disabled
1: enabled when
LOS1_EN = 0
Rx input-based
LOS
0: disabled
1: enabled
R
RW
LOS1_EN
LOS polarity
0: inverse
1: normal
R
R
R
R
R
RW
RW
RW
RW
RW
5
4
3
2
1
LOS_POL
RX_POL
SQ_EN
1
1
0
1
0
Receiver
Control
Rx polarity
0: inverse
1: normal
Register 2
Address =
H0x01
RXCTRL2
Squelch
0: disabled
1: enabled
Rx control
0: disabled
1: enabled
RX_EN
Rx deemphasis
0: disabled
RXDE_EN
1: enabled
Rx autozero
control
0: disabled
1: enabled
R
RW
0
AZ_EN
1
Receiver
Status
Register
Address =
H0x02
POR -> V
limit violation
low
CC
R
R
R
R
1 (sticky)
0 (sticky)
POR_2d
LOS_2d
X
X
RXSTAT
Copy of LOS
status
______________________________________________________________________________________ 21
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Table 12. Register Map (continued)
REGISTER
FUNCTION/
ADDRESS
REGISTER
NAME
NORMAL SETUP
BIT NUMBER/
TYPE
DEFAULT
VALUE
BIT NAME
NOTES
MODE
MODE
MSB output level
DAC
R
RW
7
SET_CML[7]
0
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
6
5
4
3
2
1
SET_CML[6]
SET_CML[5]
SET_CML[4]
SET_CML[3]
SET_CML[2]
SET_CML[1]
1
0
1
1
1
0
CML Output
Level
Setting
Register
Address =
H0x03
SET_CML
LSB output level
DAC
R
R
RW
RW
0
5
SET_CML[0]
SET_LOS[5]
0
0
MSB LOS thresh-
old DAC
LOS
Threshold
Assert Level
Setting
Register
Address =
H0x04
R
R
R
R
RW
RW
RW
RW
4
3
2
1
SET_LOS[4]
SET_LOS[3]
SET_LOS[2]
SET_LOS[1]
0
1
1
0
SET_LOS
LSB LOS thresh-
old DAC
R
RW
RW
0
7
SET_LOS[0]
0
0
MSB mode con-
trol
RW
MODECTRL[7]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
6
5
4
3
2
1
MODECTRL[6]
MODECTRL[5]
MODECTRL[4]
MODECTRL[3]
MODECTRL[2]
MODECTRL[1]
0
0
0
0
0
0
General
Control
Register
Address =
H0x0E
MODECTRL
LSB mode con-
trol
RW
RW
0
MODECTRL[0]
0
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
6
5
4
3
2
1
0
SET_LOSTIMER[6]
SET_LOSTIMER[5]
SET_LOSTIMER[4]
SET_LOSTIMER[3]
SET_LOSTIMER[2]
SET_LOSTIMER[1]
SET_LOSTIMER[0]
0
0
0
0
0
0
0
MSB LOS timer
LOS Timer
Setting
Register
Address =
H0x12
SET_LOSTIMER
LSB LOS timer
22 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Select the Offset-Correction Capacitor
Design Procedure
Programming CML Output Levels
The capacitor between CAZ and ground determines the
time constant of the signal path DC-offset cancellation
loop. A 0.1FF capacitor between CAZ and ground is
recommended for the MAX3945.
See Tables 13 and 14. For each value of the bits
RXDE1 and RXDE0 in Table 13, the value of deempha-
sis does vary with the SET_CML[7:0] setting. In Table
13, the values of deemphasis are given for the setting
SET_CML[7:0] = 120d. The variation of deemphasis for
other values of SET_CML[7:0] is shown in the Typical
Operating Characteristics (see the Deemphasis Value
vs. SET_CML DAC Setting (RATE_SEL = 1) graph). Note
that even though RXDE_EN = 0, there is still some deem-
phasis for RATE_SEL=1forvaluesofamplitudecontrolbelow
SET_CML[7:0] = 170d.
Applications Information
Layout Considerations
Use good, high-frequency layout techniques and mul-
tiple-layer boards with uninterrupted ground planes to
minimize EMI and crosstalk.
Exposed-Pad Package
The exposed pad on the 16-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the MAX3945 and
must be soldered to the circuit board ground for proper
thermal and electrical performance. Refer to Application
Note 862: HFAN-08.1: Thermal Considerations of QFN
and Other Exposed-Paddle Packages for additional
information.
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors C and C
IN
OUT
should be selected to minimize the receiver’s determin-
istic jitter. Jitter is decreased as the input low frequency
cutoff (f ) is decreased: f
= 1/[2G(50)(C )]. The
IN
IN
IN
recommended value of C and C
is 0.1FF for the
IN
OUT
MAX3945.
Table 13. CML Output Amplitude Equations (Typical)
RXCTRL1[1]
RXCTRL2[1]
RXCTRL1[7:6]
RXDE1 RXDE0
DEEMPHASIS (dB)
(SET_CML[7:0] = 120d)
EQUATION FOR (V
- V
)
ROUT+
ROUT-
RATE_SEL
RXDE_EN
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
45mV
+ 4.5mV
x SET_CML
P-P
P-P
X
0
0
1
1
X
0
1
0
1
0.72
1.17
1.89
2.48
3.86
4.5mV
x SET_CML
P-P
-4mV
-7mV
+ 4.1mV
+ 3.9mV
x SET_CML
x SET_CML
P-P
P-P
P-P
P-P
-10mV
-13mV
+ 3.6mV
+ 3.3mV
x SET_CML
x SET_CML
P-P
P-P
P-P
P-P
Table 14. SET_CML DAC Codes for 400mV
and 800mV
Output Levels
P-P
P-P
RXCTRL1[1]
RXCTRL2[1]
RXCTRL1[7:6]
SET_CML DAC CODE
RATE_SEL
RXDE_EN
RXDE1
RXDE0
400mV
80
800mV
169
P-P
P-P
0
1
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
91
181
98
194
106
115
126
208
225
245
______________________________________________________________________________________ 23
1.0625Gbps to 11.3Gbps,
SFP+ Dual-Path Limiting Amplifier
Typical Application Circuit
SFP
SFP+ OPTICAL RECEIVER
HOST BOARD
CONNECTOR
+3.3V
SUPPLY
FILTER
HOST
FILTER
VCC_RX
0.1µF
+3.3V
4.7kΩ
EP
V
CAZ
EE
V
CCR
LOS
C
IN
0.1µF
0.1µF
RIN+
RIN-
ROUT+
ROUT-
MAX3945
11.3Gbps
Z
DIFF
= 100Ω
0.1µF
C
OUT
0.1µF
I
RPMIN
10G PIN
FLEX ROSA
RPMIN
100pF
R
RPMIN
2kΩ
SCL
3-WIRE
INTERFACE
SDA
CSEL
POWER-ON RESET
3-WIRE
INTERFACE
MODE_DEF2 (SDA)
MODE_DEF1 (SCL)
RATE SELECT
2
I C
SFP+
CONTROLLER
ADC
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0136
16 TQFN-EP
T1633+5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
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2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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