MAX3950EVKIT [MAXIM]
Evaluation Kit for the MAX3950 ; 评估板MAX3950\n
| 型号： | MAX3950EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Evaluation Kit for the MAX3950
|
| 文件： | 总6页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1866; Rev 0; 12/00
MAX3950 Evaluation Kit
General Description
Features
o +3.3V Single Supply
The MAX3950 evaluation kit (EV kit) is an assembled
surface-mount demonstration board that provides easy
evaluation of the MAX3950 10Gbps, 1:16 deserializer
with low-voltage differential signal (LVDS) outputs. All
components necessary to interface with 3.3V CML
inputs and LVDS outputs are included on the EV kit.
o 9.95Gbps/10.7Gbps Evaluation
o Fully Assembled and Tested Surface-Mount
Board
Component List
Ordering Information
PART
TEMP. RANGE
IC-PACKAGE
DESIGNATION
QTY
DESCRIPTION
MAX3950EVKIT
-40 C to +85 C
68 QFN
1000pF 10ꢀ ceramic
capacitors (0402)
C1, C10−C13
5
Murata GRM36X7R102K050A
0.01µF 10ꢀ ceramic
capacitors (0402)
Murata GRM36X7R103K016A
C2, C6−C9,
C14–C17
9
33µF 10ꢀ, 10V min tantalum
capacitor, AVX TAJC336K035
C3
C4
1
1
2.2µF 10ꢀ, 16V min tantalum
capacitor, AVX TAJC225K016
0.1µF 10ꢀ ceramic capacitor
(0603)
Murata GRM39X7R104K016A
C5
1
Component Suppliers
J1, J2, J7−J38
J3−J6
34
4
SMB connectors (PC mount)
SMA connectors (edge mount)
Test points
SUPPLIER
AVX
PHONE
FAX
843-626-3123
—
843-448-9411
770-684-7821
Murata
J39, J40
J41–J46
J47
2
Note: Please indicate that you are using the MAX3950 when
6
Not installed
contacting the suppliers.
×
2 10 header (0.1in center)
1
56nH inductor
Coilcraft 0805HS-560TKBC
L1
1
R1−R17
U1
17
1
Not installed
MAX3950EGK 68-pin QFN
MAX3950 EV kit circuit board
MAX3950 data sheet
None
None
None
1
1
1
MAX3950 EV kit data sheet
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX3950 Evaluation Kit
Shunt Configuration of J47
Detailed Description
✕
The 2 10 header on J47 should be shunted as shown
in Figure 1. Other jumper arrangements will cause the
IC to operate erroneously.
The MAX3950 EV kit simplifies evaluation of the
MAX3950 1:16 deserializer. The EV kit operates from a
single +3.3V supply and includes all the external com-
ponents necessary to interface with 3.3V CML inputs
and LVDS outputs. Transmission line test structures are
included on the evaluation board to allow for measure-
ment of signal loss and dispersion of clock and data
signals at 10GHz.
Applications information
Connecting LVDS Outputs to 50
Oscilloscope Inputs
To monitor LVDS signals with 50 oscilloscope inputs,
set the inputs of the oscilloscope to “AC coupling” or
place a DC block in series with each output. If you are
observing only one output with a 50 probe, balance
the complementary output with a DC block and a 50
terminator to ground.
Figure 1. Shunt Arrangement for J47
Layout Consideration
The MAX3950’s performance can be greatly affected
by circuit-board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductances and using fixed-impedance trans-
mission lines on the data and clock signals.
Connecting LVDS Outputs to High-
Impedance Oscilloscope Inputs
To monitor LVDS signals with high-impedance oscillo-
scope inputs, install 100 0402 resistors on locations R1
through R17. Note that this does not provide as good a
termination scheme as using the 50 inputs on an oscil-
loscope and the resulting output will be degraded.
Exposed Pad Package
The 68-pin QFN package with exposed pad incorpo-
rates features that provide a very low thermal-resis-
tance path for heat removal from the IC—either to a PC
board or to an external heatsink. The MAX3950’s
exposed pad must be soldered directly to a ground
plane with good thermal conductance.
2
_______________________________________________________________________________________
MAX3950 Evaluation Kit
G N D
G N D
G N D
G N D
V c c
V c c
V c c
V c c
P D 4 +
P D 1 0 -
P D 4 -
P D 3 +
P D 3
P D 1 0 +
P D 1 1 -
P D 1 1 +
G N D
V c c
G N D
V c c
P D 1 2 -
P D 1 2 +
P D 1 3 -
P D 1 3 +
P D 1 4 -
P D 2 +
P D 2 -
P D 1 +
P D 1 -
P D 0 +
P D 0 -
G N D
P D 1 4 +
G N D
Figure 2. MAX3950 EV Kit Schematic
_______________________________________________________________________________________
3
MAX3950 Evaluation Kit
1.0"
Figure 3. MAX3950 EV Kit PC Board Layout—Solder Side
1.0"
Figure 4. MAX3950 EV Kit PC Board Layout—Power Plane
4
_______________________________________________________________________________________
MAX3950 Evaluation Kit
1.0"
Figure 5. MAX3950 EV Kit PC Board Layout—Ground Plane
1.0"
Figure 6. MAX3950 EV Kit PC Board Layout—Component Side
_______________________________________________________________________________________
5
MAX3950 Evaluation Kit
1.0"
Figure 7. MAX3950 EV Kit Component Placement Guide—Component Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 ______________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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