MAX3964_V01 [MAXIM]
3.0V to 5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector;
| 型号： | MAX3964_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.0V to 5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector |
| 文件： | 总11页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1314; Rev 5; 8/06
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
General Description
Features
The MAX3969 is a recommended upgrade for the
MAX3964 and MAX3968. The MAX3964A limiting amplifi-
♦ Single Supply: +3.0V to +5.5V
♦ 2mV Input Sensitivity
P-P
er, with 2mV
input sensitivity and PECL data outputs, is
P-P
♦ 1.2ns Output Edge Speed
ideal for low-cost ATM, FDDI, and Fast Ethernet fiber
optic applications.
♦ Loss-of-Signal Detector with Programmable
Threshold
The MAX3964A features an integrated power detector
that senses the input-signal power. It provides a
received-signal-strength indicator (RSSI), which is an
analog indication of the power level and complementary
PECL loss-of-signal (LOS) outputs, which indicate when
the power level drops below a programmable threshold.
The threshold can be adjusted to detect signal ampli-
tudes as low as 2.7mV . An optional squelch function
P-P
disables switching of the data outputs by holding them at
a known state during an LOS condition.
The MAX3968 provides the same functionality as the
MAX3964A, but has data-output edge speed suitable for
ESCON and 266Mbps fibre channel applications.
The MAX3964A/MAX3968 are available in die form, as
tested wafers, and in 20-pin QSOP packages. The
MAX3964AETP is available in a 20-pin thin QFN package.
♦ Analog Received-Signal-Strength Indicator
♦ Output Squelch Function
♦ Compatible with 4B/5B Data Coding
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
20 Thin QFN**
20 Thin QFN**
MAX3964AETP
MAX3964AETP+
MAX3964AC/D
MAX3968CEP
MAX3968C/D
Dice*
20 QSOP
Dice*
0°C to +70°C
*Dice are designed to operate over a 0°C to +100°C junction
temperature (Tj) range, but are tested and guaranteed only at T
= +25°C.
A
Applications
125Mbps FDDI Receivers
155Mbps LAN ATM Receivers
Fast Ethernet Receivers
**Package Code: T2044-1
+Denotes lead-free package.
ESCON Receivers
155Mbps FTTx Receivers
Pin Configurations and Selector Guide appear at end of data
sheet.
Typical Operating Circuit
C
1µF
AZ
V
CC
CZP
V
CC
CZN
FILTER
10nF
0.1µF
RSSI
V
CC
FILTER
SQUELCH
LOS+
V
CC0
V
CC
V
CC
C
IN
LOS-
4700pF
MAX3964A
MAX3968
PHOTODIODE
50Ω
155Mbps
TIA
OUT-
OUT-
OUT+
IN-
IN+
50Ω
OUT+
SUB*
GND
C
50Ω
IN
IN
4700pF
50Ω
GND
R1
≥100kΩ
V
TH
INV
V
- 2V
CC
R2
*PIN NOT AVAILABLE ON MAX3964AETP.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
ABSOLUTE MAXIMUM RATINGS
(SUB, GND tied to ground)
, V .............................................................-0.5V to +7.0V
Continuous Power Dissipation (T = +70°C)
A
20-Lead Thin QFN
V
CC CCO
FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH,
LOS+, LOS-, INV, VTH, OUT+, OUT- ......-0.5V to (V
(derate 16.9mW/°C above +70°C)..........................1349mW
20-Pin QSOP (derate 6.7mW/°C above +70°C)...........500mW
Operating Temperature Range ...........................-40°C to +85°C
Operating Junction Temperature Range (die).....-40°C to +150°C
Processing Temperature (die) ........................................+400°C
Storage Temperature Range .......................... -65°C to +160°C
Lead Temperature (soldering, 10s) ................................+300°C
+ 0.5V)
CC
PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA
Differential Voltage Between CZP and CZN..........-1.5V to +1.5V
Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX3964ACEP/MAX3968CEP
(V
are at V
= +3.0V to +5.5V, PECL outputs terminated with 50Ω to (V
- 2V), T = 0°C to +70°C, unless otherwise noted. Typical values
CC
A
CC
= +3.3V and T = +25°C.) (Note 1)
CC
A
PARAMETER
SYMBOL
CONDITIONS
PECL outputs open
Input = 3.3mV to 90mV
MIN
TYP
22
5
MAX
40
UNITS
mA
dB
Supply Current
I
CC
LOS Hysteresis
(Note 2)
P-P
3.8
8.0
P-P
SQUELCH Input Current
PECL Output Voltage High
PECL Output Voltage Low
PECL LOS Output Voltage High
PECL LOS Output Voltage Low
LOS Assert Accuracy
Minimum LOS Assert Input
Maximum LOS Deassert Input
Input Sensitivity
V
= V , T = +25°C
27
100
µA
SQUELCH
CC
A
(Note 3)
-1025
-1810
-1035
-1810
-2.5
-880
-1620
-880
-1620
+2.5
2.7
mV
mV
mV
mV
dB
(Note 3)
(Note 3)
(Note 3)
Input = 7mV
or 90mV
P-P
P-P
mV
mV
mV
P-P
P-P
P-P
143
2.0
3.3
Input Overload
1.5
0.92
0.4
V
P-P
20% to 80% transition time, MAX3964A
1.2
0.8
50
2.20
1.2
Output Transition Time
Pulse-Width Distortion
t , t
ns
ps
r
f
MAX3968
(Note 4)
200
2
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
ELECTRICAL CHARACTERISTICS—MAX3964AETP
(V
= +3.0V to +5.5V, PECL outputs terminated with 50Ω to (V
- 2V), T = -40°C to +85°C. Typical values measured at V
=
CC
CC
A
CC
+3.3V and T = +25°C, unless otherwise noted.)
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
PECL outputs open
MIN
TYP
22
5
MAX
45
UNITS
mA
dB
µA
I
CC
LOS Hysteresis
Input = 4.0mV
(Note 2)
3.0
8.0
P-P
SQUELCH Input Current
PECL Output Voltage High
PECL Output Voltage Low
27
100
(Note 3)
(Note 3)
-1.085
-1.830
-3
-0.880
-1.550
+3
V
V
Input = 7mV
Input = 7mV
or 90mV , 0°C to +85°C
P-P
P-P
LOS Assert Accuracy
dB
or 90mV , -40°C to 0°C
-3.6
+3.6
2.7
P-P
P-P
Minimum LOS Assert Input
Maximum LOS Deassert Input
Input Sensitivity
mV
mV
mV
P-P
P-P
P-P
143
1.5
2
4
Input Overload
V
P-P
Output Transition Time
Pulse-Width Distortion
t , t
20% to 80%
(Note 4)
1.6
50
2.4
ns
ps
r
f
250
P-P
Note 1: Dice are tested and guaranteed at T = +25°C only.
A
Note 2: LOS hysteresis = 20log(V
/ V
).
LOS-DEASSERT
LOS-ASSERT
Note 3: Voltage measurements are relative to supply voltage (V ).
CC
Note 4: PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern.
Typical Operating Characteristics
(MAX3964A EV kit, V
= +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (V
- 2V), T = +25°C,
CC
CC A
unless otherwise noted.)
PULSE-WIDTH DISTORTION
vs. INPUT AMPLITUDE
RSSI VOLTAGE vs. INPUT AMPLITUDE
RSSI VOLTAGE vs. TEMPERATURE
3.00
2.3
100
90
80
70
60
50
40
30
23 -
INPUT PATTERN IS 2 1 PRBS
2.2
2.1
2.0
1.9
1.8
1.7
INPUT = 100mV
2.50
2.00
1.50
1.00
LOS DEASSERTED
LOS ASSERTED
INPUT = 10mV
INPUT = 5mV
1.6
1.5
1
10
100
1k
1
10
100
1k
10k
-40 -20
0
20
40
60
80 100
INPUT AMPLITUDE (mV)
INPUT AMPLITUDE (mV
)
P-P
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Typical Operating Characteristics (continued)
(MAX3964A EV kit, V = +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (V - 2V), T = +25°C,
CC
CC
A
unless otherwise noted.)
DATA OUTPUT EDGE SPEED
(20% to 80%) vs. TEMPERATURE
OUTPUT AMPLITUDE vs. INPUT VOLTAGE
(DIFFERENTIAL SIGNAL LEVELS)
3.0
2.4
1.8
1.2
0.6
0
1600
1400
1200
1000
800
MAX3964A
MAX3968
600
-50
-25
0
25
50
75
100
0.1
1
10
100
1k
10k
TEMPERATURE (°C)
INPUT VOLTAGE (mV)
MAX3964A
EYE DIAGRAM (INPUT = 3.3mV)
LOS OPERATION WITH SQUELCH
DATA
INPUT
200mV/div
DATA
OUTPUT
LOS+
10µs/div
1ns/div
4
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Pin Description
PIN
NAME
FUNCTION
THIN
QFN
QSOP
Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+
high during a loss-of-signal condition. Connect to GND or leave unconnected to disable.
Connect to V to enable squelching.
CC
19
20
1
SQUELCH
Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a
V
TH
2
3
resistor from V to INV and from INV to ground (minimum resistance 100kΩ) to program the
TH
desired threshold voltage.
Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1).
Connect a resistor from V to INV and from INV to ground (minimum resistance 100kΩ) to
1
INV
TH
program the desired threshold voltage.
Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed
together at FILTER to generate the received-signal-strength indicator (RSSI). Connect a
4
5
2
3
FILTER
RSSI
capacitor from FILTER to V
for proper operation.
CC
Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input
signal power. The RSSI output is reduced approximately 120mV when LOS+ is asserted.
6
7
4
5
IN-
IN+
Inverting Data Input
Noninverting Data Input
Substrate. Connect to ground.
Ground
8
—
SUB
GND
9, 10
6, 7, 8
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
11
12
13
9
CZP
CZN
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
10
11
Output Buffer Supply Voltage. Connect to the same potential as V , but filter V
CC
and V
CC
CCO
V
CCO
separately.
14
15
12
13
OUT+
OUT-
Noninverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
Inverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS
threshold. This pin is PECL compatible and should be terminated with 50Ω to (V - 2V).
16
17
14
15
LOS-
CC
Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the
LOS+
LOS threshold. This pin is PECL compatible and should be terminated with 50Ω to (V
MAX3964A/MAX3968: This pin can be left open or connected to the positive supply.
+3.0V to +5.5V Supply Voltage
- 2V).
CC
18
16
V
CCO
19, 20
17, 18
V
CC
Exposed
Pad
—
EP
Connect the exposed pad to board ground for optional electrical and thermal performance.
_______________________________________________________________________________________
5
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
C
AZ
V
CC
V
CCO
CZP
CZN
OFFSET
CORRECTION
I
I
LIMITER
LIMITER
LIMITER
LIMITER
OUT+/OUT-
SQUELCH
O
IN+/IN-
LOS+
FWD
FWD
FWD
FWD
RSSI
FILTER
LOS+/LOS-
1.2V
REFERENCE
C
FILTER
LOS
COMPARATOR
MAX3964A
MAX3968
V
CC
VTR
INV
SUB
GND
R1
R2
FWD = FULL-WAVE DETECTOR
Figure 1. Functional Diagram
This relation translates to a 25mV increase in V
for
RSSI
Detailed Description
every 1dB increase in V (25mV/dB). The RSSI output is
IN
The MAX3964A contains a series of limiting amplifiers
and power detectors, offset correction, data-squelch cir-
cuitry, and PECL output buffers for data and loss-of-sig-
nal (LOS) outputs. The MAX3968 provides PECL LOS
outputs with data outputs suitable for 266Mbps. Figure 1
shows a functional diagram of the MAX3964A/MAX3968.
reduced approximately 120mV when LOS+ is asserted.
PECL Outputs
The data outputs (OUT+, OUT-) and the MAX3964A/
MAX3968 loss-of-signal outputs (LOS+, LOS-) are sup-
ply-referenced PECL outputs. Standard PECL termina-
tion at each output of 50Ω to (V
- 2V) is recommended
CC
Limiting Amplifiers
A series of four limiting amplifiers provides gain of
approximately 65dB.
for best performance.
Input Offset Correction
A low-frequency feedback loop around the limiting
amplifier improves receiver sensitivity and powerdetec-
tor accuracy. The offset-correction loop’s bandwidth is
determined by an external capacitor (CAZ) connected
between the CZP and CZN pins.
Power Detector
Each amplifier stage contains a full-wave logarithmic
detector (FWD), which indicates the RMS input signal
power. The FWD outputs are summed together at the
FILTER pin where the signal is filtered by an external
capacitor (CFILTER) connected between FILTER and
The offset correction is optimized for data streams with
a 50% duty cycle. A different average duty cycle
results in increased pulse-width distortion and loss of
sensitivity. The offset-correction circuitry is less sensi-
tive to variations of input duty cycle (for example, the
40% to 60% duty cycle encountered in 4B/5B coding)
V
. The FILTER signal generates the RSSI output volt-
age, which is proportional to the input power in deci-
CC
bels. When LOS+ is low, V
following equation:
is approximated by the
RSSI
V
(V) = 1.2V + 0.5log (V )
IN
RSSI
when the input is less than 30mV
.
P-P
where V is measured in mV
.
P-P
IN
6
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Loss-of-Signal Comparator
The LOS comparator indicates when the input signal
120
power is below the programmed LOS threshold. To
ensure supply and temperature independence, VTH is
200kV/W
100
generated by a 1.2V bandgap reference. The op amp’s
external gain-setting resistors (R1 and R2) can be
chosen to set V
between 1.2V and 2.4V. To ensure
TH
80
60
40
20
0
chatter-free operation, the LOS comparator is designed
with approximately 5dB of hysteresis.
100kV/W
30kV/W
Squelch
The squelch function disables the data outputs by forc-
ing OUT- low and OUT+ high during a LOS condition.
This function ensures that when there is a loss of sig-
nal, the limiting amplifier (and all downstream devices)
does not respond to input noise or corrupt data.
Connect SQUELCH to GND or leave it unconnected to
20kV/W
15kV/W
10kV/W
-40
-38
-36
-34
-32
-30
-28
-26
disable squelch. Connect SQUELCH to V
data squelching.
to enable
CC
OPTICAL INPUT POWER AT LOS ASSERT (dBm)
Applications Information
Figure 2. LOS Assert Programming Resistor vs. LOS Assert
Power (for Various PIN-TIA Gains )
Program the LOS Threshold
Figure 2 provides information for selecting the LOS
threshold voltage (V ). If R1 is 100kΩ and if the
TH
responsivities of the photodiode and preamplifier are
known, then the value of R2 can be selected from Figure
2 to provide LOS assert at the desired input power.
Wire Bonding
For high-current density and reliable operation, the
MAX3964A series uses gold metalization. Diepad size
is 4mils square with a 6mil pitch. Die thickness is
15mils.
Select Capacitors
A typical MAX3964A/MAX3968 implementation requires
four external capacitors (C , C
, and two input
FILTER
AZ
coupling capacitors). For all applications up to
266Mbps, Maxim recommends the following:
C
= 1µF
AZ
C
= 10nF
FILTER
C
IN
= 4700pF
_______________________________________________________________________________________
7
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Pin Configurations
TOP VIEW
V
V
V
1
2
20
19
18
17
16
15
SQUELCH
CC
V
TH
CC
INV
3
CCO
INV
FILTER
RSSI
IN-
1
2
3
4
5
15 LOS+
14 LOS-
13 OUT-
12 OUT+
FILTER
4
LOS+
LOS-
OUT-
MAX3964A
MAX3968
5
RSSI
IN-
MAX3964AETP
6
7
14 OUT+
IN+
11
V
CCO
IN+
SUB
8
13
12
11
V
CCO
CZN
CZP
9
GND
GND
10
THIN QFN
QSOP
Selector Guide
Chip Topography
PART
MAX3964A*
MAX3968
DATA RATE (Mbps)
125 to 155
LOS OUTPUTS
PECL
MAX3964A
MAX3968
125 to 266
PECL
SQUELCH
*The MAX3964A is functionally equivalent to MAX3964, but offers
slightly improved ESD tolerance. The MAX3969 is a recommend-
ed upgrade for the MAX3964, MAX3964A, and MAX3968.
V
CC
V
CC0
V
V
CC
TH
LOS+
LOS-
INV
FILTER
RSSI
IN-
0.047"
(1.19mm)
OUT-
OUT+
IN+
V
CCO
GND
CZP
SUB
GND
0.057"
(1.45mm)
CZN
TRANSISTOR COUNT: 915
SUBSTRATE CONNECTED TO SUB
SUB CONNECTED TO GND ON MAX3964AETP
8
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
F
1
_______________________________________________________________________________________
9
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
E
21-0139
2
10 ______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
E
21-0139
2
Revision History
Rev 0;
Rev 1;
Rev 2;
Rev 3;
Rev 4;
Rev 5;
10/98:
10/02:
5/03:
9/04:
2/06:
8/06:
Initial data sheet release.
Added MAX3964ETP.
Added package code for TQFN (page 1); updated package drawing (pages 11, 12).
Added MAX3964A (pages 1 to 13).
Added lead-free package information to Ordering Information table (page 1).
Removed references to MAX3964 and MAX3965, TTL Loss of Signal, GNDO; updated CAZ
value to 0.1µF and CIN from 10nF to 4700pF. Updated Typical Application Circuit.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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