MAX3965CEP [MAXIM]
APPLICATION SPECIFIC AMPLIFIER|SINGLE|SSOP|20PIN|PLASTIC ; 专用放大器|单| SSOP | 20PIN |塑料
| 型号： | MAX3965CEP |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | APPLICATION SPECIFIC AMPLIFIER|SINGLE|SSOP|20PIN|PLASTIC
|
| 文件： | 总8页 (文件大小：705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1314; Rev 0; 10/98
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
________________General Description
The MAX3964 limiting amplifier, with 3.3mV input sensi-
tivity and PECL data outputs, is ideal for low-cost ATM,
FDDI, and Fast Ethernet fiber optic applications.
____________________________Features
ꢀ Single Supply: +3.0V to +5.5V
ꢀ 3.3mV Input Sensitivity
ꢀ 1.4ns Output Edge Speed
The MAX3964 features an integrated power detector that
senses the input-signal power. It provides a received-sig-
nal-strength indicator (RSSI), which is an analog indica-
tion of the power level and complementary PECL
loss-of-signal (LOS) outputs, which indicate when the
power level drops below a programmable threshold. The
threshold can be adjusted to detect signal amplitudes as
low as 2.7mVp-p. An optional squelch function disables
switching of the data outputs by holding them at a known
state during an LOS condition.
ꢀ Loss-of-Signal Detector with Programmable
Threshold
ꢀ Analog Received-Signal-Strength Indicator
ꢀ Output Squelch Function
ꢀ Choice of TTL or PECL LOS Outputs
ꢀ Compatible with 4B/5B Data Coding
Ordering Information
The MAX3965 provides the same functionality, but
offers TTL-compatible LOS outputs. The MAX3968 pro-
vides the same functionality as the MAX3964, but has
data-output edge speed suitable for ESCON and
266Mbps fibre channel applications.
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
20 QSOP
Dice*
MAX3964CEP
MAX3964C/D
MAX3964C/DW
MAX3965CEP
MAX3965C/D
MAX3965C/DW
MAX3968CEP
MAX3968C/D
MAX3968C/DW
Wafers*
20 QSOP
Dice*
The MAX3964/MAX3965/MAX3968 are available in die
form, as tested wafers, and in 20-pin QSOP packages.
Wafers*
20 QSOP
Dice*
________________________Applications
125Mbps FDDI Receivers
155Mbps LAN ATM Receivers
Fast Ethernet Receivers
Wafers*
*Dice and wafers are designed to operate over a 0°C to +100°C
junction temperature (T ) range, but are tested and guaranteed
j
ESCON Receivers
only at T = +25°C.
A
266Mbps Fibre Channel Receivers
Pin Configurations appear at end of data sheet.
Typical Operating Circuit
V
CC
C
AZ
27nF
CZP
V
CC
LOS TERMINATIONS
ARE USED ONLY
FOR THE MAX3964
AND MAX3968
CZN
FILTER
10nF
10nF
RSSI
V
CC
FILTER
SQUELCH
V
LOS+
CC0
V
CC
V
CC
C
IN
10nF
LOS-
MAX3964
MAX3965
MAX3968
50Ω
50Ω
PHOTODIODE
OUT-
OUT-
OUT+
IN-
IN+
MAX3960
OUT+
SUB
50Ω
C
10nF
IN
IN
50Ω
GND
GNDO
INV
GND
VTH
(MAX3965 ONLY)
V
- 2V
CC
R2
R1
≥ 100k
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
ABSOLUTE MAXIMUM RATINGS
(SUB, GND, GNDO tied to ground)
, V
Continuous Power Dissipation (T = +70°C)
A
V
.............................................................-0.5V to +7.0V
QSOP (derate 6.7mW/°C above +70°C).......................500mW
Operating Temperature Range............................-40°C to +85°C
Operating Junction Temperature Range (die).....-40°C to +150°C
Processing Temperature (die) .........................................+400°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC CCO
FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH,
LOS+, LOS-, INV, VTH, OUT+, OUT-......-0.5V to (V
+ 0.5V)
CC
PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA
Differential Voltage Between CZP and CZN..........-1.5V to +1.5V
Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +5.5V, PECL outputs terminated with 50Ω to (V
- 2V), T = 0°C to +70°C, unless otherwise noted. Typical values
CC A
CC
are at V
= +3.3V and T = +25°C.) (Note 1)
A
CC
PARAMETER
CONDITIONS
Excludes PECL output current
(Note 2)
MIN
TYP
22
5
MAX
40
UNITS
mA
Supply Current
LOS Hysteresis
3.8
8.0
dB
SQUELCH Input Current
PECL Output Voltage High
PECL Output Voltage Low
PECL LOS Output Voltage High
PECL LOS Output Voltage Low
LOS Assert Accuracy
Minimum LOS Assert Input
Maximum LOS Deassert Input
Input Sensitivity
V
= V , T = +25°C
27
100
µA
SQUELCH
CC
A
(Note 3)
(Note 3)
(Note 3)
(Note 3)
-1025
-1810
-1035
-1810
-2.5
-880
-1620
-880
-1620
2.5
mV
mV
mV
mV
Input = 7mVp-p or 90mVp-p
dB
2.7
mVp-p
mVp-p
mVp-p
Vp-p
143
2.0
3.3
Input Overload
1.5
0.92
0.4
20% to 80% transition time, MAX3964/MAX3965
1.2
0.8
50
2.2
1.2
ns
Data Output Edge Speed
MAX3968
(Note 4)
Pulse-Width Distortion
TTL Output High
TTL Output Low
200
ps
V
I
I
= -200µA
= 200µA
2.4
0
3.1
0.3
V
CC
OH
OL
0.4
V
Note 1: Dice are tested and guaranteed at T = +25°C only.
A
Note 2: LOS hysteresis = 20log(V
/ V
). Input = 3.3mVp-p to 90mVp-p.
LOS-ASSERT
LOS-DEASSERT
Note 3: Voltage measurements are relative to supply voltage (V ).
CC
Note 4: PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern.
2
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
__________________________________________Typical Operating Characteristics
(MAX3964 evaluation kit, V
+25°C, unless otherwise noted.)
= +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (V
- 2V), T =
CC
A
CC
PULSE-WIDTH DISTORTION vs.
INPUT AMPLITUDE
RSSI VOLTAGE vs. INPUT AMPLITUDE
RSSI VOLTAGE vs. TEMPERATURE
3.00
2.3
100
90
80
70
60
50
40
30
23-
INPUT PATTERN IS 2 1 PRBS
2.2
2.1
2.0
1.9
1.8
1.7
INPUT = 100mV
2.50
2.00
1.50
1.00
LOS DEASSERTED
LOS ASSERTED
INPUT = 10mV
INPUT = 5mV
1.6
1.5
1
10
100
1k
-40 -20
0
20
40
60
80 100
1
10
100
1k
10k
INPUT AMPLITUDE (mV)
TEMPERATURE (°C)
INPUT AMPLITUDE (mVp-p)
DATA OUTPUT EDGE SPEED
(20% to 80%) vs. TEMPERATURE
OUTPUT AMPLITUDE vs. INPUT VOLTAGE
(DIFFERENTIAL SIGNAL LEVELS)
3.0
2.4
1.8
1.2
0.6
0
1600
1400
1200
1000
800
MAX3964/MAX3965
MAX3968
600
-50
-25
0
25
50
75
100
0.1
1
10
100
1k
10k
TEMPERATURE (°C)
INPUT VOLTAGE (mV)
MAX3964/MAX3965
EYE DIAGRAM (INPUT = 3.3mV)
LOS OPERATION WITH SQUELCH
DATA
INPUT
100mV/
div
DATA
OUTPUT
LOS+
1ns/div
10µs/div
_______________________________________________________________________________________
3
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Pin Description
PIN
NAME
FUNCTION
Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high
1
SQUELCH
during a loss-of-signal condition. Connect to GND or leave unconnected to disable. Connect to V
to enable squelching.
CC
Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor
from VTH to INV, and from INV to ground (minimum resistance 100kΩ) to program the desired thresh-
old voltage.
2
3
VTH
INV
Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a
resistor from VTH to INV, and from INV to ground (minimum resistance 100kΩ) to program the desired
threshold voltage.
Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed together at
FILTER to generate the received-signal-strength indicator (RSSI). Connect a capacitor from FILTER to
4
5
FILTER
RSSI
V
CC
for proper operation.
Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input signal
power. The RSSI output is reduced approximately 120mV when LOS+ is asserted.
6
7
IN-
IN+
Inverting Data Input
Noninverting Data Input
Substrate. Connect to ground.
Ground
8
SUB
GND
9, 10
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
11
CZP
CZN
Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offset-
correction-loop bandwidth.
12
13
Output Buffer Supply Voltage. Connect to the same potential as V , but filter V
CC
and V
CC
CCO
V
CCO
separately.
14
15
OUT+
OUT-
Noninverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
Inverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS threshold.
16
17
LOS-
For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with 50Ω to (V
-
CC
2V). For the MAX3965, this output is TTL-compatible and does not require termination.
Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the LOS
threshold. For the MAX3964/MAX3968, this pin is PECL-compatible and should be terminated with
LOS+
50Ω to (V
- 2V). For the MAX3965, this output is TTL-compatible and does not require termination.
CC
V
MAX3964/MAX3968: This pin may be left open or connected to the positive supply.
MAX3965: This pin must be connected to ground.
+3.0V to +5.5V Supply Voltage
CCO
18
GNDO
19, 20
V
CC
4
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
C
AZ
V
CC
V
CCO
CZP
CZN
OFFSET
CORRECTION
I
I
LIMITER
LIMITER
LIMITER
LIMITER
OUT+/OUT-
SQUELCH
O
IN+/IN-
LOS+
FWD
FWD
FWD
FWD
RSSI
FILTER
LOS+/LOS-
1.2V
REFERENCE
C
FILTER
MAX3964
MAX3965
MAX3968
LOS
COMPARATOR
V
CC
VTR
INV
SUB
GND
GNDO
(MAX3965 ONLY)
R1
R2
FWD = FULL-WAVE DETECTOR
Figure 1. Functional Diagram
This relation translates to a 25mV increase in V
for
RSSI
Detailed Description
every 1dB increase in V (25mV/dB). The RSSI output is
IN
The MAX3964 contains a series of limiting amplifiers
and power detectors, offset correction, data-squelch
circuitry, and PECL output buffers for data and loss-of-
signal (LOS) outputs. The MAX3965 is functionally the
same, but it provides TTL buffers on the LOS outputs.
The MAX3968 provides PECL LOS outputs with data
outputs suitable for 266Mbps. Figure 1 shows a func-
tional diagram of the MAX3964/MAX3965/MAX3968.
reduced approximately 120mV when LOS+ is asserted.
PECL Outputs
The data outputs (OUT+, OUT-) and the MAX3964/
MAX3968 loss-of-signal outputs (LOS+, LOS-) are sup-
ply-referenced PECL outputs. Standard PECL termina-
tion at each output of 50Ω to (V
mended for best performance.
- 2V) is recom-
CC
Limiting Amplifiers
A series of four limiting amplifiers provides gain of
approximately 65dB.
TTL Outputs
The MAX3965 LOS outputs (LOS+, LOS-) are imple-
mented with open-collector Schottky-clamped TTL-
compatible outputs. The LOS outputs are pulled to V
CC
Power Detector
Each amplifier stage contains a full-wave logarithmic
detector (FWD), which indicates the RMS input signal
power. The FWD outputs are summed together at the
FILTER pin where the signal is filtered by an external
internally with 2kΩ resistors and do not require external
pull-up resistors.
Input Offset Correction
A low-frequency feedback loop around the limiting
amplifier improves receiver sensitivity and power-
detector accuracy. The offset-correction loop’s band-
capacitor (C
CC
) connected between FILTER and
FILTER
V
. The FILTER signal generates the RSSI output volt-
age, which is proportional to the input power in deci-
bels. When LOS+ is low, V
following equation:
width is determined by an external capacitor (C
connected between the CZP and CZN pins.
)
AZ
is approximated by the
RSSI
The offset correction is optimized for data streams with
a 50% duty cycle. A different average duty cycle
results in increased pulse-width distortion and loss of
V
RSSI
(V) = 1.2V + 0.5log (V )
IN
where V is measured in mVp-p.
IN
_______________________________________________________________________________________
5
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
sensitivity. The offset-correction circuitry is less sensi-
Applications Information
tive to variations of input duty cycle (for example, the
Program the LOS Threshold
40% to 60% duty cycle encountered in 4B/5B coding)
when the input is less than 30mVp-p.
Figure 2 provides information for selecting the LOS
threshold voltage (V ). If R1 is 100kΩ and if the
TH
Loss-of-Signal Comparator
The LOS comparator indicates when the input signal
power is below the programmed LOS threshold. To
responsivities of the photodiode and preamplifier are
known, then the value of R2 can be selected from
Figure 2 to provide LOS assert at the desired input
power.
ensure supply and temperature independence, V
is
TH
generated by a 1.2V bandgap reference. The op amp’s
external gain-setting resistors (R1 and R2) can be
Select Capacitors
A typical MAX3964/MAX3965/MAX3968 implementation
chosen to set V
between 1.2V and 2.4V. To ensure
TH
requires four external capacitors (C , C , and
FILTER
chatter-free operation, the LOS comparator is designed
AZ
two input coupling capacitors). For all applications up
with approximately 5dB of hysteresis.
to 266Mbps, Maxim recommends the following:
Squelch
The squelch function disables the data outputs by forc-
ing OUT- low and OUT+ high during a LOS condition.
This function ensures that when there is a loss of sig-
nal, the limiting amplifier (and all downstream devices)
does not respond to input noise or corrupt data.
Connect SQUELCH to GND or leave it unconnected to
C
= 27nF
AZ
C
= 10nF
FILTER
C
= 10nF
IN
Wire Bonding
For high-current density and reliable operation, the
MAX3964 series uses gold metalization. Make connec-
tions to the dice with gold wire only, using ball-bonding
techniques (wedge bonding is not recommended). Die-
pad size is 4mils square with a 6mil pitch. Die thickness
is 15mils.
disable squelch. Connect SQUELCH to V
data squelching.
to enable
CC
120
200kV/W
100
80
100kV/W
60
40
20
0
30kV/W
20kV/W
15kV/W
10kV/W
-34
-40
-38
-36
-32
-30
-28
-26
OPTICAL INPUT POWER AT LOS ASSERT (dBm)
Figure 2. LOS Assert Programming Resistor vs. LOS Assert
Power (for various PIN-TIA gains )
6
_______________________________________________________________________________________
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Pin Configurations
Chip Topographies
MAX3964/MAX3968
SQUELCH
TOP VIEW
V
V
CC0
CC
VTH
V
CC
V
1
2
20
19
18
17
16
15
SQUELCH
VTH
CC
V
V
CC
LOS+
LOS-
INV
FILTER
RSSI
IN-
INV
3
CCO
0.047"
(1.19mm)
FILTER
4
LOS+
LOS-
OUT-
MAX3964
MAX3968
5
RSSI
IN-
OUT-
OUT+
6
IN+
7
14 OUT+
IN+
V
CCO
SUB
8
13
12
11
V
CCO
CZN
CZP
9
GND
GND
GND
CZP
SUB
GND
0.057"
(1.45mm)
CZN
10
QSOP
MAX3965
SQUELCH
V
1
2
20
19
18
17
16
15
SQUELCH
VTH
CC
V
CC
GNDO
VTH
V
CC
V
CC
INV
3
GNDO
LOS+
LOS-
OUT-
LOS+
LOS-
FILTER
4
INV
FILTER
RSSI
IN-
MAX3965
5
RSSI
IN-
0.047"
6
(1.19mm)
7
14 OUT+
IN+
OUT-
OUT+
SUB
8
13
12
11
V
CCO
IN+
MAX3964
CZN
CZP
9
GND
GND
V
CCO
10
GND
CZP
SUB
GND
0.057"
(1.45mm)
CZN
QSOP
TRANSISTOR COUNT: 915
SUBSTRATE CONNECTED TO SUB
_______________________________________________________________________________________
7
+3.0V to +5.5V, 125Mbps to 266Mbps
Limiting Amplifiers with Loss-of-Signal Detector
Package Information
8
_______________________________________________________________________________________
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