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MAX41463GUB+T [MAXIM]

Consumer Circuit,;
MAX41463GUB+T
型号： MAX41463GUB+T
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Consumer Circuit,

商用集成电路
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EVALUATION KIT AVAILABLE  
Click here for production status of specific part numbers.  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
General Description  
Benefits and Features  
● Low Implementation Cost  
The MAX41463/MAX41464 is a UHF sub-GHz ISM/SRD  
transmitter designed to transmit Frequency-Shift Keying  
(FSK), or Gaussian (G)FSK (or 2GFSK) data in the 286MHz  
to 960MHz frequency range. It integrates a fractional phase-  
locked-loop (PLL) so that a single, low-cost crystal can be  
used to generate commonly used world-wide sub-GHz  
frequencies. The fast response time of the PLL allows for  
frequency-hoppingspreadspectrumprotocolsforincreased  
range and security. The chip also features preset modes  
with pin-selectable frequencies so that only one wire is  
required for an external microcontroller interface. The only  
frequency-dependent components required are for the  
external antenna-matching network. A buffered clock-out  
signal at 800kHz is also provided. Optionally, the device  
can be put into programmable mode and programmed  
• Bits-to-RF Single Wire Operation  
• Low Bill-of-Materials (BOM)  
• Uses Single, Low-Cost, 16MHz Crystal  
• Small 3mm x 3mm TSSOP10 Package  
● Increased Range, Data Rates, and Security  
• Up to +16dBm PA Output Power  
• Fast Frequency Switching for FHSS/DSSS  
• Fast-On Oscillator: <250μs Startup Time  
• Up to 200kbps NRZ Data Rate  
● Extend Battery Life with Low Supply Current  
• < 12mA Typical Current Consumption at 315MHz  
• Selectable Standby and Shutdown Modes  
• Auto Shutdown at < 20nA (typ) Current  
● Ease-of-Use  
2
• Pin-Selectable Frequencies  
using an I C interface. The crystal-based architecture  
• Pin-Compatible ASK and FSK Versions  
• +1.8V to +3.6V Single-Supply Operation  
• Fully Programmable with 400kHz/1MHz I C  
of the MAX41463/MAX41464 eliminates many of the  
common problems with SAW-based transmitters by  
providing greater modulation depth, faster frequency  
settling, higher tolerance of the transmit frequency, and  
reduced temperature dependence.  
2
Interface  
Ordering Information appears at end of data sheet.  
The MAX41463/MAX41464 provides output power up  
to +13dBm into a 50Ω load while drawing < 12mA at  
315MHz. The output load can be adjusted to increase  
power up to +16dBm, and a PA boost mode can be  
enabled at frequencies above 850MHz to compensate for  
losses. The PA output power can also be controlled using  
2
programmable register settings in I C mode.  
Simplified Block Diagram  
The MAX41463/MAX41464 also features single-supply  
operation from +1.8V to +3.6V. The device has an auto-  
shutdown feature to extend battery life and a fast oscillator  
wake-up with data activity detection.  
DATA  
/SDA  
PA CONTROL  
VDD  
GND  
The MAX41463/MAX41464 is available in a 10-pin  
TSSOP package and is specified over the -40°C to  
+105°C extended temperature range.  
DATA ACTIVITY  
DETECTOR  
PA  
PAOUT  
PAGND  
SEL[1:0]  
Applications  
LOCK DETECT  
FRAC-N  
PLL  
● Building Automation and Security  
● Wireless Sensors and Alarms  
● Remote and Passive Keyless Entry (RKE/PKE)  
● Tire Pressure Monitoring Systems (TPMS)  
● Automatic Meter Reading (AMR)  
● Garage Door Openers (GDO)  
● Radio Control Toys  
XTAL1  
XTAL2  
CLKOUT  
/SCL  
CRYSTAL OSCILLATOR  
/16  
● Internet of Things (IoT)  
19-100324; Rev 1; 11/18  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Absolute Maximum Ratings  
DD  
All Others Pins to GND ............................ -0.3V to (V  
Continuous Power Dissipation  
V
to GND ............................................................-0.3V to +4V  
Junction Temperature......................................................+150°C  
Storage Temperature Range............................ -60°C to +150°C  
Lead Temperature (reflow) ..............................................+300°C  
Soldering Temperature (reflow).......................................+260°C  
+ 0.3)V  
DD  
(T = +70°C, derate 5.6mW/°C above +70°C.)........444.4mW  
A
Operating Temperature Range......................... -40°C to +105°C  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these  
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect  
device reliability.  
Package Information  
TSSOP-10  
Package Code  
U10+2  
Outline Number  
21-0061  
90-0330  
Land Pattern Number  
Thermal Resistance, Single-Layer Board:  
Junction to Ambient (θ  
)
180 °C/W  
36 °C/W  
JA  
Junction to Case (θ  
)
JC  
Thermal Resistance, Four-Layer Board:  
Junction to Ambient (θ  
)
113.1 °C/W  
36 °C/W  
JA  
Junction to Case (θ  
)
JC  
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,  
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing  
pertains to the package regardless of RoHS status.  
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.  
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.  
Maxim Integrated  
│ 2  
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Electrical Characteristics  
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V  
+13dBm for 300-450MHz or +11dBm for 863-928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V  
= +1.8V to +3.6V, T = -40°C to +105°C, P  
=
A
DD  
A
OUT  
= +3V, T  
DD  
= +25°C, unless otherwise noted. (Note 1))  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DC CHARACTERISTICS  
PA_BOOST = 0  
PA_BOOST = 1  
1.8  
1.8  
3
3.6  
3.0  
21  
Supply Voltage  
V
V
DD  
2.7  
12  
13  
19  
f
f
f
f
= 315MHz  
RF  
RF  
RF  
RF  
= 434MHz  
27.5  
39  
= 863MHz–928MHz  
= 315MHz,  
28  
27  
43  
FSK (Note 2)  
P
= 16dBm (Note 5)  
OUT  
f
P
= 434MHz,  
RF  
= 16dBm (Note 5)  
OUT  
f
P
= 863MHz–928MHz,  
RF  
= 16dBm (Note 5)  
OUT  
Operating Current  
I
mA  
DD  
f
f
f
f
f
f
f
f
f
= 315MHz  
15  
17  
20.5  
2
RF  
RF  
RF  
RF  
RF  
RF  
RF  
RF  
RF  
FSK, Low Phase  
Noise mode  
(Note 2)  
= 434MHz  
= 863MHz–928MHz  
= 315MHz  
3
3
4
PA off (Note 2)  
= 434MHz  
2
= 863MHz–928MHz  
= 315MHz  
3
4
PA off, Low Phase  
Noise mode  
(Note 2)  
= 434MHz  
4
= 863MHz–928MHz  
= 25°C  
5
T
T
T
200  
250  
50  
500  
100  
Crystal oscillator  
on, everything off.  
A
A
A
Standby Current  
I
μA  
STDBY  
= 105°C  
Shutdown Current  
I
Everything off.  
= 25°C  
nA  
SHDN  
MODULATION PARAMETERS  
FSK Frequency  
Deviation  
Default value  
±39  
±1  
kHz  
kHz  
FSK Minimum  
Frequency Deviation  
FSK Minimum  
Frequency Deviation  
for Gaussian Shaping  
±10  
kHz  
FSK Maximum  
Frequency Deviation  
±100  
4
kHz  
kbps  
kbps  
Minimum MSK Data  
Rate  
FSK modulation index = 0.5  
Maximum NRZ Data  
Rate  
200  
Maxim Integrated  
│
3
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Electrical Characteristics (continued)  
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V  
+13dBm for 300-450MHz or +11dBm for 863-928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V  
= +1.8V to +3.6V, T = -40°C to +105°C, P  
=
A
DD  
A
OUT  
= +3V, T  
DD  
= +25°C, unless otherwise noted. (Note 1))  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
POWER AMPLIFIER  
f
f
f
f
= 300MHz–450MHz (Note 4)  
13  
17  
11  
RF  
RF  
RF  
RF  
= 300MHz–450MHz (Note 4, Note 5)  
= 863MHz–928MHz (Note 4)  
Output Power  
P
dBm  
dBc  
OUT  
= 863MHz–928MHz (Note 4, Note 5),  
16  
PA_BOOST = 1  
PA_BOOST = 0. Supply current, output power,  
and harmonics are dependent on board layout  
and PAOUT match.  
Maximum Carrier  
Harmonics  
-24  
PLL  
Low Current mode (default)  
286  
286.7  
425  
960  
320  
480  
960  
Low Phase Noise mode, LODIV = DIV12  
Low Phase Noise mode, LODIV = DIV8  
Low Phase Noise mode, LODIV = DIV4  
Frequency Range  
MHz  
860  
f
= 315MHz,  
f
f
f
f
f
f
= 200kHz  
= 1MHz  
-82  
-90  
-80  
-90  
-82  
-104  
RF  
OFFSET  
OFFSET  
OFFSET  
OFFSET  
OFFSET  
OFFSET  
Low Current mode  
(default)  
f
= 434MHz,  
= 200kHz  
= 1MHz  
RF  
PLL Phase Noise  
Low Current mode  
(default)  
dBc/Hz  
f
= 915MHz,  
= 200KHz  
= 1MHz  
RF  
Low Phase Noise  
mode  
4
8
LO Divider Settings  
12  
Minimum Synthesizer  
Frequency Step  
16  
f
/2  
Hz  
XTAL  
f
f
f
f
= 315MHz  
= 434MHz  
= 868MHz  
= 915MHz  
f
f
f
f
± f  
± f  
± f  
± f  
-67  
RF  
RF  
RF  
RF  
RF  
RF  
RF  
RF  
XTAL  
-60  
-57  
-56  
XTAL  
XTAL  
XTAL  
Reference Spur  
dBc  
Reference Frequency  
Input Level  
500  
mV  
P-P  
26MHz frequency step, 902MHz to 928MHz  
band, time from end of register write to frequency  
settled to within 5kHz of desired carrier  
Frequency Switching  
Time  
50  
μs  
kHz  
Loop Bandwidth  
LBW  
300  
Maxim Integrated  
│
4
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Electrical Characteristics (continued)  
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V  
+13dBm for 300-450MHz or +11dBm for 863-928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V  
= +1.8V to +3.6V, T = -40°C to +105°C, P  
=
A
DD  
A
OUT  
= +3V, T  
DD  
= +25°C, unless otherwise noted. (Note 1))  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Low-Frequency  
Divider Range  
N
11  
72  
f
f
= 315MHz  
= 915MHz  
30  
90  
RF  
RF  
Turn-On Time of PLL  
t
μs  
PLL  
CRYSTAL OSCILLATOR  
Crystal Frequency  
f
Recommended value (Note 3)  
12.8  
16  
19.2  
MHz  
XTAL  
Crystal Oscillator  
Startup Time  
t
Refer to Preset Mode Transmission section  
243  
μs  
XO  
Frequency Pulling  
by VDD  
3
ppm/V  
pF  
Crystal Input  
Capacitance  
Internal capacitance of XTAL1 and XTAL2 pins  
to ground.  
C
12  
X
CMOS INPUT/OUTPUT  
V
SCL/SDA  
1.8V compatible  
1.8V compatible  
0.36  
V
V
IL  
Input Low Voltage  
0.1 x  
V
SEL0/SEL1  
SCL/SDA  
IL_SEL  
V
DD3  
V
1.44  
IH  
Input High Voltage  
0.9 x  
V
SEL0/SEL1  
IH_SEL  
V
DD3  
Input Current  
I /I  
±10  
μA  
IL IH  
Output Low Voltage  
V
I
I
= 650μA  
0.25  
V
OL  
SINK  
V
-
DD  
Output High Voltage  
V
= 350μA  
V
OH  
SOURCE  
0.25  
Maximum  
Capacitance at SEL0/  
SEL1 Pins  
C
10  
10  
pF  
L_SEL  
Maximum Load  
Capacitance at  
CLKOUT Pin  
C
pF  
LOAD  
SERIAL INTERFACE (FIGURE 1)  
SCL Clock Frequency  
f
400  
500  
1000  
kHz  
ns  
SCL  
Bus Free Time  
Between STOP and  
START Conditions  
t
BUF  
Hold Time (Repeated)  
START Condition  
t
260  
ns  
HD:STA  
Low Period of SCL  
High Period of SCL  
t
500  
260  
ns  
ns  
LOW  
t
HIGH  
Maxim Integrated  
│
5
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Electrical Characteristics (continued)  
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V  
+13dBm for 300-450MHz or +11dBm for 863-928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V  
= +1.8V to +3.6V, T = -40°C to +105°C, P  
=
A
DD  
A
OUT  
= +3V, T  
DD  
= +25°C, unless otherwise noted. (Note 1))  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0
TYP  
MAX  
UNITS  
Receive  
Transmit  
150  
Data Hold Time  
t
ns  
HD:DAT  
0
Data Setup Time  
Start Setup Time  
t
50  
260  
ns  
ns  
SU:DAT  
t
SU:STA  
SDA and SCL Rise  
Time  
t
120  
120  
ns  
ns  
R
SDA and SCL Fall  
Time  
20 x  
t
F
V
/5.5  
IO  
Stop Setup Time  
t
260  
ns  
ns  
SU:STO  
Noise Spike Reject  
t
25  
SP  
Note 1: Supply current, output power and efficiency are greatly dependent on board layout and PA output match.  
Note 2: 100% tested at T = +25°C. Limits over operating temperature and relevant supply voltage are guaranteed by design and  
A
characterization over temperature.  
Note 3: Guaranteed by design and characterization. Not production tested.  
Note 4: Typical values are average, peak power is 3dB higher.  
Note 5: Using high output power match, refer to Table 3.  
SDA  
t
BUF  
t
HD:STA  
t
t
F
SP  
t
LOW  
SCL  
t
SU:STA  
t
t
HD:STA  
HIGH  
t
R
t
SU:STO  
t
t
HD:DAT  
SU:DAT  
REPEATED  
START  
STOP  
START  
NOTE: TIMING IS REFERENCED TO V  
AND V  
.
IL (MAX)  
IH (MIN)  
Figure 1. Serial Interface Timing Diagram  
Maxim Integrated  
│
6
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Typical Operating Characteristics  
(Typical Application Circuit, RF output terminated to 50Ω. Typical values are at V  
= +3V, T = +25°C, unless otherwise noted.)  
A
DD  
FSK SUPPLY CURRENT vs. VOLTAGE  
SHUTDOWN CURRENT vs. TEMPERATURE  
STANDBY CURRENT vs. TEMPERATURE  
toc02  
toc01  
toc03  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
500  
400  
300  
200  
100  
0
868MHz  
434MHz  
315MHz  
6
-100  
-50  
-25  
0
25  
50  
75  
100  
125  
1.6  
2.1  
2.6  
3.1  
3.6  
-50  
-25  
0
25  
50  
75  
100  
125  
TEMPERATURE (°C)  
SUPPLY LEVEL (V)  
TEMPERATURE (°C)  
FREQUENCY SETTLING  
fC = 868.3MHz, 2.5kbps  
PHASE NOISE vs. OFFSET FREQUENCY  
C = 915MHz  
PHASE NOISE vs. OFFSET FREQUENCY  
fC = 433.92MHz  
f
toc04  
toc05  
toc06  
-40  
-50  
-40  
-50  
868.34  
868.33  
868.32  
868.31  
868.3  
-60  
-60  
LOW CURRENTMODE  
(DEFAULT)  
LOW CURRENTMODE  
(DEFAULT)  
-70  
-70  
STANDBY  
-80  
-80  
-90  
-90  
868.29  
868.28  
868.27  
868.26  
868.25  
-100  
-110  
-120  
-130  
-140  
-100  
-110  
-120  
-130  
-140  
LOW PHASE  
NOISE MODE  
LOW PHASE  
NOISE MODE  
SHUTDOWN  
100  
1,000  
10,000  
100,000 1,000,000 10,000,000  
0.0  
0.5  
1.0  
1.5  
100  
1,000  
10,000  
100,000 1,000,000 10,000,000  
TIME (ms)  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
UNMODULATED SPECTRUM OUTPUT  
C = 433.92MHz, RBW = 3kHz  
FSK 39kHz MODULATED SPECTRUM OUTPUT  
fC = 433.92MHz, RBW = 3kHz  
UNMODULATED SPECTRUM OUTPUT  
fC = 915MHz, RBW = 3kHz  
f
toc09  
toc08  
toc07  
20  
10  
20  
10  
20  
10  
0
0
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-10  
-20  
-30  
-40  
-50  
-60  
413.9  
421.9  
429.9  
437.9  
445.9  
453.9  
895.0  
903.0  
911.0  
919.0  
927.0  
935.0  
433.4  
433.6  
433.8  
434.0  
434.2  
434.4  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
Maxim Integrated  
│ 7  
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Typical Operating Characteristics (continued)  
(Typical Application Circuit, RF output terminated to 50Ω. Typical values are at V  
= +3V, T = +25°C, unless otherwise noted.)  
A
DD  
FSK ±39kHz MODULATED SPECTRUM OUTPUT  
FSK 100kHz MODULATED SPECTRUM OUTPUT  
fC = 915MHz, RBW = 3kHz  
fC = 433.92MHz, RBW = 3kHz  
toc11  
toc10  
20  
10  
20  
10  
0
-10  
-20  
-30  
-40  
-50  
-60  
0
-10  
-20  
-30  
-40  
-50  
-60  
914.5  
914.7  
914.9  
915.1  
915.3  
915.5  
433.4  
433.6  
433.8  
434.0  
434.2  
434.4  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FSK 39kHz MODULATED SPECTRUM OUTPUT  
fC = 915MHz, RBW = 3kHz  
PA POWER OUTPUT vs. TEMPERATURE  
FSK, fC = 433.92MHz  
toc12  
toc13  
20  
20  
10  
18  
16  
14  
12  
10  
8
3.6V  
0
-10  
-20  
-30  
-40  
-50  
-60  
3.0V  
6
1.8V  
4
2
0
-50  
-25  
0
25  
50  
75  
100  
125  
914.5  
914.7  
914.9  
915.1  
915.3  
915.5  
TEMPERATURE (°C)  
FREQUENCY (MHz)  
PA POWER OUTPUT vs. TEMPERATURE  
ASK, fC = 930MHz  
PA OUTPUT POWER vs. PAPWR CODE  
toc14  
toc15  
20  
18  
16  
14  
12  
10  
8
15  
10  
5
315MHz  
3.6V  
3.0V  
0
6
930MHz  
-5  
-10  
4
1.8V  
2
0
-1  
0
1
2
3
4
5
6
7
8
-50  
-25  
0
25  
50  
75  
100  
125  
CODE  
TEMPERATURE (°C)  
Maxim Integrated  
│ 8  
www.maximintegrated.com  
MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Typical Operating Characteristics (continued)  
(Typical Application Circuit, RF output terminated to 50Ω. Typical values are at V  
= +3V, T = +25°C, unless otherwise noted.)  
A
DD  
ADJUSTABLE PA CAPACITANCE vs. PACAP CODE  
CRYSTAL STARTUP TIME vs. SUPPLY  
fC = 434MHz, CPA ≈ 4.7pF  
FSK, fC = 433.92MHz  
toc16  
toc17  
7
6
500  
450  
400  
350  
300  
250  
200  
150  
5
4
3
-40°C  
2
+25°C  
1
0
+105°C  
-1  
1.6 1.8  
2
2.2 2.4 2.6 2.8  
SUPPLY VOLTAGE (V)  
3
3.2 3.4 3.6 3.8  
-8  
0
8
16  
24  
32  
PACAP CODE  
FSK SPECTRUM  
FSK SPECTRUM  
LOW-CURRENT vs. LOW-PHASE NOISE MODE  
C = 433.92MHz, 39kHz, RBW = 100kHz, MAX-HOLD  
LOW-CURRENT vs.LOW-PHASENOISEMODE  
fC = 915MHz, 39kHz,RBW = 100kHz, MAX-HOLD  
f
toc19  
toc18  
20  
10  
20  
10  
LOW CURRENTMODE  
(DEFAULT)  
LOW CURRENTMODE  
(DEFAULT)  
0
0
-10  
-20  
-30  
-40  
-50  
-60  
-10  
-20  
-30  
-40  
-50  
-60  
LOW PHASE  
NOISE MODE  
LOW PHASE  
NOISE MODE  
910.4 911.3 912.3 913.2 914.1 915.0 915.9 916.8 917.7 918.7 919.6  
431.8 432.2 432.6 433.1 433.5 433.9 434.4 434.8 435.2 435.7 436.1  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Pin Configurations  
MAX41460  
TOP VIEW  
XTAL1  
GND  
1
2
3
4
5
10 XTAL2  
9
8
7
6
CSB  
MAX41460  
VDD  
SCLK  
DATA/  
SDI  
GND_PA  
PA  
CLKOUT/  
SDO  
10-TSSOP  
MAX41461-64  
TOP VIEW  
XTAL1  
GND  
1
10 XTAL2  
2
3
4
5
9
8
7
6
SEL1  
SEL0  
MAX41461-  
MAX41464  
VDD  
DATA/  
SDA  
GND_PA  
PA  
CLKOUT/  
SCL  
10-TSSOP  
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Transmitter with I C Interface  
2
Pin Description  
PIN  
NAME  
FUNCTION  
MAX41461/  
MAX41460  
MAX41464  
XTAL2  
GND  
XTAL2  
GND  
1
2
2nd Crystal Input. See Crystal (XTAL) Oscillator section.  
Ground. Connect to system ground.  
Supply Voltage. Bypass to GND with a 100nF capacitor as close to the pin as  
possible.  
VDD  
GND_PA  
PA  
VDD  
GND_PA  
PA  
3
4
5
Ground for the Power Amplifier (PA). Connect to system ground.  
Power-Amplifier Output. The PA output requires a pullup inductor to the supply  
voltage, which can be part of the output-matching network to an antenna.  
MAX41460: Buffered Clock Output or SPI Data Output.  
2
MAX41461–MAX41464: Buffered Clock Output. I C clock input for register  
CLKOUT/SDO  
CLKOUT/SCL  
6
programming when in Serial Interface mode (SEL0 and SEL1 are unconnected or HIZ).  
The frequency of CLKOUT is 800kHz when not in Program Mode.  
MAX41460: Data Input. SPI bus serial data input for register programming when  
CSB is at logic-low.  
2
MAX41461-MAX41464: Data Input. I C serial data input for register programming  
DATA/SDI  
SCLK  
DATA/SDA  
SEL0  
7
8
when in Serial Interface mode (SEL0 and SEL1 are unconnected or HIZ). When  
not in Progam mode, DATA also controls the power-up state (see Auto-Shutdown  
in Preset Mode section).  
MAX41460: SPI Bus Serial Clock Input.  
MAX41461-MAX41464: Tri-State Mode Input. See Preset Modes for details. For  
tri-state input open mode, the impedance on the pin must be greater than 1MΩ.  
MAX41460: SPI Bus Chip Enable. Active-Low.  
CSB  
SEL1  
9
MAX41461-MAX41464: Tri-State Mode Input. See Preset Modes for details. For  
tri-state input open mode, the impedance on the pin must be greater than 1MΩ.  
XTAL1  
XTAL1  
10  
1st Crystal Input. See Crystal (XTAL) Oscillator section.  
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300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
used world-wide sub-GHz frequencies. A buffered clock-  
out signal make the device compatible with almost any  
microcontroller or code-hopping generator.  
Detailed Description  
The MAX41463/MAX41464 is part of the MAX4146x  
family of UHF sub-GHz ISM/SRD transmitters designed  
to transmit (G)FSK data in the 286MHz to 960MHz  
frequency range. The MAX4146x family is available in the  
following versions.  
The MAX41463/MAX41464 provides +13dBm output  
power into a 50Ω load at 315MHz using an integrated  
high efficiency power amplifier (PA). The output load  
can be adjusted to increase power up to +16dBm and  
a PA boost mode can be enabled at frequencies above  
850MHz to compensate for losses. The PA output power  
can also be controlled using programmable register  
settings. The MAX41463/MAX41464 feature fast  
oscillator wake-up upon data activity detection and has an  
auto-shutdown feature to extend battery life.  
The MAX41460 uses a SPI programming interface,  
The MAX41461–MAX41464 feature an I C interface, as  
2
well as preset modes (pin-selectable output frequencies  
using only one crystal frequency). In preset modes, no  
programming is required and only a single-input data  
interface to an external micro-controller is needed. The  
MAX41463/MAX41464 parts are identical when put in  
2
The MAX41463/MAX41464 operates at a supply voltage  
of +1.8V to +3.6V and is available in a 10-pin TSSOP  
package that is specified over the -40°C to +105°C  
extended temperature range.  
I C programming mode. All MAX4146x versions are fully  
programmable for all output frequencies, as described in  
the Electrical Characteristics table. The only frequency-  
dependent components required are for the external  
antenna match.  
The crystal-based architecture of the MAX41463/  
MAX41464 provides greater modulation depth, fast-  
er frequency settling, higher tolerance of the transmit  
frequency, and reduced temperature dependence. It  
integrates a fractional phase-locked-loop (PLL) so a  
single low-cost crystal can be used to generate commonly  
Preset Modes  
The MAX41463/MAX41464 contain preset settings  
depending on the state of pins SEL1 and SEL0. All pre-  
sets must use a 16MHz crystal. The frequency of the  
CLKOUT pin is always 800kHz. By default, the frequency  
deviation is ±39kHz and Gaussian frequency shaping is  
enabled.  
Table 1. MAX4146x Versions  
VERSION  
MAX41460  
MAX41461  
MAX41462  
MAX41463  
MAX41464  
MODULATION AND INTERFACE  
PRESET FREQUENCIES  
No presets, programmable through SPI  
ASK/FSK with SPI  
2
ASK (optional I C)  
315/318/319.51/345/433.42/433.92/908/915 [MHz]  
315/433/433.92/434/868/868.3/868.35/868.5 [MHz]  
315/433.42/433.92/908/908.42/908.8/915/916 [MHz]  
315/433.92/868.3/868.35/868.42/868.5/868.95/869.85 [MHz]  
2
ASK (optional I C)  
2
FSK (optional I C)  
2
FSK (optional I C)  
Table 2. Programming and Preset Modes  
SEL1 STATE  
Ground  
Ground  
Ground  
Open  
SEL0 STATE  
Ground  
Open  
MAX41463  
MAX41464  
2
2
I C Mode  
I C Mode  
315  
916  
315  
VDD  
433.92  
868.42  
868.95  
868.3  
Ground  
Open  
908.42  
908.8  
908  
Open  
Open  
VDD  
VDD  
Ground  
Open  
915  
869.85  
868.5  
VDD  
433.92  
433.42  
VDD  
VDD  
868.35  
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300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Preset Mode Transmission  
Power Amplifier  
The wake-up of the device is as follows:  
The MAX41463/MAX41464 PA is a high-efficiency, open-  
drain switching-mode amplifier. In a switching-mode  
amplifier, the gate of the final-stage FET is driven with a  
25% duty-cycle square wave at the transmit frequency.  
The PA also has an internal set of capacitors that can  
be switched in and out to present different capacitance  
values at the PA output using the PACAP[4:0] register  
values. This allows extra flexibility for tuning the output  
matching network. When the matching network is tuned  
correctly, the output FET resonates the attached tank  
circuit (pullup inductor from PA to VDD) with a minimum  
amount of power dissipated in the FET. With a proper out-  
put-matching network, the PA can drive a wide range of  
antenna impedances, which include a PCB trace antenna  
or a 50Ω antenna. The output-matching π-network sup-  
presses the carrier harmonics and transforms the antenna  
impedance to an optimal impedance at the PA pin. The  
Typical Application Circuit can deliver an output power of  
+13dBm with a +3.0V supply. Table 3 has approximate PA  
load impedances for desired output powers.  
1) The microcontroller sends a wake-up pulse on DATA.  
The duration of the wake-up pulse should be longer  
than t  
+ t  
.
XO  
PLL  
2) After the falling edge of wake-up pulse, the microcon-  
troller should wait for at least t time and start data  
TX  
transmission. In preset mode, t = 10 μs.  
TX  
3) CLKOUT is generated 80 μs after internal 3.2MHz  
clock is available.  
Auto-Shutdown in Preset Mode  
The MAX41463/MAX41464 in preset mode has an auto-  
matic shutdown feature that places the device in low-  
power shutdown mode if the DATA input stays at logic 0  
12  
for a wait time equal to 2 cycles of the internal 3.2MHz  
clock. This equates to a wait time of approximately 1.3ms.  
When the device is in automatic shutdown, a pulse on  
DATA initiates the warm up of the crystal and PLL. See  
the Preset Mode Transmission section for requirements  
on the wake-up pulse.  
The PAPWR bits in the PA1 register control the output  
power of the PA. This setting adjust the number of paral-  
lel drivers used, which determine the final output power  
(see Figure 3).  
When the device is operating, each occurrence of logic 1  
on the data line resets an internal counter to zero and it  
begins to count again. If the counter reaches the end-of-  
count, the device enters shutdown mode.  
> (t + t  
XO PLL  
)
> t  
TX  
WAKEUP PULSE  
TRANSMITTING  
DATA  
t
XO  
OSCILLATING  
3.2 MHz  
CLOCK  
80 ms  
OSCILLATING  
CLKOUT  
Figure 2. Wake-up timing diagram for preset mode  
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2
Boost Mode  
Programmable Output Capacitance  
The PA can deliver up to 16dBm of output power.  
High output power can be achieved in two ways:  
The MAX41463/MAX41464 has an internal set of capacitors  
that can be switched in and out to present different capacitor  
values at the PA output. The capacitors are connected  
from the PA output to ground. This allows changing the  
tuning network along with the synthesizer divide ratio  
each time the transmitted frequency changes, making it  
possible to maintain maximum transmitter power while  
moving rapidly from one frequency to another.  
● Lower the load impedance for the PA by adjusting the  
output matching network,  
● For frequencies over 850MHz, change the duty cycle  
of the square wave driving the FET from 25% to 50%  
by setting PA_BOOST = 1 in register SHDN (0x05)  
and adjusting the output matching network.  
The variable capacitor is programmed through register  
PA2 (0x07) bits 4:0 (PACAP). The tuning capacitor has a  
nominal resolution of 0.18pF, from 0pF to 5.4pF. In preset  
mode, the variable capacitor is set to 0pF.  
Note that, when using PA_BOOST = 1, the maximum supply  
voltage should not exceed 3V. For frequencies under  
850MHz, the PA_BOOST bit should remain at 0, the output  
match can be adjusted to provide higher output power.  
PA  
LODRV[7]  
5
PACAP[4:0]  
LODRV[2]  
LODRV[1]  
LODRV[0]  
FREQUENCY  
SYNTHESIZER  
DUTY CYCLE  
GENERATOR  
+
PA_BOOST  
PAPWR[2:0]  
3
PAPWR[2:0] IS ON REGISTER PA1 (ADDRESS 0x06).  
PACAP[4:0] IS ON REGISTER PA2 (ADDRESS 0x07).  
Figure 3. Power Amplifier  
Table 3. PA Load Impedance for Desired Output Power  
FREQUENCY  
OUTPUT POWER  
PA LOAD IMPEDANCE  
315MHz  
13dBm  
165Ω  
16dBm  
(PA_BOOST = 0)  
315MHz  
45Ω  
180Ω  
57Ω  
434MHz  
434MHz  
13dBm  
16dBm  
(PA_BOOST = 0)  
863MHz–928MHz  
11dBm  
190Ω  
34Ω  
16dBm  
(PA_BOOST = 1)  
863MHz–928MHz  
Refer to the MAX4146x EV Kit User's Guide for details.  
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300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Additional pulling can be calculated if the electrical  
parameters of the crystal are known. The frequency pull-  
ing is given by:  
Transmitter Power Control  
The transmitter power of the MAX41463/MAX41464  
can be set in approximately 2.5dB steps by setting  
2
PAPWR[2:0] register bits using the I C interface. The  
C
M
1
+ C  
1
+ C  
6
transmitted power (and the transmitter current) can be  
lowered by increasing the load impedance on the PA.  
Conversely, the transmitted power can be increased by  
lowering the load impedance.  
f
=
−
× 10  
P
2
C
C
(
)
CASE  
LOAD  
CASE  
SPEC  
where:  
f is the amount the crystal frequency pulled in ppm  
P
Preset Mode Output Power  
C
C
C
C
is the motional capacitance of the crystal  
is the case capacitance  
M
The output power of the PA in Preset mode (where both  
SEL0 and SEL1 pins are not connected to GND) is always  
set for maximum power level (PAPWR[2:0] = 0x7) for a  
given load impedance. In order to adjust output power  
levels in preset mode, the load impedance must be  
adjusted accordingly.  
CASE  
SPEC  
LOAD  
is the specified load capacitance  
is the load capacitance  
When the crystal is loaded as specified (i.e., C  
=
LOAD  
C
), the frequency pulling equals zero. For additional  
SPEC  
Crystal (XTAL) Oscillator  
details on crystal pulling and load capacitance affects,  
refer to Maxim Tutorial 5422 - Crystal Calculations for ISM  
RF Products.  
The XTAL oscillator in the MAX41463/MAX41464 is  
designed to present a capacitance of approximately 12pF  
from the XTAL1 and XTAL2 pins to ground. In most cases,  
this corresponds to a 6pF load capacitance applied to  
the external crystal when typical PCB parasitics are  
included. It is very important to use a crystal with a load  
capacitance equal to the capacitance of the MAX41463/  
MAX41464 crystal oscillator plus PCB parasitics. If a  
crystal designed to oscillate with a different load  
capacitance is used, the crystal is pulled away from its  
stated operating frequency introducing an error in the  
reference frequency. The crystal’s natural frequency is  
typically below its specified frequency. However, when  
loaded with the specified load capacitance, the crystal  
is pulled and oscillates at its specified frequency. This  
pulling is already accounted for in the specification of the  
load capacitance. Accounting for typical board parasit-  
ics, a 16MHz, 12pF crystal is recommended. Note that  
adding discrete capacitance on the crystal also increases  
the startup time and adding too much capacitance could  
prevent oscillation altogether.  
Turn-On Time of Crystal Oscillator  
The turn-on time of crystal oscillator (XO), t , is defined  
XO  
as elapsed time from the instant of turning on XO circuit  
to the first rising edge of XO divider clock output. The  
external microcontroller turns on the XO by,  
1) Sending a wakeup pulse for MAX41461–MAX41464  
in the preset mode, or  
2
2) Writing to device I C address for MAX41461–  
2
MAX41464 in the I C mode, or  
3) Pulling CSB pin low on the MAX41460.  
Crystal Divider  
The recommended crystal frequencies are 13.0  
MHz, 16.0 MHz, and 19.2 MHz. An internal clock of  
3.2MHz±0.1MHz frequency is required. To maintain the  
internal 3.2MHz time base, XOCLKDIV[1:0] (register  
CFG1, 0x00, bit 4) must be programmed, based on the  
crystal frequency, as shown in the table below.  
Table 4. Required Crystal Divider Programming  
CRYSTAL FREQUENCY  
13.0MHz  
CRYSTAL DIVIDER RATIO  
XOCLKDIV[1:0]  
4
5
6
00  
01  
10  
16.0MHz  
19.2MHz  
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Transmitter with I C Interface  
2
Crystal Frequency in Preset Mode  
Table 5. LODIV Setting  
For MAX41463/MAX41464 in preset mode (where both  
SEL0 and SEL1 pins are not connected to GND), crystal  
frequency must be 16MHz to ensure accurate output  
frequency.  
FREQUENCY RANGE  
LODIV SETTING  
286MHz–960MHz, Low Noise Mode  
286MHz–320MHz, Low Phase Noise  
425MHz–480MHz, Low Phase Noise  
860MHz–960MHz, Low Phase Noise  
0x0  
0x3  
0x2  
0x1  
Phase-Locked Loop (PLL)  
The MAX41463/MAX41464 utilizes a fully integrated  
fractional-N PLL for its frequency synthesizer. All PLL  
components, including loop filter, are included on-chip.  
The synthesizer has a 16-bit fractional-N topology with  
a divide ratio that can be set from 11 to 72, allowing  
the transmit frequency to be adjusted in increments of  
Using an odd value (logic 1 at bit 0) of the 24-bit FREQ  
register will produce lower PLL spurious compared to  
even values (logic 0 at bit 0).  
Turn-on Time of PLL  
f /65536. The fractional-N architecture also allows  
XTAL  
The turn-on time of PLL, t  
, is defined as elapsed time  
PLL  
exact FSK frequency deviations to be programmed. FSK  
deviations as low as ±1kHz and as high as ±100kHz can  
be set by programming the appropriate registers.  
from the instant when the XO output is available to the  
instant when PLL frequency acquisition is complete.  
2
Two-Wire I C Serial Interface  
The internal VCO can be tuned continuously from 286MHz  
to 960MHz in normal mode, and from 286MHz–320MHz,  
425MHz–480MHz, and 860MHz–960MHz in low phase  
noise mode.  
When pins SEL0 and SEL1 are grounded, the MAX41463/  
2
MAX41464 features a 2-wire I C-compatible serial  
interface consisting of a serial-data line (SDA) and a  
serial-clock line (SCL). SDAand SCLfacilitate bidirectional  
communication between the MAX41463/MAX41464 and  
the master at clock frequencies up to 1MHz. The master  
device initiates a data transfer on the bus and generates  
the SCL signal to permit data transfer. The MAX41463/  
Frequency Programming  
The desired frequency can be programmed by setting bits  
FREQ in registers PLL3, PLL4, and PLL5 (0x0B, 0x0C,  
0x0D). To calculate the FREQ bits, use:  
2
MAX41464 functions as an I C slave device that transfers  
and receives data to and from the master. Pull SDA and  
65536  
f
x f  
C
FREQ[23 : 0] = ROUND  
SCL high with external pull-up resistors of 1kΩ or greater,  
(
)
XTAL  
2
referenced to VDD for proper I C operation.  
One bit transfers during each SCL clock cycle. A minimum  
of nine clock cycles is required to transfer a byte into or  
out of the MAX41463/MAX41464 (8 bits and an ACK/  
NACK). The data on SDA must remain stable during the  
high period of the SCL clock pulse. Changes in SDA while  
SCL is high and stable are considered control signals (see  
the START and STOP Conditions section). Both SDA and  
SCL remain high when the bus is not busy.  
Follow Table 4 to program the LODIV bits in register PLL1  
(0x08) when choosing a LO frequency. It is recommend-  
ed to leave bits CPVAL and CPLIN at factory defaults. If  
integer-N synthesis is desired, set bit FRACMODE = 0 in  
register PLL1.  
Fractional-N Spurious  
The 16-bit fractional-N, delta-sigma modulator can  
produce spurious that can show up on the power amplifier  
output spectrum. If slight frequency offsets can be tolerated,  
set the LSB of FREQ (register PLL5, bit 0) to logic-high.  
2
2
Figure 4 and Figure 5 show I C Write transaction and I C  
Read transaction protocols, respectively.  
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Transmitter with I C Interface  
2
SCLK  
S6 S5 S4 S3 S2 S1 S0  
0
A
A7 A6  
A4 A3 A2 A1 A0  
A5  
A
D7 D6 D5 D4 D3 D2 D1 D0 A  
SDI  
START  
DEVICE ADD  
REG ADD  
WR DATA  
STOP  
R/W = 0  
0
A
ACK FROM SLAVE  
2
Figure 4. I C Write  
SCLK  
S6 S5 S4 S3 S2 S1 S0 0  
A
A7 A6 A5 A4 A3 A2 A1 A0 A  
S6 S5 S4 S3 S2 S1 S0 1  
DEVICE ADD  
A
D7 D6 D5 D4 D3 D2 D1 D0 A  
SDI  
START  
DEVICE ADD  
R/W = 0  
REG ADD  
START  
RD DATA  
STOP  
ACK FROM MASTER  
1
0
A
ACK FROM SLAVE  
R/W = 1  
A
2
Figure 5. I C Read  
must pull SDA low before the rising edge of the acknowledge-  
related clock pulse (ninth pulse) and keep it low during the  
high period of the clock pulse.  
START and STOP Conditions  
The master initiates a transmission with a START  
condition (S), which is a high-to-low transition on SDA  
while SCL is high. The master terminates a transmission  
with a STOP condition (P), which is a low-to-high  
transition on SDA while SCL is high.  
To generate a not-acknowledge condition, the receiver  
allows SDA to be pulled high before the rising edge of  
the acknowledge-related clock pulse, and leaves SDA  
high during the high period of the clock pulse. Monitoring  
the acknowledge bits allows for detection of unsuccessful  
data transfers. An unsuccessful data transfer happens if a  
receiving device is busy or if a system fault has occurred.  
In the event of an unsuccessful data transfer, the bus  
master must reattempt communication at a later time.  
Acknowledge and Not-Acknowledge Conditions  
Data transfers are framed with an acknowledge bit (ACK)  
or a not-acknowledge bit (NACK). Both the master and  
the MAX41463/MAX41464 (slave) generate acknowledge  
bits. To generate an acknowledge, the receiving device  
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Transmitter with I C Interface  
2
2
Figure 6 illustrates I C Burst Write transaction protocol.  
Slave Address  
2
The MAX41463/MAX41464 has a 7-bit I C slave address  
that must be sent to the device following a START  
condition to initiate communication. The slave address is  
internally programmed to 0xD2 for WRITE and 0xD3 for  
READ. The MAX41463/MAX41464 continuously awaits  
a START condition followed by its slave address. When  
the device recognizes its slave address, it acknowledges  
by pulling the SDA line low for one clock period, then it is  
ready to accept or send data, depending on the R/W bit.  
Read Cycle  
When addressed with a read command, the MAX41463/  
MAX41464 allows the master to read back a single  
register or multiple successive registers.  
A read cycle begins with the bus master issuing a START  
condition, followed by the 7 slave address bits and a  
write bit (R/W = 0). The device issues an ACK if the slave  
address byte is successfully received. The bus master  
must then send the address of the first register it wishes  
to read. The slave acknowledges the address. A START  
condition is then issued by the master, followed by the 7  
slave address bits and a read bit (R/W = 1). The device  
issues an ACK if the slave address byte is successfully  
received. The device starts sending data MSB first with  
each SCL clock cycle. At the 9th clock cycle, the master  
can issue an ACK and continue to read successive  
registers, or the master can terminate the transmission by  
issuing a NACK. The read cycle does not terminate until  
the master issues a STOP condition.  
Write Cycle  
When addressed with a write command, the MAX41463/  
MAX41464 allows the master to write to either a single  
register or to multiple successive registers.  
A write cycle begins with the bus master issuing a START  
condition, followed by the 7 slave address bits and a  
write bit (R/W = 0). The MAX41463/MAX41464 issues an  
ACK if the slave address byte is successfully received.  
The bus master must then send the address of the first  
register it wishes to write to (see Register Map). The slave  
acknowledges the address and the master can then write  
one byte to the register at the specified address. Data is  
written beginning with the most significant bit (MSB). The  
MAX41463/MAX41464 again issues an ACK if the data is  
successfully written to the register.  
Buffered Clock Output  
MAX41463/MAX41464 provides a buffered clock output  
(CLKOUT) on pin 6 of the chip in the preset mode,  
2
and the frequency of CLKOUT is 800kHz. In I C mode,  
MAX41463/MAX41464 uses pin 6 as the SCL line of the  
The master can continue to write data to the succes-  
sive internal registers with the MAX41463/MAX41464  
acknowledging each successful transfer, or the master  
can terminate transmission by issuing a STOP condition.  
The write cycle does not terminate until the master issues  
a STOP condition.  
2
I C interface.  
CLKOUT_DELAY[1:0] (register CFG2, address 0x01,  
bits 7:6) is only used in the preset modes, with a preset  
value of 0x02. These two register bits are not used in  
programming mode.  
SCLK  
…..  
…..  
S6 S5 S4 S3 S2 S1 S0  
0 A  
A7 A6 A5 A4 A3 A2 A1 A0  
A
D7 D6 D5 D4 D3 D2 D1 D0  
WR DATA TO ADDR  
A
D7 D6 D5 D4 D3 D2 D1 D0  
WR DATA TO ADDR+1  
A
D7 D6 D5 D4 D3 D2 D1 D0  
WR DATA TO ADDR+2  
A
D7 D6 D5 D4 D3 D2 D1 D0  
WR DATA TO ADDR+N  
A
SDI  
START  
DEVICE ADDR  
R/W = 0  
REG ADDR  
STOP  
….  
0
A
ACK FROM SLAVE  
NOTE: ADDRESS AUTO-INCREMENT  
2
Figure 6. I C Burst Write  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
data transmission. The event trigger of data transmission  
is a rising edge on I2C_TXEN, which is a special signal  
with two register-bit aliases I2C_TXEN1 (register CFG6,  
0x0A, bit 2) and I2C_TXEN2 (register CFG7, 0x10, bit  
2). A rising edge on I2C_TXEN can be generated by  
clearing I2C_TXEN1 and setting I2C_TXEN2 in a single  
State Diagrams  
In the preset mode, the MAX41463/MAX41464 device has  
two major states: shutdown and transmitter-enabled.  
In the shutdown state, the crystal oscillator (XO), the PLL  
synthesizer, and the power amplifier (PA) are all turned  
off.  
2
I C transaction.  
In transmitter-enabled state, XO and PLL are turned on;  
PA is turned on with a ramp-up process.  
I2C_TXEN is automatically cleared in two cases: 1) wake-  
up from shutdown, 2) return to programming state from  
the transmitter-enabled state. In those two cases, a rising  
edge on I2C_TXEN can be generated by setting I2C_  
TXEN2 in CFG7, without explicit clearing of I2C_TXEN1.  
After power is applied, the device enters the shutdown  
state. See Initial Programming. A rising edge on DATA  
(pin 7) initiates the warm-up of the XO and PLL. After PLL  
is locked, a falling edge on DATA enables the transmitter.  
The device returns to shutdown state when there is no  
DATA activity, i.e. DATA stays at 0 for 4096 cycles of the  
internal 3.2MHz clock.  
Data to be transmitted are written into a special register,  
byte I2C_TX_DATA[7:0] (register I2C3, 0x13, bits 7:0).  
2
Automatic incrementing of addresses in I C burst-write  
are disabled for this special register. Each data byte  
written into I2C_TX_DATA will be transferred into a FIFO  
buffer. The device has an internal 1-bit signal FIFO_STOP.  
At the end of data transmission, FIFO_STOP is set, and  
the device references the PWDN_MODE[1:0] (register  
CFG4, 0x03, bits 1:0) to enter shutdown, standby, or  
programming state.  
2
In the I C programming mode, the device has four major  
states: shutdown, programming, transmitter-enabled, and  
standby.  
● Shutdown state: The crystal oscillator (XO), the PLL  
synthesizer, and the power amplifier (PA) are all  
turned off.  
In both standby and shutdown states, programming  
● Programming state: XO and PLL are turned on; PA is  
2
through the I C interface is not allowed. The device will  
turned off.  
2
exit the standby or shutdown state once its 7-bit I C  
● Standby state: XO is turned on; PLL and PA are  
address is received.  
turned off.  
Initial Programming  
After turning on power supply (or a soft reset), two I C  
● Transmitter-enabled state: XO and PLL are turned  
2
on; PA is turned on with a ramp-up process.  
transactions are required to initialize the PLL frequency  
synthesizer. The first transaction ensures register ADDL2  
at address 0x1A is written to its default of 0x80. The  
second transaction burst-writes 20 consecutive registers  
from address 0x00 to 0x13.  
2
A wakeup byte with 7-bit device address from the I C bus  
initiates the warm-up of the XO and PLL.  
2
The device can support two types of I C transactions:  
register access only, and register access followed by  
FALLING  
DATA  
XO CLOCK  
AVAILABLE  
XO+PLL  
WARM-UP  
WAIT FOR PLL  
SETTLING  
TX  
ENABLED  
SHUT-DOWN TIMER  
TIMEOUT  
RISING DATA  
POWER-ON-RESET  
SHUTDOWN  
PA RAMP  
DOWN  
Figure 7. State Diagram in Preset Mode  
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2
2
The device needs to transmit an 8-bit dummy packet  
for initial programming. The initial programming must  
clear MODMODE (register CFG1, address 0x00, bit  
0), clear I2C_TXEN1 (register CFG6, address 0x0A,  
bit 2), configure FREQ[23:0] (register PLL3, PLL4 and  
PLL5) to desired frequency, set I2C_TXEN2 (register  
CFG7, address 0x10, bit 2), and configure I2C_TX_  
DATA[7:0] (register I2C3, address 0x13) to 0x00. In  
addition, BCLK_POSTDIV[2:0], BCLK_PREDIV[7:0], and  
PKTLEN_MODE should be configured to default values  
in the register map.  
Case 1: Using Two I C Transactions for Startup from  
Shutdown  
The startup of MAX41463/MAX41464 in programming  
mode, from the shutdown state, uses two I C transactions:  
2
one for configuration update and the other for data  
transmission. FSK modulation can only be enabled  
through configuration update because the initial programming  
must clear MODMODE (register CFG1, address 0x00, bit  
0).  
2
In the first I C transaction, the master device burst-writes  
consecutive registers that are a portion or all of the 16  
registers from address 0x00 to 0x0F. Those consecutive  
registers may or may not include CFG6. If CFG6 is  
included, the I2C_TXEN1 bit should be cleared; otherwise,  
I2C_TXEN1 is automatically cleared in the wake-up from  
shutdown.  
Initial programming cannot be completed by a single  
burst-write transaction because the I2C_TX_DATA  
register at address 0x13 is a special register that  
2
disables automatic address increment. However, two I C  
transactions may be merged to a combined transaction,  
where each write begins with a START mark and the  
slave address.  
2
In the second I C transaction, the master device can  
set I2C_TXEN2 (register CFG7, address 0x10, bit 2),  
configure PKTLEN_MODE (register I2C1, address 0x11,  
bit 7) and PKTLEN[14:0], and write the data to be  
transmitted into I2C_TX_DATA (register I2C3, address  
0x13). Automatic increment of register address during  
burst write is disabled at address 0x13.  
After initial programming, the device will enter the shut-  
down, standby, or programming state according to the  
setting of PWDN_MODE[1:0] (register CFG4, address  
0x03, bit[1:0] ). Configuration register values are retained  
unless changed by programming.  
2
Startup  
The event-trigger for wake-up is the recognition of I C  
address of the device. The event trigger for data trans-  
mission is the rising edge I2C_TXEN that has two aliases  
of I2C_TXEN1 and I2C_TXEN2. The time lag between  
Programming Mode  
This section assumes that initial programming is done  
after power on (or soft reset). Until the next time of power  
off/on (or soft reset), configuration registers are retained  
unless changed by programming.  
those two triggers must be longer than t +t  
. To meet  
XO PLL  
this requirement, the master device can adjust the wait  
2
time between the two I C transactions.  
PROGRAMMING  
XO+PLL  
WARM-UP  
PLL ENABLED  
(PLL ON)  
FIFO STOP,  
PWDN_MODE  
== 2  
7-BIT ADDRESS  
RECOGNIZED  
RISING  
I2C_TXEN  
7-BIT ADDRESS  
RECOGNIZED  
FIFO STOP,  
FIFO STOP,  
PWDN_MODE  
== 0  
PWDN_MODE  
== 1  
POWER-ON-RESET  
PA RAMP  
DOWN  
TX  
ENABLED  
STANDBY  
(PLL OFF)  
PA RAMP  
DOWN  
SHUTDOWN  
Figure 8. Simplified State Diagram in Programming Mode  
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2
2
2
Case 2: Using a Single I C Transaction for Startup  
bined I C transaction with repeated START marks. In a  
combined transaction, the master device can do multiple  
read/write operations without losing control to other master  
2
from Shutdown (Recommended for Use with I C Fast  
Mode)  
2
devices on the I C bus. For example, the combined  
transaction can have a burst-read operation followed by a  
burst-write operation.  
From shutdown state, the start up of device in program-  
ming mode may use a single I C transaction to burst-  
2
write consecutive registers starting from address 0x00.  
Data to be transmitted are written into I2C_TX_DATA  
(register I2C3, address 0x13). Automatic incrementing of  
register addresses during burst-write is disabled at  
address 0x13. The programming should clear I2C_  
TXEN1 and set I2C_TXEN2.  
In the burst-write operation, the master device should write  
consecutive registers starting from CFG7 (address 0x10)  
or any register preceding CFG7. Data to be transmitted  
are written into I2C_TX_DATA (register I2C3, address  
0x13). Automatic incrementing of register addressed  
during burst-write is disabled at address 0x13. The  
programming should set I2C_TXEN2 (and clear I2C_  
TXEN1 if CFG6 is included in the registers to write).  
2
The event-trigger for wake-up is the recognition of I C  
address of the device. The event-trigger for data trans-  
mission is the rising edge of I2C_TXEN that two aliases  
of I2C_TXEN1 and I2C_TXEN2. The time lag between  
those two triggers, here 162 cycles of SCL, must be  
. To meet this requirement, the fast  
mode I C speed with 400kHz SCL is recommended.  
The event-trigger for wake-up is the recognition of device  
address in the burst-read operation. The event-trigger for  
data transmission is the rising edge of I2C_TXEN that has  
two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag  
longer than t +t  
XO PLL  
2
between those two triggers must be longer than t +t  
To meet this requirement, the master device can adjust  
the number of registers to read in the burst-read operation.  
.
2
XO PLL  
Case 3: Using a Combined I C Transactions for  
2
Startup from Shutdown (Recommended for Most I C  
Clock Rates)  
From shutdown state, the start up of MAX41463/  
MAX41464 in programming mode can use a com-  
SHUTDOWN  
1ST  
DEVICE  
ADDR  
DEVICE  
ADDR  
SET  
TXEN  
DATA  
BYTE  
SDA  
BYTE  
+ACK  
BYTE BYTE BYTE BYTE BYTE BYTE  
+ACK +ACK +ACK +ACK +ACK +ACK  
...  
PROGRAMMING  
CFG7 I2C1  
I2C2  
I2C3  
> (tXO + tPLL  
)
2
Figure 9. Using two I C transactions to start data transmission from the shutdown state.  
SHUTDOWN  
1ST  
DEVICE  
ADDR  
CLEAR  
TXEN  
SET  
TXEN  
DATA  
BYTE  
SDA  
BYTE BYTE BYTE  
+ACK +ACK +ACK  
CFG1  
BYTE  
+ACK  
CFG6  
BYTE BYTE BYTE BYTE  
+ACK +ACK +ACK +ACK  
...  
...  
PLL3~7  
...  
CFG7  
I2C1  
I2C2  
I2C3  
> (tXO + tPLL  
)
2
Figure 10. Using a single I C transaction to start data transmission from the shutdown state.  
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2
2
2
Case 4: Using a Single I C Transaction for Startup  
Case 5: Using a Single I C Transaction for Startup  
from Programming Mode  
2
from Standby (recommended for use with I C Fast-  
mode and I C Fast-mode Plus)  
2
The MAX41463/MAX41464 device can transmit a  
data packet each time in the transmitter-enabled state.  
After data transmission, the device refers to the setting  
of PWDN_MODE[1:0] to enter the shutdown, standby, or  
programming state. If the next data packet requires fast  
start-up, PWDN_MODE[1:0] can be configured to 2 so  
that the device returns to the programming state.  
From standby state, the start-up of MAX41463/MAX41464  
in programming mode can use a single I C transaction  
2
to burst-write consecutive registers starting from CFG6  
(address 0x0A) or any register preceding CFG6. Data  
to be transmitted are written into I2C_TX_DATA (register  
I2C3, address 0x13). Automatic incrementing of regis-  
ter addresses during burst-write is disabled at address  
0x13. The programming should clear I2C_TXEN1 and  
set I2C_TXEN2.  
2
Then, the master device can use a single I C transaction  
to burst-write consecutive registers starting from CFG7  
(address 0x10) or any register preceding CFG7. Data to  
be transmitted are written into I2C_TX_DATA (register  
I2C3, address 0x13). Automatic incrementing of regis-  
ter addresses during burst-write is disabled at address  
0x13. The programming should set I2C_TXEN2 (and  
clear I2C_TXEN1 if CFG6 is included in the registers to  
2
The event-trigger for wake-up is the recognition of I C  
address of the device. The event-trigger for data trans-  
mission is the rising edge of I2C_TXEN that two aliases  
of I2C_TXEN1 and I2C_TXEN2. The time lag between  
those two triggers, here ≥ 72 cycles of SCL, must be lon-  
ger than t  
for startup from standby. This requirement is  
2
write). There is no restrictions arising from t  
and t  
.
PLL  
XO  
PLL  
met for the fast-mode I C with 400kHz SCL. In the case of  
Fast-mode Plus, I C with 1MHz SCL, the master device  
2
can burst-write registers starting from PLL1.  
SHUTDOWN  
1ST  
DATA  
BYTE  
DEVICE  
ADDR  
DEVICE  
ADDR  
SET  
TXEN  
SDA  
BYTE  
+ACK  
REG  
READ  
BYTE BYTE  
+ACK +ACK  
BYTE BYTE BYTE BYTE  
+ACK +ACK +ACK +ACK  
...  
OPTIONAL  
CFG7 I2C1  
I2C2  
I2C3  
> (t + t  
XO PLL  
)
2
Figure 11. Using a Combined I C Transaction to Start Data Transmission from the Shutdown State.  
STANDBY  
1ST  
CLEAR  
TXEN  
SET  
TXEN  
DATA  
BYTE  
DEVICE  
ADDR  
SDA  
BYTE BYTE  
+ACK +ACK  
BYTE  
+ACK  
BYTE BYTE BYTE BYTE  
+ACK +ACK +ACK +ACK  
...  
...  
OPTIONAL  
CFG6  
PLL3~7  
CFG7  
I2C1  
I2C2  
I2C3  
> tPLL  
2
Figure 12. Using a Single I C Transaction to Start Data Transmission from the Standby State.  
PROGRAMMING STATE  
1ST  
DATA  
BYTE  
DEVICE  
ADDR  
SET  
TXEN  
SDA  
BYTE BYTE  
+ACK +ACK  
BYTE BYTE BYTE BYTE  
+ACK +ACK +ACK +ACK  
...  
OPTIONAL  
CFG7  
I2C1  
I2C2  
I2C3  
2
Figure 13. Using a Single I C Transaction to Start Data Transmission from the Programming State.  
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2
FIFO underflow or overflow. An internal 1-bit flag FIFO_  
STOP is set at the end of data transmission. The rising  
edge of FIFO_STOP serves as the event trigger to disable  
the transmitter. See the State Diagrams section.  
FIFO Buffer  
2
The I C interface is a bus connected to multiple master or  
slave devices. The microcontroller is a master device and  
the MAX41463/MAX41464 is a slave device. The micro-  
controller can initiate communication with the slave device  
When the number of bauds to be transmitted is known  
before data transmission and less than 32768, it is  
recommended to set PKTLEN_MODE and configure  
PKTLEN[14:0] as the number of bauds to be transmitted.  
Otherwise, clear PKTLEN_MODE and utilize FIFO under-  
flow to stop data transmission. Once the microcontroller  
stops writing I2C_TX_DATA, FIFO underflow will occur  
after the data stored in FIFO buffer are transmitted.  
2
by I C addressing (e.g., sending a START mark followed  
by 7-bit device address). The slave device is required to  
acknowledge every byte transferred through I C.  
2
For data transmission, the microcontroller can burst-  
write consecutive registers, including CFG7 and I2C3.  
The purpose of writing CFG7 is to set I2C_TXEN2 and,  
therefore, generate a trigger to enable the transmitter.  
2
Automatic increment of register address in I C burst-write  
Read-only register I2C4, I2C5, and I2C6 are provided to  
report diagnostic information for the FIFO buffer.  
is disabled for the I2C3 register, which is also named  
I2C_TX_DATA. Once the transmitter is enabled, all bytes  
written to I2C_TX_DATA are moved into a FIFO buffer.  
The buffer size is 4 bytes. The FIFO buffer is enabled only  
in the transmitter-enabled state.  
Frequency Hopping  
In programming mode, the frequency synthesizer is  
initialized to a frequency in a selected ISM band by Initial  
Programming. After that, for the purpose of frequency  
dithering or frequency hopping, the FREQ[23:0] registers  
can be updated to a new frequency in the same selected  
band for each data packet to be transmitted.  
A programmable baud-rate clock is used for retrieving  
and transmitting bits from the FIFO buffer. The baud rate  
is programmable by BCLK_PREDIV[7:0] (register CFG3,  
0x02, bits 7:0) and BCLK_POSTDIV[2:0] (register CFG2,  
0x01, bits 2:0) as the following expression:  
Because programming is not allowed in the transmitted-  
enabled state (see the State Diagrams section),  
frequency configuration cannot be changed when PA is  
enabled. See the Startup section for details on how to  
program the device for data transmission.  
f
CLK  
BaudRate =  
BCLK_POSTDIV  
2 × (1 + BCLK_PREDIV) × 2  
where f  
is the crystal-divider output clock rate (nomi-  
CLK  
After transmitting a data packet, the device enters the  
shutdown, standby, or programming states according  
to the setting of PWDN_MODE[1:0] register. The three  
options have different startup times for transmitting the  
next data packet.  
nally, 3.2 MHz). Valid values of BCLK_PREDIV are from  
3 to 255. Valid values of BCLK_POSTDIV are from 1 to 5.  
To avoid underflow of the FIFO buffer, the baud-rate  
must be lower than 8/9 of the SCL clock rate. The  
device can support three modes of SCL clock frequencies:  
100kHz, 400kHz, and 1MHz. In the 100kHz mode, it is  
recommended to limit baud-rate to no more than 50kbps.  
The startup time from shutdown is at least (t  
+ t  
+
XO  
PLL  
t
t
), where t  
is the turn-on time of crystal oscillator,  
TX  
XO  
is the turn-on time of PLL, t is the turn-on time of  
PLL  
TX  
2
transmitter.  
A FIFO overflow is avoided by utilizing the I C clock  
stretching mechanism. Clock stretching is done before the  
ACK bit. There is no clock-stretching timeout.  
The startup time from standby is at least (t  
+ t ).  
TX  
PLL  
The t time is 27 cycles of the SCL clock plus 2 cycles  
TX  
Each time before data transmission, the I2C1 and I2C2  
registers are configured to specify PKTLEN_MODE and  
PKTLEN[14:0]. Data transmission stops when PKTLEN_  
MODE is set and the number of bauds transmitted is  
equal to PKTLEN[14:0]. Data transmission also stops at  
of the baud-rate clock. For example, the SCL clock rate  
is 1MHz, the baud rate is 100kbps, the value of t  
is  
TX  
47μs. Refer to the Electrical Characteristics for typical  
values of t and t  
.
PLL  
XO  
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2
Register Map  
ADDRESS  
TX  
NAME  
MSB  
LSB  
FSK-  
SHAPE  
0x00  
0x01  
CFG1[7:0]  
XOCLKDELAY[1:0]  
XOCLKDIV[1:0]  
–
–
SYNC  
MODMODE  
CLKOUT_  
DELAY[1:0]  
CFG2[7:0]  
–
–
–
–
–
BCLK_POSTDIV[2:0]  
PWDN_MODE[1:0]  
0x02  
0x03  
0x04  
CFG3[7:0]  
CFG4[7:0]  
CFG5[7:0]  
BCLK_PREDIV[7:0]  
–
–
–
–
–
–
–
TSTEP[5:0]  
RE-  
RE-  
0x05  
SHDN[7:0]  
–
–
–
–
–
–
PA_BOOST  
SERVED SERVED  
0x06  
0x07  
PA1[7:0]  
PA2[7:0]  
RESERVED[2:0]  
–
PAPWR[2:0]  
–
PACAP[4:0]  
FRAC-  
MODE  
0x08  
0x09  
0x0A  
PLL1[7:0]  
PLL2[7:0]  
CFG6[7:0]  
CPLIN[1:0]  
RESERVED[1:0]  
LODIV[1:0]  
LOMODE  
CPVAL[1:0]  
RE-  
RE-  
–
–
–
–
–
–
–
SERVED SERVED  
I2C_  
RE-  
–
–
RESERVED  
TXEN1 SERVED  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
PLL3[7:0]  
PLL4[7:0]  
PLL5[7:0]  
PLL6[7:0]  
PLL7[7:0]  
FREQ[23:16]  
FREQ[15:8]  
FREQ[7:0]  
–
–
DELTAF[6:0]  
DELTAF_SHAPE[3:0]  
I2C_ RE-  
TXEN2 SERVED  
–
–
–
–
–
–
0x10  
CFG7[7:0]  
–
–
RESERVED  
PK-  
0x11  
I2C1[7:0]  
TLEN_  
MODE  
PKTLEN[14:8]  
0x12  
0x13  
I2C2[7:0]  
I2C3[7:0]  
PKTLEN[7:0]  
I2C_TX_DATA[7:0]  
PKT-  
COM-  
PLETE  
0x14  
I2C4[7:0]  
TX_PKTLEN[14:8]  
TX_PKTLEN[7:0]  
0x15  
0x16  
0x17  
0x18  
0x19  
0x1A  
I2C5[7:0]  
FIFO_  
EMPTY  
FIFO_  
FULL  
I2C6[7:0]  
UFLOW OFLOW  
–
–
FIFO_WORDS[2:0]  
CFG8[7:0]  
CFG9[7:0]  
ADDL1[7:0]  
ADDL2[7:0]  
–
–
–
–
–
–
SOFTRESET  
RESERVED  
RE-  
RE-  
RESERVED[4:0]  
RESERVED[1:0]  
SERVED SERVED  
RESERVED[1:0]  
RESERVED[1:0]  
RESERVED[1:0]  
RE-  
SERVED  
RESERVED[6:0]  
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MAX41463/MAX41464  
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Transmitter with I C Interface  
2
Register Details  
CFG1 (0ꢀ00)  
BIT  
Field  
7
6
5
4
3
–
–
–
2
1
0
XOCLKDELAY[1:0]  
0x2  
XOCLKDIV[1:0]  
0x1  
FSKSHAPE  
0b0  
SYNC  
0b0  
MODMODE  
0b0  
Reset  
Access Type  
Write, Read  
Write, Read  
Write, Read Write, Read Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: No delay. XO clock is immediately enabled to  
rest of digital block  
0x1: XO clock is enabled after 16 cycles to rest of  
XOCLK  
DELAY  
Start delay before enabling XO clock to digital digital block  
7:6  
5:4  
block  
0x2: XO clock is enabled after 32 cycles to rest of  
digital block  
0x3: XO clock is enabled after 64 cycles to rest of  
digital block  
0x0: Divide XO clock by 4 for digital clock  
0x1: Divide XO clock by 5 for digital clock. High  
time is 2 cycles, low time is 3 cycles  
0x2: Divide XO clock by 6 for digital clock.  
0x3: Divide XO clock by 7 for digital clock. High  
time is 3 cycles, and low time is 4 cycles.  
XOCLKDIV  
XO clock division ratio for digital block  
Sets the state of FSK Gaussain Shaping  
0x0: FSK Shaping disabled  
0x1: FSK Shaping enabled  
FSKSHAPE  
SYNC  
2
1
0
Controls if clock output acts as an input.  
When an input, it will sample the DATA pin.  
0x0  
0x1  
0x0: ASK Mode  
0x1: FSK Mode  
MODMODE  
Configures modulator mode  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
CFG2 (0ꢀ01)  
BIT  
Field  
7
6
5
–
–
–
4
–
–
–
3
–
–
–
2
1
BCLK_POSTDIV[2:0]  
0x1  
0
CLKOUT_DELAY[1:0]  
0x2  
Reset  
Access Type  
Write, Read  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: CLKOUT will start toggling after 64 cycles  
whenever moving into normal mode from shutdown  
mode  
0x1: CLKOUT will start toggling after 128 cycles  
whenever moving into normal mode from shutdown  
mode  
0x2: CLKOUT will start toggling after 256 cycles  
whenever moving into normal mode from shutdown  
mode  
Selects the delay when CLKOUT starts  
toggling upon exiting SHUTDOWN mode, in  
divided XO clock cycles  
CLKOUT_  
DELAY  
7:6  
0x3: CLKOUT will start toggling after 512 cycles  
whenever moving into normal mode from shutdown  
mode  
0x0: RESERVED  
0x1: Divide by 1  
0x2: Divide by 2  
0x3: Divide by 3  
0x4: Divide by 4  
0x5: Divide by 5  
0x6: RESERVED  
0x7: RESERVED  
BCLK_  
POSTDIV  
2:0  
Baud clock post-divider setting.  
CFG3 (0ꢀ02)  
BIT  
Field  
7
6
5
4
3
2
1
0
BCLK_PREDIV[7:0]  
0x3  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x00: RESERVED  
0x01: RESERVED  
BCLK_  
REDIV  
Baud clock predivision ratio. Valid values are 0x02: RESERVED  
7:0  
from 3 to 255.  
0x03: Divide by 3  
...  
0xFF: Divide by 255  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
CFG4 (0ꢀ03)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
–
–
–
1
0
PWDN_MODE[1:0]  
0x0  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: SHUTDOWN low power state is enabled.  
While entering low power state, XO, PLL, and PA  
are shutdown.  
0x1: STANDBY low power state is enabled. While  
entering low power state, XO is enabled. PLL and  
PA are shutdown  
PWDN_  
MODE  
1:0  
Power Down Mode Select  
0x2: FAST WAKEUP low power state is enabled.  
While entering low power state, XO and PLL are  
enabled. PA is shutdown.  
0x3: Will revert to 0x2  
CFG5 (0ꢀ04)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
4
3
2
1
0
TSTEP[5:0]  
0x00  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
Controls GFSK shaping. See Digital FSK Modulation section.  
TSTEP  
5:0  
SHDN (0ꢀ05)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
1
0
RESERVED RESERVED PA_BOOST  
0x1 0x0 0x0  
Reset  
Access Type  
Write, Read Write, Read Write, Read  
BITFIELD  
RESERVED  
RESERVED  
BITS  
DESCRIPTION  
DECODE  
2
1
Write to 1 binary.  
Write to 0 binary.  
1
0
Enables a boost in PA output power for  
frequencies above 850MHz. This requires  
a different PA match compared to normal  
operation.  
0x0: PA Output power in normal operation.  
0x1: PA Output power in boost mode for more  
output power.  
PA_BOOST  
0
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
PA1 (0ꢀ06)  
BIT  
Field  
7
6
5
4
–
–
–
3
–
–
–
2
1
0
RESERVED[2:0]  
0x4  
PAPWR[2:0]  
0x0  
Reset  
Access Type  
Write, Read  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
RESERVED  
7:5  
Write to 100 binary.  
100  
0x0: Minimum, 1 driver  
0x1: 2 Drivers  
0x2: 3 Drivers  
0x3: 4 Drivers  
0x4: 5 Drivers  
0x5: 6 Drivers  
0x6: 7 Drivers  
0x7: 8 Drivers  
Controls the PA output power by enabling  
parallel drivers.  
PAPWR  
2:0  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
PA2 (0ꢀ07)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
3
2
1
0
PACAP[4:0]  
0x0  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x00: 0  
0x01: 175  
0x02: 350  
0x03: 525  
0x04: 700  
0x05: 875  
0x06: 1050  
0x07: 1225  
0x08: 1400  
0x09: 1575  
0x0A: 1750  
0x0B: 1925  
0x0C: 2100  
0x0D: 2275  
0x0E: 2450  
0x0F: 2625  
0x10: 2800  
0x11: 2975  
0x12: 3150  
0x13: 3325  
0x14: 3500  
0x15: 3675  
0x16: 3850  
0x17: 4025  
0x18: 4200  
0x19: 4375  
0x1A: 4550  
0x1B: 4725  
0x1C: 4900  
0x1D: 5075  
0x1E: 5250  
0x1F: 5425  
PACAP  
4:0  
Controls shunt capacitance on PA output in fF.  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
PLL1 (0ꢀ08)  
BIT  
Field  
7
6
5
4
3
2
1
0
FRAC-  
MODE  
CPLIN[1:0]  
RESERVED[1:0]  
LODIV[1:0]  
LOMODE  
Reset  
0x1  
0x1  
0x00  
0x0  
0b0  
Access Type  
Write, Read  
Write, Read  
Write, Read  
Write, Read  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
Sets the level of charge pump offset current  
for fractional N mode to improve close in  
phase noise. Set to 'DISABLED' for integer  
N mode.  
0x0: No extra current  
0x1: 5% of charge pump current  
0x2: 10% of charge pump current  
0x3: 15% of charge pump current  
CPLIN  
7:6  
Sets PLL between fractional-N and integer-N  
mode.  
0x0: Integer N Mode  
0x1: Fractional N Mode  
FRACMODE  
RESERVED  
5
4:3  
Write to 00 binary.  
00  
0x0: Disabled  
0x1: LC VCO divided by 4  
0x2: LC VCO divided by 8  
0x3: LC VCO divided by 12  
LODIV  
2:1  
0
Sets LO generation. For lower power, choose  
LOWCURRENT. For higher performance,  
choose LOWNOISE.  
0x0: Ring Oscillator Mode  
0x1: LC VCO Mode  
LOMODE  
PLL2 (0ꢀ09)  
BIT  
Field  
7
6
5
–
–
–
4
–
–
–
3
–
–
–
2
–
–
–
1
0
RESERVED RESERVED  
0x0 0b0  
CPVAL[1:0]  
Reset  
0x0  
Access Type Write, Read Write, Read  
Write, Read  
BITFIELD  
RESERVED  
RESERVED  
BITS  
DESCRIPTION  
DECODE  
7
6
Write to 0 binary.  
0
Write to 0 binary.  
0
0x0: 5µA  
0x1: 10µA  
0x2: 15µA  
0x3: 20µA  
CPVAL  
1:0  
Sets Charge Pump Current  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
CFG6 (0ꢀ0A)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
1
0
I2C_TXEN1 RESERVED RESERVED  
0x0 0x0 0x0  
Reset  
Access Type  
Write, Read Write, Read Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
2
2
Enables DATA transmission in I C mode. 0x0: Data transmission not enabled in I C mode.  
I2C_TXEN1  
2
2
Aliased address for I2C_TXEN1.  
0x1: Data transmission enabled in I C mode.  
RESERVED  
RESERVED  
1
0
Write to 0 binary.  
Write to 0 binary.  
PLL3 (0ꢀ0B)  
BIT  
Field  
7
7
7
6
5
5
5
4
3
2
1
0
0
0
FREQ[23:16]  
0x13  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
FREQ  
7:0  
FREQ value to PLL. LO frequency= FREQ<23:0>/2^16*fXTAL  
PLL4 (0ꢀ0C)  
BIT  
Field  
6
4
3
2
1
FREQ[15:8]  
0xB0  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
FREQ  
7:0  
FREQ value to PLL  
PLL5 (0ꢀ0D)  
BIT  
Field  
6
4
3
2
1
FREQ[7:0]  
Reset  
0x00  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
FREQ  
7:0  
FREQ value to PLL  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
PLL6 (0ꢀ0E)  
BIT  
Field  
7
–
–
–
6
5
4
3
2
1
0
DELTAF[6:0]  
0x28  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
For FSK mode, MODMODE = 1 and FSKSHAPE = 0, sets the frequency  
DELTAF  
6:0  
deviation from the space frequency for the mark frequency. f  
= DEL-  
DELTA  
TAF[6:0] * f  
/8192  
XTAL  
PLL7 (0ꢀ0F)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
2
1
0
DELTAF_SHAPE[3:0]  
0x4  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
For FSK mode, MODMODE = 1 and FSKSHAPE = 1, sets the frequency  
DELTAF_SHAPE  
3:0  
deviation from the space frequency for the mark frequency. f  
= DEL-  
DELTA  
TAF_SHAPE[3:0] * f  
/81920  
XTAL  
CFG7 (0ꢀ10)  
BIT  
Field  
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
1
0
I2C_TXEN2 RESERVED RESERVED  
0x0 0x0 0x0  
Reset  
Access Type  
Write, Read Write, Read Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: Data transmission not enabled in  
2
Enables DATA transmission in I C  
mode. Aliased address for I2C_  
TXEN1.  
2
I C mode.  
0x1: Data transmission enabled in I C  
I2C_TXEN2  
2
1
2
mode.  
RESERVED  
RESERVED  
0
Write to 0 binary.  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
I2C1 (0ꢀ11)  
BIT  
Field  
Reset  
7
6
5
4
3
2
1
0
PKTLEN_  
MODE  
PKTLEN[14:8]  
0x0  
0x0  
Access Type Write, Read  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: PKTLEN[14:0] need not be programmed. FIFO  
underflow event will be treated as end of packet  
event. For cases where actual packet length is  
greater than 32767 bits, it is expected that the µC will  
pad such a packet to make it an integral multiple of  
8-bits  
0x1: PKTLEN[14:0] will provide the length of packet.  
Once FIFO is read for PKTLEN[14:0] bits, or if FIFO  
underflow, MAX41463/MAX41464 will consider that  
as an end of packet event.  
PKTLEN_  
MODE  
7
Packet Length Mode  
Packet Length  
PKTLEN  
6:0  
I2C2 (0ꢀ12)  
BIT  
Field  
7
6
5
4
3
2
1
0
PKTLEN[7:0]  
0xFF  
Reset  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
PKTLEN  
7:0  
Packet Length  
I2C3 (0ꢀ13)  
BIT  
Field  
7
6
5
4
3
2
1
0
I2C_TX_DATA[7:0]  
0x0  
Reset  
Access Type  
Write, Read  
BITFIELD  
I2C_TX_DATA  
BITS  
DESCRIPTION  
2
Transmit data to be written into FIFO for I C mode of operation. At this  
2
2
7:0  
address, I C register address will not auto increment within an I C transaction  
burst, and subsequent writes will keep going to FIFO  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
I2C4 (0ꢀ14)  
BIT  
Field  
7
6
5
4
3
2
1
0
PKTCOM-  
PLETE  
TX_PKTLEN[14:8]  
Reset  
0x0  
0x0  
Access Type  
Read Only  
Read Only  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
PKTCOM-  
PLETE  
0x0: Packet transmission is not completed  
0x1: Packet transmission is completed  
7
Indicates if Packet tranmission is completed  
Provides status information of bits transmitted  
for the current packet  
TX_PKTLEN  
6:0  
I2C5 (0ꢀ15)  
BIT  
Field  
7
6
5
4
3
2
1
0
TX_PKTLEN[7:0]  
0x0  
Reset  
Access Type  
Read Only  
BITFIELD  
BITS  
DESCRIPTION  
TX_PKTLEN  
7:0  
Provides status information of bits transmitted for the current packet  
I2C6 (0ꢀ16)  
BIT  
7
6
5
4
3
2
1
0
FIFO_EMP-  
TY  
Field  
UFLOW  
OFLOW  
FIFO_FULL  
–
FIFO_WORDS[2:0]  
Reset  
0x0  
0x0  
0x1  
0x0  
–
–
0x0  
Access Type  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
BITFIELD  
BITS  
DESCRIPTION  
UFLOW  
7
6
5
4
FIFO Underflow status  
FIFO Overflow status  
FIFO Empty Status  
FIFO Full Status  
OFLOW  
FIFO_EMPTY  
FIFO_FULL  
This field captures the number of locations currently filled in FIFO. Each  
location corresponds to 8-bit data word  
FIFO_WORDS  
2:0  
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300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
CFG8 (0ꢀ17)  
BIT  
Field  
7
6
5
4
3
2
1
0
SOFTRE-  
SET  
–
–
–
–
–
–
–
Reset  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0b0  
Access Type  
Write, Read  
BITFIELD  
BITS  
DESCRIPTION  
DECODE  
0x0: Deassert the reset  
0x1: Resets the entire digital, until this bit is set to 0  
SOFTRESET  
0
Places DUT into software reset.  
CFG9 (0ꢀ18)  
BIT  
Field  
7
6
5
4
3
2
1
0
RESERVED[4:0]  
0x0  
RESERVED RESERVED RESERVED  
0x0 0x0 0x0  
Reset  
Access Type  
Write, Read  
Write, Read Write, Read Write, Read  
BITFIELD  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
BITS  
DESCRIPTION  
DECODE  
7:3  
2
Write to 0_0000 binary.  
Write to 0 binary.  
Write to 0 binary.  
Write to 0 binary.  
00000  
0
0
0
1
0
ADDL1 (0ꢀ19)  
BIT  
Field  
7
6
5
4
3
2
1
0
RESERVED[1:0]  
0x0  
RESERVED[1:0]  
0x0  
RESERVED[1:0]  
0x0  
RESERVED[1:0]  
0x0  
Reset  
Access Type  
Write, Read  
Write, Read  
Write, Read  
Write, Read  
BITFIELD  
RESERVED  
RESERVED  
RESERVED  
RESERVED  
BITS  
DESCRIPTION  
DECODE  
7:6  
5:4  
3:2  
1:0  
Write to 00 binary.  
Write to 00 binary.  
00  
00  
00  
00  
Write to 00 binary.  
Write to 00 binary.  
ADDL2 (0ꢀ1A)  
BIT  
Field  
7
6
5
4
3
2
1
0
RESERVED  
0x1  
RESERVED[6:0]  
0x0  
Reset  
Access Type Write, Read  
Write, Read  
BITFIELD  
RESERVED  
RESERVED  
BITS  
7
DESCRIPTION  
Write to 1 binary.  
Write to 000_0000 binary.  
DECODE  
1
6:0  
0000000  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
filtered frequency shaping to help reduce spectral  
emissions.  
Applications Information  
Power-On Programming  
Preset Mode  
To ensure the MAX41463/MAX41464 device enters shut-  
down state after power-on, the DATA pin must be held  
low at power-on. If the DATA pin cannot be guaranteed  
low at power-on, then a high value pulldown resistor is  
The space frequency is defined by the FREQ[23:0] bits  
(registers PLL3, PLL4, PLL5). To set the space frequency,  
use the following equation:  
65536  
* f  
SPACE  
XTAL  
FREQ[23 : 0]  
=
f
recommended. After V  
has settled, a logic low-high-  
DD  
low transition on DATA must occur in the preset mode.  
If the pulse duration of low-high-low transition is longer  
The mark frequency is defined by the space frequency  
plus a frequency deviation. If frequency shaping is  
disabled by setting FSKSHAPE = 0 (register CFG1, bit  
2), the frequency deviation is defined by DELTAF[6:0]  
(register PLL6, bits 6:0).  
than t  
+ t  
, it is a valid wake-up pulse before data  
XO  
PLL  
transmission. It is also allowed to have a short pulse  
duration between 5μs and 20μs. The short pulse will not  
wake up the device.  
f
*
8192  
Δ
DELTAF[6 : 0]  
=
Programming Mode  
f
XTAL  
2
After turning on power supply in I C mode, a logic-high-low-  
high transition on SDA must occur to minimize leakage cur-  
rent in shutdown state. It is highly recommended that the I C  
resistors are connected to the MAX41463/MAX41464 VDD.  
If frequency shaping is enabled by setting FSKSHAPE = 1  
(register CFG1, bit 2), the frequency deviation is defined  
by DETLAF_SHAPE[3:0] (register PLL7, bits 3:0).  
2
2
Two I C transactions are required to initialize the PLL  
f
f
*
8192  
10  
Δ
frequency synthesizer. The first transaction ensures  
register ADDL2 at address 0x1A is written to its default  
of 0x80. The second transaction burst-writes 20 consecutive  
registers from address 0x00 to 0x13. The device is  
programmed to transmit a dummy packet with 8 zero bits  
in ASK mode. There is no RF emission at PA output. See  
Initial Programming section.  
DELTAF_SHAPE[3 : 0]  
=
*
XTAL  
When FSK shaping is enabled by setting FSKSHAPE = 1,  
the frequency is transitioned in 16 steps between the  
two frequencies using a Gaussian filter shape. The time  
between each step is controlled by TSTEP[5:0] (register  
CFG5, bits 5:0). The time step can be adjusted based on  
the data rate.  
For example, the crystal frequency is 16MHz, the RF  
frequency is 315MHz, the 20 consecutive registers from  
address 0x00 to 0x13 can be configured as:  
200000  
TSTEP[5 : 0]  
=
minimum 64, floor  
(
− 1  
f
[0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60,  
0x00, 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x04, 0x00,  
0xFF, 0x00]  
(
)
)
DATA_RATE  
where f  
has a unit of bits per second. For  
DATARATE  
After initial programming, the device will enter the shut-  
down, standby, or programming state according to the setting  
of PWDN_MODE[1:0] (register CFG4, address 0x03,  
bit[1:0] ). Configuration register values are retained unless  
changed by programming or if the device is powered off  
or undergoes a SOFTRESET. See the Startup section for  
how to program the device for data transmission.  
example, if f  
floor(200000/47000) -1 = 3.  
is 47kbps, then TSTEP is  
DATARATE  
In the preset mode, the frequency deviation is fixed at  
78kHz.and TSTEP = 1.  
FSK shaping supports a data rate up to 110kbps. Higher  
data rates is not recommended.  
Digital FSK Modulation  
The FSK moduIation in MAX41463/MAX41464 is defined  
by the space frequency and the mark frequency. The  
space frequency is the lower frequency that represents a  
logic 0. The mark frequency is the higher frequency that  
represents a logic 1. The device defaults to Gaussian  
Maxim Integrated  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
In the programming mode, the crystal divider ratio is  
programmable. The crystal divider ratio should be config-  
ured so that the divided clock frequency is 3.2±0.1MHz.  
In addition, the PLL synthesizer requires a reference  
frequency (same as crystal frequency) between 12.8MHz  
and 19.2MHz. Therefore, when crystal divider ratio is 4, 5, or  
6,allowedrangeofcrystalfrequencyis12.8MHz~13.2MHz,  
15.5MHz~16.5MHz, or 18.6MHz~19.2MHz.  
Tuning Capacitor Settings  
The internal variable shunt capacitor, which can be used  
to match the PA to the antenna with changing transmitter  
frequency, is controlled by setting the 5-bit cap variable in  
the registers. This allows for 32 levels of shunt capacitance  
control. Since the control of these 5 bits is independent of  
the other settings, any capacitance value can be chosen  
at any frequency, making it possible to maintain maximum  
transmitter efficiency while moving rapidly from one  
frequency to another. The internal tuning capacitor adds 0  
to 5.425pF to the PA output in 0.175pF steps.  
In another example, desired RF frequencies are  
319.5MHz,  
345.0MHz,  
and  
433.92MHz,  
and  
recommended crystal selection is 13±0.002MHz so  
that integer boundary spurs are completely suppressed  
for three desired RF frequencies. Nevertheless, the  
16±0.002MHz and 19.2±0.002MHz crystals are also  
acceptable.  
Crystal Frequency Selection  
In order to avoid integer boundary spurs in fractional-N  
PLL synthesizers, the crystal should be selected so that  
the RF carrier frequency is more than 0.4MHz apart from  
the nearest integer multiple of crystal frequency.  
In the preset mode, the crystal divider ratio is preset at 5.  
When the RF carrier frequency is very close to an integer  
multiple of 16MHz, the crystal selection can change to  
16.384MHz or 16.128MHz, and the RF carrier frequency  
should be preset through OTP memory in production.  
For example, the 16±0.002MHz crystals can be selected  
for the 433.92MHz RF carrier, which is more than 0.4MHz  
apart from the nearest integer multiple of crystal frequency  
at 432±0.054MHz. However, the 16±0.002MHz crystals  
are not suitable for a RF carrier at 912MHz or 928MHz.  
Maxim Integrated  
│ 37  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Typical Application Circuit  
CLKOUT /  
SCL  
GND  
VDD  
DATA / SDA  
SEL1  
SEL0  
MAX41461-64  
L1A  
XTAL1  
XTAL2  
PA  
Y1  
L2  
C7  
C6  
C8  
GND_PA  
Ordering Information  
PART NUMBER  
MAX41463GUB+  
MAX41463GUB+T  
MAX41464GUB+  
MAX41464GUB+T  
TEMP RANGE  
PIN-PACKAGE  
TSSOP-10  
TSSOP-10  
TSSOP-10  
TSSOP-10  
-40°C to +105°C  
-40°C to +105°C  
-40°C to +105°C  
-40°C to +105°C  
+ Denotes a lead(Pb)-free/RoHS-compliant package.  
T Denotes tape-and-reel.  
Maxim Integrated  
│ 38  
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MAX41463/MAX41464  
300MHz–960MHz (G)FSK  
Transmitter with I C Interface  
2
Revision History  
REVISION REVISION  
PAGES  
CHANGED  
DESCRIPTION  
NUMBER  
DATE  
0
1
6/18  
Initial release  
—
11/18  
Updated Ordering Information  
38  
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.  
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses  
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)  
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.  
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.  
2018 Maxim Integrated Products, Inc.  
│ 39  

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