MAX4456CQH-D [MAXIM]
Cross Point Switch, 1 Func, 8 Channel, CMOS, PQCC44, PLASTIC, MO-047AC, LCC-44;
| 型号： | MAX4456CQH-D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Cross Point Switch, 1 Func, 8 Channel, CMOS, PQCC44, PLASTIC, MO-047AC, LCC-44 PC 输出元件 |
| 文件： | 总16页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1389; Rev 1; 12/99
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
General Description
Features
The MAX4359/MAX4360/MAX4456 low-cost video cross-
point switches are designed to reduce component count,
board space, design time, and system cost. Each con-
tains a matrix of T-switches that connect any of their four
(MAX4359) or eight (MAX4360/MAX4456) video inputs to
any of their buffered outputs, in any combination. Each
matrix output is buffered by an internal, high-speed
(250V/µs), unity-gain amplifier that is capable of driving
400Ω and 20pF at 2.6Vp-p. For applications requiring
increased drive capability, buffer the MAX4359/
MAX4360/MAX4456 outputs with the MAX497 quad,
gain-of-two video line driver.
ꢀ Eight (MAX4456) or Four (MAX4359/MAX4360)
Internal Buffers
250V/µs Slew Rate
Three-State Output Capability
Power-Saving Disable Feature
65MHz -3dB Bandwidth
ꢀ Routes Any Input Channel to Any Output Channel
ꢀ Serial or Parallel Digital Interface
ꢀ Expandable for Larger Switch Matrices
ꢀ 80dB All-Channel Off-Isolation at 5MHz
ꢀ 70dB Single-Channel Crosstalk
The MAX4456 has a digitally controlled 8x8 switch matrix
and is a low-cost pin-for-pin compatible alternative to the
popular MAX456. The MAX4359/MAX4360 are similar to
the MAX4456, with the 8x8 switch matrix replaced by a
4x4 (MAX4359) or an 8x4 (MAX4360) switch matrix.
ꢀ Straight-Through Pinouts Simplify Layout
ꢀ Low-Cost Pin-Compatible Alternative to
MAX456 (MAX4456)
Three-state output capability and internal, programmable
active loads make it feasible to parallel multiple devices
to form larger switch arrays. The inputs and outputs are
on opposite sides, and a quiet power supply or digital
input line separates each channel, which reduces
crosstalk to -70dB at 5MHz. For applications demanding
better DC specifications, see the MAX456 8x8 video
crosspoint switch.
Ordering Information
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
36 SSOP
MAX4359EAX
MAX4359EWG
MAX4360EAX
MAX4456CPL
MAX4456CQH
MAX4456EPL
MAX4456EQH
24 SO
36 SSOP
40 Plastic DIP
44 PLCC
0°C to +70°C
________________________Applications
-40°C to +85°C
-40°C to +85°C
40 Plastic DIP
44 PLCC
High-Speed Signal
Video Test Equipment
Video Conferencing
Security Systems
Routing
Pin Configurations appear at end of data sheet.
Video-On-Demand
Systems
_________________________________________________Typical Application Circuits
8 INPUT CHANNELS
4 INPUT CHANNELS
(8 INPUT CHANNELS)
MAX497
= +2
(MAX4360)
A
Z = 75Ω
0
V
75Ω
MAX497
= +2
WR
LATCH
A
V
Z = 75Ω
0
75Ω
WR
LATCH
75Ω
MAX4456
75Ω
MAX4359
(MAX4360)
A2
A1
A0
OUTPUT
SELECT
A1
A0
OUTPUT
SELECT
8x8
T-SWITCH
MATRIX
4x4
(8x4)
T-SWITCH
MATRIX
INPUT
SELECT
OR
SERIAL
I/O
D3
D2
INPUT
SELECT
OR
SERIAL
I/O
D3
D2
D1/SER OUT
D0/SER IN
D1/SER OUT
D0/SER IN
A
= +2
V
MAX497
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ...........................................+±2V
Positive Supply Voltage (V+) Referred to AGND .......-0.3V to +±2V
Negative Supply Voltage (V-) Referred to AGND ......-±2V to +0.3V
DGND to AGND..................................................................±0.3V
Buffer Short Circuit to Ground when
Continuous Power Dissipation (T = +70°C)
A
36-Pin SSOP (derate ±±.8mW/°C above +70°C)...........94±mW
24-Pin SO (derate ±±.8mW/°C above +70°C)................94±mW
40-Pin Plastic DIP (derate ±±.3mW/°C above +70°C)....889mW
44-Pin PLCC (derate ±3.3mW/°C above +70°C) .......±066mW
Operating Temperature Ranges
Not Exceeding Package Power Dissipation.............Indefinite
Analog Input Voltage............................(V+ + 0.3V) to (V- - 0.3V)
Digital Input Voltage .............................(V+ + 0.3V) to (V- - 0.3V)
Input Current, Power On or Off
Digital Inputs.................................................................±20mA
Analog Inputs ...............................................................±50mA
MAX4456C _ _ ....................................................0°C to +70°C
MAX4_ _ _E_ _.................................................-40°C to +85°C
Junction Temperature......................................................+±50°C
Storage Temperature Range.............................-65°C to +±50°C
Lead Temperature (soldering, ±0sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V, V
= +5V (internal load resistors on), V
= V
= V = 0, T = T
DGND
to T , unless otherwise noted.
MAX
LOAD
IN_
AGND
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
Operating Supply Voltage
Input Voltage Range
CONDITIONS
Inferred from PSRR test
MIN
±4.5
-±.3
TYP
MAX
±5.5
±.3
UNITS
V
V
Inferred from swing test
T = +25°C
0.99
0.98
±.0
±.0
±±
±.0±
±.02
±±5
±20
A
Internal load resistors on,
Voltage Gain
V/V
no external load, V = 0 to ±V
IN
T = T
to T
MAX
A
MIN
T = +25°C
A
Buffer Offset Voltage
Offset Voltage Drift
mV
T = T
to T
MAX
A
MIN
20
20
µV/°C
T = +25°C
32
37
50
65
5
A
MAX4359/MAX4360
MAX4456
T = T
A
to T
MAX
MIN
Supply Current, All Buffers On
(no external load)
mA
T = +25°C
39
A
T = T
A
to T
MIN
MAX
Supply Current, All Buffers Off
Power-Supply Rejection Ratio
Analog Input Current
±.6
64
mA
dB
nA
nA
±4.5V to ±5.5V
50
±0.±
±±00
±±00
600
Output Leakage Current
Internal load resistors off, all buffers off
T = +25°C
250
200
400
±0
A
Internal Amplifier Load Resistor
V
LOAD
= 5V
Ω
T = T
A
to T
765
MIN
MAX
Buffer Output Voltage Swing
Digital Input Current
Internal load resistors on, no external load
±±.3
V
µA
Ω
V
±±
0.8
0.4
Output Impedance at DC
Input Logic Low Threshold
Input Logic High Threshold
2.4
4
V
I
I
= 0.4mA
= -0.4mA
Serial mode,
= 5V
OL
SER OUT Output Logic Low/High
V
V
SER/PAR
OH
2
_______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
AC ELECTRICAL CHARACTERISTICS
(V+ = +5V, V- = -5V, V
= +5V (internal load resistors on), V
= V
= 0, T = +25°C, unless otherwise noted.)
DGND
A
LOAD
AGND
PARAMETER
DYNAMIC SPECIFICATIONS
Output-Buffer Slew Rate
Single-Channel Crosstalk
All-Hostile Crosstalk
CONDITIONS
MIN
TYP
MAX
UNITS
Internal load resistors on, ±0pF load
250
70
57
80
35
65
4
V/µs
dB
5MHz, V = 2Vp-p (Note ±)
IN
5MHz, V = 2Vp-p (Notes ±, 2)
dB
IN
All-Channel Off-Isolation
-3dB Bandwidth
5MHz, V = 2Vp-p (Note ±)
dB
IN
±0pF load, V = 2Vp-p (Note ±)
MHz
MHz
MHz
degrees
%
IN
Small-Signal -3dB Bandwidth
0.±dB Bandwidth
±0pF load, V = ±00mVp-p (Note ±)
IN
±0pF load, V = ±00mVp-p (Note ±)
IN
Differential Phase Error
Differential Gain Error
Input Noise
(Note 3)
±.0
0.5
0.3
6
(Note 3)
DC to 40MHz
All buffer inputs grounded
mV
RMS
Input Capacitance
pF
Additional capacitance for each output buffer
connected to channel input
Buffer Input Capacitance
Output Capacitance
2
7
pF
pF
Output buffer off
SWITCHING CHARACTERISTICS
(Figure 4, V+ = +5V, V- = -5V, V
= +5V (internal load resistors on), V
= V
= V
= 0, T = T
to T
, unless other-
MAX
LOAD
IN_
AGND
DGND
A
MIN
wise noted. Typical values are at T = +25°C.) (Note 4)
A
PARAMETER
Chip-Enable to Write Setup
Write Pulse Width High
Write Pulse Width Low
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
t
CE
t
80
80
240
±60
0
ns
WH
t
ns
WL
Parallel mode
Data Setup
t
ns
DS
Serial mode
Data Hold
t
ns
ns
ns
ns
ns
ns
DH
Latch Pulse Width
t
L
80
80
Latch Delay
t
D
Switch Break-Before-Make Delay
LATCH Edge to Switch Off
LATCH Edge to Switch On
t
t
±5
35
50
ON - OFF
t
LATCH on
OFF
t
ON
Note 1: See Dynamic Test Circuits section.
Note 2: 3dB typical crosstalk improvement when R = 0.
S
Note 3: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to ±00IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers. ±40IRE = ±.0V.
Note 4: Guaranteed by design.
_______________________________________________________________________________________
3
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Pin Description
PIN
MAX4359
SSOP
MAX4360
SSOP
MAX4456
NAME
FUNCTION
SO
DIP
PLCC
D±/
SER OUT
Parallel Data Bit D± when SER/PAR = GND. Serial out-
±
±
±
±
2
put for cascading multiple parts when SER/PAR = V
.
CC
Parallel Data Bit D0 when SER/PAR = GND. Serial
2
2
2
2
3
D0/SER IN
A_
input when SER/PAR = V
.
CC
3, 5
3, 5
3, 5
3, 4, 6
4, 5, 7
Output Buffer Address Lines
4, 6, 8, ±0, 5, 7, 9, ±±, 6, 8, ±0, ±3,
4, 6, 8, ±0 4, 6, 8, ±0 ±2, ±4, ±6, ±3, ±5, ±7, ±5, ±7, ±9,
IN_
Video Input Lines
±8
±9
2±
Asynchronous Control Line. When LOAD = V , all the
CC
400Ω internal active loads are on. When LOAD = GND,
external 400Ω loads must be used. The buffers must
have a resistive load to maintain stability.
7
9
7
9
7
8
9
LOAD
Digital Ground. DGND pins must have the same
potential and be bypassed to AGND. DGND should
be within ±0.3V of AGND.
9
±0, ±2
±4
±±, ±4
±6
DGND
When this control line is high, the 2nd-rank registers
are loaded with the rising edge of LATCH. If this con-
trol line is low, the 2nd-rank registers are transparent
when LATCH is low, passing data directly from the
±st-rank registers to the decoders.
EDGE/
LEVEL
±±
±±
±±
±2–±6, ±8,
22–26
±, ±2, 23,
34
—
±2
±3
22–26
±7
—
±8
N.C.
SER/PAR
V-
No connection. Not internally connected.
Connect to V
for serial mode; connect to GND for
CC
±7
20
parallel mode.
Negative Supply. All V- pins must be connected to each
other and bypassed to GND separately (Figure 2).
±9, 30
±9, 30
20, 34
22, 38
In serial mode, WR (write) shifts data into the input regis-
ter. In parallel mode, WR loads data into the ±st-rank
registers. Data is latched on the rising edge.
±4
20
2±
20
2±
2±
22
24
25
WR
If EDGE/LEVEL = V , data is loaded from the ±st-
CC
rank registers to the 2nd-rank registers on the rising
edge of LATCH. If EDGE/LEVEL = GND, data is
loaded while LATCH = GND. In addition, data is
loaded during the execution of parallel-mode func-
±5
LATCH
tions ±0±± through ±±±0, or if LATCH = V
during
CC
the execution of the parallel-mode “software-latch”
command (±±±±).
4
_______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Pin Description (continued)
PIN
MAX4359
SSOP
MAX4360
SSOP
MAX4456
NAME
FUNCTION
SO
DIP
PLCC
Active-Low Chip Enable. WR is enabled when
—
—
—
23
24
26
CE = GND and CE = V . WR is disabled when
CE
CE
CC
CE = V and CE = GND.
CC
Active-High Chip Enable. WR is enabled when
CE = GND and CE = V . WR is disabled when
CC
±6
27
27
27
CE = V
and CE = GND.
CC
25, 27, 29, 28, 30, 32,
3±, 33, 35, 35, 37, 39,
±7, ±9, 2±, 28, 3±, 33, 28, 3±, 33,
Buffer Outputs. Buffer inputs are internally grounded with
a ±000 or ±00± command from the D3–D0 lines.
OUT_
23
35
35
37, 39
4±, 43
Analog Ground. AGND must be at 0.0V, since the gain-
±8
29
±5, 29
28, 30, 32 3±, 33, 36
AGND setting resistors of the buffers are connected to these
pins.
Parallel Data Bit when SER/PAR = GND. When
D3 = GND, D0–D2 specify the input channel to be con-
20
32
32
36
38
40
42
D3
nected to specified buffer. When D3 = V , D0–D2
specify control codes. D3 is not used in serial mode
CC
(SER/PAR = V ).
CC
Parallel Data Bit D2 when SER/PAR = GND. Not used
22
24
34
36
34
D2
V+
when SER/PAR = V
.
CC
Positive Supply. All V+ pins must be connected to each
other and bypassed to AGND separately (Figure 2).
±3, 36
±6, 26, 40 ±8, 29, 44
_______________________________________________________________________________________
5
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
buffers can be active and only one set of loads can be
driven. When active, the buffer must have either ±) an
internal load, 2) the internal load of another buffer in
another MAX4359/MAX4360/MAX4456, or 3) an exter-
nal load.
Detailed Description
Output Buffers
The MAX4456 video crosspoint switch consists of 64
T-switches in an 8x8 grid (Figure ±). The eight matrix
outputs are followed by eight wideband buffers opti-
mized for driving 400Ω and 20pF loads. The
MAX4359’s core is a 4x4 switch matrix with each of its
outputs followed by a wideband buffer. The MAX4360
has an 8x4 matrix and four output buffers. Each buffer
has an internal active load on the output that can be
readily shut off through the LOAD input (off when LOAD
= 0V). The shut-off is useful when two or more cross-
points are connected in parallel to create more input
channels. With more input channels, only one set of
Each output can be disabled under logic control. When
a buffer is disabled, its output enters a high-impedance
state. In multichip parallel applications, the disable
function prevents inactive outputs from loading lines
driven by other devices. Disabling the inactive buffers
reduces power consumption.
The outputs connect easily to MAX497 quad, gain-of-
two buffers when back-terminated 75Ω coaxial cable
must be driven.
IN4
IN5
IN1
IN2
IN3
IN6
IN7
IN0
OUTPUT
BUFFERS
A = +1
OUT0
400Ω
MAX4456
8x8
SWITCH
MATRIX
LOAD
A = +1
OUT7
LATCH
400Ω
2nd-RANK REGISTERS
1st-RANK REGISTERS
EDGE/LEVEL
WR
CE
CE
SER/PAR
V+ V-
DGND
AGND
A0
A1
D3
A2
D2
D1/SER OUT
D0/SER IN
Figure 1. MAX4456 Functional Diagram
6
_______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
through 0±±± (D3–D0) for the MAX4360, and codes
0000 through 00±± (D3–D0) for the MAX4359. Note that
the MAX4359 does not use codes 0±00 through 0±±±.
The eight codes ±000 through ±±±± control other func-
tions, as listed in Table ±.
Power-On RESET
The MAX4359/MAX4360/MAX4456 have an internal
power-on reset (POR) circuit that remains low for 5µs
after power is applied. POR also remains low if the total
supply voltage is less than 4V. The POR disables all
buffer outputs at power-up, but the switch matrix is
not preset to any initial condition. The desired switch
state should be programmed before the buffer outputs
are enabled.
7-Bit Parallel-Interface Mode (MAX4456)
In the MAX4456’s parallel-interface mode (SER/PAR =
GND), the seven data bits specify an output channel
(A2, A±, A0) and the input channel to which it connects
(D3–D0). This data is loaded on the rising edge of WR.
The input channels are selected by codes 0000
through 0±±± (D3–D0) for the MAX4456. The remaining
eight codes ±000 through ±±±± control other functions,
as listed in Table ±.
Digital Interface
The desired switch state can be loaded in a parallel-
interface mode or serial-interface mode (Table 3 and
Figures 4, 5, 6). All action associated with the WR line
occurs on its rising edge. The same is true for the
LATCH line if EDGE/LEVEL is high. Otherwise, the sec-
ond-rank registers update while LATCH is low (when
EDGE/LEVEL is low). WR is logically ANDed with CE
and CE (when present) to allow active-high or active-
low chip enable.
16-Bit Serial-Interface Mode
(MAX4359/MAX4360)
In serial mode (SER/PAR = V ), all first-rank registers
CC
are loaded with data, making it unnecessary to specify
an output address (A±, A0). The input data format is
D3–D0, starting with OUT0 and ending with OUT3 for
±6 total bits. For the MAX4360, only codes 0000
through ±0±0 are valid. For the MAX4359, only the
codes 0000 through 00±± and codes ±000 through
±0±0 are valid. Code ±0±0 disables a buffer, while
code ±00± enables it. After data is shifted into the ±6-
bit first-rank register, it is transferred to the second rank
by LATCH (Table 2), which updates the switches.
6-Bit Parallel-Interface Mode
(MAX4359/MAX4360)
In the MAX4359/MAX4360’s parallel-interface mode
(SER/PAR = GND), the six data bits specify an output
channel (A±, A0) and the input channel to which it con-
nects (D3–D0). This data is loaded on the rising edge
of WR. The input channels are selected by codes 0000
Table 1. Parallel-Interface Mode Functions
A2, A1, A0
D3–D0
FUNCTION
Connect the buffer selected by A2–A0 (MAX4456) or A±–A0 (MAX4359/MAX4360) to the
input channel selected by D3–D0.
0000 to 0±±±
Connect the buffer selected by A2–A0 (MAX4456) or A±–A0 (MAX4359/MAX4360) to
DGND. Note, if the buffer output is on, its output is its offset voltage.
±000
±0±±
±±00
±±0±
±±±0
Shut off the buffer selected by A2–A0 (MAX4456) or A±–A0 (MAX4359/MAX4360) and
retain 2nd-rank registers contents.
Turn on the buffer selected by A2–A0 (MAX4456) or A±–A0 (MAX4359/MAX4360, and
restore the previously connected channel.
Selects
Output
Buffer
Turn off all buffers, and leave 2nd-rank registers unchanged.
Turn on all buffers, and restore the connected channels.
Send a pulse to the 2nd-rank registers to load them with the contents of the ±st-rank
registers. When latch is held high, this “software-LATCH” command performs the same
function as pulsing LATCH low.
±±±±
Do not use these codes in the parallel-interface mode. These codes are for the serial-
interface mode only.
±00± and ±0±0
0±00 and 0±±±
For the MAX4359, unused codes.
_______________________________________________________________________________________
7
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
32-Bit Serial-Interface Mode (MAX4456)
Table 2. Serial-Interface Mode Functions
In serial mode (SER/PAR = V ), all first-rank registers
CC
are loaded with data, making it unnecessary to specify
an output address (A2, A±, A0). The input data format
is D3–D0, starting with OUT0 and ending with OUT7 for
32 total bits. Only codes 0000 through ±0±0 are valid.
Code ±0±0 disables a buffer, while code ±00± enables
it. After data is shifted into the 32-bit first-rank register, it
is transferred to the second rank by LATCH (Table 2),
which updates the switches.
D3–D0
FUNCTION
Connect the selected buffer to the input
channel selected by D3–D0. Note that 0±00
through 0±±± are not valid for the MAX4359.
0000 to 0±±±
Connect the input of the selected buffer to
GND. Note: If the buffer output remains
on, its input is its offset voltage.
±000
±00±
Turn on the selected buffer and connect
its input to GND. Use this code to turn on
buffers after power is applied. The default
power-up state is all buffers disabled.
Shut off the selected buffer at the speci-
fied channel, and erase data stored in the
2nd rank of registers. The 2nd rank now
holds the command word ±0±0.
±0±0
Do not use these codes in the serial-inter-
face mode. They inhibit the latching of the
2nd-rank registers, which prevents proper
data loading.
±0±± to ±±±±
Table 3. Input/Output Line Configurations
SERIAL /
PARALLEL
(A2), A1,
D3
D2
D1
D0
COMMENT
A0
Serial
Output
H
X
X
Serial Input
X
Serial Mode
Output
Buffer
Address
Parallel
Input
Parallel
Input
Parallel
Input
Parallel Mode,
D0–D2 = Control Code
L
L
H
L
Output
Buffer
Address
Parallel
Input
Parallel
Input
Parallel
Input
Parallel Mode,
D0–D2 = Input Address
X = Don’t care, H = 5V, L = 0V
( ) are for MAX4456 only.
8
_______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
MAX497
Z = 75Ω
0
75Ω
IN0
OUT0
5
39
2
16
OUT0
IN0
A = 2
V
7
9
11
13
15
17
19
37
35
33
31
29
27
25
24
14
8
4
6
8
14
12
10
IN1
IN2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CE
IN1
IN2
IN3
OUT1
OUT2
OUT3
75Ω
8 INPUT
VIDEO
CHANNELS
IN3
IN4
IN5
IN6
IN7
MAX4456
V
V
GND
EE
CC
1, 3, 5, 7
9,15
11,13
-5V
EDGE/LEVEL
22
21
LOAD
V+
V+
LATCH
WR
1
2
40
26
14
+5V
3
4
5
6
7
8
2
1
38
36
6
28, 30, 32
10, 12
20
34
23
18
16
AGND
DGND
V-
V-
CE
SER/PAR
V+
D0/SER IN
D1/SER OUT
D2
D3
A0
A1
A2
18
19
20
21
22
23
24
25
-5V
4
3
+5V
DB–25
NOTE: ALL BYPASS CAPACITORS ARE 0.1µF CERAMIC.
Figure 2. MAX4456 (plastic DIP) Typical Application Circuit
The short BASIC program in Figure 3 loads program-
ming data into the MAX4456 from any IBM PC or com-
patible. It uses the computer’s “LPT±” output to interface
to the circuit, then automatically finds the address for
LPT± and displays a table of valid input values to be
used. The program does not keep track of previous
commands, but it does display the last data sent to
LPT±, which is written and latched with each transmis-
sion. A similar application is possible with the
MAX4359/MAX4360.
Typical Application
Figure 2 shows a typical application of the MAX4456
(PDIP) with MAX497 quad, gain-of-two buffers at the
outputs to drive 75Ω loads. This application shows the
MAX4456 digital-switch control interface set up in the 7-
bit parallel mode. The MAX4456 uses seven data lines
and two control lines (WR and LATCH). Two additional
lines may be needed to control CE and LOAD when
using multiple MAX4456s.
The input/output information is presented to the chip at
A2, A±, A0, and D3–D0 by a parallel printer port. The
data is stored in the ±st-rank registers on the rising
edge of WR. When the LATCH line goes high, the
switch configuration is loaded into the 2nd-rank regis-
ters, and all eight outputs enter the new configuration at
the same time. Each 7-bit word updates only one out-
put buffer at a time. If several buffers are to be updat-
ed, the data is individually loaded into the ±st-rank reg-
isters. Then, a single LATCH pulse is used to reconfig-
ure all channels simultaneously.
Chip Information
MAX4359 TRANSISTOR COUNT: 2372
MAX4360 TRANSISTOR COUNT: 2372
MAX4456 TRANSISTOR COUNT: 3820
_______________________________________________________________________________________
9
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Figure 3. BASIC Program for Loading Data into the MAX4456 from a PC Using Figure 2’s Circuit
Timing Diagrams
A0–A2
VALID DATA N-1
VALID DATA N
D0–D3
t
DS
t
DH
t
WL
t
WH
WR
t
D
t
L
LATCH
Figure 4. Write Timing for Serial- and Parallel-Interface Modes
10 ______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Timing Diagrams (continued)
NOTE: SEE FIGURE 4 FOR WR AND LATCH TIMING.
DATA (N)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
1st-RANK REGISTER DATA
DATA (N)
DATA (N)
DATA (N + 1)
DATA (N + 2)
2nd-RANK REGISTER DATA
(EDGE/LEVEL = GND)
DATA (N + 1)
2nd-RANK REGISTER DATA
DATA (N)
DATA (N + 1)
(EDGE/LEVEL = V
)
CC
Figure 5. Parallel-Interface Mode Format (SER/PAR = GND)
NOTES: SEE TABLE 2 FOR INPUT DATA.
SEE FIGURE 4 FOR WR AND LATCH TIMING.
INPUT DATA FOR OUT0
INPUT DATA FOR OUT1 TO OUT6
INPUT DATA FOR OUT7
0D3
0D2
0D1
0D0
1D3
1D2
7D3
7D2
7D1
7D0
WR
LATCH
2nd-RANK REGISTER DATA
(EDGE/LEVEL = GND)
DATA VALID
2nd-RANK REGISTER DATA
DATA VALID
(EDGE/LEVEL = V
)
CC
Figure 6. Serial-Mode Interface Format (SER/PAR = V
)
CC
______________________________________________________________________________________ 11
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Dynamic Test Circuits
IN0
OUT0
OUT1
OUT2
OUT0
OUT1
OUT2
IN0
V
V
V
OUT
OUT
OUT
OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V
OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
MAX4456
OUT3
OUT4
OUT5
OUT6
OUT3
OUT4
OUT5
OUT6
MAX4456
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT7
LOAD
OUT7
LOAD
+5V
+5V
V
IN
R
S
= 2Vp-p AT 5MHz
= 75Ω
V
R
= 2Vp-p, SWEEP FREQUENCY
= 75Ω
IN
S
-3dB BANDWIDTH (NOTES 1–4)
ALL-CHANNEL OFF-ISOLATION (NOTES 1, 5–8)
IN0
IN0
OUT0
OUT1
OUT2
V
OUT
OUT0
V
V
V
V
OUT
OUT
OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN1
IN2
IN3
IN4
IN5
IN6
IN7
OUT1
OUT2
75Ω
OUT3
OUT4
OUT5
OUT6
OUT3
OUT4
OUT5
OUT6
MAX4456
OUT
MAX4456
7 x 75Ω
V
OUT
OUT
OUT
V
V
OUT7
LOAD
OUT7
LOAD
+5V
+5V
V
IN
R
S
= 2Vp-p AT 5MHz
= 75Ω
V
IN
R
S
= 2Vp-p AT 5MHz
= 75Ω
SINGLE-CHANNEL CROSSTALK (NOTES 1, 5, 9–11)
ALL-HOSTILE CROSSTALK (NOTES 1, 5, 9, 11, 12)
Note 1: Connect LOAD to +5V (internal 400Ω loads on at all outputs).
Note 2: Program any one input to connect to any one output. See Table ± or 2 for programming codes.
Note 3: Turn on the buffer at the selected output (Table ± or 2).
Note 4: Drive the selected input with V , and measure V
at the -3dB frequency at the selected output.
IN
OUT
Note 5: Program each numbered input to connect to the same numbered output (IN0 to OUT0, IN± to OUT±, etc., for the MAX4456;
also IN4 to OUT0, IN5 to OUT±, etc., for the MAX4360.) See Table ± or 2 for programming codes.
Note 6: Turn off all output buffers (Table ± or 2).
Note 7: Drive all inputs with V , and measure V
at any output.
IN
OUT
Note 8: Isolation (in dB) = 20log (V
/V ).
±0 OUT IN
Note 9: Turn on all output buffers (Table ± or 2).
Note 10: Drive any one input with V , and measure V
at any undriven output.
OUT
IN
Note 11: Crosstalk (in dB) = 20log (V
/V ).
±0 OUT IN
Note 12: Drive all but one input with V , and measure V
at the undriven output.
IN
OUT
12 ______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Pin Configurations
TOP VIEW
D1/SER OUT
D0/SER IN
A1
1
2
3
4
5
6
7
8
9
36 V+
D1/SER OUT
D0/SER IN
A1
1
2
3
4
5
6
7
8
9
36 V+
D1/SER OUT
D0/SER IN
A1
1
2
3
4
5
6
7
8
9
24 V+
35 OUT0
34 D2
35 OUT0
34 D2
23 OUT0
22 D2
IN0
33 OUT1
32 D3
IN0
33 OUT1
IN0
21 OUT1
20 D3
A0
MAX4359
A0
32
D3
A0
MAX4359
MAX4360
IN1
31 OUT2
30 V-
IN1
31 OUT2
30 V-
IN1
19 OUT2
18 AGND
17 OUT3
16 CE
LOAD
IN2
LOAD
IN2
LOAD
IN2
AGND
29
AGND
29
DGND
28 OUT3
27 CE
DGND
28 OUT3
27 CE
DGND
IN3 10
EDGE/LEVEL 11
N.C. 12
IN3 10
EDGE/LEVEL 11
IN4 12
IN3 10
EDGE/LEVEL 11
SER/PAR 12
15 LATCH
14 WR
26 N.C.
25 N.C.
24 N.C.
23 N.C.
22 N.C.
21 LATCH
20 WR
26 N.C.
25 N.C.
24 N.C.
23 N.C.
22 N.C.
21 LATCH
20 WR
13 V-
N.C. 13
V+ 13
SO
N.C. 14
IN5 14
N.C. 15
AGND 15
IN6 16
N.C. 16
D1/SER OUT
1
V+
40
SER/PAR 17
N.C. 18
SER/PAR 17
IN7 18
D0/SER IN
2
OUT0
39
19 V-
19 V-
A2
3
D2
38
A1
4
SSOP
SSOP
OUT1
37
MAX4456
IN0
5
D3
36
A0
6
OUT2
V-
35
34
33
32
31
IN1
7
44
43 42 41 40
6
5
4
3
2
1
LOAD
8
OUT3
AGND
OUT4
AGND
OUT5
AGND
OUT6
V+
IN2
9
A0
IN1
39 OUT2
38 V-
7
8
DGND
10
IN3
11
30
29
28
27
26
25
24
23
22
21
LOAD
IN2
9
37 OUT3
36 AGND
DGND
12
10
IN4
13
DGND 11
N.C. 12
35
34
33
32
31
30
OUT4
N.C.
MAX4456
EDGE/LEVEL
14
IN3 13
AGND
OUT5
AGND
OUT6
IN5
15
DGND 14
IN4 15
V+
16
OUT7
CE
IN6
17
EDGE/LEVEL 16
IN5 17
SER/PAR
18
CE
29 V+
IN7
19
LATCH
WR
18 19 20 21 22 23 24 25 26 27 28
V-
20
DIP
PLCC
______________________________________________________________________________________ 13
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Package Information
14 ______________________________________________________________________________________
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Package Information (continued)
______________________________________________________________________________________ 15
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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