MAX4588CWI [MAXIM]
Low-Voltage, High-Isolation, Dual 4-Channel RF/Video Multiplexer; 低电压，高隔离，双路4通道射频/视频多路复用器
| 型号： | MAX4588CWI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Voltage, High-Isolation, Dual 4-Channel RF/Video Multiplexer |
| 文件： | 总20页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1425; Rev 0; 1/99
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX4588 low-voltage, dual 4-channel multiplexer
is designed for RF and video signal processing at fre-
quencies up to 180MHz in 50Ω and 75Ω systems. A
flexible digital interface allows control of on-chip func-
tions through either a parallel interface or an SPI™/
MICROWIRE™ serial port.
♦ Low Insertion Loss: -2.5dB up to 100MHz
♦ High Off-Isolation: -74dB at 10MHz
♦ Low Crosstalk: -70dB up to 10MHz
♦ 16MHz -0.1dB Signal Bandwidth
♦ 180MHz -3dB Signal Bandwidth
Each channel of the MAX4588 is designed using a “T”
switch configuration, ensuring excellent high-frequency
off-isolation. The MAX4588 has low on-resistance of
60Ω max, with an on-resistance match across all chan-
ne ls of 4Ω ma x. Ad d itiona lly, on-re s is ta nc e is fla t
across the specified signal range (2Ω max). The off-
♦ 60Ω (max) On-Resistance with ±5V Supplies
♦ 4Ω (max) On-Resistance Matching with ±5V
Supplies
♦ 2Ω (max) On-Resistance Flatness with ±5V
leakage current is under 1nA at T = +25°C, and less
A
Supplies
than 10nA at T = +85°C.
A
♦ +2.7V to +12V Single Supply
The MAX4588 operates from single +2.7V to +12V or
dual ±2.7V to ±6V supplies. When operating with a +5V
supply, the inputs maintain TTL- and CMOS-level com-
patibility. The MAX4588 is available in 28-pin narrow
DIP, wide SO, and space-saving SSOP packages.
±2.7V to ±6V Dual Supplies
♦ Low Power Consumption: <20µW
♦ Rail-to-Rail®, Bidirectional Signal Handling
♦ Parallel or SPI/MICROWIRE-Compatible Serial
Ap p lic a t io n s
Interface
RF Switching
Automatic Test Equipment
♦ >±2kV ESD Protection per Method 3015.7
Video Signal Routing
High-Speed Data Acquisition
Networking
♦ TTL/CMOS-Compatible Inputs with V = +5V
L
P in Co n fig u ra t io n
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
TOP VIEW
MAX4588CAI
MAX4588CWI
MAX4588CPI
MAX4588EAI
MAX4588EWI
MAX4588EPI
GND
COM1
V+
1
2
3
4
5
6
7
8
9
28 COM2
MAX4588
28 Wide SO
27 V-
28 Narrow Plastic DIP
28 SSOP
26 NO5
25 GND
24 NO6
23 GND
22 NO7
21 GND
20 NO8
NO1
28 Wide SO
GND
NO2
28 Narrow Plastic DIP
GND
NO3
GND
NO4 10
4/8 11
19 V
L
18 SER/PAR
17 EN
RS 12
CONTROL
LOGIC
LE/CS 13
A2/SCLK 14
16 A0/DOUT
15 A1/DIN
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
SSOP/SO/DIP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
ESD per Method 3015.7.......................................................±2kV
V+ ........................................................................-0.3V to +13.0V
Continuous Power Dissipation (T = +70°C)
A
V .......................-0.3V to (V+ + 0.3V) or 7V (whichever is lower)
V- ........................................................................-13.0V to +0.3V
V+ to V-................................................................-0.3V to +13.0V
SSOP (derate 9.52mW/°C above +70°C) ....................762mW
Wide SO (derate 12.50mW/°C above +70°C)................1.00W
Plastic DIP (derate 14.29mW/°C above +70°C) ............1.14W
Operating Temperature Ranges
L
V
, V
(Note 1) ..........................(V- - 0.3V) to (V+ + 0.3V)
NO_ COM_
MAX4588C_ I ......................................................0°C to +70°C
MAX4588E_ I ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
4/8, RS, LE/CS, A2/SCLK, A1/DIN,
A0/DOUT, EN, SER/PAR to GND ...............-0.3V to (V+ + 0.3V)
Continuous Current into Any Terminal..............................±20mA
Peak Current into Any Terminal
MAX458
(pulsed at 1ms, 10% duty cycle)..................................±40mA
Note 1: Voltages on these pins exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current
rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V+ = V = +4.5V to +5.5V, V- = -4.5V to -5.5V, V
= +2.4V, V
= +0.8V, T = T
to T , unless otherwise noted. Typical val-
MAX
L
INH
INL
A
MIN
ues are at T = +25°C, V+ = V = +5V, V- = -5V.) (Note 2)
A
L
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOGSWITCH
Analog Signal Range
(Note 3)
V
V
,
COM_
V-
V+
V
Ω
NO
+25°C
C, E
40
1
60
75
4
V+ = 5V, V- = -5V, V
= ±2V,
NO_
On-Resistance
R
ON
I
= 4mA
COM_
+25°C
C, E
On-Resistance Match Between
Channels (Note 4)
V+ = 5V, V- = 5V, V
= ±2V,
NO_
∆R
Ω
ON
I
= 4mA
COM_
5
+25°C
C, E
0.5
2.5
3
On-Resistance Flatness
(Note 5)
V+ = 5V; V- = -5V; V
= 1V, 0, -1V;
NO_
R
Ω
FLAT(ON)
I
= 1mA
COM_
+25°C
C, E
-1
-10
-2
0.01
0.01
0.01
1
NO_ Off-Leakage Current
(Note 6)
V+ = 5.5V, V- = -5.5V,
= ±4.5V, V
I
nA
nA
nA
NO_(OFF)
–
V
COM_
=
=
4.5V
4.5V
NO_
+
10
2
+25°C
C, E
COM_ Off-Leakage Current
(Note 6)
V+ = 5.5V, V- = -5.5V,
= ±4.5V, V
I
COM_(OFF)
–
V
COM_
NO_
+
-20
-2
20
2
+25°C
C, E
COM_ On-Leakage Current
(Note 6)
V+ = 5.5V, V- = -5.5V, V
= ±4.5V,
COM_
I
COM_(ON)
V
NO_
= ±4.5V or floating
-20
20
LOGIC INPUTS (4/8, RS, LE/CS, A2/SCLK, A1/DIN, A0/DOUT, EN, SER/PAR)
Input Logic Threshold High
Input Logic Threshold Low
Input Threshold Hysteresis
Input Current
V
C, E
C, E
2.4
-1
1.7
1.5
V
V
INH
V
INL
0.8
1
0.2
V
I
V
IN_
= 0 or V
L
C, E
0.03
µA
IN
LOGIC OUTPUT(SERIAL INTERFACE)
DOUT Logic Low Output
DOUT Logic High Output
V
I
= 3.2mA
C, E
C, E
0.4
V
V
OL
SINK
V
OH
I
= -1mA
V - 1
L
SOURCE
2
_______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = V = +4.5V to +5.5V, V- = -4.5V to -5.5V, V
= +2.4V, V
= +0.8V, T = T
to T
, unless otherwise noted. Typical val-
L
INH
INL
A
MIN
MAX
ues are at T = +25°C, V+ = V = +5V, V- = -5V.) (Note 2)
A
L
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
380
150
MAX
UNITS
A
SWITCHDYNAMICCHARACTERISTICS
+25°C
C, E
550
600
300
350
V
= 3V, V+ = 4.5V, V- = -4.5V,
NO_
Turn-On Time
Turn-Off Time
t
ns
ns
ON
Figure 1
+25°C
C, E
V
= 3V, V+ = 4.5V, V- = -4.5V,
NO_
t
OFF
Figure 1
Break-Before-Make Time Delay
(Note 3)
V
NO_
Figure 2
= ±3V, V+ = 5.5V, V- = -5.5V,
t
C, E
10
180
15
ns
BBM
Q
C
= 1.0nF, V
= 0, R = 0,
S
L
NO_
Charge Injection
+25°C
pC
Figure 3
NO_ Off-Capacitance
COM_ Off-Capacitance
COM_ On-Capacitance
C
V
= 0, f = 1MHz, Figure 4
+25°C
+25°C
+25°C
2
4
7
pF
pF
pF
NO_(OFF)
NO_
IN
C
C
V
= 0, f = 1MHz, Figure 4
COM_(OFF)
COM_(ON)
COM_ IN
V
COM_
= 0, f = 1MHz, Figure 4
IN
V
= 1V
, f = 10MHz,
NO_
RMS
Off-Isolation (Note 7)
Channel-to-Channel Crosstalk
-3dB Bandwidth
V
+25°C
+25°C
+25°C
-74
dB
dB
ISO
all channels off, Figure 5
V
V
NO_
= 1V
RMS
, f = 10MHz, Figure 5
4-channel mode
8-channel mode
4-channel mode
8-channel mode
-70
180
140
16
CT
BW
BW
Figure 5
Figure 5
MHz
-0.1dB Bandwidth
+25°C
MHz
11
PARALLEL-INTERFACETIMING
A_, EN to LE Rise Setup Time
A_, EN to LE Rise Hold Time
LE Low Pulse Width
t
Figure 6
Figure 6
Figure 6
Figure 6
C, E
C, E
C, E
C, E
80
0
ns
ns
ns
ns
DS
t
DH
t
L
80
80
t
RS Low Pulse Width
RS
SERIAL-INTERFACETIMING
Operating Frequency
f
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
C, E
C, E
C, E
C, E
C, E
C, E
C, E
C, E
6.25
MHz
ns
CLK
SCLK Pulse Width High
t
80
80
60
0
CH
SCLK Pulse Width Low
t
ns
CL
DS
DH
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Rise to DOUT Valid
CS Rise to SCLK Rise Hold Time
t
ns
t
ns
t
t
50
ns
CSS0
t
C
= 50pF, Figure 7
L
150
ns
DO
Figure 7
0
ns
CSH1
CS Rise to SCLK Rise Setup
Time
t
Figure 7
C, E
80
ns
CSS1
t
Figure 7
Figure 6
C, E
C, E
80
80
ns
ns
CS Fall to SCLK Rise Hold Time
RS Low Pulse Width
CSS1
t
RS
_______________________________________________________________________________________
3
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = V = +4.5V to +5.5V, V- = -4.5V to -5.5V, V
= +2.4V, V
= +0.8V, T = T
to T
, unless otherwise noted. Typical val-
L
INH
INL
A
MIN
MAX
ues are at T = +25°C, V+ = V = +5V, V- = -5V.) (Note 2)
A
L
PARAMETER
SYMBOL
CONDITIONS
T
A
MIN
TYP
MAX
UNITS
POWERSUPPLY
V+, V-
±2.7
2.7
-1
±6
V+
1
Power-Supply Range
V+ Supply Current
V - Supply Current
V
V
L
+25°C
C, E
0.0001
0.0001
2
MAX458
I+
I-
V+ = 5.5V, V- = -5.5V
µA
-10
-1
10
1
+25°C
C, E
V+ = 5.5V, V- = -5.5V
µA
µA
-10
-10
10
10
V Supply Current
L
I
L
V = 5.5V, all V = 0 or V
L
C, E
L
IN_
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = V = +4.5V to +5.5V, V- = 0, V
= +2.4V, V
= +0.8V, T = T
to T
, unless otherwise noted. Typical values are at T
L
INH
INL
A
MIN
MAX A
= +25°C, V+ = V = +5V.) (Note 2)
L
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOGSWITCH
V
V
,
COM_
Analog Signal Range (Note 3)
On-Resistance
0
V+
V
Ω
NO_
+25°C
C, E
80
1
120
150
8
R
V+ = 5V, V
= 3V, I
= 3V, I
= 4mA
= 4mA
ON
NO_
COM_
+25°C
C, E
On-Resistance Match Between
Channels (Note 4)
∆R
V+ = 5V, V
Ω
ON
NO_
COM_
10
10
12
1
= 4mA,
COM_
+25°C
C, E
4
On-Resistance Flatness
(Note 5)
V+ = 5V, I
R
Ω
FLAT(ON)
V
= 2V, 3V, 4V
NO_
+25°C
C, E
-1
-10
-2
0.005
0.005
0.005
NO_ Off Leakage Current
(Notes 6, 9)
V+ = 5.5V; V
= 4.5V, 1V;
COM_
COM_
COM_
I
nA
nA
nA
NO_(OFF)
V
NO_
= 1V, 4.5V
10
2
+25°C
C, E
COM_ Off Leakage Current
(Notes 6, 9)
V+ = 5.5V; V
= 4.5V, 1V;
= 4.5V, 1V;
I
COM(OFF)
V
NO_
= 1V, 4.5V
-20
-2
20
2
+25°C
C, E
COM_ On Leakage Current
(Notes 6, 9)
V+ = 5.5V; V
I
COM_(ON)
V
NO_
= 4.5V, 1V, or floating
-20
20
LOGIC INPUTS (4/8, RS, LE/CS, A2/SCLK, A1/DIN, A0/DOUT, EN, SER/PAR)
Input Logic Threshold High
Input Logic Threshold Low
Input Threshold Hysteresis
Input Current
V
C, E
C, E
2.4
-1
1.7
1.5
0.2
V
V
INH
V
INL
0.8
1
V
I
V
IN
= 0 or V
L
C, E
µA
IN
LOGICOUTPUT(SERIAL INTERFACE)
DOUT Logic Low Output
DOUT Logic High Output
V
I
= 3.2mA
C, E
C, E
0.4
V
V
OL
SINK
V
OH
I
= -1mA
V - 1
L
SOURCE
4
_______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = V = +4.5V to +5.5V, V- = 0, V
= +2.4V, V
= +0.8V, T = T
to T , unless otherwise noted. Typical values are at T
MAX A
L
INH
INL
A
MIN
= +25°C, V+ = V = +5V.) (Note 2)
L
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
550
150
MAX
UNITS
A
SWITCHDYNAMICCHARACTERISTICS
+25°C
C, E
800
900
300
350
Turn-On Time
Turn-Off Time
t
V
= 3V, V+ = 4.5V, Figure 1
= 3V, V+ = 4.5V, Figure 1
= 3V, V+ = 5.5V, Figure 2
NO_
ns
ns
ON
NO_
+25°C
C, E
t
V
NO_
OFF
Break-Before-Make Time Delay
(Note 3)
t
V
C, E
10
200
5
ns
BBM
Q
C
= 1.0nF, V = 2.5V, R = 0,
NO_ S
L
Charge Injection
+25°C
pC
Figure 3
V
= 1V
, f = 10MHz,
RMS
NO_
Off-Isolation
V
+25°C
+25°C
+25°C
-65
dB
dB
ISO
all channels off, Figure 5
Channel-to-Channel Crosstalk
-3dB Bandwidth
V
V
NO_
= 1V
RMS
, f = 10MHz, Figure 5
4-channel mode
8-channel mode
4-channel mode
8-channel mode
-70
100
75
10
7
CT
BW
BW
Figure 5
Figure 5
MHz
-0.1dB Bandwidth
+25°C
MHz
PARALLEL-INTERFACETIMING
A_, EN to LE Rise Setup Time
A_, EN to LE Rise Hold Time
LE Low Pulse Width
t
Figure 6
Figure 6
Figure 6
Figure 6
C, E
C, E
C, E
C, E
80
0
ns
ns
ns
ns
DS
t
DH
t
L
80
80
t
RS Low Pulse Width
RS
SERIAL-INTERFACETIMING
Operating Frequency
f
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
C, E
C, E
C, E
C, E
C, E
C, E
C, E
6.25
MHz
ns
CLK
SCLK Pulse Width High
t
80
80
60
0
CH
SCLK Pulse Width Low
t
ns
CL
DS
DH
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
CS Fall to SCLK Rise Setup Time
CS Fall to SCLK Rise Hold Time
t
ns
t
ns
t
t
50
80
ns
CSS0
CSS1
ns
t
Figure 7
Figure 7
C, E
C, E
0
ns
ns
CS Rise to SCLK Rise Hold Time
CSH1
CS Rise to SCLK Rise Setup
Time
t
80
CSS1
SCLK Rise to DOUT Valid
t
C
= 50pF, Figure 7
L
C, E
C, E
150
ns
ns
DO
t
Figure 6
80
RS Low Pulse Width
RS
_______________________________________________________________________________________
5
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = V = +4.5V to +5.5V, V- = 0, V
= +2.4V, V
= +0.8V, T = T
to T , unless otherwise noted. Typical values are at T
MAX A
L
INH
INL
A
MIN
= +25°C, V+ = V = +5V.) (Note 2)
L
PARAMETER
SYMBOL
V+
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
POWERSUPPLY
2.7
2.7
2.7
-1
12
V+
6.5
1
Power-Supply Range
V+ ≤ 6.5V
V
V
L
V+ > 6.5V
MAX458
+25°C
C, E
V+ Supply Current
I+
V+ = 5.5V, V = 0 or V
µA
µA
L
IN
-10
-10
10
10
V Supply Current
I
L
V = 5.5V, all V = 0 or V
L
C, E
2
L
L
IN_
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = V = +2.7V to +3.6V, V- = 0, V
= +2V, V
= +0.5V, T = T
to T , unless otherwise noted. Typical values are at T =
MAX A
L
INH
INL
A
MIN
+25°C, V+ = V = +3.0V.)
L
PARAMETER
SYMBOL
CONDITIONS
T
A
MIN
TYP
MAX
UNITS
ANALOGSWITCH
V
V
,
COM_
Analog Signal Range
On-Resistance
0
V+
V
NO_
+25°C
C, E
240
350
450
V+ = 2.7V, V
= 1V,
NO_
R
Ω
ON
I
= 1mA
COM_
LOGIC INPUTS (4/8, RS, LE/CS, A2/SCLK, A1/DIN, A0/DOUT, EN, SER/PAR)
Input Logic Threshold High
Input Logic Threshold Low
Input Current
V
C, E
C, E
C, E
2.0
-1
V
V
INH
V
INL
0.5
1
I
V
IN_
= 0 or V
µA
L
IN
SWITCHDYNAMICCHARACTERISTICS
+25°C
C, E
700
250
1000
200
400
500
Turn-On Time
Turn-Off Time
t
V
= 1.5V, V+ = 2.7V, Figure 1
= 1.5V, V+ = 2.7V, Figure 1
= 1.5V, V+ = 3.6V, Figure 2
NO_
ns
ns
ns
ON
NO_
+25°C
C, E
t
V
NO_
OFF
Break-Before-Make Time Delay
(Note 3)
t
V
+25°C
10
350
BBM
PARALLEL-INTERFACETIMING
A_, EN to LE Rise Setup Time
A_, EN to LE Rise Hold Time
LE Low Pulse Width
t
Figure 6
Figure 6
Figure 6
Figure 6
C, E
C, E
C, E
C, E
200
0
ns
ns
ns
ns
DS
t
DH
t
200
200
L
t
RS Low Pulse Width
RS
SERIAL-INTERFACETIMING
Operating Frequency
f
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 6
C, E
C, E
C, E
C, E
C, E
C, E
2.1
MHz
ns
CLK
SCLK Pulse Width High
SCLK Pulse Width Low
t
200
200
100
0
CH
t
ns
CL
DS
DH
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
RS Low Pulse Width
t
ns
t
ns
t
200
ns
RS
6
_______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = V = +2.7V to +3.6V, V- = 0, V
= +2V, V
= +0.5V, T = T
to T , unless otherwise noted. Typical values are at T =
MAX A
L
INH
INL
A
MIN
+25°C, V+ = V = +3.0V.)
L
PARAMETER
SYMBOL
CONDITIONS
T
MIN
100
0
TYP
MAX
UNITS
ns
A
t
Figure 7
Figure 7
C, E
C, E
CS Fall to SCLK Rise Setup Time
CS Rise to SCLK Rise Hold Time
CSS0
t
ns
CSH1
CS Rise to SCLK Rise Setup
Time
t
t
Figure 7
C, E
200
200
ns
CSS1
Figure 7
C, E
C, E
ns
ns
CS Fall to SCLK Rise Hold Time
SCLK Rise to DOUT Valid
POWERSUPPLY
CSS1
t
C
= 50pF, Figure 7
L
250
DO
I+
+25°C
C, E
-1
1
V+ Supply Current
V+ = 3.6V, V = 0 or V
µA
µA
L
IN
-10
-10
10
10
V Supply Current
L
I
L
V = 3.6V, all V = 0 or V
L L
C, E
1
IN
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: Guaranteed by design.
Note 4: ∆R
= ∆R
- ∆R
.
ON(MIN)
ON
ON(MAX)
Note 5: Resistance flatness is defined as the difference between the maximum and the minimum value of on-resistance as
measured over the specified analog-signal range.
Note 6: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at T = +25°C.
A
Note 7: Off isolation = 20log [V
/ (V
or V
)], V
= output, V
or V
= input to off switch.
10 COM_
NC_
NO_
COM_
NC_
NO_
Note 8: Between any two switches.
Note 9: Leakage testing for single-supply operation is guaranteed by testing with dual supplies.
_______________________________________________________________________________________
7
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V+ = V = +5V, V- = -5V, T = +25°C, unless otherwise noted.)
L
A
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
(SINGLE SUPPLY)
(DUAL SUPPLIES)
100
90
80
70
60
50
40
30
20
10
0
250
200
V- = 0
V+ = +2.5V
±2.5V
±3V
MAX458
150
100
50
V+ = +3.0V
V+ = +3.6V
±4V
±5V
V+ = +5V
±6V
V+ = +9V
V+ = +12V
10 12
0
0
2
4
6
8
-6
-4
-2
0
2
4
6
V
COM
(V)
V
COM
(V)
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
AND TEMPERATURE (DUAL SUPPLIES)
AND TEMPERATURE (SINGLE SUPPLY)
70
65
60
55
50
45
40
35
30
25
20
140
130
120
110
100
90
V- = 0
T = +85°C
A
T = +85°C
A
T = +50°C
A
T = +50°C
A
T = +25°C
A
T = +25°C
A
80
T = 0°C
A
T = 0°C
A
70
T = -40°C
A
60
T = -40°C
A
50
40
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
COM
(V)
V
COM
(V)
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
CHARGE INJECTION vs. V
COM
35
30
25
20
15
10
5
10n
1n
DUAL SUPPLIES
100p
10p
1p
ON-LEAKAGE
OFF-LEAKAGE
SINGLE SUPPLY
0
0.1p
-5 -4 -3 -2 -1
0
1
2
3
4
5
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
V
(V)
COM
8
_______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V+ = V = +5V, V- = -5V, T = +25°C, unless otherwise noted.)
L
A
ON/OFF TIME vs. TEMPERATURE
ON/OFF TIME vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
500
400
300
200
10µ
1µ
600
500
400
300
200
100
0
I
L
t
ON
100n
10n
1n
t
ON
t
OFF
t
OFF
100p
10p
1p
I+
100
0
I-
-40-30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (±V)
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
INSERTION LOSS, OFF-ISOLATION,
AND CROSSTALK vs. FREQUENCY
(DUAL SUPPLIES)
INSERTION LOSS, OFF-ISOLATION,
AND CROSSTALK vs. FREQUENCY
(SINGLE SUPPLY)
10
0
10
0
ON LOSS
INSERTION LOSS
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R = 75Ω
R = 600Ω
L
R = 75Ω
R = 600Ω
L
S
S
CROSSTALK
OFF-ISOLATION
CROSSTALK
1M
OFF-ISOLATION
100k
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
_______________________________________________________________________________________
9
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
P in De s c rip t io n
PIN
NAME
FUNCTION
1, 5, 7,
9, 21,
GND
Ground. Connect all ground pins to a ground plane. See Grounding section.
23, 25
2
3
COM1
V+
Analog Switch Common Terminal. See Truth Table.
Analog Positive Supply Voltage Input
MAX458
4
NO1
NO2
NO3
NO4
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
6
8
10
Multiplexer Configuration Control. Connect to V to select dual 2-channel mode. Connect to GND for single
L
4-channel multiplexer operation. See Truth Tables.
11
12
4/8
Active-Low Reset Input. In serial mode, drive RS low to force the latches and shift registers to the power-
on reset state and force all switches open. In parallel mode, drive RS low to force the latches to the power-
on reset state and force all switches open. See Truth Tables.
RS
In parallel mode, this pin is the transparent Latch Enable. In the serial mode, this pin is the Chip-Select
Input. See Truth Tables.
13
14
15
LE/CS
A2/SCLK
A1/DIN
Most Significant Address Bit in parallel mode with 4/8 low. If 4/8 pin is high, this pin is ignored. In the serial
mode, this is the Serial Shift Clock Input. Data is loaded on the rising edge of SCLK. See Truth Tables.
Address Input in the parallel mode. Serial Data Input in serial mode. In serial mode, data is loaded on
SCLK’s rising edge.
Least Significant Address Input in the parallel mode. In the serial mode this is an output from the internal
4-bit shift register. DOUT is intended for daisy-chain cascading. DOUT is not three-stated by CS. See
Serial Operation.
16
A0/DOUT
Switch Enable. Drive EN low to force all channels off. Drive high to allow normal multiplexer operation.
Operates asynchronously in serial mode. In parallel mode, EN is latched when LE signal is high.
17
18
19
EN
Interface Select Input. Drive low for parallel data interface operation. Drive high for serial data interface
operation and to enable the DOUT driver.
SER/PAR
Logic Supply Input. Powers the DOUT driver and other digital circuitry. V sets both the digital input and
L
output logic levels.
V
L
20
22
24
26
27
28
NO8
NO7
NO6
NO5
V-
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
Normally Open Analog Input Terminal. See Truth Tables.
Analog Negative Supply Voltage Input. Connect to ground plane for single-supply operation.
Analog Switch Common Terminal. See Truth Tables.
COM2
10 ______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
V+
V+
EN
LE/CS
EN
NO_
50%
V
50%
NO_
MAX4588
90%
90%
COM_
GND
V
OUT
V
OUT
30pF
300Ω
V-
V-
t
t
ON
OFF
Figure 1. Turn-On/Turn-Off Time
V+
V+
NO_
NO_
A0
LE/CS
SER/PAR
V
NO_
V
OUT
MAX4588
90%
A0
COM_
GND
V
OUT
30pF
300Ω
GND
V-
V-
t
BBM
Figure 2. Break-Before-Make Time Delay
V+
V+
NO_
V
NO_
LE/CS
1nF
10µF
EN
SER/PAR
MAX4588
EN
COM_
GND
V
OUT
V
OUT
∆V
OUT
C
L
Q = ∆V · C
OUT
L
V-
V-
∆V IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER
OUT
ERROR Q WHEN THE CHANNEL TURNS OFF.
Figure 3. Charge Injection
______________________________________________________________________________________ 11
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
V+
FLOATING
V+
NO_
NO_
1MHz
CAPACITANCE
ANALYZER
MAX4588
MAX4588
FLOATING
COM_
GND
COM_
GND
1MHz
CAPACITANCE
ANALYZER
MAX458
V-
V-
Figure 4. NO_, COM_ Capacitance
V+
V+
NO_
50Ω
+
-
49.9Ω
56Ω
MAX4588
NO_
MEASURE
NODE
24.9Ω
560Ω
50Ω
COM_
MEASURE
NODE
V-
V-
50Ω
ALL SIGNALS NORMALIZED TO V
= 0dB.
COM
Figure 5. Off-Isolation, Crosstalk, and Bandwidth
t
L
LE
t
DS
t
DH
MAX4588
A0, A1, A2, EN
RS
t
RS
NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t AND t <10ns. TIMING IS MEASURED FROM 50% OF DIGITAL SIGNAL.
R
F
Figure 6. Parallel Timing Diagram
12 ______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
CS
t
t
CH
t
CL
t
CSH
CSS
MAX4588
SCLK
DIN
t
DS
t
DH
A0
A2
DISABLE
A1
t
DO
DOUT
NOTE: ALL INPUT SIGNALS ARE SPECIFIED WITH t AND t < 10ns.
R
F
TIMING IS MEASURED FROM 50% OF DIGITAL SIGNAL.
Figure 7. Serial Timing Diagram
De t a ile d De s c rip t io n
NORMALLY OPEN SWITCH CONSTRUCTION
N1
Lo g ic -Le ve l Tra n s la t o rs
The MAX4588 is constructed of high-frequency “T”
switches, as shown in Figure 8. The logic-level inputs
are translated by amplifier A1 into a V+ to V- logic sig-
nal that drives amplifier A2. Amplifier A2 drives the
gates of N-channel MOSFETs N1 and N2 from V+ to V-,
turning them fully on or off. The same signal drives
inverter A3 (which drives the P-channel MOSFETs P1
and P2, turning them fully on or off) from V+ to V-, and
turns the N-channel MOSFET N3 on and off. The logic-
N2
COM_
NO_
P1
P2
V+
V
CC
A1
A2
A3
INPUT
N3
level threshold is determined by V and GND.
L
GND
V-
S w it c h On Co n d it io n
V+
V+
When the switch is on, MOSFETs N1, N2, P1, and P2
are on and MOSFET N3 is off (Figure 8). The signal
path is COM_ to NO_, and because both N-channel
and P-channel MOSFETs act as pure resistances, it is
symmetrical (i.e., signals may pass in either direction).
The off MOSFET, N3, has no DC conduction, but has a
s ma ll a mount of c a p a c ita nc e to GND. The four on
MOSFETs a ls o ha ve c a p a c ita nc e to g round tha t,
together with the series resistance, forms a lowpass fil-
ter. All of these capacitances are distributed evenly
along the series resistance, so they act as a transmis-
sion line rather than a simple R-C filter. The MAX4588’s
construction allows an exceptional 180MHz bandwidth
when the switches are on.
ESD DIODES
ON GND, NO_,
AND COM_
Figure 8. T-Switch Construction
Typical attenuation in 75Ω systems is 2.5dB and is rea-
sonably flat up to 50MHz. Higher-impedance circuits
s how e ve n lowe r a tte nua tion (a nd vic e ve rs a ), b ut
slightly lower bandwidth due to the increased effect of
the internal and external capacitance and the switch’s
internal resistance.
______________________________________________________________________________________ 13
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
The MAX4588 is optimized for ±5V operation. Using
lower supply voltages or a single supply increases
switching time, on-resistance (and therefore on-state
attenuation), and nonlinearity.
analog switches. This drive signal is the only connec-
tion between the logic supplies and the analog sup -
plies.
Bipolar-Supply Operation
The MAX4588 operates with bipolar supplies between
±2.7V and ±6V. The V+ and V- supplies are not required
to be symmetrical, but their sum cannot exceed the
absolute maximum rating of 13.0V. Do not connect the
MAX4588 V+ pin to +3V and connect the logic-level
input pins to +5V logic-level signals. This level
exceeds the absolute maximum ratings, and may
cause damage to the part and/or external circuits.
S w it c h Off Co n d it io n
When the switch is off, MOSFETs N1, N2, P1, and P2
are off and MOSFET N3 is on (Figure 8). The signal
path is through the parasitic off-capacitances of the
series MOSFETs, but it is shunted to ground by N3.
This forms a highpass filter whose exact characteristics
are dependent on the source and load impedances. In
75Ω systems, and below 10MHz, the attenuation can
exceed 80dB. This value decreases with increasing fre-
quency and increasing circuit impedances. External
capacitance and board layout have a major role in
determining overall performance.
MAX458
CAUTION: The absolute maximum V+ to V- differen-
tial voltage is 13.0V. Typical “±6-Volt” or “12-Volt”
supplies with ±10% tolerances can be as high as
13.2V. This voltage can damage the MAX4588. Even
±5% tolerance supplies may have overshoot or
noise spikes that exceed 13.0V.
Ap p lic a t io n s In fo rm a t io n
P o w e r-S u p p ly Co n s id e ra t io n s
Single-Supply Operation
The MAX4588 operates from a single supply between
+ 2.7V a nd + 12V whe n V- is c onne c te d to GND.
Observe all of the precautions listed in the Bipolar-
Supply Operation section. Note, however, that these
parts are optimized for ±5V operation, and AC and DC
characteristics are degraded significantly when operat-
ing at less than ±5V. As the overall supply voltage (V+
to V-) is reduced, switching speed, on-resistance, off-
isolation, and distortion are degraded (see Typical
Operating Characteristics).
Overview
The MAX4588 construction is typical of many CMOS
analog switches. It has four supply pins: V+, V-, V , and
L
GND. V+ and V- are used to drive the internal CMOS
switches and set the limits of the analog voltage on any
switch. Reverse ESD-protection diodes are internally
connected between each analog signal pin and both
V+ and V-. If the voltage on any pin exceeds V+ or V-,
one of these diodes will conduct. During normal opera-
tion these reverse-biased ESD diodes leak, forming the
only current drawn from V- and V+.
Single-supply operation also limits signal levels and
interferes with grounded signals. When V- = 0, AC sig-
nals are limited to -0.3V. Voltages below -0.3V can be
clipped by the internal ESD-protection diodes, and the
parts can be damaged if excessive current flows.
Virtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical, and therefore fairly well balanced,
they are reverse-biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages vary as the signal varies. The difference in the
two diode leakages from the signal path to the V+ and
V- pins constitutes the analog signal-path leakage cur-
rent. All analog leakage current flows to the supply ter-
minals, not to the other switch terminal. This explains
how both sides of a given switch can show leakage
currents of either the same or opposite polarity.
Power Off
When power to the MAX4588 is off (i.e., V+ = 0 and V-
= 0), the Absolute Maximum Ratings still apply. This
means that none of the MAX4588 pins can exceed
±0.3V. Voltages beyond ±0.3V cause the internal ESD-
protection diodes to conduct, with potentially cata -
strophic consequences.
The re is no c onne c tion b e twe e n the a na log s ig na l
paths and GND. The analog signal paths consist of an
N-channel and P-channel MOSFET with their sources
and drains paralleled and their gates driven out of
phase with V+ and V- by the logic-level translators.
Power-Supply Sequencing
Whe n a p p lying p owe r to the MAX4588, follow this
se que nc e : V+, V- (if bia se d to p ote ntia l othe r tha n
ground), V , then logic inputs. Apply signals on the
L
analog NO_ and COM_ pins any time after V+, V-, and
GND voltages are set. Turning on all pins simultaneous-
ly is acceptable only if the circuit design guarantees
concurrent power-up.
V and GND power the internal logic and logic-level
L
translators, and set the input logic thresholds. The
log ic -le ve l tra ns la tors c onve rt the log ic le ve ls to
switched V+ and V- signals to drive the gates of the
14 ______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
The p owe r-d own s e q ue nc e is the op p os ite of the
turability requirements. Again, do not use the through-
hole pads as the current path for any other components.
power-up sequence. That is, the V and logic inputs
L
must go to zero potential before (or simultaneously
with) the V- then V+ supplies. The Absolute Maximum
Ratings must always be observed in order to ensure
proper operation.
Bypass all V+ and V- pins to the ground plane with sur-
face-mount 0.01µF capacitors. Locate these capacitors
as close as possible to the pins on the same side of the
board as the device. Do not use feedthroughs or vias
for bypass capacitors. If board layout dictates that the
bypass capacitors are mounted on the opposite side of
the PC board, use short feedthroughs or vias, directly
under the V+ and V- pins. Use multiple vias if possible.
If V- is 0, connect it directly to the ground plane with
solid copper. Keep all traces short.
Gro u n d in g
DC Ground Considerations
Satisfactory high-frequency operation requires that
careful consideration be given to grounding. For most
applications, a ground plane is strongly recom-
mended, and all GND pins must connect to it with
solid copper. While the V+ and V- power-supply pins
are common to all switches in a given package, each
input is separated with ground pins that are not inter-
nally connected to each other. This contributes to the
overall high-frequency performance by reducing chan-
nel-to-channel crosstalk. All the GND pins have ESD
diodes to V+ and V-.
S ig n a l Ro u t in g
Keep all signal leads as short as possible. Separate all
signal leads from each other, and keep them away from
a ny othe r tra c e s tha t c ould ind uc e inte rfe re nc e .
Separating the signal traces with generously sized
ground wires also helps minimize interference. Routing
signals via coaxial cable, terminated as close to the
MAX4588 as possible, provides the highest isolation.
In systems that have separate digital and analog (sig-
nal) grounds, connect all GND pins to analog signal
ground. Preserving a good signal ground is much more
important than preserving a digital ground. Ground cur-
rent is only a few nanoamperes.
Bo a rd La yo u t
IC sockets degrade high-frequency performance and
should not be used if signal bandwidth exceeds 5MHz.
Surfa c e -mount p a rts , ha ving s horte r inte rna l le a d
frames, provide the best high-frequency performance.
Keep all bypass capacitors close to the device, and
separate all signal leads with ground planes. Such
grounds tend to be wedge-shaped as they get closer to
the device. Use vias to connect the ground planes on
each side of the board, and place the vias in the apex of
the wedge-shaped grounds that separate signal leads.
Logic-level signal lead placement is not critical.
The digital inputs have voltage thresholds determined by
V and GND (V- does not influence the logic-level thresh-
L
old). With +5V applied to V , the threshold is about 1.6V,
L
ensuring compatibility with TTL- and CMOS-logic drivers.
AC Ground and Bypassing
A ground plane is mandatory for satisfactory high-
frequency operation. Prototyping using hand wiring or
wire-wrap boards is not recommended. Connect all
GND pins to the ground plane with solid copper. (The
GND pins extend the high-frequency ground through
the package wire-frame, into the silicon itself, thus
improving isolation.) Make the ground plane solid metal
underneath the device, without interruptions. There
should be no traces under the device itself. For DIP
packages, this applies to both sides of a two-sided
board. Failure to observe this has a minimal effect on
the “on” characteristics of the switch at high frequen-
cies, but will degrade the off-isolation and crosstalk.
Im p e d a n c e Ma t c h in g
The MAX4588 is inte nd e d for us e in 75Ω s ys te ms ,
where the inputs are terminated external to the IC and
the COM terminals see an impedance of 600Ω or high-
er. The MAX4588 can operate in 50Ω and 75Ω systems
with terminations through the IC. However, variations in
R
and R
flatness cause nonlinearities.
ON
ON
Cro s s t a lk a n d Off-Is o la t io n
The graphs shown in Typical Operating Characteristics
for crosstalk and off-isolation are taken on adjacent
channels. The adjacent channel is the worst-case con-
dition. For example, NO1 has the worst off-isolation to
COM1 due to their proximity. Furthermore, NO1 has the
most crosstalk to NO2, and the least crosstalk to NO4.
Choosing channels wisely necessitates separating the
mos t s e ns itive c ha nne ls from the mos t offe ns ive .
Conversely, the above information also applies to the
NO5–NO8 inputs to the COM2 pin.
When using the MAX4588’s SO package on PC boards
with a buried ground plane, connect each GND pin to the
ground plane with a separate via. Do not share this via
with any other ground path. Providing a ground via on
both sides of the SMT land further enhances the off-isola-
tion by lowering the parasitic inductance. The DIP pack-
age can have the through-holes directly tied to the buried
plane, or thermally relieved as required to meet manufac-
______________________________________________________________________________________ 15
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
This allows cascading of multiple MAX4588s using only
P o w e r-On Re s e t (P OR)
The MAX4588 ha s inte rna l c irc uitry to g ua ra nte e a
known state on power-up. In the default state, A0 = A1
= A2 = 0, disable = 1, and all switches are off. This
state is equivalent to asserting RS during normal opera-
tion.
one chip-select line. For example, one 16-bit write could
load the shift registers of four cascaded MAX4588s. The
data from the shift register is moved to the internal con-
trol latches only upon the rising edge of CS, so all four
MAX4588s change state simultaneously.
P a ra lle l Op e ra t io n
The parallel mode is activated by driving SER/PAR to a
logic low. The MAX4588 is programmed by a latched
parallel bus scheme. Refer to Figure 6 for a detailed
diagram of the parallel-interface logic. Note that 4/8 is
not latched. It is best to hard-wire 4/8 to a known state
for the desired mode of operation, or to use a dedicat-
ed microcontroller port pin.
S e ria l Op e ra t io n
The serial mode is activated by driving the SER/PAR
input pin to a logic high. The data is then entered using a
normal SPI/MICROWIRE write operation. Refer to Figure
7 for a detailed diagram of the serial-interface logic.
There are four flip-flops in the shift register, with the out-
put of the fourth shift register being output on the DOUT
pin. Note: DOUT changes on the rising edge of SCLK.
MAX458
Tru t h Ta b le s
Parallel Operation
A2
A1
A0
EN
4/8
SWITCH STATES
Maintain previous state.
SER/PAR
LE
RS
0
x
x
x
x
x
x
x
x
x
1
x
1
0
x
x
All switches off, latches are cleared.
Serial Mode. Refer to Serial Operation
Truth Table.
1
x
x
x
x
x
1
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
x
0
0
0
0
0
0
0
0
1
1
1
1
All switches off.
Connects NO1 to COM1
Connects NO2 to COM1
Connects NO3 to COM1
Connects NO4 to COM1
Connects NO5 to COM2
Connects NO6 to COM2
Connects NO7 to COM2
Connects NO8 to COM2
Connect NO1 to COM1 and NO5 to COM2
Connect NO2 to COM1 and NO6 to COM2
Connect NO3 to COM1 and NO7 to COM2
Connect NO4 to COM1 and NO8 to COM2
x = Don’t Care
Note: 4/8 is not latched when LE is high. When LE is low, all latches are transparent. A2, A1, A0, and EN are latched.
Connect COM1 to COM2 externally for 1-of-8 single-ended operation.
16 ______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
Tru t h Ta b le s (c o n t in u e d )
Serial Operation
SCLK
DIN
x
EN
x
DOUT
0
ON SWITCHES/STATES
SER/PAR
CS
x
RS
0
All switches off. Latches and shift register are
cleared. This is the power-on reset (POR) state.
1
0
x
x
Parallel Mode. Refer to Parallel Operation Truth
Table.
x
x
x
x
High-Z
1
1
x
1
x
x
x
x
0
1
1
1
*
*
All switches off.
Chip unselected.
Input shift register loads one bit from DIN. DOUT
updates on SCLK’s rising edge.
1
1
0
0
0
1
x
1
1
1
1
1
1
*
*
*
Input shift register loads one bit from DIN. DOUT
updates on SCLK’s rising edge.
Contents of shift register transferred to control
latches.
1
x
x = Don’t Care
*DOUT is delayed by 4 clock cycles from DIN.
Control Bit and 4/8 Logic
DISABLE
BIT
A2
BIT
A1
BIT
A0
BIT
4/
8
PIN
ON SWITCHES/STATES
1
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
x
x
All switches off.
0
0
Connect NO1 to COM1
1
0
Connect NO2 to COM1
0
0
Connect NO3 to COM1
1
0
Connect NO4 to COM1
0
0
Connect NO5 to COM2
1
0
Connect NO6 to COM2
0
0
Connect NO7 to COM2
1
0
Connect NO8 to COM2
0
1
Connect NO1 to COM1 and NO5 to COM2
Connect NO2 to COM1 and NO6 to COM2
Connect NO3 to COM2 and NO7 to COM2
Connect NO4 to COM2 and NO8 to COM2
1
1
0
1
1
1
x = Don’t Care
Note: DISABLE, A2, A1, and A0 are the 4 bits latched into the MAX4588 with a MICROWIRE/SPI write. A0 is the LSB (first bit in
time). DISABLE is the MSB (last bit in time).
______________________________________________________________________________________ 17
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
____________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 1033
P a c k a g e In fo rm a t io n
MAX458
18 ______________________________________________________________________________________
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
MAX458
P a c k a g e In fo rm a t io n (c o n t in u e d )
______________________________________________________________________________________ 19
Lo w -Vo lt a g e , Hig h -Is o la t io n ,
Du a l 4 -Ch a n n e l RF/Vid e o Mu lt ip le x e r
P a c k a g e In fo rm a t io n (c o n t in u e d )
MAX458
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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