MAX5039 [MAXIM]
Voltage-Tracking Controllers for PowerPC.DSPs.and ASICs ; 电压跟踪控制器的ASIC PowerPC.DSPs.and\n
| 型号： | MAX5039 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Voltage-Tracking Controllers for PowerPC.DSPs.and ASICs
|
| 文件： | 总20页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2461; Rev 0; 5/02
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
General Description
Features
The MAX5039/MAX5040 provide intelligent control to
power systems where two supply voltages need track-
ing. These cases include PowerPC®, DSP, and ASIC
systems, which require a lower CORE voltage supply
and a higher I/O voltage supply.
ꢀ Provide Tracking of Two External Power Supplies
During Power-Up and Power-Down
ꢀ Compatible with a Wide Range of External Power
Supplies Independent of Output Power
The MAX5039/MAX5040 control the output voltage of
the CORE and I/O supplies during power-up, power-
down, and brownout situations. They ensure that the
two power supplies rise or fall at the same rate, limiting
the voltage difference between the CORE and I/O sup-
plies. This eliminates stresses on the processor. The
MAX5039/MAX5040 shut down both the CORE and I/O
supplies if either one is shorted or otherwise fails to
come up.
ꢀ Bus Voltage Undervoltage Lockout Enables/
Disables CORE and I/O Supplies Together
ꢀ Detect Short Circuit on V
and V , Disable
I/O
CORE
CORE and I/O Supplies in Either Case
ꢀ Output Undervoltage Monitoring
ꢀ POK Status (MAX5040)
ꢀ Operating V
Supply Voltage Range: 2.5V to 5.5V
CC
The MAX5040 provides a power-OK (POK) signal that
signals the processor if the CORE supply, the I/O sup-
ꢀ I/O Voltage Range: V
to 4V
CORE
ꢀ CORE Voltage Range: 0.8V to V
ply, and the system bus supply (V ) are above their
CC
I/O
respective specified levels. The MAX5039/MAX5040
are targeted for nominal bus V
voltages from 4V to
CC
5.5V. The MAX5039/MAX5040 work with CORE volt-
ages ranging from 800mV to about 3V (depending on
the gate-to-source turn-on threshold of the external N-
channel MOSFET) and I/O voltages ranging from
Ordering Information
PART
MAX5039EUA-T
MAX5040EUB-T
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
10 µMAX
V
to 4V. The MAX5039/MAX5040 provide tracking
CORE
control of the I/O and CORE voltages using a single
external N-channel MOSFET connected across them.
This MOSFET is not in series with the power paths and
does not dissipate any additional power during normal
system operation. The external MOSFET is only on for
brief periods during power-up/power-down cycling so a
low-cost, small-size MOSFET with a rating of 1/4th to
1/8th of the normal supply current is suitable.
The MAX5039/MAX5040 are offered in space-saving
8-pin µMAX and 10-pin µMAX packages, respectively.
I/O
V
CC
WITH MAX5039
OR MAX5040
CORE
CORE
Applications
PowerPC Systems
Embedded DSPs and ASICs
WITHOUT
MAX5039
OR MAX5040
V
CC
Embedded 16- and 32-Bit Controller Systems
Telecom/Base Station/Networking
I/O
Power-On and Power-Off With and Without Voltage Tracking
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
PowerPC is a registered trademark of IBM Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND)
Continuous Power Dissipation (T = +70°C)
A
V
, NDRV, SDO, and POK ..................................-0.3V to +14V
8-Pin µMAX (derate 4.5mW/°C above +70°C).............362mW
CC
CORE_FB, UVLO, I/O_SENSE, I/O, CORE..........-0.3V to +4.25V
All Pins to V (except POK)............................................. +0.3V
NDRV Continuous Current .................................................50mA
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Continuous Current, All Other Pins .....................................20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.5V to 5.5V, V
= 2V, V
= 1.8V, V
= 2.5V, V
= 1V, V
= 2V (MAX5040 only),
I/O_SENSE
CC
UVLO
CORE
I/O
CORE_FB
T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at V = 5V, T = +25°C.)
CC A
PARAMETER
EXTERNAL SUPPLY CONDITIONS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
(Note 1)
(Note 2)
2.5
5.5
2.25
0.9
V
mA
V
CC
CC
CC
Supply Current
Where SDO Is Valid
I
1.3
CC
Lowest V
V
V
CC
CCLO
SDO Output Low Voltage at
V
V
= V
= V , I = 50µA,
CCLO SDO
(Note 2)
SDO
UVLO
CC
0.4
2.5
V
= V
measure V
CC
CCLO
V
rising
2.43
0.05
CC
V
IC Turn-On Voltage
CC
V
V
Threshold (Note 3)
Hysteresis
I/O and CORE valid, V
CORE Voltage Range
= 5.5V (Notes 4, 5)
0.8
V
I/O
CORE
CC
I/O and CORE valid (Note 5) V
> 4V
V
V
4.0
CC
CORE
I/O Voltage Range
V
V
I/O
I/O and CORE valid (Note 5),
V
CORE
CC
2.5V ≤ V
≤ 4V
CC
USER-PROGRAMMABLE UNDERVOLTAGE LOCKOUT
V
rising
1.200
1.230
110
1.260
250
V
UVLO
UVLO Trip Threshold
V
UVCC
Hysteresis
= 2V
mV
nA
UVLO Input Bias Current
V
UVLO
CORE AND I/O REGULATION
CORE Feedback, CORE_FB, and
Reference Voltage
V
784
800
60
816
mV
dB
C_REF
CORE Regulator Large-Signal Gain
A
V
CORE_FB to NDRV
CORE_FB to NDRV
CORE Regulator Crossover
Frequency
400
kHz
Pullup strength,
V
≥ 3V
40
50
13
17
80
100
27
CC
CC
CC
CC
V
V
= 1V,
= 2V, I
I/O
CORE
V
≥ 2.5V
≥ 3V
= -10mA
= 10mA
NDRV
NDRV Output Resistance
Ω
Pulldown strength,
V
V
V
V
= 2V,
I/O
≥ 2.5V
35
= 1V, I
CORE
NDRV
V
V
- V , V falling
60
90
0
130
15
CORE
CORE
I/O I/O
I/O-CORE Comparator Trip
Threshold (Note 6)
V
mV
TH
- V , V rising
I/O I/O
-15
2
_______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.5V to 5.5V, V
= 2V, V
= 1.8V, V
= 2.5V, V
= 1V, V
= 2V (MAX5040 only),
I/O_SENSE
CC
UVLO
CORE
I/O
CORE_FB
T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at V = 5V, T = +25°C.)
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CORE Pulldown Resistance
MONITOR OUTPUTS
V
= 1.8V, V
= 1V, V
= 2.5V
= 2.5V
20
50
Ω
CORE
UVLO
CC
CC
SDO Output Low Voltage
V
I
I
= 1.8mA, V
= 1V, V
0.4
V
V
OLSDO
SDO
SDO
UVLO
V
0.4V
-
CC
= -1.0mA, V
= -1.0mA, V
= 4V
CC
CC
SDO Output High Voltage
V
OHSDO
V
-
CC
I
= 2.5V
SDO
0.55V
V
rising
1.200
1.230
25
1.260
V
mV
V
I/O_SENSE
I/O_SENSE Trip Threshold
V
I/O_REF
Hysteresis
= 1.8mA
POK Output Low Voltage
POK Leakage Current
POK Glitch Rejection Time
Fault Time
V
I
0.4
1.0
OLPOK
POK
I
V
= V
CC
µA
µs
ms
LPOK
POK
t
(Note 7)
(Note 8)
50
15
POK
FAULT
t
10
20
I/O and CORE INPUTS
I/O Input Bias Current
CORE Input Bias Current
I/O_SENSE Input Bias Current
CORE_FB Input Bias Current
V
V
V
V
= 1V
20
20
µA
µA
nA
nA
I/O
= 1V
CORE
= 0.8V
250
300
I/O_SENSE
CORE_FB
= 1.2V
Note 1: V
slew-rate limited to 30V/µs.
CC
Note 2: SDO automatically goes low when the UVLO pin drops below its threshold (or V
drops below 2.5V). SDO remains low as
CC
V
CC
falls. For some V
below V
SDO may float.
CC
CCLO
Note 3: This undervoltage lockout disables the MAX5039/MAX5040 at V
voltages below which the device cannot effectively oper-
CC
ate. When V
drops below the threshold, SDO goes low, the bleeder turns off, and POK is high impedance.
CC
Note 4: In order to regulate correctly, V
must be higher than V
plus the turn-on voltage of the external N-channel MOSFET.
CC
CORE
Note 5: I/O and CORE valid mean the voltages on these pins have settled within their target specifications for normal operation.
Note 6: CORE and I/O supplies rise and fall rates must be limited to less than 6.6V/µs.
Note 7: POK does not deassert for glitches less than t
.
POK
Note 8: A fault condition is latched when either of the two following conditions maintains for longer than t
:
FAULT
V
V
< V
CORE
(i.e., V
is less than its set point)
CORE_FB
C_REF
CORE
< V
I/O
A FAULT condition forces SDO and POK (MAX5040 only) low. CORE discharges to GND through 20Ω while V
> 2.5V.
CC
Cycle UVLO or V
low, then high, to clear a FAULT.
CC
_______________________________________________________________________________________
3
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Typical Operating Characteristics
(V
= 5V, V
= 1.8V, V = 3.3V, T = +25°C, unless otherwise specified.)
CORE I/O A
CC
SYSTEM POWER-UP/POWER-DOWN
WITHOUT MAX5039/MAX5040
SYSTEM POWER-UP/POWER-DOWN
(V RISING BEFORE V
)
CORE
MAX5039/40 toc01
(V RISING BEFORE V
)
I/O
I/O
CORE
MAX5039/40 toc02
V
V
CC
V
CC
5V/div
CC
5V/div
V
NDRV
CC
NDRV
5V/div
SDO
POK
SDO
AND POK
5V/div
I/O
I/O
I/O
AND CORE
1V/div
I/O
AND CORE
1V/div
CORE
5ms/div
CORE
5ms/div
CORE REGULATOR LOOP BODE PLOT
CORE_FB REFERENCE (V
)
C_REF
(SEE FIGURE 9)
vs. V AND TEMPERATURE
CC
MAX5039/40 toc04
804
60
50
40
30
20
10
0
180
150
120
90
V
= 5V, V = 3.3V, V
I/O
= 1.8V AT 1A
CORE
CC
803
802
801
800
799
798
797
T
T
= +85°C
= +25°C
A
A
PHASE
60
30
GAIN
0
T
= -40°C
A
-30
-60
-10
-20
796
100
1k
10k
100k
2.5
3.5
4.5
5.5
FREQUENCY (Hz)
V
(V)
CC
V
vs. I V = 0.9V
SDO(SINK) CC
V
vs. I
V = 2.5V
SDO(SINK) CC
SDO
SDO
400
400
350
300
250
200
150
100
50
350
300
250
200
150
100
50
T
= +85°C
A
T
= +85°C
A
T
= +25°C
A
T
= +25°C
A
T
= -40°C
A
T
= -40°C
A
0
0
0
0.1
0.2
0.3
0.4
(mA)
0.5
0.6
0
1
2
3
4
I
I
(mA)
SDO(SINK)
SDO(SINK)
4
_______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Typical Operating Characteristics (continued)
(V
= 5V, V
= 1.8V, V = 3.3V, T = +25°C, unless otherwise specified.)
CC
CORE
I/O
A
V
vs.I
SDO(SOURCE)
SDO
NDRV PULLDOWN STRENGTH
NDRV PULLUP STRENGTH
5
4
3
2
1
500
450
400
350
300
250
200
150
100
50
6
T
= -40°C
V
= 2.5V
A
CC
V
= 4.5V
CC
T
T
= -40°C
A
T
= +85°C
A
V
= 5V
CC
5
4
= +85°C
A
T
= +25°C
A
T
T
= +25°C
= -40°C
A
T
= +85°C
A
T
T
= +25°C
= -40°C
A
V
= 2.5V
A
T
T
= -40°C
CC
A
3
2
1
0
V
= 2.5V
A
CC
T
= +85°C
A
T
= +25°C
A
T
= -40°C
T
= +85°C
A
A
T
= +25°C
A
T
= +25°C
A
= +85°C
V
= 5V
CC
A
0
0
0
0.5
1.0
I
1.5
2.0
(mA)
2.5
3.0
0
4
8
I
12
16
20
0
4
8
I
12
(mA)
16
20
(mA)
SDO(SOURCE)
NDRV
NDRV
UVLO RISING THRESHOLD vs. V
UVLO HYSTERESIS vs. V
I/O_SENSE THRESHOLD (V
) vs. V
I/O_REF
CC
CC
CC
1.239
1.238
1.237
1.236
1.235
1.234
1.233
1.232
1.231
115
110
1.244
1.242
1.240
1.238
1.236
1.234
1.232
1.230
T
= +85°C
= -40°C
T
T
= +85°C
= +25°C
A
A
T
T
= +85°C
= +25°C
A
A
T
= +25°C
A
105
100
A
T
A
T
= -40°C
A
T
= -40°C
A
95
90
1.230
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
49
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
V
CC
CC
CC
POK GLITCH REJECTION vs. V
I/O_SENSE HYSTERESIS vs. V
CC
CC
30
29
28
27
26
25
24
23
22
21
20
48
47
T
T
= +85°C
= +25°C
A
A
T
T
= +85°C
A
A
46
45
44
43
= +25°C
T
= -40°C
A
T
= -40°C
A
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
CC
CC
_______________________________________________________________________________________
5
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Pin Description
PIN
NAME
FUNCTION
MAX5039 MAX5040
Active-Low Shutdown Output. Connect SDO to active-low shutdown input of both CORE and
I/O supplies. SDO is high when V ≥ V and V ≥ 2.5V and if there is no fault.
1
2
1
2
SDO
UVLO
UVCC
CC
Supply Voltage Input. Connect V
to the supply voltage that powers the CORE and I/O
CC
V
CC
supplies. Bypass V
to GND with a 1µF capacitor.
CC
User-Programmable Undervoltage Lockout. Connect to midpoint of the voltage-divider from
to GND. Set trip point below minimum V voltage. V ≤ V forces SDO and
POK (MAX5040 only) low. Use UVLO as an active-low shutdown input to turn on/off the
V
CC
CC
UVLO
UVCC
3
4
3
4
UVLO
GND
CORE and I/O supplies if desired.
Ground
CORE Feedback Input. Connect CORE_FB to the midpoint of the voltage-divider from CORE to
GND. The MAX5039/MAX5040 keep CORE_FB from dropping below V
by controlling
C_REF
NDRV. Any time V
falls below V
, NDRV rises above ground to a voltage
C_REF
CORE_FB
sufficient to maintain V
= V
. If V
remains below V
for longer than
CORE_FB
C_REF
CORE_FB
C_REF
t
, a latched FAULT is generated. During a FAULT, MAX5039/MAX5040 continue to
FAULT
5
7
8
CORE_FB
regulate CORE_FB.
Three things halt regulation of CORE_FB:
• If V
• If I/O falls below CORE, NDRV goes to V
• If V
falls below 2.5V, NDRV goes to GND.
CC
.
CC
rises above V , NDRV goes to GND.
C_REF
CORE_FB
CORE Supply Sense Input. Connect CORE to the core output voltage. If V
goes to V , POK (MAX5040 only) goes low. FAULT is latched if this condition lasts longer
> V , NDRV
I/O
CORE
6
CORE
CC
than t
. A 20Ω bleeder discharges CORE to GND whenever SDO is low and V
> 2.5V.
FAULT
CC
I/O Supply Sense Input. Connect to I/O output voltage. If V
POK (MAX5040 only) drives low. A FAULT is latched if this condition lasts longer than t
> V , NDRV goes to V
,
CORE
I/O
CC
7
8
9
I/O
.
FAULT
N-Channel MOSFET Gate Driver. Connect NDRV to the gate of the external N-channel
MOSFET that shunts I/O to CORE.
10
NDRV
I/O Feedback Input. Use a resistor-divider to divide V and apply to this pin. When
I/O
—
5
6
I/O_SENSE V
≤ V
, POK drives low. I/O_SENSE can also be used to monitor any other
I/O_REF
I/O_SENSE
voltage.
Open-Drain Power-OK Output. POK drives low when any condition below is true:
• V ≤ 2.5V
• V
CC
≤ V
UVLO
CORE_FB
UVCC
≤ V
• V
—
POK
C_REF
• V ≤ V
I/O
CORE
• V
≤ V
I/O_SENSE
I/O_REF
• MAX5039/MAX5040 latches a FAULT
6
_______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
turns on, pulling the I/O voltage above the CORE volt-
Performance During
age. At this point, the MAX5040 brings NDRV to GND
Typical Operation
and POK goes high. On power-down, when V
drops
CC
Scope shots are of the MAX5040 EV kit. Figures 1
through 8 demonstrate system performance of the
MAX5040 under various power-up, power-down, and
fault conditions. In some cases (described in detail
below), startup or shutdown of the I/O and CORE sup-
plies were purposely delayed with respect to each
other to simulate possible system operating conditions.
low enough to bring V
below V
, SDO immedi-
UVLO
UVCC
ately falls, turning the I/O and CORE supplies off.
Simultaneously POK falls, indicating power-down to the
processor. When the CORE voltage drops below its reg-
ulation point, NDRV begins to regulate it (at around
30ms). When I/O falls below CORE, NDRV is pulled up to
V
CC
to short the two supplies together.
In Figure 1 (with MAX5040), V
ramps up slowly and
In Figure 4 (without MAX5040), V
and the CORE voltage comes up before the I/O volt-
age. It takes about 8ms before the I/O supply finally
comes up above the CORE supply. When V
down, the supplies do not turn off together. CORE
remains high for around 14ms after I/O falls.
ramps up slowly
CC
CC
the I/O supply comes up before the CORE supply. As
soon as V
goes to V
rises above 2.5V (at about 7.5ms) NDRV
CC
shorting the I/O and CORE supplies togeth-
powers
CC
CC
er. When V
rises above 4.5V (bringing V
above
CC
UVLO
V
), SDO goes high enabling the I/O and CORE
UVCC
supplies. Although the CORE PWM supply turns on 5ms
after the I/O PWM supply, both supply voltages come up
together because NDRV is held at V , shorting the sup-
CC
plies together through the N-channel FET. The I/O supply
supports both the I/O line and the CORE line. Once
In Figure 5 (with MAX5040), the system power-up is
attempted with the CORE supply held in shutdown. As
soon as V
rises above 2.5V, NDRV goes to V
,
CC
CC
shorting the I/O and CORE supplies together. Next,
when V rises above 4.5V (bringing V above
CC
UVLO
V
rises close to its set point, NDRV falls to around
CORE
2.8V to regulate V
V
), SDO goes high, enabling the I/O and CORE
UVCC
at its set point. At around 22ms,
CORE
supplies. Both supplies come up together because
NDRV is high. Note that the CORE supply is still off;
CORE is held up through the N-channel FET shunt.
the CORE supply comes up, NDRV goes to GND, and
POK goes high. On power-down, when V drops low
CC
enough to bring V
below V
, SDO immediately
UVCC
UVLO
Once V
rises close to its set point, the linear regu-
CORE
CORE
lator holds V
falls, turning the I/O and CORE supplies off. Simultane-
ously, POK falls, indicating power-down to the proces-
sor. When the I/O voltage drops below the CORE
to its set point by regulating NDRV to
around 2.8V. After 15ms of regulating CORE, the
MAX5040 latches a fault. SDO goes low, NDRV goes to
voltage, NDRV goes to V
(at around 36ms), shorting
CC
V
, and both supplies power down together. POK
CC
the supplies together. NDRV remains at V
falls below 2.5V and then it returns to GND.
until V
CC
CC
remains low throughout because a valid operating state
was not achieved.
In Figure 2 (without MAX5040), V
ramps up slowly
CC
In Figure 6 (with MAX5040), V
is set to 5V. Toggling
CC
and the CORE and I/O supplies are turned on when
exceeds 2.5V. The I/O voltage comes up before
UVLO from low to high controls system startup. While
UVLO is low and the V is 5V, NDRV is high, causing
V
CC
CC
the CORE voltage. There is a 3.3V difference between
the I/O and CORE supplies for about 4ms before the
the supplies to be shorted together. When UVLO goes
high, SDO also goes high, turning on the CORE and I/O
supplies (at around 3ms). In this example, the I/O sup-
ply comes up before the CORE supply. The MAX5040
regulates CORE by driving NDRV to about 2.8V until the
CORE supply comes up (at around 7ms), then NDRV
falls to GND and POK goes high. When UVLO is driven
low, SDO goes low, disabling the CORE and I/O sup-
CORE supply finally comes up. When V
down, I/O remains high for about 10ms after CORE
reaches GND.
powers
CC
In Figure 3 (with MAX5040), V
ramps up slowly and
CC
the CORE supply comes up before the I/O supply. As
soon as V rises above 2.5V (at about 7.5ms), NDRV
CC
goes to V , shorting the I/O and CORE supplies togeth-
plies. NDRV goes to V
down together.
and both supplies power
CC
CC
er. When V
rises above 4.5V (bringing V
above
CC
UVLO
V
), SDO goes high, enabling the I/O and CORE
UVCC
In Figure 7 (with MAX5040), V
is set to 5V. Toggling
CC
supplies. Although the I/O PWM supply turns on 8ms
after the CORE PWM supply, both supply voltages come
up together because NDRV is held at V , shorting the
CC
supplies together through the N-channel FET. The CORE
supply supports both the CORE line and the I/O line until
the I/O supply comes up. At around 23ms, the I/O supply
UVLO from low to high controls system startup. While
UVLO is low and the V is 5V, NDRV is high, shorting
CC
the supplies together while they are both off. When
UVLO does go high, SDO also goes high, turning on
the CORE and I/O supplies (at around 8ms). In this
example, the CORE supply comes up before the I/O
_______________________________________________________________________________________
7
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
SYSTEM POWER-UP/POWER-DOWN
WITHOUT MAX5039/MAX5040
(V RISING BEFORE V
SYSTEM POWER-UP/POWER-DOWN
(V RISING BEFORE V
)
CORE
I/O
)
CORE
I/O
V
V
CC
CC
5V/div
V
CC
5V/div
NDRV
NDRV
5V/div
V
CC
SDO
POK
SDO
AND POK
5V/div
I/O
I/O
I/O
AND CORE
1V/div
I/O
AND CORE
1V/div
CORE
5ms/div
CORE
5ms/div
Figure 1. System Power-Up/Power-Down (V
Rising Before
Figure 2. System Power-Up/Power-Down Without MAX5039/
MAX5040 (V Rising Before V
I/O
V
)
)
CORE
CORE
I/O
SYSTEM POWER-UP/POWER-DOWN
WITHOUT MAX5039/MAX5040
SYSTEM POWER-UP/POWER-DOWN
(V
RISING BEFORE V )
CORE
I/O
(V
RISING BEFORE V )
CORE
I/O
V
CC
V
CC
5V/div
V
CC
5V/div
NDRV
NDRV
5V/div
V
CC
SDO
POK
SDO
AND POK
5V/div
I/O
I/O
I/O
AND CORE
1V/div
I/O
AND CORE
1V/div
CORE
CORE
5ms/div
5ms/div
Figure 3. System Power-Up/Power-Down (V
Rising
Figure 4. System Power-Up/Power-Down Without MAX5039/
MAX5040 (V Rising Before V
CORE
Before V
)
)
I/O
I/O
CORE
supply. The MAX5040 holds up I/O by driving NDRV to
(because the I/O voltage is less than the CORE
NDRV goes high, and POK goes low immediately.
NDRV shorts the I/O supply to the CORE supply, bring-
ing the supplies down together. After 15ms, the
MAX5040 latches a fault and SDO goes low turning off
the supplies.
V
CC
voltage) until the I/O supply comes up (at around
16ms). At this point, NDRV goes to GND and POK goes
high. UVLO is driven low (at around 22ms), causing
SDO to go low, disabling the CORE and I/O supplies.
The CORE supply powers down at about 23ms and
NDRV goes to 2.8V to regulate the CORE supply until
Detailed Description
The MAX5039/MAX5040 voltage-tracking controllers
limit the maximum differential voltage between two
power supplies during power-up, power-down, and
brownout conditions. The devices provide a shutdown
output control signal, SDO, which is used to turn on
I/O falls. Then NDRV goes to V
when the I/O voltage
CC
falls to the CORE voltage (at around 36ms).
Figure 8 (with MAX5040) starts out with the supplies in
their normal range. At 3ms, CORE is shorted to GND.
8
_______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
and off the CORE and I/O power supplies. The
MAX5039/MAX5040 monitor and compare the CORE
and I/O voltages as follows.
equals V
, NDRV goes into regulation mode. If the
C_REF
CORE_FB voltage is higher than V
, the linear reg-
C_REF
ulator goes into standby mode and pulls NDRV low,
turning off the external N-channel MOSFET.
When the I/O voltage is greater than or equal to the
CORE voltage, MAX5039/MAX5040 regulate the exter-
nal N-channel MOSFET as a linear regulator by control-
ling NDRV. The linear regulator regulates the CORE
voltage to the value set by the external resistor-divider
connected from CORE to CORE_FB and GND (see
Figures 9 and 10). If the CORE_FB voltage is far less
When the I/O voltage is lower than the CORE voltage by
V
(90mV), the MAX5039/MAX5040 turn the external N-
TH
channel MOSFET on by driving NDRV high to V
.
CC
Whenever SDO is high, the MAX5039/MAX5040 track the
time that NDRV is in regulation mode or driven high. If
NDRV is in regulation mode or driven high for longer than
than its regulation point, V
(800mV), NDRV drives
C_REF
t
(15ms), a fault occurs and SDO is pulled low.
FAULT
high to V , effectively shorting CORE and I/O together
CC
through the external MOSFET. If the CORE_FB voltage
SYSTEM TURN-ON/TURN-OFF
UNDER UVLO CONTROL
SYSTEM FAULT STARTUP
(CORE SUPPLY FAILS TO TURN ON)
(V RISING BEFORE V
)
I/O
CORE
UVLO
V
CC
5V/div
UVLO
SDO
NDRV
5V/div
SDO
5V/div
V
CC
NDRV
5V/div
POK
POK
5V/div
SDO
POK
SDO
5V/div
POK
NDRV
5V/div
5V/div
NDRV
I/O
I/O
I/O
AND CORE
2V/div
I/O
AND CORE
1V/div
CORE
CORE
4ms/div
2ms/div
Figure 6. System Turn-On/Turn-Off Under UVLO Control
(V Rising Before V
Figure 5. System Power-Up/Power-Down, Fault Startup
(CORE Supply Fails to Turn On)
)
CORE
I/O
SYSTEM TURN-ON/TURN-OFF
UNDER UVLO CONTROL
SHORT-CIRCUIT RESPONSE
(CORE SHORTENED TO GND)
(V
RISING BEFORE V
)
CORE
UVLO
SDO
I/O
UVLO
5V/div
NDRV
NDRV
5V/div
SDO
5V/div
POK
SDO
POK
SDO
5V/div
POK
5V/div
POK
5V/div
NDRV
NDRV
5V/div
I/O
I/O
I/O
AND CORE
1V/div
I/O
AND CORE
1V/div
CORE
CORE
5ms/div
2ms/div
Figure 7. System Turn-On/Turn-Off Under UVLO Control
(V Rising Before V
Figure 8. Short-Circuit Response (CORE Shorted to GND)
)
I/O
CORE
_______________________________________________________________________________________
9
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Functional Diagram
800mV
MAX5040
CORE_FB
V
CC
R
V
CC
R
NDRV
UVLO
1.23V
400mV
FAULT
GENERATOR
I/O
FAULT
15ms TIMER
CORE
SDO
POK
BLEED
GND
I/O_SENSE
1.23V
10 ______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
V
IN
(5V)
V
= 3.3V AT 2.0A
I/O
POWER
SUPPLY
I/O
OUT
SHDN
IN
IN
I/O
C
I/O
100µF
Q1
Si9428
SO-8
PowerPC/
DSP/ASIC
V
CORE
= 1.8V AT 2.0A
CORE
POWER
SUPPLY
OUT
SHDN
CORE
C
CORE
100µF
R4
50Ω
R1
9.53kΩ
1%
C2
1.5nF
CORE
I/O
NDRV
SDO
V
CC
C
IN
C1
100nF
R3
10kΩ
R7
1µF
25.5kΩ
1%
MAX5039
R2
UVLO
CORE_FB
10kΩ
1%
R8
10kΩ
1%
GND
Figure 9. Typical Application Circuit for the MAX5039
ulators that supply the CORE and I/O voltages. Using
this single control signal, the MAX5039/MAX5040 turn
the CORE and I/O power supplies on and off together,
minimizing the voltage differential between them.
Designing with MAX5039/MAX5040
The MAX5039/MAX5040 provide intelligent control to
power systems where two power supplies need track-
ing. Follow the steps below for designing with the
MAX5039/MAX5040:
SDO is low when:
1) Select an appropriate external N-channel MOSFET
• The voltage on the UVLO pin is below V
UVCC
(see the N-Channel MOSFET Selection section).
(1.230V).
2) Set the CORE regulation voltage (see the Program-
ming the CORE Voltage section).
• V
is below the IC turn-on voltage threshold (2.43V).
CC
• A fault condition is detected.
3) Set the UVLO voltage trip threshold (see the
The MAX5039/MAX5040 prevent premature turn-on of
the CORE and I/O power supplies during power-up by
actively holding SDO low as soon as V
0.9V, provided the condition for SDO to stay low is valid.
Programming UVLO Voltage section).
4) Compensate the CORE linear regulator loop (see
rises above
CC
the Linear Regulator Compensation section).
5) Set the POK voltage trip threshold (MAX5040 only,
NDRV
NDRV controls the gate of the external N-channel MOSFET
(which is connected between the I/O and CORE voltages),
see the Programming I/O_SENSE Voltage section).
Figures 9 and 10 show an application example.
as needed, as long as V is within its operating range.
CC
Functional Description
NDRV is driven high to V
when V < V
.
CC
I/O
CORE
SDO
SDO is the shutdown signal output. Connect SDO to the
CORE and I/O power-supply shutdown pins. SDO
allows the MAX5039/MAX5040 to control the turning on
and off of the external switching regulators or linear reg-
NDRV regulates the external MOSFET as a linear regu-
lator when V > V
and V
< V
C_REF
.
I/O
CORE
CORE_FB
NDRV is driven low when V
> V and V
CORE CORE_FB
I/O
> V
.
C_REF
______________________________________________________________________________________ 11
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
V
(5V)
IN
V
= 3.3V AT 2.0A
I/O
POWER
SUPPLY
I/O
OUT
SHDN
IN
I/O
C
I/O
R5
13.3kΩ
1%
100µF
Q1
Si9428
SO-8
PowerPC/
DSP/ASIC
V
CORE
= 1.8V AT 2.0A
CORE
POWER
SUPPLY
IN
OUT
SHDN
CORE
C
CORE
100µF
R6
10kΩ
1%
R4
50Ω
GPIO
R1
9.53kΩ
1%
CORE
I/O
SDO
C2
1.5nF
I/O_SENSE
NDRV
V
CC
C
IN
1µF
R7
C1
100nF
R3
10kΩ
25.5kΩ
1%
MAX5040
R2
UVLO
CORE_FB
POK
10kΩ
1%
R8
10kΩ
1%
GND
Figure 10. Typical Application Circuit for the MAX5040
UVLO
UVLO is a user-programmable undervoltage lockout
input. When the UVLO voltage is above V , the
voltages, as long as V
is within its operating voltage
CC
range. It is important to discharge the output capacitors
to ground before V drops out of its range. Figure 11
UVCC
CC
MAX5039/MAX5040 hold SDO high, given that V
is
illustrates a method to prolong V
down/brownout condition.
after a power-
CC
CC
within its operating range and there is no fault condition
present. When the UVLO voltage falls below V
,
UVCC
The hold-up capacitor, C , holds the voltage at V
HD
CC
SDO is pulled low. Use a resistor-divider from the input
of the CORE and I/O power supplies to UVLO to GND
to set the undervoltage lockout (see the Typical
Application Circuit). The MAX5039/MAX5040 keep the
CORE and I/O power supplies off (through the SDO)
until their input voltage is within its operating range.
up and provides the power to the MAX5039/MAX5040
to keep them in operation even after V has gone
IN
down.
Power-Up
The MAX5039/MAX5040 prevent premature turning on
of the CORE and I/O power supplies during power-up
UVLO can be used to turn off the CORE and I/O power
supplies through SDO. Pull the UVLO pin low with an
open-collector driver to assert SDO, which turns off the
power supplies.
by actively holding SDO low as soon as V
rises
CC
above 0.9V, provided the condition for SDO to stay low
is valid. The MAX5039/MAX5040 completely turn on
and NDRV is operational when V
rises above the
CC
Active Bleeder
The MAX5039/MAX5040 contain an internal 20Ω N-
channel MOSFET bleeder that connects CORE to
ground. The bleeder turns on whenever the MAX5039/
V
IC turn-on voltage threshold (2.43V). In this state,
CC
the MAX5039/MAX5040 maintain tight tracking of the
CORE and I/O output voltages. The MAX5039/
MAX5040 continue to hold SDO low until the UVLO volt-
MAX5040 hold SDO low and V
is above the V
IC
age rises above V
(1.230V).
CC
CC
UVCC
turn-on voltage threshold (2.43V). This bleeder assists
in discharging the output capacitor(s) during power-
down/brownout conditions. The MAX5039/MAX5040
maintain tight voltage tracking of the CORE and I/O
Once the UVLO voltage rises above V
high, enabling the CORE and I/O power supplies at the
same time. Without voltage tracking, depending on the
, SDO goes
UVCC
12 ______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Without voltage tracking, depending on the output capac-
itance and loading, CORE and I/O voltages may not fall at
the same rate. Similar to the power-up condition, the
MAX5039/MAX5040 keep CORE and I/O voltages track-
ing together by controlling NDRV, dynamically driving
NDRV high, low, or in regulation mode, depending on the
CORE and I/O voltage condition.
V
IN
V
CC
During power-down/brownout, V
is dropping and the
CC
C
10µF
HD
UVLO voltage is also dropping. When the UVLO voltage
falls below V , SDO is pulled low, disabling the
MAX5039
MAX5040
UVCC
CORE and I/O power supplies. Similar to the shutdown
condition, the MAX5039/MAX5040 keep CORE and I/O
UVLO
voltages together. It is important that V
remains in its
CC
operating voltage range in order to keep the MAX5039/
MAX5040 operating to provide tracking until the output
voltages have discharged to a safe level. Figure 11 illus-
Figure 11. Circuit Prolongs V
Condition
After a Brownout/Power-Down
trates a method to prolong V
after a power-
CC
CC
down/brownout condition. The bleeder circuitry is
helpful in this power-down/brownout condition because
the bleeder helps speed up the discharge process.
power supplies startup delay and/or soft-start timing,
which are specific to each of the power supplies,
CORE and I/O outputs may not rise at the same time or
at the same rate. Output loading and capacitance fur-
ther separate the two output’s rise time. The
MAX5039/MAX5040 help the system to overcome these
differences and keeps CORE and I/O voltages tracking
together by controlling NDRV, dynamically driving
NDRV high, low, or in regulation mode, depending on
the CORE and I/O voltage condition.
FAULT Condition
While SDO is high, the MAX5039/MAX5040 keep track of
the time NDRV is driven high or in regulation mode. In a
typical system during power-up, power-down/
brownout, and normal operation, the time NDRV is driven
high or in regulation mode should last for only a few mil-
liseconds. If this time exceeds t
(15ms), indicating
FAULT
an abnormal condition, a fault is generated. During a
fault condition, SDO is driven low and NDRV continues
its operation as described in the NDRV section.
Normal Operation
After the power-up period is over, CORE and I/O output
voltages settle to their respective regulated values. The
linear regulator formed by MAX5039/MAX5040 and the
external MOSFET is turned off. During normal opera-
tion, the linear regulator goes into a standby mode and
NDRV is driven low.
A fault condition is latched. To clear a fault, toggle V
and/or UVLO to unlatch and restart the system.
CC
Output Short-Circuit Condition
If any of the outputs are shorted to ground, NDRV is dri-
ven high to keep the CORE and I/O voltages tracking
each other. The current through the external MOSFET is
limited by the current limit provided by the external
power supply. If the short-circuit condition lasts more
The resistor-divider from CORE to CORE_FB to GND
must be set so that the linear regulator regulation voltage
is less than the CORE power-supply regulation voltage.
See the Programming the CORE Voltage section.
than t
, a fault is generated, SDO is driven low
FAULT
(which turns off the CORE and I/O power supplies), and
NDRV continues its operation as described in the
NDRV section.
During normal operation, the MAX5039/MAX5040 con-
stantly monitor the CORE, I/O, and CORE_FB voltages.
NDRV responds as needed, according to the condi-
tions described in the NDRV section.
Applications Information
Power-Down/Brownout or Shutdown
The MAX5039/MAX5040 continue to provide tracking
for the CORE and I/O output voltages during power-
down/brownout or shutdown.
N-Channel MOSFET Selection
The external N-channel MOSFET connected between
CORE and I/O power supplies is expected to turn on
briefly during power-up and power-down/brownout
conditions. During normal operation, this MOSFET is
turned off. In general, only a small size MOSFET is
needed. A MOSFET capable of carrying 1/4th to 1/8th
During shutdown (UVLO is pulled below V ), SDO is
UVCC
pulled low, disabling the CORE and I/O power supplies
together. The CORE and I/O output voltages start to fall.
______________________________________________________________________________________ 13
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
of the maximum output current rating of the CORE or
I/O power supplies is adequate. However, care should
be taken when selecting this MOSFET to make sure it is
capable of sustaining all of the worst-case conditions,
as well as riding through all of the fault conditions. The
following are guidelines for selecting the external N-
channel MOSFET:
well as the charging of the CORE output
capacitor. For most practical cases, the
power charging the CORE output capacitor
can be ignored. The power dissipation in the
MOSFET for this case is (V
- V
) x
CORE
I/O
I
, where V
is the regulated I/O volt-
CORE
age, V
I/O
is the regulated CORE voltage,
is the CORE full-load current.
CORE
and I
CORE
1) MOSFET drain-to-source maximum voltage rating:
V
DS
rating > V maximum voltage.
•
During power-up, the CORE voltage comes
up first, and the I/O power supply fails to turn
on. The MOSFET turns on hard, keeping the
I/O voltage close to the CORE voltage. The
MOSFET in this case supports the I/O load
current, as well as the charging of the I/O
output capacitor. For most practical cases,
the power charging the I/O output capacitor
can be ignored. Since the I/O voltage never
reaches its final value, the I/O load current
might be off and the power dissipation in the
MOSFET is minimal. However, assuming the
worst-case condition that the I/O load draws
its full-load current, the power dissipation in
I/O
2) MOSFET gate-to-source maximum voltage rating:
rating > V maximum.
V
GS
CC
3) MOSFET gate turn-on threshold voltage: V
<
GS(th)
minimum operating voltage of (V
- V
). For
CC
CORE
example, if V
minimum operating voltage is 4.5V,
CC
CORE voltage is 1.8V, then V
< (4.5V - 1.8V) =
GS(th)
2.7V. A MOSFET with logic-level gate turn-on
threshold voltage is appropriate for this application.
4) Determine the maximum current that can go
through the MOSFET during power-up, power-
down/brownout, or output short-circuit conditions.
In most cases, this maximum current is the current
limit of the CORE or the I/O power supplies,
whichever is larger. Choose the MOSFET with
pulse current rating sufficiently higher than this cur-
rent. Note that typical MOSFET pulse current rating
is much larger than its continuous current rating.
the MOSFET would be I 2 x R
I/O
, where
DS(ON)
I/O
I
is the I/O full-load current.
The worst-case single-shot power dissipation in
the MOSFET is the maximum value from the steps
above and for a maximum duration of t
.
FAULT
5) Determine the MOSFET maximum R
such that
DSON
7) Next, select the MOSFET that can take this single
pulse energy without going over its maximum junc-
tion temperature rating. The maximum MOSFET
junction temperature can be calculated as follows:
under worst-case current, the voltage drop across
its drain-to-source is within the tracking limit
(approximately 400mV for most PowerPCs, ASICs,
and DSPs).
T = T
J
+ P
x Z
AMB
PULSE θJA
6) Determine the maximum single-shot power dissipa-
tion in the MOSFET during power-up, or during an
output short-circuit condition. Considering the fol-
lowing cases:
where T is the junction temperature, T
is the
J
AMB
ambient temperature, P
is the single-shot
PULSE
power dissipation calculated in step 6 above, and
is the junction-to-ambient thermal impedance
Z
θJA
•
When either the I/O or CORE is shorted to
GND, NDRV is driven high to V , turning the
CC
of the selected MOSFET for a single pulse of
duration. Z is specified in all typical
t
FAULT
θJA
MOSFET on. The current through the MOSFET
is the maximum current that the supply not
shorted can produce (the CORE supply maxi-
mum current if I/O is shorted or vice versa).
Depending on which supply is shorted, take
the maximum short-circuit current that either
the I/O or CORE supplies produce. Call this
MOSFET data sheets.
Example: I/O = 3.3V, I/O power supply has a current
limit (I )) of 6A, I/O full-load current is 3A. CORE is
I/O(LIM
1.8V, CORE power supply has a current limit
(I ) of 6A, CORE full-load current is 4A. V
=
CC
CORE(LIM)
5V + 0.5V. CORE and I/O voltages must track to within
400mV.
current I
. In this case, the power dissi-
PSLIM
2
pation in the MOSFET is I
x R
.
Choose a Si9428DY (N-channel MOSFET, V
max =
at +25°C = 0.04Ω at V = 2.5V, R
GS DS(ON)
PSLIM
DS(ON)
DS
20V, R
DS(ON)
at +125°C = 1.5 x R
data sheet, V max = 8V).
•
During power-up, the I/O voltage comes up
first, and the CORE power supply fails to turn
on. The MOSFET is in linear regulator mode,
supporting the CORE full-load current, as
at 25°C, from the MOSFET
DS(ON)
GS
14 ______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
NORMALIZED THERMAL TRANSIENT IMPEDANCE, JUNCTION TO AMBIENT
2
1
DUTY CYCLE = 0.5
0.2
NOTES:
0.1
P
DM
0.1
0.05
t
1
t
2
t
t
1
2
1. DUTY CYCLE, D =
0.02
2. PER UNIT BASE = RthJA = +70°C/W
(t)
3. T - T = P Z
JM
A
DM thJA
SINGLE PULSE
4. SURFACE MOUNTED
0.01
0.0001
0.001
0.01
0.1
SQUARE WAVE PULSE DURATION (s)
1
1 0
100
600
Figure 12. Normalized Thermal Transient Impedance
From step 5: the maximum V
and V
differential
CORE
To calculate the high-side limit, set the maximum CORE
voltage set point at the minimum system CORE voltage
minus the total system tolerance:
I/O
voltage = (I
= 360mV.
) x (R
) = 6A x 0.04Ω x 1.5
CORE(LIM)
DS(ON)
2
From step 6 (first bullet): power dissipation = I
x
-
CORESET
= CORE
- TOL
PSLIM
MAX
MIN
R
= (6A)2 x 0.04Ω x 1.5 = 2.16W.
DS(ON)
(TOL = Total Tolerance)
From step 6 (second bullet): power dissipation = (V
I/O
Calculate the low-side constraint by taking the maxi-
mum system I/O voltage, subtracting the maximum
allowable I/O to CORE difference and adding the total
system tolerance.
V ) x I
CORE
= (3.3V - 1.8V) x 4A = 6W.
CORE
2
From step 6 (third bullet): power dissipation = I
x
I/O
R
= (3A)2 x 0.04Ω x 1.5 = 0.54W.
DS(ON)
So, the worst-case power dissipation in the MOSFET is
6W for a maximum duration of 20ms. From the
Si9428DY data sheet, under the normalized thermal
CORESET
= I/O
- ∆V
+ TOL
MIN
MAX
I/OC
The following comprise the sources for the total
system tolerance:
transient impedance curve (Figure 12), the Z
is 0.05
θJA
•
•
•
Resistor mismatch
x +70°C/W for a single pulse. The worst-case junction
temperature of the MOSFET at +85°C ambient temper-
ature is:
MAX5039/MAX5040 reference error
Loop gain error
T = T
+ P
x Z
J
AMB
PULSE θJA
For example:
= +85°C + 6W x 0.05 x +70°C/W = +106°C
•
•
•
V
= 1.800 5%
CORE
Programming the CORE Voltage
See the application circuit examples in Figures 9 and 10.
The following explains constraints on the CORE voltage.
V
= 3.300 5%
I/O
Maximum voltage that I/O can exceed CORE
without damage to the processor:
The high-side constraint requires that the CORE regula-
tor maintain a minimum voltage during normal opera-
tion. The low-side limit requires that the CORE regulator
hold the CORE voltage such that the voltage difference
from I/O to CORE does not exceed the processor’s
maximum allowable voltage difference:
∆V
= (V - V
)
= 2V
I/OC
I/O
CORE MAX
•
System gain = 200V/V
______________________________________________________________________________________ 15
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Resistor mismatch:
Table 1. Error Summation
ERROR
Divider Mismatch (1% resistor)
Reference Voltage
Loop Gain Error
AMOUNT (%)
ERROR
(%) =RES_TOL
RES
1.0
2.0
800mV
× 2× 1−Ratio ; Ratio =
(
)
}
{
V
REGNOM
0.5
If the CORE set point is 1.6V, the ratio is
800mV/1600mV = 0.5. With 1% resistors, the resistor
error is:
Total = TOL
3.5%
mable UVLO feature allows V to get to a certain value
IN
before MAX5039/MAX5040 turn the system power sup-
ERROR
(%) = 1% x {2 x (1 - 0.5)} = 1%
RES
plies on together. V is usually the input voltage to the
IN
MAX5039/MAX5040 reference error: 2.0%.
system power supplies and it can be the same as V
.
CC
The UVLO pin also provides the system a way to turn
on/off the system power supplies (see the UVLO sec-
tion). Choose the UVLO trip point such that the mini-
Loop gain error: Loop gain error is due to the finite sys-
tem gain. A loop gain of 200 yields a 0.5% gain error.
Calculate the maximum and minimum regulator core
voltage set point as follows:
mum V voltage exceeds the maximum UVLO rising
IN
threshold. Follow the guidelines below to program the
UVLO voltage:
CORESET
= CORE
- TOL
MAX
MIN
= (1.8V - 5%) - 3.5%
= 1.8V x 91.5% = 1.647V
CORESET = I/O - ∆V + TOL
1) Determine the V tolerance; 5% is common.
IN
2) Determine the V
rising threshold tolerance:
UVLO
MIN
MAX
I/OC
Undervoltage lockout rising trip threshold, V
tolerance: 1.230V 2.5%
,
UVCC
= ((3.3V + 5%) - 2V) + 3.5%
= (3.465V - 2V) x 103.5%
= 1.465V x 103.5% = 1.516V
Programming resistor tolerance: pick a 1% resistor
or better ( 2% over temperature)
Set the CORE voltage set point (V
) between
REGNOM
1.516V and 1.647V and as close to the upper value
(1.647V) as possible.
Resistor-divider stack-up tolerance: 1% maximum
for 1% resistors
Connect the midpoint of a voltage-divider between
CORE and GND to CORE_FB, as shown in the Typical
Application Circuit. Set the midpoint voltage to 800mV
for a maximum CORE voltage set point of 1.647V.
Choose a value for R2 of 10kΩ.
Resistor value resolution: 0.5% (can be zero if
exact resistor value is available)
Extra margin: 1%
Total = 7%
3) Set V
nominal value to:
UVLO
Calculate R1 with the following equation:
V
nominal value - (V tolerance + V
tolerance)
IN
IN
UVLO
V
REGNOM
R1=
−1 R2
4) Calculate R7 using the equation:
V
C_REF
Example:
V
UVLONOM
R7 =
−1 R8
V
UVCC
V
1.647V
0.8V
REGNOM
R1=
−1 R2 =
−1 10kΩ =10.6kΩ
where R is typically 10kΩ.
8
V
C_REF
Example: V nominal value = 5V, V tolerance = 5%;
IN
UVLO
IN
set the V
nominal value to 5V - (5% + 7%) = 4.4V.
Using a standard 10.0kΩ ( 1%) resistor in series with a
604Ω (1%) resistor yields negligible resolution error.
Choose R8 = 10.0kΩ, 1%:
Programming UVLO Voltage
V
4.4V
UVLONOM
See the application circuit examples in Figures 9 and 10.
R7 =
−1 R8 =
−1 10kΩ = 25.8kΩ
V
1.230V
UVCC
The MAX5039/MAX5040 provide a user-programmable
undervoltage lockout feature through the UVLO pin.
When using a resistor-divider, R7 and R8, from an input
voltage rail (V ) to UVLO to GND, the user-program-
IN
16 ______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
In Figures 9 and 10, a resistor value of 50Ω is used
for R4 for extra margin.
Linear Regulator Compensation
See the application circuit examples in Figures 9 and 10.
The external MOSFET, together with the feedback resis-
tor-divider, R1 and R2, from CORE to CORE_FB to GND,
and NDRV form a linear regulator loop. This linear regu-
lator should be compensated for stable operation.
Programming I/O_SENSE Voltage
(MAX5040 Only)
See the application circuit examples in Figures 9 and 10.
I/O_SENSE is used to monitor the I/O output voltage or
any other voltage. The result is reported by the POK out-
put signal. Choose the I/O_SENSE trip point such that
the minimum monitored voltage at I/O_SENSE exceeds
the maximum I/O_SENSE rising threshold.
Note: The linear regulator spends most of its time in idle
mode. It operates in transient mode and regulation mode
only during system power-up/power-down, brownout,
and occasional system load transient conditions. Loop
stability applies when the linear regulator is in the regula-
tion mode. Follow these simple guidelines to stabilize the
linear loop: (see the Core Regulator Loop Bode Plot in
the Typical Operating Characteristics).
Follow the guidelines below to program the I/O_SENSE
voltage:
1) Determine the tolerance of the output voltage to be
monitored, VO: 5% is common.
1) Place C1, a 100nF, ceramic capacitor (X5R, X7R
type or better) from NDRV to GND.
2) Determine V
rising threshold tolerance:
I/O_SENSE
2) Select R1 and R2, a resistor-divider from CORE
to CORE_FB to GND to set the linear regulator
output regulation voltage (see the Programming
Core Voltage section).
I/O sense trip-point threshold, V
1.230V 2.5%
, tolerance:
I/O_REF
Programming resistor tolerance: pick 1% resistor
or better ( 2% over temperature)
3) Place R3 and C2, an RC network from CORE_FB
to NDRV. Set R3 = R1 and calculate C2 as follows:
Resistor-divider stackup tolerance: 1% maximum
for 1% resistors
Resistor value resolution: 0.5% (can be zero if
exact resistor value is available)
1
C2 =
2π ×10kHz×R3
Extra margin: 1%
Total = 7%
4) Place R4, a preload resistor from CORE to GND.
Calculate R4 as follows:
3) Set VI/O_SENSE rising nominal value to: VO nominal
value - (VO tolerance + VI/O_SENSE tolerance).
gfs V
CORE
R4≤
4) Calculate using the following equation:
2π ×250Hz ×C
I
D
CORE
V
I/O_SENSENOM
R5 =
−1 R6
where gfs is the transconductance of the external
MOSFET, Q1, as specified in its data sheet and I
D
is the current where gfs is specified. R4 must be
sized to properly handle its power dissipation.
V
I/O_REF
where R6 is typically 10kΩ.
Example: V nominal value = 3.3V, set V
I/O
I/O_SENSE
Example: CORE power supply = 1.8V, V
=
REGNOM
nominal value to 3.3V - (5% + 7%) = 2.904V.
1.6V, C
Siliconix):
= 100µF, Q = Si9428 (Vishay
CORE
1
Choose R6 = 10.0kΩ, 1%:
R1 = R2 = R3 = 10.0kΩ, 1%
V
I/O_SENSENOM
1
R5 =
R5 =
−1 R6
C2 =
=1.6nF
V
I/O_REF
2× π ×10kHz×10kΩ
(
)
2.904V
1.230V
−1 10kΩ =13.61kΩ
Use 1.5nF standard value.
From the Si9428 data sheet, gfs = 24S at I = 6A:
D
gfs V
24S 1.6V
CORE
R4≤
=
= 78Ω
2π ×250Hz ×C
I
2π ×250Hz ×100µF 6A
CORE
D
______________________________________________________________________________________ 17
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Typical Operating Circuit
Pin Configurations
TOP VIEW
V
IN
I/O
POWER
SUPPLY
V
I/O
OUT
IN
IN
I/O
SDO
1
2
3
4
8
7
6
5
NDRV
I/O
SHDN
V
PowerPC/
DSP/ASIC
CC
MAX5039
UVLO
GND
CORE
CORE_FB
CORE
POWER
SUPPLY
V
CORE
OUT
CORE
SHDN
µMAX
CORE I/O
NDRV
SDO
V
CC
SDO
1
2
3
4
5
10 NDRV
MAX5039
CORE_FB
V
CC
9
8
7
6
I/O
UVLO
MAX5040
UVLO
GND
CORE
CORE_FB
POK
GND
I/O_SENSE
µMAX
Chip Information
TRANSISTOR COUNT: 1272
PROCESS: BiCMOS
18 ______________________________________________________________________________________
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50±0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6±0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
α
S
0.6±0.1
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
α
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
______________________________________________________________________________________________________ 19
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50±0.1
0.6±0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6±0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
α
TOP VIEW
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
α
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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