MAX5065 [MAXIM]
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers; 双相， + 0.6V至+ 3.3V输出可并联，平均电流模式控制器
| 型号： | MAX5065 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers |
| 文件： | 总32页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3035; Rev 1; 11/03
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
General Description
Features
The MAX5065/MAX5067 dual-phase, PWM controllers
provide high-output-current capability in a compact
package with a minimum number of external compo-
nents. The MAX5065/MAX5067 utilize a dual-phase,
average-current-mode control that enables optimal use
ꢀ +4.75V to +5.5V or +8V to +28V Input Voltage
Range
ꢀ Adjustable V
OUT
+0.6V to +3.3V (MAX5065)
+0.8V to +3.3V (MAX5067)
of low R
MOSFETs, eliminating the need for exter-
DS(ON)
nal heatsinks even when delivering high output currents.
ꢀ Up to 60A Output Current
Differential sensing enables accurate control of the out-
put voltage, while adaptive voltage positioning provides
optimum transient response. An internal regulator
enables operation with input voltage ranges of +4.75V to
+5.5V or +8V to +28V. The high switching frequency, up
to 500kHz per phase, and dual-phase operation allow
the use of low-output inductor values and input capacitor
values. This accommodates the use of PC board-
embedded planar magnetics achieving superior reliabili-
ty, current sharing, thermal management, compact size,
and low system cost.
ꢀ Internal Voltage Regulator for a +12V or +24V
Power Bus
ꢀ Programmable Adaptive Output Voltage
Positioning
ꢀ True Differential Remote Output Sensing
ꢀ Out-of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
Dissipation
ꢀ Average-Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
The MAX5065/MAX5067 also feature a clock input
(CLKIN) for synchronization to an external clock, and a
clock output (CLKOUT) with programmable phase delay
(relative to CLKIN) for paralleling multiple phases. The
MAX5065/MAX5067 also limit the reverse current if the
bus voltage becomes higher than the regulated output
voltage. These devices are specifically designed to limit
current sinking when multiple power-supply modules are
paralleled. The MAX5065 offers an adjustable +0.6V to
+3.3V output voltage. The MAX5067 output voltage is
adjustable from +0.8V to +3.3V and features an overvolt-
age protection and a power-good output signal.
Accurate Current Limit Eliminates MOSFET and
Inductor Derating
ꢀ Limits Reverse-Current Sinking in Paralleled
Modules
ꢀ Integrated 4A Gate Drivers
ꢀ Selectable Fixed Frequency 250kHz or 500kHz Per
Phase (Up to 1MHz for Two Phases)
ꢀ External Frequency Synchronization from 125kHz
The MAX5065/MAX5067 operate over the extended
temperature range (-40°C to +85°C). The MAX5065 is
available in a 28-pin SSOP package. The MAX5067 is
available in a 44-pin thin QFN package. Refer to the
MAX5037A data sheet for a VRM 9.0/VRM 9.1-compati-
ble, VID-controlled output voltage controller in a 44-pin
QFN package.
to 600kHz
ꢀ Internal PLL with Clock Output for Paralleling
Multiple DC-DC Converters
ꢀ Thermal Protection
ꢀ 28-Pin SSOP Package (MAX5065)
ꢀ 44-Pin Thin QFN Package (MAX5067)
Applications
Servers and Workstations
Ordering Information
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
Networking Systems
Large-Memory Arrays
RAID Systems
MAX5065EAI
MAX5067ETH
44 Thin QFN
High-End Desktop Computers
Selector Guide and Pin Configurations appear at end of
data sheet.
________________________________________________________________Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
ABSOLUTE MAXIMUM RATINGS
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND........................................................-0.3V to +35V
Continuous Power Dissipation (T = +70°C)
A
28-Pin SSOP (derate 9.5mW/°C above +70°C) ............762mW
44-Pin Thin QFN (derate 27.0mW/°C above+70°C) ...2162mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DH_ to LX_ .................................-0.3V to [(V
_ - V _) + 0.3V]
BST
LX
DL_ to PGND..............................................-0.3V to (V
BST_ to LX_ ..............................................................-0.3V to +6V
+ 0.3V)
CC
V
V
to SGND............................................................-0.3V to +6V
CC
CC
, V
DD
to PGND...................................................-0.3V to +6V
SGND to PGND .....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (V + 0.3V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
8
28
5.50
10
Input Voltage Range
V
V
IN
Short IN and V
operation
together for +5V input
CC
4.75
Quiescent Supply Current
Efficiency
I
EN = V
or SGND
4
mA
%
Q
CC
η
I
= 52A (26A per phase)
90
LOAD
OUTPUT VOLTAGE
No load
0.5952
0.594
0.6
0.6
0.8
0.8
0.6048
0.6064
0.8064
0.808
MAX5065
MAX5067
No load, V
or V = +8V to +28V
IN
= +4.75V to +5.5V
CC
SENSE+ to SENSE- Accuracy
(Note 4)
V
No load
0.7936
0.792
No load, V
= +4.75V to +5.5V
CC
or V = +8V to +28V
IN
STARTUP/INTERNAL REGULATOR
V
Undervoltage Lockout
UVLO
V
V
rising
CC
4.0
4.15
200
5.1
4.5
V
mV
V
CC
V
Undervoltage Lockout
CC
Hysteresis
Output Accuracy
V
= +8V to +28V, I = 0 to 80mA
SOURCE
4.85
5.30
3
CC
IN
MOSFET DRIVERS
Output Driver Impedance
R
Low or high output
1
4
Ω
A
ON
Output Driver Source/Sink
Current
I
_, I
DH
_
DL
Nonoverlap Time
t
C
_ _ = 5nF
DH /DL
60
ns
NO
OSCILLATOR AND PLL
CLKIN = SGND
CLKIN = V
238
475
125
250
500
262
525
600
Switching Frequency
f
kHz
SW
CC
PLL Lock Range
PLL Locking Time
f
t
kHz
µs
PLL
200
PLL
2
_______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
115
85
TYP
120
90
60
5
MAX
125
95
UNITS
PHASE = V
CC
CLKOUT Phase Shift
(At f = 125kHz)
φCLKOUT
degrees
PHASE = unconnected
PHASE = SGND
SW
55
65
CLKIN Input Pulldown Current
CLKIN High Threshold
CLKIN Low Threshold
I
3
7
µA
V
CLKIN
V
2.4
CLKINH
V
0.8
V
CLKINL
CLKIN High Pulse Width
PHASE High Threshold
PHASE Low Threshold
PHASE Input Bias Current
CLKOUT Output Low Level
CLKOUT Output High Level
CURRENT LIMIT
t
200
4
ns
V
CLKIN
V
PHASEH
V
1
V
PHASEL
I
-50
4.5
+50
100
µA
mV
V
PHASEBIAS
V
I
= 2mA (Note 2)
CLKOUTL
SINK
V
I
= 2mA (Note 2)
CLKOUTH SOURCE
Average Current-Limit Threshold
Reverse Current-Limit Threshold
Cycle-by-Cycle Current Limit
V
CSP_ to CSN_
45
-3.9
90
48
51
mV
mV
mV
CL
V
CSP_ to CSN_
-0.2
130
CLR
V
CSP_ to CSN_ (Note 3)
112
260
CLPK
Cycle-by-Cycle Overload
Response Time
t
V
_ to V _ = +150mV
CSN
ns
R
CSP
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
R
_
4
kΩ
V
CS
V
-0.3
-1
+3.6
+1
CMR(CS)
V
mV
V/V
MHz
OS(CS)
Amplifier Gain
A
V(CS)
18
4
3dB Bandwidth
f
3dB
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance
Open-Loop Gain
gm
ca
VOL(CE)
550
50
µS
dB
A
No load
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range
DIFF Output Voltage
Input Offset Voltage
Amplifier Gain
V
-0.3
+1.0
V
V
CMR(DIFF)
V
V
= V = 0
SENSE-
0.6
CM
SENSE+
V
-1
+1
mV
V/V
MHz
mA
OS(DIFF)
A
0.997
1
3
1.003
V(DIFF)
3dB Bandwidth
f
C
= 20pF
DIFF
3dB
OUT(DIFF)
Minimum Output Current Drive
I
1.0
50
SENSE+ to SENSE- Input
Resistance
R
VS
_
100
kΩ
_______________________________________________________________________________________
3
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain
A
70
3
dB
MHz
nA
VOL(EA)
Unity-Gain Bandwidth
EAN Input Bias Current
f
UGEA
I
V
= +2.0V
EAN
-100
810
+100
918
B(EA)
Error-Amplifier Output Clamping
Voltage
V
With respect to V
mV
CLAMP(EA)
CM
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN
PGOOD goes low when V
window
is outside this
OUT
V
V
+6
+8
+10
-8.5
0.2
1
OV
PGOOD Trip Level (MAX5067)
%V
OUT
PGOOD goes low when V
window
is outside this
OUT
-12.5
-10
UV
PGOOD Output Low Level
(MAX5067)
V
I
= 4mA
V
PGLO
SINK
PGOOD Output Leakage Current
(MAX5067)
I
PGOOD = V
µA
PG
CC
Phase Failure Trip Threshold
(MAX5067)
PGOOD goes low when CLP_ is higher
than V
V
2
V
V
PH
PH
OVPIN Trip Threshold (MAX5067)
OVP
With respect to SGND
0.792
190
0.8
280
0.808
370
TH
OVPIN Input Resistance
(MAX5067)
R
kΩ
OVPIN
THERMAL SHUTDOWN
Thermal Shutdown
T
150
8
°C
°C
SHDN
Thermal-Shutdown Hysteresis
EN INPUT
EN Input Low Voltage
EN Input High Voltage
EN Pullup Current
V
1
V
V
ENL
V
3
ENH
I
4.5
5
5.5
µA
EN
Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2: Guaranteed by design. Not production tested.
Note 3: See Peak-Current Comparator section.
Note 4: Does not include an error due to finite error amplifier gain. See the Voltage-Error Amplifier section.
4
_______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 500kHz
f = 250kHz
V = +12V
IN
V
IN
= +12V
V
IN
= +5V
V
IN
= +5V
V
f
= +1.8V
OUT
V
f
= 1V
V
V
= +5V
OUT
OUT
IN
= 250kHz
= 250kHz
= +1.8V
SW
SW
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
OUTPUT CURRENT (A)
I
I
OUT
OUT
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
OUT
= +1.5V
V
OUT
= +1.5V
V
OUT
= +1.8V
V
OUT
= +1.8V
V
OUT
= +1V
V
OUT
= +1V
V
V
f
= +24V
OUT
= 125kHz
IN
= +1.8V
V
f
= +12V
IN
V
f
= +12V
IN
= 500kHz
= 250kHz
SW
SW
SW
4
0
4
8
12 16 20 24 28 32 36 40 44 48 52
OUTPUT CURRENT (A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
8
12 16 20 24 28 32 36 40 44 48 52
OUTPUT CURRENT (A)
I
OUT
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
12.0
11.5
11.0
10.5
10.0
9.5
100
90
80
70
60
50
40
30
20
10
0
250kHz
125kHz
V
= +24V
IN
9.0
8.5
V
IN
= +12V
8.0
7.5
V
C
C
= +12V
= 22nF
DH_
IN
DL_
7.0
V
SW
= +12V
V
IN
= +5V
IN
EXTERNALCLOCK
NO DRIVER LOAD
6.5
f
= 250kHz
= 8.2nF
6.0
1
3
5
7
9
11
13
15
100 150 200 250 300 350 400 450 500 550 600
FREQUENCY (kHz)
-40
-15
10
35
60
85
C
(nF)
TEMPERATURE (°C)
DRIVER
_______________________________________________________________________________________
5
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
OVERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
UNDERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
10
10
55
54
53
52
51
50
49
48
47
46
45
V
V
= +3.3V
= +0.8V
OUT
V
V
= +3.3V
= +0.8V
OUT
1
1
PHASE 2
OUT
OUT
PHASE 1
0.1
0.1
5.5
4.7 4.8 4.9 5.0 5.1 5.2 5.3
(V)
5.5
4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4
(V)
5.4
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
V
V
IN
V
OUT
(V)
IN
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGE
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (R /R )
DIFFERENTIAL AMPLIFIER BANDWIDTH
F
IN
MAX5065/67 toc14
1.90
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
90
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
IN
= +12V
NO DRIVER
45
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
R /R = 40
F
IN
R /R = 20
PHASE
F
IN
0
-45
-90
-135
-180
-225
R /R = 10
F
IN
GAIN
R /R = 7.5
F
IN
-270
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
∆V (V)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0.01
0.1
1
10
I
FREQUENCY (MHz)
SENSE
LOAD
V
LOAD REGULATION
vs. INPUT VOLTAGE
CC
V
LINE REGULATION
V
LINE REGULATION
CC
CC
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
V
= +24V
IN
I
= 0
CC
V
IN
= +12V
I
= 40mA
CC
V
IN
= +8V
DC LOAD
15 30 45 60 75 90 105 120 135 150
(mA)
I
= 80mA
9
CC
0
8
10 12 14 16 18 20 22 24 26 28
(V)
8
10
11
12
13
I
V
IN
V
IN
(V)
CC
6
_______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
HIGH-SIDE DRIVER (DH_)
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
SINK AND SOURCE CURRENT
MAX5065/67 toc21
120
110
100
90
80
70
60
50
40
30
20
10
0
120
110
100
90
80
70
60
50
40
30
20
10
0
DL_
DH_
DL_
DH_
DH_
1.6A/div
V
SW
= +12V
= 250kHz
V = +12V
IN
DH_
IN
V
SW
= +12V
= 250kHz
IN
f
C
= 22nF
f
1
6
11
16
21
26
31
36
100ns/div
1
6
11
16
21
26
31
36
C
(nF)
DRIVER
C
(nF)
DRIVER
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
MAX5065/67 toc22
MAX5065/67 toc23
CLKOUT
5V/div
350kHz
PLLCMP
200mV/div
DL_
1.6A/div
250kHz
= +12V
0
V
= +12V
= 22nF
V
IN
IN
C
DL_
NO LOAD
100ns/div
100µs/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz
MAX5065/67 toc24
MAX5065/67 toc25
CLKOUT
5V/div
CLKOUT
5V/div
250kHz
PLLCMP
200mV/div
500kHz
PLLCMP
200mV/div
150kHz
0
250kHz
V
= +12V
V
= +12V
IN
IN
NO LOAD
NO LOAD
0
100µs/div
100µs/div
_______________________________________________________________________________________
7
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
HIGH-SIDE DRIVER (DH_)
FALL TIME
HIGH-SIDE DRIVER (DH_)
RISE TIME
MAX5065/67 toc27
MAX5065/67 toc26
DH_
2V/div
DH_
2V/div
V
= +12V
DH_
IN
C
V
= +12V
DH_
IN
C
= 22nF
= 22nF
40ns/div
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIME
LOW-SIDE DRIVER (DL_)
FALL TIME
MAX5065/67 toc28
MAX5065/67 toc29
DL_
2V/div
DL_
2V/div
V
= +12V
DL_
V
= +12V
DL_
IN
C
IN
C
= 22nF
= 22nF
40ns/div
40ns/div
OUTPUT RIPPLE
INPUT STARTUP RESPONSE
MAX5065/67 toc30
MAX5065/67 toc31
V
PGOOD
1V/div
V
OUT
1V/div
V
OUT
(AC-COUPLED)
10mV/div
V
IN
5V/div
V
V
= +12V
IN
V
= +12V
IN
V
= +1.75V
OUT
= 52A
OUT
= +1.75V
OUT
OUT
I
I
= 52A
500ns/div
2ms/div
8
_______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
REVERSE CURRENT SINK
vs. TEMPERATURE
ENABLE STARTUP RESPONSE
LOAD-TRANSIENT RESPONSE
MAX5065/67 toc32
MAX5065/67 toc33
2.8
2.7
2.6
2.5
2.4
2.3
V
PGOOD
1V/div
V
= +3.3V
EXTERNAL
V
OUT
1V/div
V
OUT
50mV/div
V
EN
V
= +2V
V
V
I
= +12V
EXTERNAL
IN
OUT
STEP
RISE
2V/div
V
V
I
= +12V
= +1.75V
= 8A TO 52A
= 1µs
IN
= +1.75V
= 52A
OUT
OUT
V
V
= +12V
= 1.5V
IN
OUT
t
R1 = R2 = 1.5mΩ
35 60 85
1ms/div
-40
-15
10
TEMPERATURE (°C)
40µs/div
REVERSE CURRENT SINK AT INPUT TURN-ON
REVERSE CURRENT SINK AT INPUT TURN-ON
(V = 12V, V
= 1.5V, V
= 3.3V)
EXTERNAL
MAX5065/67 toc36
(V = 12V, V
= 1.5V, V
= 2.5V)
EXTERNAL
MAX5065/67 toc35
IN
OUT
IN
OUT
REVERSE
CURRENT
10A/div
REVERSE
CURRENT
5A/div
0A
0A
R1 = R2 = 1.5mΩ
R1 = R2 = 1.5mΩ
200µs/div
200µs/div
REVERSE CURRENT SINK AT ENABLE TURN-ON
REVERSE CURRENT SINK AT ENABLE TURN-ON
(V = 12V, V
= 1.5V, V
= 2.5V)
EXTERNAL
MAX5065/67 toc37
(V = 12V, V
= 1.5V, V
= 3.3V)
EXTERNAL
MAX5065/67 toc38
IN
OUT
IN
OUT
REVERSE
CURRENT
5A/div
REVERSE
CURRENT
10A/div
0A
0A
R1 = R2 = 1.5mΩ
R1 = R2 = 1.5mΩ
200µs/div
200µs/div
_______________________________________________________________________________________
9
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Pin Description
PIN
NAME
FUNCTION
MAX5065 MAX5067
Current-Sense Differential Amplifier Positive Inputs. Sense the inductor current. The differential
voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of
18.
CSP2,
CSP1
1, 13
2, 14
3
39, 16
40, 17
41
CSN2,
CSN1
Current-Sense Differential Amplifier Negative Inputs. Together with CSP_, sense the inductor
current.
Phase-Shift Setting Input. Connect PHASE to V
for 120°, leave PHASE unconnected for 90°,
CC
PHASE or connect PHASE to SGND for 60° of phase shift between the rising edge of CLKOUT and
CLKIN/DH1.
External Loop-Compensation Input. Connect compensation network for the phase-locked loop
(see the Phase-Locked Loop section).
4
42
PLLCMP
CLP2,
CLP1
Current-Error Amplifier Outputs. Compensate the current loop by connecting an RC network to
ground.
5, 7
6
43, 7
5, 20, 35
SGND
Signal Ground. Ground connection for the internal control circuitry.
Differential Output-Voltage-Sensing Positive Input. Used to sense a remote load. The MAX5065
and MAX5067 regulate the difference between SENSE+ and SENSE- according to the factory
preset reference voltage of +0.6V and +0.8V, respectively.
8
10
SENSE+
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect
9
11
12
13
SENSE-
DIFF
SENSE- to V
or PGND at the load.
OUT-
Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain
amplifier.
10
11
Voltage-Error Amplifier Inverting Input. Receives a signal from the output of the differential
remote-sense amplifier. Referenced to SGND.
EAN
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The
12
14
EAOUT external error amplifier gain-setting resistors determine the amount of adaptive voltage
positioning.
Output Enable. A logic-low shuts down the power drivers. EN has an internal 5µA pullup
current.
15
19
EN
BST1,
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver
supply. Connect a 0.47µF ceramic capacitor between BST_ and LX_.
16, 26
17, 25
22, 34
23, 32
DH1,
DH2
High-Side Gate-Driver Outputs. Drive the gate of the high-side MOSFET.
Inductor Connection. Source connection for the high-side MOSFETs. Also serve as the return
terminal for the high-side driver.
18, 24
19, 23
20
24, 31
25, 30
27
LX1, LX2
DL1, DL2 Low-Side Gate-Driver Outputs. Synchronous MOSFET gate drivers for the two phases.
Internal +5V Regulator Output. V is derived internally from the IN voltage. Bypass to SGND
CC
V
CC
with 4.7µF and 0.1µF ceramic capacitors in parallel.
Supply Voltage Connection. Connect IN to V for a +5V system. Connect the unregulated
CC
21
22
28
29
IN
power source to IN through an RC lowpass filter comprised of a 2.2Ω resistor and a 0.1µF
ceramic capacitor.
Power Ground. Connect the V
bypass capacitors, input capacitors, output capacitors, and
CC
PGND
low-side synchronous MOSFET source to PGND.
10 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
MAX5065 MAX5067
Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount determined by the
PHASE input. Use CLKOUT to parallel additional MAX5065/MAX5067s.
27
36
CLKOUT
CMOS Logic Clock Input. Drive CLKIN with a frequency range between 125kHz and 600kHz or
connect to V
connect to V
current.
or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or
to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown
CC
CC
28
38
CLKIN
Overvoltage Protection Circuit Input. Connect OVPIN to the center of the resistive-divider
between V and GND. When OVPIN exceeds +0.8V with respect to SGND, OVPOUT latches
DH_ low and DL_ high. Toggle EN low to high or recycle the power to reset the latch.
—
—
6
8
OVPIN
OUT
Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a
safety device such as an SCR.
OVPOUT
Power-Good Output. The open-drain, active-low PGOOD output goes low when the output
voltage falls out of regulation or a phase failure is detected. The power-good window-
comparator thresholds are +8% and -10% of the output voltage. Forcing EN low also forces
PGOOD low.
—
9
PGOOD
N.C.
1, 2, 3, 4,
15, 18,
21, 33,
37, 44
—
—
No Connection. Not internally connected.
Supply Voltage for Low-Side and High-Side Drivers. V
powers V . Connect a parallel
DD
CC
combination of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to V
to filter
26
V
CC
DD
out the high peak currents of the driver from the internal circuitry.
+3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) using
a resistive-divider at SENSE+ and SENSE-.
Detailed Description
The MAX5065/MAX5067 average-current-mode PWM
controllers drive two out-of-phase buck converter chan-
nels. Average-current-mode control improves current
sharing between the channels while minimizing compo-
nent derating and size. Parallel multiple MAX5065/
MAX5067 regulators to increase the output current
capacity. For maximum ripple rejection at the input, set
the phase shift between phases to 90° for two paral-
leled converters, or 60° for three paralleled converters.
Paralleling the MAX5065/MAX5067s improves design
flexibility in applications requiring upgrades (higher
load).
V
IN
, V , V
DD
CC
The MAX5065/MAX5067 accept a wide input voltage
range of +4.75V to +5.5V or +8V to +28V. All internal
control circuitry operates from an internally regulated
nominal voltage of +5V (V ). For input voltages of +8V
CC
CC
or greater, the internal V
regulator steps the voltage
down to +5V. The V
output voltage regulates to +5V
while sourcing up to 80mA. Bypass V
CC
to SGND with
CC
4.7µF and 0.1µF low-ESR ceramic capacitors for high-
frequency noise rejection and stable operation (Figures
1, 2, and 3).
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor
ripple current, effectively multiplying the switching fre-
quency by the number of phases. Each phase of the
MAX5065/MAX5067 consists of an inner average cur-
rent loop controlled by a common outer-loop voltage-
error amplifier (VEA). The combined action of the two
inner current loops and the outer voltage loop corrects
the output voltage errors and forces the phase currents
to be equal. Program the output voltage from +0.6V to
Calculate power dissipation in the MAX5065/MAX5067
as a product of the input voltage and the total V
reg-
CC
ulator output current (I ). I
includes quiescent cur-
CC CC
rent (I ) and gate-drive current (I ):
Q
DD
(1)
(2)
P = V x I
D
IN CC
I
= I + f
x (Q + Q + Q + Q
)
G4
CC
Q
SW
G1
G2
G3
______________________________________________________________________________________ 11
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Functional Diagrams
EN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
IN
TO INTERNAL CIRCUITS
V
CC
DRV_V
SHDN
CC
TO INTERNAL CIRCUITS
CSP1
CSN1
CLP1
BST1
CSP1
CSN1
CLP1
DH1
LX1
DL1
PHASE 1
RAMP1
CLK
SGND
MAX5065
GM
IN
PGND
PHASE-
LOCKED
LOOP
CLKIN
PHASE
CLKOUT
PLLCMP
RAMP
GENERATOR
DIFF
SENSE-
0.6V
DIFF
AMP
PGND
SENSE+
EAOUT
EAN
ERROR
AMP
DRV_V
SHDN
PGND
CC
CLK
V
REF
= 0.6V + V
CM
RAMP2
DH2
LX2
PHASE 2
GM
IN
CLP2
CSN2
CSP2
CLP2
DL2
CSN2
CSP2
BST2
12 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Functional Diagrams (continued)
EN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
IN
V
V
CC
TO INTERNAL CIRCUITS
DD
DRV_V
SHDN
CC
CSP1
CSN1
CLP1
BST1
CSP1
CSN1
CLP1
DH1
LX1
DL1
PHASE 1
RAMP1
CLK
SGND
MAX5067
GM
IN
PGND
PHASE-
LOCKED
LOOP
CLKIN
PHASE
RAMP
GENERATOR
CLKOUT
PLLCMP
CLP1
DIFF
PGOOD
PGND
POWER-
GOOD
GENERATOR
DIFF
N
CLP2
SENSE-
+0.6V
V
REF
DIFF
AMP
SENSE+
EAOUT
EAN
OVPOUT
OVP
COMP
0.8V
ERROR
AMP
DRV_V
SHDN
PGND
CC
CLK
V
= 0.8V + V
CM
REF
RAMP2
DH2
LX2
PHASE 2
GM
IN
OVPIN
CLP2
CSN2
CSP2
CLP2
DL2
CSN2
CSP2
BST2
______________________________________________________________________________________ 13
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Figure 1. Typical Application Circuit, V = +5V
IN
14 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Figure 2. Typical VRM Application Circuit, V = +8V to +28V
IN
______________________________________________________________________________________ 15
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
9
SENSE-
8
SENSE+
14
3
CSN1
CSP1
PHASE
13
V
IN
15
EN
IN
C3–C7
R1
V
IN
= +12V
21
C1,
C2
17
18
19
C39
DH1
LX1
DL1
Q1
R2
L1
V
CC
C12
Q2
28
4
CLKIN
D1
MAX5065
16
20
BST1
D3
PLLCMP
+1.8V AT 60A
V
CC
R4
V
OUT
C25
C34
C32
C31
R
R
H
C26
R7
R8
10
11
12
D4
R3
DIFF
EAN
V
V
CC
IN
C14,
C15
C16–C24,
C33
C8–C11
LOAD
L
R
X
EAOUT
25
24
23
DH2
LX2
DL2
Q1
Q2
L2
7
5
R6
CLP1
C29
C13
D2
C30
C28
26
BST2
CLP2
R5
C27
1
2
6
SGND
PGND
CSP2
CSN2
22
Figure 3. MAX5065 Typical Application Circuit
16 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
where, Q , Q , Q
and Q
are the total gate
G4
Control Loop
The MAX5065/MAX5067 use an average-current-mode
control scheme to regulate the output voltage (Figure
4). The main control loop consists of an inner current
loop and an outer voltage loop. The inner loop controls
G1
G2
G3,
charge of the low-side and high-side external
MOSFETs, I is 4mA (typ), and f is the switching fre-
Q
SW
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the V regulator by connecting IN and V together.
the output currents (I
and I
) while the
PHASE2
PHASE1
CC
CC
outer loop controls the output voltage. The inner current
loop absorbs the inductor pole reducing the order of
the outer voltage loop to that of a singlepole system.
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5065/MAX5067 include an undervoltage lock-
out with hysteresis and a power-on reset circuit for con-
verter turn-on and monotonic rise of the output voltage.
The UVLO threshold is internally set between +4.0V
and +4.5V with a 200mV hysteresis. Hysteresis at
UVLO eliminates “chattering” during startup.
The current loop consists of a current-sense resistor
(R ), a current-sense amplifier (CA_), a current-error
S
amplifier (CEA_), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM_). The precision
CA_ amplifies the sense voltage across R by a factor
S
of 18. The inverting input to the CEA_ senses the CA_
output. The CEA_ output is the difference between the
voltage-error amplifier output (EAOUT) and the gained-
up voltage from the CA_. The RC compensation net-
work connected to CLP1 and CLP2 provides external
frequency compensation for the respective CEA_. The
start of every clock cycle enables the high-side drivers
and initiates a PWM ON cycle. Comparator CPWM_
compares the output voltage from the CEA_ with a 0 to
+2V ramp from the oscillator. The PWM ON cycle termi-
nates when the ramp voltage exceeds the error voltage.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5065/MAX5067 draw up to 4mA of current before
the input voltage reaches the UVLO threshold.
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes a parallel combination of
capacitors (C34, C36) and resistors (R5, R6) in series
with other capacitors (C33, C35) (see Figures 1 and 2).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
The outer voltage control loop consists of the differen-
tial amplifier (DIFF AMP), reference voltage, and VEA.
The unity-gain differential amplifier provides true differ-
ential remote sensing of the output voltage. The differ-
ential amplifier output connects to the inverting input
(EAN) of the VEA. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5067 reference voltage is set to +0.8V
and the MAX5065 reference is set to +0.6V. The VEA
controls the two inner current loops (Figure 4). Use a
resistive feedback network to set the VEA gain as
required by the adaptive voltage-positioning circuit
(see the Adaptive Voltage Positioning section).
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2V
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
P-P
frequency to 250kHz or connect CLKIN to V
internal oscillator to 500kHz.
to set the
CC
CLKIN is a CMOS logic clock input for the phase-
locked loop (PLL). When driven externally, the internal
oscillator locks to the signal at CLKIN. A rising edge at
CLKIN starts the ON cycle of the PWM. Ensure that the
external clock pulse width is at least 200ns. CLKOUT
provides a phase-shifted output with respect to the ris-
ing edge of the signal at CLKIN. PHASE sets the
amount of phase shift at CLKOUT. Connect PHASE to
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense ampli-
fier senses the voltage across a current-sense resistor.
V
CC
for 120° of phase shift, leave PHASE unconnected
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 5).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit condi-
tions. To prevent inductor saturation, select an output
for 90° of phase shift, or connect PHASE to SGND for
60° of phase shift with respect to CLKIN.
The MAX5065/MAX5067 require compensation on
PLLCMP even when operating from the internal oscillator.
The device requires an active PLL to generate the proper
clock signal required for PWM operation.
______________________________________________________________________________________ 17
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
inductor with a saturation current specification greater
than the average current limit (48mV). Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a cracked output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current com-
parator has a delay of only 260ns.
up slope to the inverting input of the PWM comparator,
is less than the slope of the internally generated voltage
ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V
ramp. At the start of each clock
P-P
cycle, an R-S flip-flop resets and the high-side driver
(DH_) turns on. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP_ voltage,
thus terminating the ON cycle (Figure 5).
Current-Error Amplifier
Each phase of the MAX5065/MAX5067 has a dedicated
transconductance current-error amplifier (CEA_) with a
typical g of 550µS and 320µA output sink and source
m
Differential Amplifier
The differential amplifier (DIFF AMP) facilitates output
voltage remote sensing at the load (Figure 4). It pro-
vides true differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
current capability. The current-error amplifier outputs,
CLP1 and CLP2, serve as the inverting input to the
PWM comparator. CLP1 and CLP2 are externally
accessible to provide frequency compensation for the
inner current loops (Figure 4). Compensate CEA_ so
the inductor current down slope, which becomes the
C
CF
R
CF
C
CFF
MAX5065/
MAX5067
CA1
V
IN
I
PHASE1
R *
F
CEA1
DRIVE 1
SENSE+
SENSE-
CPWM1
R
S
R
IN
*
DIFF
AMP
VEA
V
OUT
V
IN
C
OUT
CEA2
R
S
V
LOAD
REF
I
PHASE2
CPWM2
DRIVE 2
CA2
C
CF
R
CF
*R AND R ARE EXTERNAL.
F
IN
C
CCF
Figure 4. MAX5065/MAX5067 Control Loop
18 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA pro-
vides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The dif-
ferential amplifier has a bandwidth of 3MHz. The differ-
ence between SENSE+ and SENSE- regulates to +0.6V
for the MAX5065 and regulates to +0.8V for the
MAX5067. Connect SENSE+ to the center of the resis-
tive-divider from the output to SENSE-.
(Figures 1, 2). V
(MAX5067).
= 0.6V (MAX5065) or 0.8V
REF
Some applications require V
equal to V
at
OUT
OUT(NOM)
no load. To ensure that the output voltage does not
exceed the nominal output voltage (V ), add a
OUT(NOM)
resistor R from V
to EAN.
CC
X
Use the following equations to calculate the value of R .
X
For MAX5065:
(4)
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop and
determines the error between the differential amplifier
R
0.6V
F
R
R
=[V −1.2]×
CC
X
X
output and the internal reference voltage (V
).
For MAX5067:
REF
(5)
The VEA output clamps to +0.9V relative to V
CM
R
F
=[V −1.4]×
CC
(+0.6V), thus limiting the average maximum current
from individual phases. The maximum average current-
limit threshold for each phase is equal to the maximum
clamp voltage of the VEA divided by the gain (18) of
the current-sense amplifier. This results in accurate set-
tings for the average maximum current for each phase.
0.8V
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current sud-
denly decreases. A larger allowed, voltage-step excur-
sion reduces the required number of output capacitors
Set the VEA gain using R and R for the amount of
F
IN
output voltage positioning required within the rated cur-
rent range as discussed in the Adaptive Voltage
Positioning section (Figure 4).
(3)
R
R + R
H L
IN
V
= 1+
×
× V
REF
OUT(NL)
R
R
L
F
where R and R are the feedback resistor network
H
L
DRV_V
CC
PEAK-CURRENT
COMPARATOR
112mV
CLP_
CSP_
CSN_
A = 18
V
G
m
=
500µS
BST_
DH_
LX_
PWM
COMPARATOR
GM
IN
Q
Q
S
R
RAMP
CLK
2 x f (V/s)
s
DL_
SHDN
PGND
Figure 5. Phase Circuit (Phase 1/Phase 2)
______________________________________________________________________________________ 19
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
compensation provides a zero defined by 1 / [R4 x
(C31 + C32)] and a pole defined by 1 / (R4 x C32). Use
the following typical values for compensating the PLL:
V
+ ∆V /2
OUT
CNTR
R4 = 7.5kΩ, C31 = 4.7nF, C32 = 470pF. If changing the
PLL frequency, expect a finite locking time of approxi-
mately 200µs.
V
CNTR
V
- ∆V /2
OUT
CNTR
The MAX5065/MAX5067 require compensation on
PLLCMP even when operating from the internal oscilla-
tor. The device requires an active PLL in order to gen-
erate the proper internal PWM clocks.
FULL LOAD
1/2 LOAD
LOAD (A)
NO LOAD
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1, 2,
and 3). The drivers’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose high-
Figure 6. Defining the Voltage-Positioning Window
or allows for the use of higher ESR capacitors.
Voltage positioning may require the output to regulate
away from a center value. Define the center value as the
voltage where the output drops (∆V
maximum output current (Figure 6).
/2) at one half the
OUT
side MOSFETs (Q1 and Q3) with a moderate R
DS(ON)
Set the voltage-positioning window (∆V
) using the
and a very low gate charge. Choose low-side
OUT
resistive feedback of the VEA. Use the following equa-
tions to calculate the voltage-positioning window for the
MAX5065/MAX5067:
MOSFETs (Q2 and Q4) with very low R
moderate gate charge.
and
DS(ON)
The driver block also includes a logic circuit that provides
an adaptive nonoverlap time to prevent shoot-through
currents during transition. The typical nonoverlap time is
60ns between the high-side and low-side MOSFETs.
(6)
I
×R
R +R
H L
OUT
IN
∆V
=
×
OUT
2×G ×R
R
C
F
L
BST_
The MAX5067 uses V
to power the low- and high-
DD
(7)
side MOSFET drivers. The high-side drivers derive their
power through a bootstrap capacitor and V supplies
0.05
G
=
C
DD
R
S
power internally to the low-side drivers. Connect a
0.47µF low-ESR ceramic capacitor between BST_ and
where R and R are the input and feedback resistors of
the VEA, G is the current-loop transconductance, and
IN
F
LX_. Bypass V
to SGND with 4.7µF and 0.1µF low-
CC
C
ESR ceramic capacitors in parallel. Reduce the PC
board area formed by these capacitors, the rectifier
R is the current-sense resistor.
S
diodes between V
and the boost capacitor, the
CC
Phase-Locked Loop: Operation and
MAX5065/MAX5067, and the switching MOSFETs.
Compensation
The PLL synchronizes the internal oscillator to the
external frequency source when driving CLKIN.
Overload Conditions
Average-current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to +0.9V with respect to the common-mode
Connecting CLKIN to V
or SGND forces the PWM
CC
frequency to default to the internal oscillator frequency
of 500kHz or 250kHz, respectively. The PLL uses a
conventional architecture consisting of a phase detec-
tor and a charge pump capable of providing 20µA of
output current. Connect an external series combination
capacitor (C31) and resistor (R4) and a parallel capaci-
tor (C32) from PLLCMP to SGND to provide frequency
compensation for the PLL (Figure 1). The pole-zero pair
voltage (V
= +0.6V) and is compared with the output
CM
of the current-sense amplifiers (CA1 and CA2) (see
Figure 4). The current-sense amplifier’s gain of 18 limits
the maximum current in the inductor or sense resistor to
I
= 50mV/R .
S
LIMIT
20 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Protection
The MAX5067 includes output overvoltage protection
(OVP), undervoltage protection (UVP), phase failure,
and overload protection to prevent damage to the pow-
ered electronic circuits.
Power-Good Generator (MAX5067)
The PGOOD output is high if all of the following condi-
tions are met (Figure 8):
1) The output is within 90% to 108% of the pro-
grammed output voltage.
2) Both phases are providing current.
3) EN is high.
Overvoltage Protection (MAX5067)
The OVP comparator compares the OVPIN input to the
overvoltage threshold (Figure 7). The overvoltage
threshold is typically +0.8V. A detected overvoltage
event latches the comparator output forcing the power
stage into the OVP state. In the OVP state, the high-
side MOSFETs turn off and the low-side MOSFETs latch
on. Use the OVPOUT high-current output driver to turn
on an external crowbar SCR. When the crowbar SCR
turns on, a fuse must blow or the source current for the
MAX5067 regulator must be limited to prevent further
damage to the external circuitry. Connect the SCR
close to the input source and after the fuse. Use an
SCR large enough to handle the peak I2t energy due to
the input and output capacitors discharging and the
current sourced by the power-source output. Connect
DIFF to OVPIN for differential output sensing and over-
voltage protection. Add an RC delay to reduce the sen-
sitivity of the overvoltage circuit and avoid nuisance
tripping of the converter (Figures 1, 2). Connect a resis-
tor-divider from the load to SGND to set the OVP output
voltage.
A window comparator compares the differential amplifier
output (DIFF) against 1.08 times the set output voltage
for overvoltage and 0.90 times the set output voltage for
undervoltage monitoring. The phase-failure comparator
detects a phase failure by comparing the current-error-
amplifier output (CLP_) with a 2.0V reference.
Use a 10kΩ pullup resistor from PGOOD to a voltage
source less than or equal to V . An output voltage
CC
outside the comparator window or a phase-failure con-
dition forces the open-drain output low. The open-drain
MOSFET sinks 4mA of current while maintaining less
than 0.2V at the PGOOD output.
R
R
A
(8)
V
= 1+
× 0.8V
OVP
DIFF
B
8% OF V
REF
PGOOD
V
REF
RA
10% OF V
REF
V
OUT
OVPIN
DIFF
RB
CLP1
MAX5067
+2.0V
R
IN
EAN
R
F
EAOUT
CLP2
PHASE-FAILURE DETECTION
Figure 7. OVP Input Delay
Figure 8. Power-Good Generator (MAX5067)
______________________________________________________________________________________ 21
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
CSN1
CSP1
SENSE+
SENSE-
V
IN
DH1
LX1
DL1
V
CC
PHASE
V
CC
V
MAX5065/
MAX5067
IN
CLKIN
IN
DH2
LX2
DL2
V
IN
DIFF
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
PHASE
V
V
IN
DH1
LX1
DL1
V
CC
MAX5065/
MAX5067
IN
IN
DH2
LX2
DL2
DIFF
V
V
= +0.6V (MAX5065)
= +0.8V (MAX5067)
OUT
OUT
LOAD
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
PHASE
V
V
IN
DH1
LX1
DL1
V
CC
MAX5065/
MAX5067
IN
IN
DH2
LX2
DL2
DIFF
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
TO OTHER MAX5065/MAX5067s
Figure 9. Parallel Configuration of Multiple MAX5065/MAX5067s
22 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
V
= +12V
IN
V
IN
C1, C2
2 x 47µF
V
CC
C31
R13
2.2Ω
C32
C43
R12
C42
0.1µF
R4
V
IN
C3–C7
5 x 22µF
OVPOUT
PLLCMP CLKIN
IN
SENSE- SENSE+ CSN1 CSP1
DH1
LX1
DL1
Q1
L1
R1
1.35mΩ
0.6µH
C12
0.47µF
Q2
D1
D3
BST1
V
V
CC
CC
C38
4.7µF
C41
0.1µF
EN
R3
V
DD
C39
1µF
C40
1µF
D4
OVPIN
DIFF
R7
R8
V
IN
MAX5067
(MASTER)
4 x 22µF
C8–C11
EAN
DH2
LX2
DL2
Q3
L2
0.6µH
R2
1.35mΩ
EAOUT
C13
0.47µF
Q4
D2
BST2
CLP1
CLP2 PGND SGND CLKOUT PHASE PGOOD CSN2 CSP2
R11
R6
R5
C36
C34
PGOOD
V
CC
C35
C33
C26–C30,
C14, C15,
C44, C45
2 x 100µF
R
RA
RB
H
C37
R24
2.2Ω
6 x 10µF
C70
R17
LOAD
C16–C25,
C57–C60
2 x 270µF
C71
EN
R
L
V
IN
C61
0.1µF
V
= +0.8V TO
OUT
+3.3V AT 104A
C46–C50
5 x 22µF
PLLCMP
IN
CLKIN SENSE- SENSE+ CSN1 CSP1
DH1
LX1
DL1
Q5
Q6
L3
R14
1.35mΩ
0.6µH
C55
0.47µF
D5
D7
D8
BST1
V
CC
C65
4.7µF
C64
0.1µF
R16
OVPOUT
OVPIN
V
DD
C62
1µF
C63
0.1µF
MAX5067
(SLAVE)
R20
V
IN
C51–C54
4 x 22µF
DIFF
EAN
R15
1.35mΩ
DH2
LX2
DL2
Q7
Q8
L4
R21
0.6µH
EAOUT
C56
0.47µF
D6
BST2
CLP1
CLP2
PGND
SGND PHASE PGOOD
CSN2 CSP2
R19
C67
R18
C68
C66
C69
V
CC
Figure 10. Four-Phase Parallel Application Circuit (V = +12V, V
= +0.8V to +3.3V at 104A)
OUT
IN
______________________________________________________________________________________ 23
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
tion, respectively. Figure 1 shows the typical application
circuit for a two-phase operation. The design criteria for
a two-phase converter includes frequency selection,
inductor value, input/output capacitance, switching
MOSFETs, sense resistors, and the compensation net-
work. Follow the same procedure for the four- and six-
phase converter design, except for the input and output
capacitance. The input and output capacitance require-
ments vary depending on the operating duty cycle.
Phase-Failure Detector (MAX5067)
Output current contributions from the two phases are
within 10% of each other. Proper current sharing
reduces the necessity to overcompensate the external
components. However, an undetected failure of one
phase driver causes the other phase driver to run con-
tinuously as it tries to provide the entire current require-
ment to the load. Eventually, the stressed operational
phase driver fails.
The examples discussed in this data sheet pertain to a
typical application with the following specifications:
During normal operating conditions, the voltage level
on CLP_ is within the peak-to-peak voltage levels of the
PWM ramp. If one of the phases fails, the control loop
raises the CLP_ voltage above its operating range. To
determine a phase failure, the phase-failure detection
circuit (Figure 8) monitors the output of the current
amplifiers (CLP1 and CLP2) and compares them to a
2.0V reference. If the voltage levels on CLP1 or CLP2
are above the reference level for more than 1250 clock
cycles, the phase failure circuit forces PGOOD low.
VIN = +12V
VOUT = +1.8V
IOUT(MAX) = 52A
fSW = 250kHz
Peak-to-Peak Inductor Current (∆IL) = 10A
Table 1 shows a list of recommended external compo-
nents (Figure 1) and Table 2 provides component sup-
plier information.
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5065/MAX5067s (six phases) to triple
the available output current (see Figures 9 and 10). The
paralleled converters operate at the same switching fre-
quency but different phases keep the capacitor ripple
RMS currents to a minimum. Three parallel MAX5065/
MAX5067 converters deliver up to 180A of output cur-
rent. To set the phase shift of the on-board PLL, leave
PHASE unconnected for 90° of phase shift (2 paralleled
converters), or connect PHASE to SGND for 60° of phase
shift (3 converters in parallel). Designate one converter
as master and the remaining converters as slaves.
Connect the master and slave controllers in a daisy-
chain configuration as shown in Figure 9. Connect CLK-
OUT from the master controller to CLKIN of the first
slaved controller, and CLKOUT from the first slaved con-
troller to CLKIN of the second slaved controller. Choose
the appropriate phase shift for minimum ripple currents
at the input and output capacitors. The master controller
senses the output differential voltage through SENSE+
and SENSE- and generates the DIFF voltage. Disable the
voltage sensing of the slaved controllers by leaving DIFF
unconnected (floating). Figure 10 shows a detailed typi-
cal parallel application circuit using two MAX5067s. This
circuit provides four phases at an input voltage of +12V
and an output voltage range of +0.6V to +3.3V
(MAX5065) and +0.8V to +3.3V (MAX5067) at 104A.
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancella-
tion depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
NPH ≈ K/D
(9)
where K = 1, 2, or 3 and the duty cycle is D = VOUT/VIN.
Choose K to make NPH an integer number. For exam-
ple, converting VIN = +12V to VOUT = +1.8V yields
better ripple cancellation in the six-phase converter
than in the four-phase converter. Ensure that the output
load justifies the greater number of components for
multiphase conversion. Generally limiting the maximum
output current to 25A per phase yields the most cost-
effective solution. The maximum ripple cancellation
occurs when NPH = K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switch-
ing MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipa-
tion in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
thereby reducing the input/output capacitance require-
ment for the same ripple performance. The lower induc-
tance value improves the large-signal response of the
converter during a transient load at the output. Consider
Applications Information
Each MAX5065/MAX5067 circuit drives two 180° out-of-
phase channels. Parallel two or three MAX5065/
MAX5067 circuits to achieve four- or six-phase opera-
24 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Table 1. Component List
DESIGNATION
C1, C2
QTY
2
DESCRIPTION
47µF,16V X5R input-filter capacitors TDK C5750X5R1C476M
22µF, 16V input-filter capacitors TDK C4532X5R1C226M
0.47µF, 16V capacitors TDK C1608X5R1A474K
100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3
270µF, 2V output-filter capacitors Panasonic EEFUE0D271R
10µF, 6.3V output-filter capacitors TDK C2012X5R05106M
4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ
470pF, 16V capacitors Murata GRM1885C1H471JAB01
0.01µF, 50V X7R capacitors Murata GRM188R71H103KA01
4.7µF, 16V X5R capacitor Murata GRM40-034X5R475k6.3
0.1µF, 10V Y5V capacitor Murata GRM188F51A105
0.1µF, 16V X7R capacitors Murata GRM188R71C104KA01
100pF—OVPIN capacitor
C3–C11
C12, C13
C14, C15
C16–C25
C26–C30, C37
C31
9
2
2
10
6
1
C32, C34, C36
C33, C35, C43
C38
3
3
1
C39
1
C40, C41, C42
C44
3
1
D1, D2
2
Schottky diodes ON-Semiconductor MBRS340T3
Schottky diodes ON-Semiconductor MBR0520LT1
0.6µH, 27A inductors Panasonic ETQP1H0R6BFX
Upper-power MOSFETs Vishay-Siliconix Si7860DP
Lower-power MOSFETs Vishay-Siliconix Si7886DP
Current-sense resistors, use two 2.7mΩ resistors in parallel, Panasonic ERJM1WSF2M7U
2.2Ω 1% resistors
D3, D4
2
L1, L2
2
Q1, Q3
2
Q2, Q4
2
R1, R2
4
R3, R13
R4
2
2
7.5kΩ 1% resistor
R5, R6
2
1kΩ 1% resistors
R
IN
1
4.99kΩ 1% resistor
R
f
1
37.4kΩ 1% resistor
R11
R12
RA
RB
RH
RL
1
10kΩ 1% resistor
1
10kΩ 1% resistor
1
See the Overvoltage Protection (MAX5067) section
See the Overvoltage Protection (MAX5067) section
See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections
See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections
Open circuit
1
1
1
RX
1
Table 2. Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.murata.com
Murata
770-436-1300
602-244-6600
714-373-7939
847-803-6100
1-800-551-6933
770-436-3030
602-244-3345
714-373-7183
847-390-4405
619-474-8920
ON Semiconductor
Panasonic
www.on-semi.com
www.panasonic.com
www.tcs.tdk.com
www.vishay.com
TDK
Vishay-Siliconix
______________________________________________________________________________________ 25
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
all these issues when determining the number of phases
necessary for the voltage regulator application.
MAX5065/MAX5067 limits the maximum peak inductor
current and prevents the inductor from saturating.
Choose an inductor with a saturating current greater
than the worst-case peak inductor current. Use the fol-
lowing equation to determine the worst-case inductor
current for each phase:
Inductor Selection
The switching frequency per phase, peak-to-peak rip-
ple current in each phase, and allowable ripple at the
output determine the inductance value.
Selecting higher switching frequencies reduces the
inductance requirement, but at the cost of lower efficien-
cy. The charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs create switching
losses. The situation worsens at higher input voltages,
since switching losses are proportional to the square of
input voltage. Use 500kHz per phase for VIN = +5V and
250kHz or less per phase for VIN > +12V.
0.051V ∆I
L
(12)
I
=
+
L_PEAK
R
2
SENSE
where RSENSE is the sense resistor in each phase.
Switching MOSFETs
When choosing a MOSFET for voltage regulators,
consider the total gate charge, RDS(ON), power dissipa-
tion, and package thermal impedance. The product of
the MOSFET gate charge and on-resistance is a figure of
merit, with a lower number signifying better performance.
Choose MOSFETs optimized for high-frequency switch-
ing applications.
Although lower switching frequencies per phase increase
the peak-to-peak inductor ripple current (∆IL), the ripple
cancellation in the multiphase topology reduces the input
and output capacitor RMS ripple current.
Use the following equation to determine the minimum
inductance value:
The average gate-drive current from the MAX5065/
MAX5067 output is proportional to the total capacitance it
drives from DH1, DH2, DL1, and DL2. The power dissi-
pated in the MAX5065/MAX5067 is proportional to the
input voltage and the average drive current. See the VIN,
section to determine the maximum total gate
charge allowed from all the driver outputs combined.
The gate charge and drain capacitance (CV2) loss, the
cross-conduction loss in the upper MOSFET due to
finite rise/fall time, and the I2R loss due to RMS current
in the MOSFET RDS(ON) account for the total losses in
the MOSFET. Estimate the power loss (PDMOS_) in the
high-side and low-side MOSFETs using the following
equations:
V
− V
× V
OUT
(
)
INMAX
OUT
(10)
L
=
MIN
V
× f
× ∆I
IN SW
L
VCC, V
DD
Choose ∆IL equal to about 40% of the output current
per phase. Since ∆IL affects the output-ripple voltage,
the inductance value may need minor adjustment after
choosing the output capacitors for full-rated efficiency.
Choose inductors from the standard high-current,
surface-mount inductor series available from various
manufacturers. Particular applications may require cus-
tom-made inductors. Use high-frequency core material
for custom inductors. High ∆IL causes large peak-to-peak
flux excursion increasing the core losses at higher fre-
quencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance
and even makes the use of planar inductors possible.
The advantages of using planar magnetics include low-
profile design, excellent current-sharing between phas-
es due to the tight control of parasitics, and low cost.
(13)
PD
= Q × V × f
+
(
(
)
MOS−HI
×I
G
DD SW
V
× t + t × f
)
IN OUT
R
F
SW
2
+1.4R
DS(ON)
×I
RMS−HI
4
where QG, RDS(ON), tR, and tF are the upper-switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively.
For example, calculate the minimum inductance at
VIN(MAX) = +13.2V, VOUT = +1.8V, ∆IL = 10A, and fSW
250kHz:
=
D
3
2
2
(14)
I
=
I
+I
+I ×I
PK
×
DC
RMS−HI
DC PK
(
)
13.2 −1.8 ×1.8
(
)
(11)
L
=
= 0.6µH
MIN
13.2 × 250k ×10
where D = VOUT/VIN, IDC = (IOUT - ∆IL)/2 and IPK
=
(IOUT + ∆IL)/2
The average-current-mode control feature of the
26 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Input Capacitors
PD
= Q × V × f
+
(
)
MOS−LO
G
DD SW
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. Increasing the number of phases increas-
es the effective switching frequency and lowers the
peak-to-average current ratio, yielding a lower input
capacitance requirement.
(15)
2
2 × C
× V
3
× f
2
OSS
IN SW
+1.4R
×I
RMS−LO
DS(ON)
where C
is the MOSFET drain-to-source capacitance.
OSS
1−D
(
)
2
2
(16)
I
=
I
+I
+I ×I
PK
×
DC
RMS−LO
DC PK
(
)
3
The input ripple is comprised of ∆VQ (caused by the
capacitor discharge) and ∆VESR (caused by the ESR of
the capacitor). Use low-ESR ceramic capacitors with
high-ripple-current capability at the input. Assume the
contributions from the ESR and capacitor discharge are
equal to 30% and 70%, respectively. Calculate the
input capacitance and ESR required for a specified rip-
ple using the following equation:
For example, from the typical specifications in the
Applications Information section with VOUT = +1.8V, the
high-side and low-side MOSFET RMS currents are 9.9A
and 24.1A, respectively. Ensure that the thermal imped-
ance of the MOSFET package keeps the junction tem-
perature at least 25°C below the absolute maximum
rating. Use the following equation to calculate maxi-
mum junction temperature:
∆V
(
)
ESR
ESR
=
IN
(17)
T = PD
J
x θ
+ T
J-A A
MOS
(18)
I
∆I
L
OUT
N
+
2
I
OUT
N
∆V × f
×D 1−D
(
)
Table 3. Peak-to-Peak Output Ripple
Current Calculations
(19)
C
=
IN
Q
SW
NUMBER OF
PHASES (N)
DUTY
CYCLE (D)
where IOUT is the total output current of the multiphase
converter and N is the number of phases.
EQUATION FOR ∆I
P-P
For example, at VOUT = +1.8V, the ESR and input
capacitance are calculated for the input peak-to-peak
ripple of 100mV or less yielding an ESR and capaci-
tance value of 1mΩ and 200µF.
V (1−2D)
O
∆I=
2
2
4
4
4
6
< 50%
> 50%
L × f
SW
V
− V 2D−1
)(
(
)
IN
O
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple volt-
age, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
∆I=
L × f
SW
V (1− 4D)
O
∆I=
0 to 25%
25% to 50%
> 50%
L × f
SW
In multiphase converter design, the ripple currents from
the individual phases cancel each other and lower the
ripple current. The degree of ripple cancellation
depends on the operating duty cycle and the number of
phases. Choose the right equation from Table 3 to calcu-
V (1−2D)(4D−1)
O
∆I=
∆I=
2×D×L × f
SW
V (2D−1)(3− 4D)
O
late the peak-to-peak output ripple (∆I ) for a given
P-P
D×L × f
SW
duty cycle of two-, four-, and six-phase converters. The
maximum ripple cancellation occurs when NPH = K / D.
V (1− 6D)
O
∆I=
< 17%
L × f
SW
______________________________________________________________________________________ 27
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (tRESPONSE) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Calculate the maximum reverse current based on V
the reverse-current-limit threshold, and the current-sense
resistor.
,
CLR
2× V
CLR
I
=
REVERSE
(24)
R
SENSE
where I
verter.
is the total reverse current into the con-
REVERSE
Compensation
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5065/MAX5067 use
an average-current-mode control scheme to regulate
the output voltage (Figure 4). IPHASE1 and IPHASE2 are
the inner average current loops. The VEA output pro-
vides the controlling voltage for these current sources.
The inner current loop absorbs the inductor pole reduc-
ing the order of the outer voltage loop to that of a sin-
gle-pole system.
∆V
ESR
(20)
ESR
=
OUT
I
STEP
A resistive feedback around the VEA provides the best
possible response, since there are no capacitors to
I
× t
STEP
RESPONSE
(21)
C
=
OUT
charge and discharge during large-signal excursions, R
F
∆V
Q
and R determine the VEA gain. Use the following equa-
IN
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
tion to calculate the value for RF:
I
× R
IN
OUT
(25)
R
=
F
N× G × ∆V
C
OUT
Current Limit
The average-current-mode control technique of the
MAX5065/MAX5067 accurately limits the maximum out-
put current per phase. The MAX5065/MAX5067 sense
the voltage across the sense resistor and limit the peak
inductor current (IL-PK) accordingly. The ON cycle ter-
minates when the current-sense voltage reaches 45mV
(min). Use the following equation to calculate maximum
current-sense resistor value:
0.05
G
=
(26)
C
R
S
where GC is the current-loop transconductance and N
is number of phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid sub-harmonic oscillations
similar to those in peak current-mode control with insuffi-
cient slope compensation. Use the following equation to
0.045
R
=
SENSE
(22)
I
OUT
N
−3
calculate the resistor RCF
:
2.5×10
(23)
PD =
R
R
SENSE
2
2× f ×L ×10
(27)
SW
R
≤
where PDR is the power dissipation in sense resistors.
Select 5% lower value of RSENSE to compensate for any
parasitics associated with the PC board. Also, select a
non inductive resistor with the appropriate wattage rating.
CF
V
×R
OUT
SENSE
For example, the maximum RCF is 12kΩ for RSENSE
1.35mΩ.
=
CCF provides a low-frequency pole while RCF provides a
midband zero. Place a zero at fZ to obtain a phase bump
at the crossover frequency. Place a high-frequency pole
Reverse Current Limit
The MAX5065/MAX5067 limit the reverse current when
BUS
V
is higher than the preset output voltage.
28 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
(fP) at least a decade away from the crossover frequency
to achieve maximum phase margin.
7) Avoid long traces between the VCC bypass capaci-
tors, driver output of the MAX5065/MAX5067,
MOSFET gates and PGND pin. Minimize the loop
formed by the VCC bypass capacitors, bootstrap
diode, bootstrap capacitor, MAX5065/MAX5067,
and upper MOSFET gate.
Use the following equations to calculate CCF and CCFF
:
1
C
=
(28)
CF
2× π × f ×R
Z
CF
8) Place the bank of output capacitors close to the load.
1
9) Distribute the power components evenly across the
board for proper heat dissipation.
C
=
(29)
CFF
2× π × f ×R
P
CF
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
PC Board Layout
Use the following guidelines to layout the switching
voltage regulator:
11) Use at least 4oz copper to keep the trace induc-
tance and resistance to a minimum. Thin copper PC
boards can compromise efficiency since high cur-
rents are involved in the application. Also, thicker
copper conducts heat more effectively, thereby
reducing thermal impedance.
1) Place the VIN and VCC bypass capacitors close to
the MAX5065/MAX5067.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
Chip Information
TRANSISTOR COUNT: 5451
3) Keep short the current loop from the lower-switch-
ing MOSFET, inductor, and output capacitor.
PROCESS: BiCMOS
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative termi-
nal of the input-filter capacitor.
Selector Guide
6) Run the current-sense lines CS+ and CS- very
close to each other to minimize the loop area.
Similarly, run the remote-voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
PART
MAX5065 Adjustable +0.6V to +3.3V
Adjustable +0.8V to +3.3V with OVP, PGOOD,
Phase Failure Detector
OUTPUT
MAX5067
______________________________________________________________________________________ 29
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Pin Configurations
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
CSP2
CSN2
CLKIN
CLKOUT
BST2
DH2
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
N.C.
DH2
LX2
DL2
PGND
IN
N.C.
N.C.
1
2
33
32
31
30
29
28
27
26
PHASE
PLLCMP
CLP2
N.C.
3
N.C.
4
MAX5067
LX2
SGND
OVPIN
CLP1
5
MAX5065
SGND
DL2
6
CLP1
PGND
IN
V
CC
7
SENSE+
SENSE-
V
DD
8
OVPOUT
PGOOD
SENSE+
SENSE-
V
CC
9
25 DL1
24 LX1
23 DH1*
DL1
LX1
DH1
BST1
EN
DIFF 10
EAN 11
10
11
EAOUT 12
CSP1 13
CSN1 14
12 13 14 15 16 17 18 19 20 21 22
44 THIN QFN*
28 SSOP
*CONNECT THE THIN QFN EXPOSED PAD TO SGND GROUND PLANE.
30
_____________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
2
1
INCHES
MILLIMETERS
MAX
MAX
1.99
0.21
0.38
0.20
DIM
A
MIN
0.068
MIN
1.73
0.05
0.25
0.09
INCHES
MAX
MILLIMETERS
MAX
6.33
6.33
7.33
MIN
MIN
6.07
6.07
7.07
8.07
N
0.078
14L
16L
20L
D
D
D
D
D
A1
B
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
0.002 0.008
0.010 0.015
0.004 0.008
C
8.33 24L
E
H
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
D
0.397 0.407 10.07 10.33
28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
______________________________________________________________________________________ 31
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
DALLAS
SEMICONDUCTOR
A
A1
A2
PROPRIETARYINFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0144
C
2
DALLAS
SEMICONDUCTOR
PROPRIETARYINFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0144
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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