MAX5066EUI+ [MAXIM]
Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, BICMOS, PDSO28, 4.40 MM, MO-153AET, TSSOP-28;
| 型号： | MAX5066EUI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, BICMOS, PDSO28, 4.40 MM, MO-153AET, TSSOP-28 信息通信管理 开关 光电二极管 |
| 文件： | 总22页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3661; Rev 1; 8/05
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
General Description
Features
The MAX5066 is a two-phase, configurable single- or
dual-output buck controller with an input voltage range of
4.75V to 5.5V or from 5V to 28V. Each phase of the
MAX5066 is designed for 180° operation. A mode pin
allows for a dual-output supply or connecting two phases
together for a single-output, high-current supply. Each
output channel of the MAX5066 drives n-channel
MOSFETs and is capable of providing more than 25A of
load current. The MAX5066 uses average current-mode
control with a switching frequency up to 1MHz per phase
where each phase is 180° out of phase with respect to
the other. Out-of-phase operation results in significantly
reduced input capacitor ripple current and output volt-
age ripple in dual-phase, single-output voltage applica-
tions. Each buck regulator output has its own high-
performance current and voltage-error amplifier that can
be compensated for optimum output filter L-C values and
transient response.
♦ 4.75V to 5.5V or 5V to 28V Input
♦ Dual-Output Synchronous Buck Controller
♦ Configurable for Two Separate Outputs or One
Single Output
♦ Each Output is Capable of Up to 25A Output
Current
♦ Average Current-Mode Control Provides Accurate
Current Limit
♦ 180° Interleaved Operation Reduces Size of Input
Filter Capacitors
♦ Limits Reverse Current Sinking When Operated in
Parallel Mode
♦ Each Output is Adjustable from 0.61V to 5.5V
♦ Independently Programmable Adaptive Voltage
Positioning
The MAX5066 offers two enable inputs with accurate
turn-on thresholds to allow for output voltage sequencing
of the two outputs. The device’s switching frequency can
be programmed from 100kHz to 1MHz with an external
resistor. The MAX5066 can be synchronized to an exter-
nal clock. Each output voltage is adjustable from 0.61V to
5.5V. Additional features include thermal shutdown, “hic-
cup mode” short-circuit protection. Use the MAX5066
with adaptive voltage positioning for applications that
require a fast transient response, or accurate output volt-
age regulation.
♦ Independent Shutdown for Each Output
♦ 100kHz to 1MHz per Phase Programmable
Switching Frequency
♦ Oscillator Frequency Synchronization from
200kHz to 2MHz
♦ Hiccup Mode Overcurrent Protection
♦ Overtemperature Shutdown
♦ Thermally Enhanced 28-Pin TSSOP Package
Capable of Dissipating 1.9W
The MAX5066 is available in a thermally enhanced 28-pin
TSSOP package capable of dissipating 1.9W. The device
is rated for operation over the -40°C to +85°C extended,
or -40°C to +125°C automotive temperature range.
♦ Operates Over -40°C to +85°C or -40°C to +125°C
Temperature Range
Ordering Information
Applications
PART
TEMP RANGE
-40°C to +85°C
-40°C to +125°C
PIN-PACKAGE
28 TSSOP-EP*
28 TSSOP-EP*
High-End Desktop Computers
MAX5066EUI
MAX5066AUI
Graphics Cards
Networking Systems
*Exposed Pad
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
RAID Systems
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ABSOLUTE MAXIMUM RATINGS
IN to AGND.............................................................-0.3V to +30V
BST_ to AGND........................................................-0.3V to +35V
REF Continuous Output Current ........................................200µA
Continuous Power Dissipation (T = +70°C)
A
DH_ to LX_ ....................................-0.3V to (V
- V ) + 0.3V
28-Pin TSSOP (derate 23.8mW/°C above +70°C) .....1904mW
BST_
LX_
DL_ to PGND..............................................-0.3V to (V
+ 0.3V)
Package Thermal Resistance (θ ) ...................................2°C/W
Operating Temperature Ranges
MAX5066EUI ...................................................-40°C to +85°C
MAX5066AUI .................................................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
JC
BST_ to LX_ ..............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
V
DD
AGND to PGND.....................................................-0.3V to +0.3V
REG, RT/CLKIN, CSP_, CSN_ to AGND ..................-0.3V to +6V
All Other Pins to AGND ............................-0.3V to (V
REG Continuous Output Current
+ 0.3V)
REG
(Limited by Power Dissipation, No Thermal or Short-Circuit
Protection).........................................................................67mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
IN
REG
DD
EN_
A
J
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
5
28
5.5
20
Input Voltage Range
V
V
IN
IN and REG shorted together for +5V
operation
4.75
Quiescent Supply Current
I
f
= 500kHz, DH_, DL_ = open
4
mA
IN
OSC
STARTUP/INTERNAL REGULATOR OUTPUT (REG)
REG Undervoltage Lockout
Hysteresis
UVLO
V
rising
4.0
4.15
200
4.5
V
mV
V
REG
V
HYST
REG Output Accuracy
REG Dropout
V
V
= 5.8V to 28V, I
= 0 to 65mA
4.75
5.10
5.30
0.5
IN
IN
SOURCE
< 5.8V, I
= 60mA
V
SOURCE
INTERNAL REFERENCE
Internal Reference Voltage
V
V
EAN_ connected to EAOUT_ (Note 2)
V = V = 4.75V to 5.5V or V = 5V to
IN
0.6135
3.3
V
EAN_
EAN_
Internal Reference Voltage
Accuracy
REG
IN
-0.9
+0.9
%
28V, EAN_ connected to EAOUT_ (Note 2)
EXTERNAL REFERENCE VOLTAGE OUTPUT (REF)
Accuracy
V
I
= 100µA
3.23
3.2
3.37
3.4
V
V
REF
REF
REF
Load Regulation
MOSFET DRIVERS
I
= 0 to 200µA
p-Channel Output Driver
Impedance
R
R
1.35
0.45
4
Ω
Ω
ON_P
n-Channel Output Driver
Impedance
1.35
ON_N
Output Driver Source Current
Output Driver Sink Current
Nonoverlap Time (Dead Time)
I
I
, I
2.5
8
A
A
DH_ DL_
, I
DH_ DL_
t
C
or C = 5nF
DL_
30
ns
NO
DH_
2
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
IN
REG
DD
EN_
A
J
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
1MHz (max)
switching
frequency per
phase
R
R
= 12.4kΩ
= 127kΩ
1000
100
RT
Switching Frequency
f
kHz
SW
RT
f
f
= 250kHz nominal, R = 50kΩ
-7.5
-10
+7.5
+10
SW
RT
Switching Frequency Accuracy
RT/CLKIN Output Voltage
%
V
= 1MHz nominal, R = 12.4kΩ
SW
RT
V
1.225
0.5
RT/CLKIN
RT/CLKIN Current Sourcing
Capability
I
mA
RT/CLKIN
RT/CLKIN Logic-High Threshold
RT/CLKIN Logic-Low Threshold
RT/CLKIN High Pulse Width
V
2.4
V
V
RT/CLKIN_H
RT/CLKIN_L
V
0.8
t
30
ns
RT/CLKIN
RT/CLKIN Synchronization
Frequency Range
f
200
2000
kHz
RT/CLKIN
CURRENT LIMIT
Average Current-Limit Threshold
Reverse Current-Limit Threshold
V
V
V
- V
- V
20.4
22.5
24.75
-0.1
mV
mV
CL_
CSP_
CSP_
CSN_
V
-3.13
-1.63
RCL_
CSN_
Cycle-by-Cycle Current-Limit
Threshold
V
V
- V
52.5
260
mV
ns
CLpk_
CSP_
CSN_
Cycle-by-Cycle Current-Limit
Response Time
t
R
DIGITAL FAULT INTEGRATION (DF_)
Number of Switching Cycles to
Shutdown in Current-Limit
Clock
cycles
NS
32,768
DF_
Number of Switching Cycles to
Recover from Shutdown
Clock
cycles
NR
524,288
DF_
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
R
1.9835
kΩ
CS_
V
V
= V
= 5V to 10V
= 4.75V to 5.5V or
REG
IN
IN
-0.3
-0.3
+3.6
+5.5
V
Common-Mode Range
V
CMR(CS)
V
= 7V to 28V
V
IN
Input Offset Voltage
Amplifier Gain
V
100
36
4
µV
OS(CS)
A
V/V
MHz
V(CS)
-3dB
-3dB Bandwidth
f
V
V
= 5.5V, sinking
= 0V, sourcing
120
30
CSP_
CSP_
CSP_ Input Bias Current
I
µA
CSA(IN)
_______________________________________________________________________________________
3
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
IN
REG
DD
EN_
A
J
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-ERROR AMPLIFIER (CEA_)
Transconductance
Open-Loop Gain
g
550
50
µS
dB
M
A
No load
VOL(CEA)
VOLTAGE ERROR AMPLIFIER (EAOUT_)
Open-Loop Gain
A
70
3
dB
MHz
nA
VOL(EA)
Unity-Gain Bandwidth
EAN_ Input Bias Current
f
UGEA
I
V
= 2.0V
EAN_
100
BIAS(EA)
Error Amplifier Output Clamping
High Voltage
V
CLMP_HI
(EA)
With respect to V
With respect to V
1.14
V
V
CM
CM
Error Amplifier Output Clamping
Low Voltage
V
CLMP_LO
(EA)
-0.234
EN_ INPUTS
EN_ Input High Voltage
EN_ Hysteresis
V
EN rising
1.204
-1
1.222
0.05
1.240
+1
ENH
V
EN_ Input Leakage Current
MODE INPUT
I
µA
EN
MODE Logic-High Threshold
MODE Logic-Low Threshold
MODE Input Pulldown
THERMAL SHUTDOWN
Thermal Shutdown
V
2.4
V
V
MODE_H
V
0.8
MODE_L
I
5
µA
PULLDWN
T
160
10
SHDN
°C
Thermal Shutdown Hysteresis
T
HYST
Note 1: The device is 100% production tested at T = +85°C (MAX5066EUI) and T = T = +125°C (MAX5066AUI). Limits at -40°C
A
A
J
and +25°C are guaranteed by design.
Note 2: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage
accuracy must include external resistor-divider tolerances.
4
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Typical Operating Characteristics
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f = 500kHz per phase.)
SW
A
IN
OUT1
OUT2
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
OSCILLATOR FREQUENCY vs. R
(V = 5V)
IN
(V = 12V)
IN
T
10,000
1000
100
16
14
12
10
8
16
14
12
10
8
C
= C = 0
DL
f
= 1MHz
DH
C
= C = 0
C
= C = 0
f
= 1MHz
SW
SW
DH
DL
DH
DL
f
= 500kHz
SW
f
= 500kHz
SW
f
= 250kHz
SW
f
= 250kHz
SW
6
6
f
= 125kHz
SW
f
= 125kHz
SW
4
4
2
2
10
0
0
0
100 200 300 400 500 600 700 800 900 1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
R (kΩ)
T
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. OSCILLATOR FREQUENCY
SUPPLY CURRENT
vs. DRIVER LOAD CAPACITANCE
(V = 24V)
IN
16
14
12
10
8
14
13
12
11
10
9
100
90
80
70
60
50
40
30
20
10
0
C
= C = 0
DL
f
= 1MHz
C
= C = C
DL
C
= C = 0
DH
SW
LOAD
DH
DH_
DL_
f
= 500kHz
SW
V
= 12V
IN
V
= 24V
IN
f
= 250kHz
SW
6
f
= 125kHz
SW
4
8
V
= 5V
IN
2
7
0
6
-40 -25 -10
5
20 35 50 65 80 95 110 125
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
0
5
10
15
20
25
30
TEMPERATURE (°C)
C
(nF)
LOAD
REG LOAD REGULATION
REG LINE REGULATION
REF LOAD REGULATION
5.10
5.05
5.00
4.95
4.90
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
3.305
3.300
3.295
3.290
3.285
I
= 0
REG
V
= 24V
IN
V
= 24V
IN
V
= 12V
IN
V
= 12V
IN
V
= 5.5V
V
= 5V
IN
IN
I
= 60mA
REG
0
10 20 30 40 50 60 70 80 90 100
(mA)
5
7
9
11 13 15 17 19 21 23
(V)
0
100 200 300 400 500 600 700 800
(µA)
I
V
I
REF
REG
IN
_______________________________________________________________________________________
5
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f
= 500kHz per phase.)
A
IN
OUT1
OUT2
SW
DRIVER RISE TIME
vs. LOAD CAPACITANCE
DRIVER FALL TIME
vs. LOAD CAPACITANCE
REF LINE REGULATION
3.303
3.302
3.301
3.300
3.299
3.298
3.297
3.296
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
DH
I
= 0
REF
DH
DL
DL
I
= 200µA
REF
0
0
5
9
11 13 15 17 19 21 23
(V)
0
2
4
6
8
10 12 14 16 18 20 22
2
4
6
8
10 12 14 16 18 20 22
7
V
C
(nF)
C
(nF)
IN
LOAD
LOAD
HIGH-SIDE DRIVER RISE TIME
(V = 12V, C = 10nF)
HIGH-SIDE DRIVER FALL TIME
(V = 12V, C = 10nF)
IN
LOAD
IN
LOAD
MAX5066 toc11
MAX5066 toc12
DH_
2V/div
DH_
2V/div
20ns/div
20ns/div
LOW-SIDE DRIVER RISE TIME
(V = 12V, C = 10nF)
IN
LOAD
MAX5066 toc13
DL_
2V/div
20ns/div
6
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f
= 500kHz per phase.)
SW
A
IN
OUT1
OUT2
LOW-SIDE DRIVER FALL TIME
(V = 12V, C = 10nF)
OUT1/OUT2 OUT-OF-PHASE WAVEFORMS
(V = 0.8V, V = 1.3V)
IN
LOAD
OUT1
OUT2
MAX5066 toc14
MAX5066 toc15
LX1
10V/div
OUT1
100mV/div
DL_
2V/div
LX2
10V/div
OUT2
100mV/div
20ns/div
10µs/div
SHORT-CIRCUIT CURRENT WAVEFORMS
TURN-ON/-OFF WAVEFORMS
(V = 5V)
(I
= I
= 10A)
IN
OUT1 OUT2
MAX5066 toc17
MAX5066 toc16
V
OUT1
I
OUT1
1V/div
10A/div
EN1
5V/div
V
OUT2
1V/div
I
OUT2
10A/div
EN2
5V/div
200ms/div
2ms/div
_______________________________________________________________________________________
7
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Pin Description
PIN
NAME
FUNCTION
Current-Sense Differential Amplifier Negative Input for Output2. Connect CSN2 to the negative
terminal of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified
1
CSN2
by the current-sense amplifier (A
= 36V/V).
V(CS)
Current-Sense Differential Amplifier Positive Input for Output2. Connect CSP2 to the positive terminal
of the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the
2
3
CSP2
current-sense amplifier (A
= 36V/V).
V(CS)
Voltage Error-Amplifier Output2. Connect to an external gain-setting feedback resistor. The error-
amplifier gain determines the output voltage load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT2 to EAN2. A resistive
network results in a drooped output voltage regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
EAOUT2
Voltage Error-Amplifier Inverting Input for Output2. Connect a resistive divider from V
to EAN2 to
OUT2
AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A
resistive network results in a drooped output-voltage-regulation characteristic. An integrator
configuration results in very tight output-voltage regulation (see the Adaptive Voltage Positioning
section).
4
EAN2
Current-Error Amplifier Output2. Compensate the current loop by connecting an R-C network from
CLP2 to AGND.
5
6
CLP2
REF
3.3V Reference Output. Bypass REF to AGND with a minimum 0.1µF ceramic capacitor. REF can
source up to 200µA for external loads.
External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to
AGND to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency
synchronization.
7
8
RT/CLKIN
AGND
Analog Ground
Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck
regulator. When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see
Figure 1) and the device operates as a two-output, out-of-phase buck regulator. When MODE is
connected to REG (logic high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.
9
MODE
CLP1
Current-Error Amplifier Output1. Compensate the current loop by connecting an R-C network from
CLP1 to AGND.
10
Voltage Error Amplifier Inverting Input for Output1. Connect a resistive divider from V
to EAN1 to
OUT1
regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output voltage regulation (see the Adaptive Voltage Positioning section).
11
EAN1
Voltage Error Amplifier Output1. Connect to an external gain-setting feedback resistor. The error
amplifier gain determines the output-voltage-load regulation for adaptive voltage positioning. This
output also serves as the compensation network connection from EAOUT1 to EAN1. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration
results in very tight output-voltage regulation (see the Adaptive Voltage Positioning section).
12
13
EAOUT1
CSP1
Current-Sense Differential Amplifier Positive Input for Output1. Connect CSP1 to the positive terminal
of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the
current-sense amplifier (A
= 36V/V).
V(CS)
8
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Pin Description (continued)
PIN
NAME
FUNCTION
Current-Sense Differential Amplifier Negative Input for Output1. Connect CSN1 to the negative
terminal of the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified
14
CSN1
by the current-sense amplifier (A
= 36V/V).
V(CS)
Output 1 Enable. A logic-low shuts down channel 1’s MOSFET drivers. EN1 can be used for output
sequencing.
15
EN1
Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST1 and LX1.
16
17
18
19
BST1
DH1
LX1
High-Side Gate Driver Output1. DH1 drives the gate of the high-side MOSFET.
External inductor connection and source connection for the high-side MOSFET for Output1. LX1 also
serves as the return terminal for the high-side MOSFET driver.
DL1
Low-Side Gate Driver Output1. Gate driver output for the synchronous MOSFET.
Supply Voltage for Low-Side Drivers. REG powers V . Connect a parallel combination of 0.1µF and
DD
1µF ceramic capacitors from V
to PGND and a 1Ω resistor from V to REG to filter out the high-
20
V
DD
DD
DD
peak currents of the driver from the internal circuitry.
Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias
circuitry. Bypass REG to AGND with a 4.7µF ceramic capacitor.
21
22
23
24
25
26
27
REG
IN
Supply Voltage Connection. Connect IN to a 5V to 28V input supply.
Power Ground. Source connection for the low-side MOSFET. Connect V ’s bypass capacitor returns
DD
to PGND.
PGND
DL2
Low-Side Gate Driver Output2. Gate driver for the synchronous MOSFET.
External inductor connection and source connection for the high-side MOSFET for Output2. Also
serves as the return terminal for the high-side MOSFET driver.
LX2
DH2
BST2
High-Side Gate Driver Output2. DH2 drives the gate of the high-side MOSFET.
Boost Flying Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST2 and LX2.
Output 2 Enable. A logic-low shuts down channel 2’s MOSFET drivers. EN2 can be used for output
sequencing.
28
EP
EN2
EP
Exposed Pad. Connect exposed pad to ground plane.
(EAOUT1 or EAOUT2) that connects to the positive
Detailed Description
input of the transconductance amplifier (CA1 or CA2) is
The MAX5066 switching power-supply controller can
be configured in two ways. With the MODE input high, it
operates as a single-output, dual-phase, step-down
switching regulator where each output is 180° out of
phase. With the MODE pin connected low, the
MAX5066 operates as a dual-output, step-down switch-
ing regulator. The average current-mode control topolo-
gy of the MAX5066 offers high-noise immunity while
having benefits similar to those of peak current-mode
control. Average current-mode control has the intrinsic
ability to accurately limit the average current sourced
by the converter during a fault condition. When a fault
condition occurs, the error amplifier output voltage
clamped thus limiting the output current.
The MAX5066 contains all blocks necessary for two
independently regulated average current-mode PWM
regulators. It has two voltage error amplifiers (VEA1
and VEA2), two current-error amplifiers (CEA1 and
CEA2), two current-sensing amplifiers (CA1 and CA2),
two PWM comparators (CPWM1 and CPWM2), and dri-
vers for both low- and high-side power MOSFETs (see
Figure 1). Each PWM section is also equipped with a
pulse-by-pulse, current-limit protection and a fault inte-
gration block for hiccup protection.
_______________________________________________________________________________________
9
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
13 CSP1
CLP1
10
CA1
CSN1
14
DF1 AND
HICCUP
LOGIC
EAOUT1 12
EAN1
11
CEA1
BST1
16
VEA1
CPWM1
17 DH1
UVLO
2V
P-P
RAMP
22
V
= 5V
IN
REG
CONTROL
AND DRIVER
LOGIC 1
LX1
18
V
20
19
DD
FOR INTERNAL
BIASING
21
REG
DL1
CEN1
EN1 15
0°
1.225V
THERMAL
SHUTDOWN
6
REF
V
= 3.3V
UV33
REF
OSCILLATOR
AND PHASE
SPLITTER
EXTERNAL FREQUENCY SYNC
RT/CLKIN
7
27 BST2
1.225V
V
= 0.61V
180°
INTREF
CEN2
DH2
LX2
26
25
EN2
28
8
CONTROL
AND DRIVER
LOGIC 2
2V
RAMP
P-P
V
DD
AGND
24 DL2
VEA2
MUX
CPWM2
23
PGND
EAN2
4
3
9
5
CEA2
EAOUT2
MODE
CLP2
DF2 AND
HICCUP
LOGIC
2
1
CSP2
CSN2
CA2
Figure 1. Block Diagram
Two enable comparators (CEN1 and CEN2) are avail-
able to control and sequence the two PWM sections
through the enable (EN1 or EN2) inputs. An oscillator,
with an externally programmable frequency generates
two clock pulse trains and two ramps for both PWM
sections. The two clocks and the two ramps are 180°
out of phase with each other.
necessary to provide for the MAX5066’s internal circuit-
ry and the power for the external MOSFET’s gate dri-
vers. A low-current linear regulator (REF) provides a
precise 3.3V reference output and is capable of driving
loads of up to 200µA. Internal UVLO circuitry ensures
that the MAX5066 starts up only when V
and V
REF
REG
are at the correct voltage levels to guarantee safe oper-
ation of the IC and of the power MOSFETs.
A linear regulator (REG) generates the 5V to supply the
device. This regulator has the output-current capability
10 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Finally, a thermal-shutdown feature protects the device
during thermal faults and shuts down the MAX5066
when the die temperature exceeds +160°C.
diodes D1 and D2 (see Figure 6). Connect a 0.1µF
ceramic capacitor between BST_ and LX_.
Minimize the trace inductance from BST_ and V
to
DD
rectifier diodes, D1 and D2, and from BST_ and LX_ to
the boost capacitors, C8 and C9 (see Figure 6). This is
accomplished by using short, wide trace lengths.
Dual-Output/Dual-Phase Select (MODE)
The MAX5066 can operate as a dual-output indepen-
dently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1) and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic high), VEA2 is dis-
connected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX5066 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold monitors V
and is inter-
REG
nally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates “chattering” during
startup. Most of the internal circuitry, including the
oscillator, turns on when V
reaches 4.5V. The
REG
MAX5066 draws up to 4mA (typ) of current before
reaches the UVLO threshold.
Supply Voltage Connections (V /V
)
IN REG
The MAX5066 accepts a wide input voltage range at IN
of 5V to 28V. An internal linear regulator steps down V
V
REG
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the current-
error amplifier output limits the maximum current avail-
able to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
IN
to 5.1V (typ) and provides power to the MAX5066. The
output of this regulator is available at REG. For V
4.75V to 5.5V, connect IN and REG together externally.
REG can supply up to 65mA for external loads. Bypass
REG to AGND with a 4.7µF ceramic capacitor for high-
frequency noise rejection and stable operation.
=
IN
REG supplies the current for both the MAX5066’s inter-
nal circuitry and for the MOSFET gate drivers (when
connected externally to V ), and can source up to
DD
65mA. Calculate the maximum bias current (I
the MAX5066:
) for
BIAS
Setting the Switching Frequency (f
)
SW
An internal oscillator generates the 180o out-of-phase
clock signals required for both PWM modulators. The
I
= I + f
× (Q
+ Q
+ Q
+ Q
)
BIAS
IN SW
GQ1
GQ2
GQ3 GQ4
oscillator also generates the 2V
voltage ramps nec-
P-P
essary for the PWM comparators. The oscillator fre-
quency can be set from 200kHz to 2MHz by an external
where I is the quiescent supply current into IN (4mA,
IN
typ), Q
, Q
, Q
, Q
are the total gate
GQ4
GQ1
GQ2
GQ3
resistor (R ) connected from RT/CLKIN to AGND (see
T
charges of MOSFETs Q1 through Q4 at V
= 5V (see
GS
Figure 6). The equation below shows the relationship
between R and the switching frequency:
T
Figure 6), and f
is the switching frequency of each
SW
individual phase.
10
2.5 ×10
Low-Side MOSFET Driver Supply (V
)
DD
f
=
Hz
OSC
V
is the power input for the low-side MOSFET dri-
R
DD
RT
vers. Connect the regulator output REG externally to
through an R-C lowpass filter. Use a 1Ω resistor
V
where R is in ohms and f
= f
/2.
OSC
DD
RT
SW(PER PHASE)
and a parallel combination of 1µF and 0.1µF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
Use RT/CLKIN as a clock input to synchronize the
MAX5066 to an external frequency (f ). Applying
RT/CLKIN
an external clock to RT/CLKIN allows each PWM section
to work at a frequency equal to f /2. An internal
RT/CLKIN
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
comparator with a 1.6V threshold detects f
. If
RT/CLKIN
f
is present, internal logic switches from the
RT/CLKIN
internal oscillator clock, to the clock present at
RT/CLKIN.
Connect BST1 and BST2 to V
through rectifier
DD
______________________________________________________________________________________ 11
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
loop consists of an inner current loop and an outer volt-
age loop. The inner current loop controls the output
current, while the outer voltage loop controls the output
voltage. The inner current loop absorbs the inductor
pole, reducing the order of the outer voltage loop to
that of a single-pole system. Figure 2 is the block dia-
gram of OUT1’s control loop.
Hiccup Fault Protection
The MAX5066 includes overload fault protection circuit-
ry that prevents damage to the power MOSFETs. The
fault protection consists of two digital fault integration
blocks that enable “hiccuping” under overcurrent con-
ditions. This circuit works as follows: for every clock
cycle the current-limit threshold is exceeded, the fault
integration counter increments by one count. Thus, if
the current-limit condition persists, then the counter
reaches its shutdown threshold in 32,768 counts and
shuts down the external MOSFETs. When the MAX5066
shuts down due to a fault, the counter begins to count
down, (since the current-limit condition has ended),
once every 16 clock cycles. Thus, the device counts
down for 524,288 clock cycles. At this point, switching
resumes. This produces an effective duty cycle of
6.25% power-up and 93.75% power-down under fault
conditions. With a switching frequency set to 250kHz,
power-up and power-down times are approximately
131ms and 2.09s, respectively.
The current loop consists of a current-sense resistor,
R
, a current-sense amplifier (CA1), a current-
SENSE
error amplifier (CEA1), an oscillator providing the carri-
er ramp, and a PWM comparator (CPWM1). The
precision current-sense amplifier (CA1) amplifies the
sense voltage across R
by a factor of 36. The
SENSE
inverting input to CEA1 senses the output of CA1. The
output of CEA1 is the difference between the voltage-
error amplifier output (EAOUT1) and the gained-up volt-
age from CA1. The RC compensation network
connected to CLP1 provides external frequency com-
pensation for the respective CEA1 (see the
Compensation section). The start of every clock cycle
enables the high-side driver and initiates a PWM on-
cycle. Comparator CPWM1 compares the output volt-
age from CEA1 against a 0 to 2V ramp from the
Control Loop
The MAX5066 uses an average current-mode control
topology to regulate the output voltage. The control
CSN1
CSP1
R
C
CF
CF
CA 1
CLP1
C
CFF
V
IN
I
CEA1
L
R
F
R
SENSE
V
OUT1
CPWM1
DRIVE
2V
P-P
R1
R2
VEA1
LOAD
C
OUT
V
= 0.61V
REF
Figure 2. Current and Voltage Loops
12 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
Voltage Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to V
= 0.61V. Set the MAX5066 out-
CM
The outer voltage control loop consists of the voltage-
error amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive volt-
age-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
put voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load the
output of the voltage error amplifier is zero.
Use the equation below to calculate the no load voltage:
⎛
⎞
R
1
V
= 0.6135 × 1+
OUT(NL)
⎜
⎟
R
⎝
⎠
2
Peak-Current Comparator
The voltage at full load is given by:
The peak-current comparator (see Figure 3) monitors
the voltage across the current-sense resistor (R
)
SENSE
⎛
⎞
R
R
1
and provides a fast cycle-by-cycle current limit with a
threshold of 52.5mV. Note that the average current-limit
threshold of 22.5mV still limits the output current during
short-circuit conditions. To prevent inductor saturation,
select an output inductor with a saturation current
specification greater than the average current limit of
V
= 0.6135 × 1+
− ∆V
OUT
OUT(FL)
⎜
⎟
⎝
⎠
2
where ∆V
is the voltage-positioning window
OUT
described in the Adaptive Voltage Positioning section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of out-
put capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
22.5mV/R
. Proper inductor selection ensures that
SENSE
only extreme conditions trip the peak-current compara-
tor, such as a damaged output inductor. The typical
propagation delay of the peak current-limit comparator
is 260ns.
Current-Error Amplifier
The MAX5066 has two dedicated transconductance
current-error amplifiers CEA1 and CEA2 with a typical
g
M
of 550µS and 320µA output sink and source capabil-
ity. The current-error amplifier outputs (CLP1 and CLP2)
serve as the inverting input to the PWM comparators.
CLP1 and CLP2 are externally accessible to provide fre-
quency compensation for the inner current loops (see
C
CFF
, C , and R in Figure 2). Compensate the cur-
CF CF
rent-error amplifier such that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
The internal 0.61V reference in the MAX5066 has a toler-
ance of 0.9%. If we use 0.1% resistors for R and R ,
1
2
we still have another 4% available for the variation in the
output voltage from nominal. This available voltage
range allows us to reduce the total number of output
capacitors to meet a given transient response require-
ment. This results in a voltage-positioning window as
shown in Figure 5.
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the current-
From the allowable voltage-positioning window we can
calculate the value of R from the equation below.
F
error amplifier output to a 2V
ramp. At the start of
P-P
each clock cycle an R-S flip-flop resets and the high-
side drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminat-
ing the on cycle.
I
× R
× 36 × R
SENSE 1
OUT
R
=
F
∆V
OUT
where ∆V
is the allowable voltage-positioning win-
is the sense resistor, 36 is the current-
OUT
dow, R
SENSE
sense amplifier gain, and R is as shown in Figure 4.
1
______________________________________________________________________________________ 13
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
V
DD
PEAK-CURRENT
COMPARATOR
52.5mV
= 36
CLP_
CSP_
CSN_
A
V
g
= 500µS
M
BST_
DH_
LX_
PWM
COMPARATOR
GM
IN
Q
Q
S
R
RAMP
CLK
2 x f (V/S)
SW
DL_
1.225V
PGND
EN_
Figure 3. Current Comparator and MOSFET Driver Logic
V
OUT
V
+ ∆V /2
OUT
CNTR
R
F
V
CNTR
R
R
1
2
EAN_
C
V
- ∆V /2
OUT
OUT
CNTR
LOAD
EAOUT_
V
= 0.61V
REF
NO LOAD
1/2 LOAD
LOAD (A)
FULL LOAD
Figure 4. Voltage Error Amplifier
Figure 5. Defining the Voltage-Positioning Window
output, voltage-regulating applications where the duty
cycle is less than 50%, choose high-side MOSFETs (Q2
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side dri-
vers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capa-
bility of these drivers provides ample drive for the fast
rise and fall times of the switching MOSFETs. Faster rise
and fall times result in reduced switching losses. For low-
and Q4, Figure 6) with a moderate R
and a very
DS(ON)
low gate charge. Choose low-side MOSFETs (Q1 and
Q3, Figure 6) with very low R and moderate gate
DS(ON)
charge. The driver block also includes a logic circuit that
provides an adaptive nonoverlap time (30ns typical) to
14 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
V
IN
C5
10µF
IN
REG
V
R3
DD
D1
1Ω
(100mA, 30V)
22Ω
C2
1µF
C3
0.1µF
C4
4.7µF
BST1
D2
22Ω
(100mA, 30V)
Q2
IRF7821
BST2
Q4
IRF7821
C8
0.1µF
DH1
LX1
L1
0.5µH
C9
0.1µF
R1
DH2
LX2
L2
0.8µH
2mΩ
0.8V/10A
Q1
IRF7832
R2
2mΩ
1.3V/10A
Q3
IRF7832
MAX5066
DL1
D3
C6
680µF
(1A, 30V)
D4
(1A, 30V)
DL2
C7
680µF
PGND
R4
1.74kΩ
CSP1
CSN1
R6
5.11kΩ
CSP2
CSN2
EAN1
EAN2
EAOUT1
R5
4.64kΩ
EAOUT2
R8
29.4kΩ
R7
4.75kΩ
R9
60.4kΩ
MODE
CLP1
V
OR V
REF
REG
R16
100kΩ
C10
15nF
R14
1kΩ
EN1
EN2
C14
0.1µF
C11
120pF
R17
100kΩ
C12
15nF
R15
1kΩ
C15
0.1µF
CLP2
RT/CLKIN
REF
AGND
C13
120pF
R
C1
T
24.9kΩ
0.22µF
EXTERNAL FREQUENCY SYNC
Figure 6. Dual-Output Buck Regulator
______________________________________________________________________________________ 15
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
V
IN
C5
10µF
IN
REG
V
R3
DD
1Ω
D1
(100mA, 30V)
22Ω
C3
0.1µF
C4
4.7µF
C2
1µF
BST1
D2
22Ω
(100mA, 30V)
Q2
IRF7821
BST2
Q4
IRF7821
C8
0.1µF
DH1
LX1
L1
0.8µH
C9
0.1µF
R1
DH2
LX2
L2
0.8µH
2mΩ
1.3V/20A
Q1
IRF7832
R2
2mΩ
Q3
IRF7832
MAX5066
DL1
D3
C6
680µF
(1A, 30V)
D4
DL2
(1A, 30V)
PGND
R4
5.11kΩ
CSP1
CSN1
CSP2
CSN2
EAN1
EAN2
EAOUT1
R5
4.75kΩ
EAOUT2
R8
60.4kΩ
MODE
CLP1
TO REG
V
OR V
REF
REG
R16
100kΩ
C10
15nF
R14
1kΩ
EN1
EN2
C14
0.1µF
C11
120pF
R17
100kΩ
C12
15nF
R15
1kΩ
C15
0.1µF
CLP2
RT/CLKIN
REF
AGND
C13
120pF
R
C1
T
24.9kΩ
0.22µF
EXTERNAL FREQUENCY SYNC
Figure 7. Dual-Phase, Single-Output Buck Regulator
16 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
prevent shoot-through currents during transition. Figure 7
shows the dual-phase, single-output buck regulator.
inductor with a saturating current greater than the
worst-case peak inductor current:
Design Procedures
−3
∆I
2
24.75 × 10
L
I
=
+
L_PEAK
Inductor Selection
The switching frequency per phase, peak-to-peak ripple
current in each phase, and allowable voltage ripple at
the output, determine the inductance value. Selecting
higher switching frequencies reduces the inductance
requirement, but at the cost of lower efficiency due to
the charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs. The situation
worsens at higher input voltages, since capacitive
switching losses are proportional to the square of the
input voltage. Lower switching frequencies on the other
hand will increase the peak-to-peak inductor ripple cur-
R
SENSE
where 24.75mV is the maximum average current-limit
threshold for the current-sense amplifier and R
the sense resistor.
is
SENSE
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, R
, power dissipation, the maximum
DS(ON)
drain-to-source voltage, and package thermal imped-
ance. The product of the MOSFET gate charge and on-
resistance is a figure of merit, with a lower number
signifying better performance. Choose MOSFETs opti-
mized for high-frequency switching applications. The
average gate-drive current from the MAX5066’s output
is proportional to the total capacitance it drives at DH1,
DH2, DL1, and DL2. The power dissipated in the
MAX5066 is proportional to the input voltage and the
average drive current. See the Supply Voltage
rent (∆I ) and therefore increase the MOSFET conduc-
L
tion losses (see the Power MOSFET Selection section for
a detailed description of MOSFET power loss).
When using higher inductor ripple current, the ripple
cancellation in the multiphase topology, reduces the
input and output capacitor RMS ripple current. Use the
following equation to determine the minimum induc-
tance value:
Connection (V /V
) and the Low-Side MOSFET
Drives Supply (V ) sections to determine the maxi-
IN REG
DD
mum total gate charge allowed from all driver outputs
together.
V
(V
− V
)
OUT IN(MAX)
OUT
L =
V
× f
× ∆I
The losses may be broken into four categories: conduc-
tion loss, gate drive loss, switching loss and output loss.
The following simplified power loss equation is true for
both MOSFETs in the synchronous buck-converter:
IN SW L
Choose ∆I to be equal to about 30% of the output cur-
rent per channel. Since ∆I affects the output-ripple volt-
L
L
age, the inductance value may need minor adjustment
after choosing the output capacitors for full-rated efficien-
cy. Choose inductors from the standard high-current, sur-
face-mount inductor series available from various
manufacturers. Particular applications may require cus-
tom-made inductors. Use high-frequency core material
P
=P
+P
+P
+P
LOSS
CONDUCTION
GATEDRIVE
SWITCH OUTPUT
For the low-side MOSFET, the P
term becomes
SWITCH
virtually zero because the body diode of the MOSFET is
conducting before the MOSFET is turned on.
for custom inductors. High ∆I causes large peak-to-peak
L
Tables 1 and 2 describe the different losses and shows
an approximation of the losses during that period.
flux excursion increasing the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆I , reduces the required minimum inductance and
L
Input Capacitance
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source, dictate the capacitance
requirement. Increasing the number of phases increas-
es the effective switching frequency and lowers the
peak-to-average current ratio, yielding lower input
capacitance requirement. It can be shown that the
even makes the use of planar inductors possible. The
advantages of using planar magnetics include low-profile
design, excellent current sharing between phases due to
the tight control of parasitics, and low cost. For example,
the minimum inductance at V = 12V, V
= 0.8V, ∆I
L
IN
OUT
= 3A, and f
= 500kHz is 0.5µH.
SW
The average current-mode control feature of the
MAX5066 limits the maximum inductor current, which
prevents the inductor from saturating. Choose an
______________________________________________________________________________________ 17
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
SEGMENT LOSS
P
=I
2 × R
CONDUCTION RMS DS(ON)
Losses associated with MOSFET on-time and
V
V
Conduction Loss on-resistance. I
and duty cycle.
is a function of load current
RMS
OUT
where I
≈
×I
LOAD
RMS
IN
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q )
G
P
= V × Q × f
DD G SW
GATEDRIVE
Gate Drive Loss
specification.
Losses during the drain voltage and drain
current transitions for every switching cycle.
(Q
+ Q
)
GS2
I
GD
P
= V ×I
× f
×
SWITCH
IN LOAD SW
Losses occur only during the Q
time period and not during the initial Q
period. The initial Q period is the rise in the
and Q
GS2
GD
GS1
GATE
GS1
Switching Loss
gate voltage from zero to V
TH.
V
DD
+ R
R
is the high-side MOSFET driver’s on-
where I
=
DH
GATE
2 × (R
)
GATE
DH
resistance and R
is the internal gate
GATE
resistance of the high-side MOSFET (Q
and
GD
Q
are found in the MOSFET data sheet).
GS2
Losses associated with Q
of the MOSFET
OSS
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs but are dissipated in the high-side
MOSFET.
Q
+ Q
OSS(LS)
OSS(HS)
P
=
× V × f
IN SW
Output Loss
OUTPUT
2
worst-case RMS current occurs when only one con-
troller section is operating. The controller section with
the highest output power needs to be used in determin-
ing the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other out-
of-phase controller section results in reducing the input
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R
).
ESR_OUT
The peak-to-peak inductor current ripple is given by:
V
(1− D)
OUT
∆I =
L
V
(V − V
)
OUT IN
OUT
L × f
SW
I
≈I
CIN(RMS) MAX
V
IN
During a load step, the allowable deviation of the out-
put voltage during the fast transient load dictates the
output capacitance and ESR. The output capacitors
supply the load step until the controller responds with a
where I
is the full load current of the regulator.
MAX
V
is the output voltage of the same regulator and
is C5 in Figure 6. The ESR of the input capacitors
OUT
C
IN
wastes power from the input and heats up the capaci-
tor. Reducing the ESR is important to maintain a high
overall efficiency and in reducing the heating of the
capacitors.
greater duty cycle. The response time (t
)
RESPONSE
depends on the closed-loop bandwidth of the regula-
tor. The resistive drop across the capacitor’s ESR and
capacitor discharge causes a voltage drop during a
18 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 2. Low-Side MOSFET Losses
LOSS
DESCRIPTION
SEGMENT LOSSES
P
=I
2 × R
CONDUCTION RMS
DS(ON)
− V
OUT
Losses associated with MOSFET on-time, I
is a function of load current and duty cycle.
RMS
V
Conduction Loss
IN
where I
≈
×I
LOAD
RMS
V
IN
Losses associated with charging and
discharging the gate of the MOSFET every
P
= V × (Q − Q )× f
DD G GD SW
GATEDRIVE
Gate Drive Loss
cycle. There is no Q
charging involved in this
GD
MOSFET due to the zero-voltage turn-on. The
charge involved is (Q - Q ).
G
GD
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
load step. Use a combination of SP polymer and
ceramic capacitors for better transient load and rip-
ple/noise performance.
Due to tolerances involved, the minimum average volt-
age at which the voltage across the current-sense
resistor is clamped is 20.4mV. Therefore, the minimum
average current limit is set at:
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
−3
20.4 × 10
(∆V
). During a load step, assume a 50% contribu-
OUT
I
=
LIMIT(MIN)
R
tion each from the output capacitance discharge and
the voltage drop across the ESR (∆V = ∆V
SENSE
OUT
ESR_OUT
+ ∆V
). Use the following equations to calculate
the required ESR and capacitance value:
For example, the current-sense resistor:
20.4mV
Q_OUT
R
=
= 2.04mΩ
SENSE
10A
∆V
ESR_OUT
R
=
ESR_OUT
for a maximum output current of 10A. The standard
value is 2mΩ. Also, adjust the value of the current-
sense resistor to compensate for parasitics associated
with the PC board. Select a noninductive resistor with
appropriate wattage rating.
I
LOAD_STEP
I
× t
LOAD_STEP RESPONSE
C
=
OUT
∆V
Q_OUT
where I
RESPONSE
is the step in load current and
is the response time of the controller.
LOAD_STEP
The second type of current limit is the peak current limit
as explained in the Peak-Current Comparator section.
t
Controller response time depends on the control-loop
bandwidth. C is C6 and C7 in Figure 6.
The third current-protection circuit is the hiccup fault
protection as explained in the Hiccup Fault Protection
section. The average current during a short at the out-
put is given by:
OUT
Current Limit
The average current-mode control technique of the
MAX5066 accurately limits the maximum average out-
put current per phase. The MAX5066 senses the volt-
age across the sense resistor and limits the maximum
inductor current accordingly. Use the equations below
to calculate the current-sense resistor values:
−3
1.41 × 10
I
=
AVG(SHORT)
R
SENSE
Reverse Current Limit
The MAX5066 limits the reverse current when the output
capacitor voltage is higher than the preset output volt-
age. Calculate the maximum reverse current limit based
−3
24.75× 10
I
=
LOAD(MAX)
R
SENSE
on V
and the current-sense resistor R
.
CLAMP_LO
SENSE
______________________________________________________________________________________ 19
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
For stability of the current loop, the amplified inductor-
−3
1.63 × 10
current downslope at the negative input of the PWM
comparator (CPWM1 and CPWM2) must not exceed
the ramp slope at the comparator’s positive input. This
puts an upper limit on the current-error amplifier gain at
the switching frequency. The inductor current downs-
I
=
REVERSE
R
SENSE
Output-Voltage Setting
The output voltage is set by the combination of resistors
lope is given by V
/L where L is the value of the
OUT
R1, R2, and R as described in the Voltage Error Amplifier
F
inductor (L1 and L2 in Figure 6) and V
is the output
OUT
section. First select a value for resistor R2. Then calculate
the value of R1 from the following equation:
voltage. The amplified inductor current downslope at
the negative input of the PWM comparator is given by:
(V
− 0.6135)
OUT(NL)
∆V
∆t
V
OUT
L
R1 =
× R2
L
=
×R
× 36×g ×R
0.6135
SENSE M CF
where V
is the voltage at no load. Then find the
OUT(NL)
where R
is the current-sense resistor (R1 and R2
SENSE
value of R from the following equation:
F
in Figure 6) and g x R is the gain of the current-error
M
CF
amplifier (CEA_) at the switching frequency. The slope
of the ramp at the positive input of the PWM comparator
I
× R
× 36 × R
SENSE 1
OUT
R
=
F
∆V
OUT
is 2V x f . Use the following equation to calculate the
SW
maximum value of R (R14 or R15 in Figure 6).
CF
where ∆V
is the allowable drop in voltage from no
OUT
load to full load. R is R8 and R9, R1 is R4 and R6, R2
F
2 × f
× L
SW
R
≤
(1)
is R5 and R7 in Figure 6.
CF
V
× R
× 36 × g
SENSE M
OUT
Compensation
The MAX5066 uses an average current-mode control
scheme to regulate the output voltage (see Figure 2).
The main control loop consists of an inner current loop
and an outer voltage loop. The voltage error amplifier
(VEA1 and VEA2) provides the controlling voltage for
the current loop in each phase. The output inductor is
“hidden” inside the inner current loop. This simplifies
the design of the outer voltage control loop and also
improves the power-supply dynamics. The objective of
the inner current loop is to control the average inductor
current. The gain-bandwidth characteristic of the cur-
rent loop can be tailored for optimum performance by
the compensation network at the output of the current-
error amplifier (CEA1 or CEA2). Compared with peak
current-mode control, the current-loop gain crossover
The highest crossover frequency f
is given by:
CMAX
f
× V
IN
SW
f
=
CMAX
2π × V
OUT
or alternatively:
f
f
× 2π × V
OUT
CMAX
=
SW
V
IN
Equation (1) can now be rewritten as:
π × f × L
C
R
=
(2)
CF
V
× R × 9 × g
IN
S
M
frequency, f , can be made approximately the same,
C
In practical applications, pick the crossover frequency
(f ) in the range of:
C
but the gain at low frequencies is much higher. This
results in the following advantages over peak current-
mode control.
f
f
SW
2
SW
10
< f
<
.
C
1) The average current tracks the programmed cur-
rent with a high degree of accuracy.
First calculate R in equation 2 above. Calculate C
CF
CF
2) Slope compensation is not required, but there is a
limit to the loop gain at the switching frequency in
order to achieve stability.
such that:
10
C
=
CF
2 × π × f × R
C
CF
3) Noise immunity is excellent.
where C is C10 and C12 in Figure 6.
CF
4) The average current-mode method can be used to
sense and control the current in any circuit branch.
20 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Calculate C
such that:
8) Distribute the power components evenly across the
top side for proper heat dissipation.
CFF
1
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
C
=
CFF
2 × π × f ×10 × R
C
CF
where C
is C11 and C13 in Figure 6.
CFF
10) Place all input bypass capacitors for each input as
close to each other as is practical.
Applications Information
Independant Turn-On and Off
Pin Configuration
The MAX5066 can be used to regulate two outputs
from one controller. Each of the two outputs can be
turned on and off independently of one another by con-
trolling the enable input of each phase (EN1 and EN2).
A logic-low on each enable pin shuts down the
MOSFET drivers for that phase. When the voltage on
the enable pin exceeds 1.2V, the drivers are turned on
and the output can come up to regulation. This method
of turning on the outputs allows the MAX5066 to be
used for power sequencing.
TOP VIEW
CSN2
CSP2
1
2
3
4
5
6
7
8
9
28 EN2
27 BST2
26 DH2
25 LX2
24 DL2
23 PGND
22 IN
EAOUT2
EAN2
CLP2
MAX5066
REF
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low loss-
es, low output noise, and clean and stable operation.
This is especially true for dual-phase converters where
one channel can affect the other. Use the following
guidelines for PC board layout:
RT/CLKIN
AGND
21 REG
MODE
20 V
DD
CLP1 10
EAN1 11
19 DL1
18 LX1
17 DH1
16 BST1
15 EN1
1) Place the V , REG, and the BST1 and BST2
DD
bypass capacitors close to the MAX5066.
EAOUT1 12
CSP1 13
2) Minimize all high-current switching loops.
*EXPOSED PADDLE
CSN1 14
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz or higher) to enhance
efficiency and minimize trace inductance and
resistance.
TSSOP
*CONNECT EXPOSED PAD TO GROUND PLANE.
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
Chip Information
TRANSISTOR COUNT: 6252
PROCESS: BiCMOS
5) Place the bank of output capacitors close to the
load.
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
______________________________________________________________________________________ 21
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
XX XX
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY,
EXPOSED PAD
1
E
21-0108
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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