MAX509AEPP+ [MAXIM]
D/A Converter, 4 Func, Serial Input Loading, 6us Settling Time, PDIP20, PLASTIC, DIP-20;
| 型号： | MAX509AEPP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 4 Func, Serial Input Loading, 6us Settling Time, PDIP20, PLASTIC, DIP-20 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0155; Rev 3; 12/10
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
_______________General Description
____________________________Features
♦ Single +5V or Dual 5V Suꢀꢀlꢁ ꢂꢀeraꢃion
♦ ꢂuꢃꢀuꢃ Buffer Amꢀlifiers Swing Rail-ꢃo-Rail
♦ Reference Inꢀuꢃ Range Includes Boꢃh Suꢀꢀlꢁ Rails
♦ Calibraꢃed ꢂffseꢃ, Gain, and Lineariꢃꢁ (1LSB TUE)
The MAX509/MAX510 are quad, serial-input, 8-bit volt-
age-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual 5V supplies.
Internal, precision buffers swing rail-to-rail. The refer-
ence input range includes both supply rails.
♦ 10MHz Serial Inꢃerface, Comꢀaꢃible wiꢃh SPI, QSPI
The MAX509 has four separate reference inputs, allow-
ing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two ref-
erence inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.
(CPꢂL = CPHA = 0) and MICRꢂWIRE
♦ Double-Buffered Regisꢃers for Sꢁnchronous
Uꢀdaꢃing
♦ Serial Daꢃa ꢂuꢃꢀuꢃ for Daisꢁ-Chaining
♦ Power-ꢂn Reseꢃ Clears Serial Inꢃerface and Seꢃs
The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to
load data into each register. Both input and DAC regis-
ters can be updated independently or simultaneously
with single software commands. Two additional asyn-
chronous control pins provide simultaneous updating
(LDAC) or clearing (CLR) of input and DAC registers.
All Regisꢃers ꢃo Zero
______________Ordering Information
TUE
(LSB)
PART
TEMP RANGE
PIN-PACKAGE
MAX509ACPP+
MAX509BCPP+
MAX509ACWP+
MAX509BCWP+
MAX509ACAP+
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 PDIP
20 PDIP
20 Wide SO
20 Wide SO
20 SSOP
1
1.5
1
1.5
1
T
he interface is compatible with MICROWIRETM and
SPI/QSPITM
.
All digital inputs and outputs are
TTL/CMOS compatible. A buffered data output provides
for readback or daisy-chaining of serial devices.
Ordering Information continued on last page.
**Contact factory for availability and processing to MIL-STD-883.
+Denotes a lead(Pb)-free/RoHS-compliant package.
_______________Functional Diagrams
_________________Pin Configurations
CLR
DGND
AGND
V
SS
DOUT
V
DD
REFB REFA
LDAC
TOP VIEW
MAX509
DECODE
CONTROL
OUTA
OUTB
OUTA
OUTC
OUTD
V
1
2
20
19
INPUT
REG A
DAC
REG A
DAC A
DAC B
DAC C
DAC D
V
SS
3
18 DD
OUTB
OUTC
OUTD
REFB
REFC
4
MAX509
17
16
15
14
13
12
11
12-BIT
SHIFT
REGISTER
INPUT
REG B
DAC
REG B
REFA
AGND
N.C.
REFD
CS
5
6
N.C.
SCLK
DIN
7
INPUT
REG C
DAC
REG C
DGND
LDAC
8
9
INPUT
REG D
DAC
REG D
SR
CONTROL
DOUT
CLR
10
DIP/SO/SSOP
REFD
Functional Diagrams continued at end of data sheet.
SCLK
REFC
CS DIN
Pin Configurations continued at end of data sheet.
MICROWIRE is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ABSꢂLUTE MAXIMUM RATINGS
V
DD
V
DD
V
SS
V
V
to DGND ..............................................................-0.3V, +6V
to AGND...............................................................-0.3V, +6V
to DGND...............................................................-6V, +0.3V
to AGND ...............................................................-6V, +0.3V
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
20-Pin Wide SO (derate 10.00mW/°C above +70°C).......800mW
20-Pin SSOP (derate 10.00mW/°C above +70°C)............800mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW
Operating Temperature Ranges:
SS
to V .................................................................-0.3V, +12V
DD
SS
Digital Input Voltage to DGND ......................-0.3V, (V
+ 0.3V)
+ 0.3V)
DD SS
MAX5_ _ _C_ _.....................................................0°C to +70°C
MAX5_ _ _E_ _..................................................-40°C to +85°C
MAX5_ _ _MJ_ ................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
DD
REF_....................................................(V - 0.3V), (V
SS
DD
OUT_..............................................................................V , V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T = +70°C)
A
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C) .........762mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW
Lead (Pb)-free packages..............................................+260°C
Packages containing lead (Pb).....................................+260°C
Noꢃe: The outputs may be shorted to V , V , or AGND if the package power dissipation is not exceeded. Typical short-circuit current
DD SS
to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.
9/MAX510
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V 10ꢀ, V = 0V to -5.5V, V
= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T
to T
, unless other-
MAX
DD
wise noted.)
SS
REF
L
L
A
MIN
PARAMETER
SYMBꢂL
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
STATIC ACCURACY
Resolution
8
Bits
MAX5_ _A
MAX5_ _B
MAX5_ _A
MAX5_ _B
1
VREF = +4V,
= 0V or -5V 10ꢀ
V
SS
VREF = -4V,
= -5V 10ꢀ
1.5
LSB
1
Total Unadjusted Error
Differential Nonlinearity
TUE
DNL
V
SS
1.5
Guaranteed monotonic
1
14
16
LSB
MAX5_ _C
MAX5_ _E
Code = 00 hex,
V
= 0V
SS
MAX5_ _M
MAX5_ _C
MAX5_ _E
20
14
16
Zero-Code Error
ZCE
mV
Code = 00 hex,
= -5V 10ꢀ
V
SS
MAX5_ _M
20
Code = 00 hex, V
= 5V 10ꢀ,
DD
Zero-Code-Error Supply Rejection
1
2
mV
V
SS
= 0V or -5V 10ꢀ
Zero-Code
Temperature Coefficient
Code = 00 hex
10
µV/°C
mV
Full-Scale Error
Code = FF hex
Code = FF hex,
14
4
MAX5_ _C
MAX5_ _E
MAX5_ _M
1
1
1
8
Full-Scale-Error Supply Rejection
V
DD
V
SS
= +5V 10ꢀ,
= 0V or -5V 10ꢀ
mV
12
Full-Scale-Error
Temperature Coefficient
Code = FF hex
10
µV/°C
2
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
ELECTRICAL CHARACTERISTICS (conꢃinued)
(V
= +5V 10ꢀ, V = 0V to -5.5V, V
= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T
to T
,
DD
SS
REF
L
L
A
MIN
MAX
unless otherwise noted.)
PARAMETER
REFERENCE INPUTS
Input Voltage Range
SYMBꢂL
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
V
SS
V
DD
V
MAX509
MAX510
MAX509
MAX510
16
24
12
Input Resistance (Note 1)
Input Capacitance (Note 2)
Code = 55 hex
kΩ
8
15
Code = 00 hex
pF
30
Channel-to-Channel Isolation
AC Feedthrough
(Note 3)
(Note 4)
-60
-70
dB
dB
DAC ꢂUTPUTS
Full-Scale Output Voltage
V
SS
V
DD
V
VREF = 4V, load regulation ≤ 1/4LSB
2
VREF = -4V, V = -5V 10ꢀ,
SS
load regulation ≤ 1/4LSB
2
Resistive Load
kΩ
VREF = V
load regulation ≤ 1LSB
MAX5_ _C/E,
DD
10
10
VREF = V MAX5_ _M,
DD
load regulation ≤ 2LSB
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
2.4
V
V
IH
V
0.8
1.0
10
IL
I
IN
V
= 0V or V
µA
pF
IN
DD
Input Capacitance
DIGITAL ꢂUTPUTS
Output High Voltage
Output Low Voltage
DYNAMIC PERFꢂRMANCE
C
(Note 5)
IN
V
OH
I
I
= 0.2mA
V - 0.5
DD
V
V
SOURCE
V
OL
= 1.6mA
SINK
0.4
MAX5_ _C
MAX5_ _E
MAX5_ _M
1.0
0.7
0.5
Voltage-Output Slew Rate
Positive and negative
V/µs
Output Settling Time (Note 6)
Digital Feedthrough
To 1/2LSB, 10kΩ II 100pF load
6
5
µs
Code = 00 hex, all digital inputs
nV-s
nV-s
from 0V to V
DD
Code 128➝127
Digital-to-Analog Glitch Impulse
12
87
VREF = 4V at 1kHz, V
= 5V,
DD
p-p
code = FF hex
Signal-to-Noise + Distortion Ratio
SINAD
dB
VREF = 4V at 20kHz, V = -5V 10ꢀ
74
1
p-p
SS
Multiplying Bandwidth
VREF = 0.5V , 3dB bandwidth
MHz
p-p
Wideband Amplifier Noise
60
µV
RMS
_______________________________________________________________________________________
3
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (conꢃinued)
(V
= +5V 10ꢀ, V = 0V to -5.5V, V
= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T
to T
,
DD
SS
REF
L
L
A
MIN
MAX
unless otherwise noted.)
PARAMETER
PꢂWER SUPPLIES
SYMBꢂL
CꢂNDITIꢂNS
MIN
TYP
MAX UNITS
Positive Supply Voltage
V
DD
For specified performance
For specified performance
4.5
-5.5
5.5
0
V
V
Negative Supply Voltage
V
SS
MAX5_ _C/E
MAX5_ _M
5
5
10
12
Outputs unloaded, all
digital inputs = 0V or V
Positive Supply Current
Negative Supply Current
I
mA
DD
DD
V
SS
= -5V 10ꢀ, outputs
MAX5_ _C/E
MAX5_ _M
5
5
10
12
I
unloaded, all digital
inputs = 0V or V
mA
SS
DD
Noꢃe 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Noꢃe 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Noꢃe 3: VREF = 4V , 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
p-p
9/MAX510
code of all other DACs to 00 hex.
Noꢃe 4: VREF = 4V , 10kHz. DAC code = 00 hex.
p-p
Noꢃe 5: Guaranteed by design.
Noꢃe 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
(V
= +5V 10ꢀ, V = 0V to -5V, V
SS
= 4V, AGND = DGND = 0V, C = 50pF, T = T
to T
, unless otherwise noted.)
MAX
DD
REF
L
A
MIN
PARAMETER
SYMBꢂL
CꢂNDITIꢂNS
MIN
40
50
0
TYP
20
MAX UNITS
MAX5_ _C/E
MAX5_ _M
(Notes 7, 8)
MAX5_ _C/E
MAX5_ _M
t
ns
ns
ns
LDAC Pulse Width Low
LDW
25
t
CS Rise to LDAC Fall Setup Time
CLR Pulse Width Low
CLL
40
50
20
25
t
CLW
SERIAL INTERFACE TIMING
CS Fall to SCLK Setup Time
MAX5_ _C/E
MAX5_ _M
40
50
0
t
ns
CSS
t
ns
ns
ns
SCLK Fall to CS Rise Hold Time
SCLK Rise to CS Rise Hold Time
SCLK Fall to CS Fall Hold Time
CSH2
t
t
(Note 9)
(Note 7)
40
0
CSH1
CSH0
MAX5_ _C/E
MAX5_ _M
40
50
0
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Clock Frequency
t
ns
DS
DH
t
ns
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
20
20
12.5
MHz
10
f
CLK
40
50
40
50
10
10
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
ns
CH
t
CL
100
ns
SCLK to DOUT Valid
t
DO
100
Noꢃe 7: Guaranteed by design.
Noꢃe 8: If LDAC is activated prior to CS's rising edge, it must stay low for t
or longer after CS goes high.
LDW
Noꢃe 9: Minimum delay from 12th clock cycle to CS rise.
4
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
__________________________________________Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
OUTPUT SINK CURRENT
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
vs. (V
- V )
SS
OUT
-25
-20
12
10
7
6
V
V
= VREF = +5V
= GND
DD
SS
DIGITAL INPUT = FF HEX
5
4
3
2
1
0
8
6
4
2
0
I
DD
-15
-10
-5
I
SS
V
V
= +5.5V
= -5.5V
DD
SS
V
V
= VREF = +5V
= GND = 0V
DD
SS
VREF = -4.75
ALL DIGITAL INPUTS = +5V
ALL DIGITAL INPUTS = 00 HEX
0
3.6
3.8 4.0 4.2 4.4 4.6 4.8 5.0
0
0.2
0.4
0.6
0.8
1.0
1.2
-60 -40 -20
0
20 40 60 80 100 120 140
V
(V)
V
- V (V)
SS
TEMPERATURE (°C)
OUT
OUT
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
THD + NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
THD + NOISE AT DAC OUTPUT
vs. REFERENCE AMPLITUDE
-20
-30
-40
-50
-60
10%
1%
6
-40
1%
V
V
= +5V
= -5V
DD
SS
V
V
= +5V
= -5V
DD
SS
-45
-50
5
4
3
2
1
0
INPUT CODE = FF HEX
V
= 0V
INPUT CODE = FF HEX
FREQ = SWEPT
SS
V
= -5V
SS
-55
-60
-65
-70
-75
-80
-85
-90
0.1%
VREF = 8Vp-p
0.1%
0.01%
FREQ = 20kHz
-70
-80
-90
VREF = 1Vp-p
FREQ = 1kHz
V
= +5V
ALL LOGIC
INPUTS = +5V
DD
0.01%
VREF = 4Vp-p
1k
10
100
10k
100k
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
2
4
6
8
10
REFERENCE FREQUENCY (Hz)
VREF VOLTAGE (V)
REFERENCE AMPLITUDE (Vp-p)
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
0
0
0
-10
-10
-10
-20
-30
-20
-30
-20
-30
V
V
= +5V
= AGND
V
V
= +5V
= AGND
DD
SS
DD
SS
V
V
= +5V
= -5V
DD
SS
VREF = 2.5VDC + 0.5Vp-p SINE WAVE
VREF = 2.5VDC + 0.05Vp-p SINE WAVE
-40
-40
-40
VREF = 2.5VDC + 4Vp-p SINE WAVE
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
_______________________________________________________________________________________
5
Quad, Serial 8-DACs
with Rail-to-Rail Outputs
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
ZERO-CODE ERROR
vs. NEGATIVE SUPPLY VOLTAGE
5.0
REFERENCE FEEDTHROUGH AT 40kHz
WORST-CASE 1LSB DIGITAL STEP CHANGE
2V
20mV
V
= +5V
DD
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
VREF = +4V
A
A
B
B
200nS
9/MAX510
A = REFA, 10V
p-p
A = CS, 2V/div
B = OUTA, 20mV ˜
TIMEBASE = 200ns/div
0
-1
-2
-3
(V)
-4
-5
-6
B = OUTA, 100μV/div, UNLOADED
TIMEBASE = 10μs/div
V
SS
V
DD
= +5V, V = -5V
SS
CODE = ALL 0s
REFERENCE FEEDTHROUGH AT 10kHz
REFERENCE FEEDTHROUGH AT 4kHz
50μV
REFERENCE FEEDTHROUGH AT 400Hz
5V
A
A
A
B
B
B
10
100μS
A = REFA, 10V
A = REFA, 10V
p-p
A = REFA, 10V
p-p
p-p
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 50μs/div
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 100μs/div
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 1ms/div
6
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
POSITIVE SETTLING TIME
(V = AGND OR -5V)
SS
CLOCK FEEDTHROUGH
5V
100mV
A
B
A
B
1μS
A = SCLK, 333kHz
B = OUT_, 10mV/div
TIMEBASE = 2μs/div
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1μs/div
V
DD
= +5V
REF_ = +4V
ALL BITS OFF TO ALL BITS ON
R
= 10kΩ, C = 100pF
L
L
NEGATIVE SETTLING TIME
NEGATIVE SETTLING TIME
(V = -5V)
(V = AGND)
SS
SS
5V
100mV
5V
100mV
A
A
B
B
1μS
1μS
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1μs/div
TIMEBASE = 1μs/div
V
DD
= +5V
V
DD
= +5V
REF_ = +4V
REF_ = +4V
ALL BITS ON TO ALL BITS OFF
ALL BITS ON TO ALL BITS OFF
R
= 10kΩ, C = 100pF
L
R
= 10kΩ, C = 100pF
L
L
L
_______________________________________________________________________________________
7
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________Pin Description
PIN
NAME
FUNCTIꢂN
MAX509 MAX510
OUTB
OUTA
DAC B Voltage Output
DAC A Voltage Output
1
1
2
3
–
4
–
5
–
6
2
3
V
SS
Negative Power Supply, 0V to -5V 10ꢀ. Connect to AGND for single-supply operation.
Reference Voltage Input for DAC B
Reference Voltage Input for DACs A and B
Reference Voltage Input for DAC A
Analog Ground
4
REFB
REFAB
REFA
AGND
N.C.
–
5
6
9/MAX510
7, 14
8
Not Internally Connected
DGND
Digital Ground
Load DAC Input (active low). Driving this asynchronous input low (level sensitive)
transfers the contents of each input latch to its respective DAC latch.
9
7
8
9
LDAC
Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be
clocked out on rising or falling edge of SCLK.
10
11
DOUT
Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input
and DAC registers and sets all DAC outputs to zero.
CLR
DIN
Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the
rising edge of SCLK. CS must be low for data to be clocked in.
12
13
15
10
11
12
Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the
rising (default) or the falling edge.
SCLK
CS
Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming
commands are executed when CS rises.
16
–
–
REFD
REFCD
REFC
Reference Voltage Input for DAC D
Reference Voltage Input for DACs C and D
Reference Voltage Input for DAC C
Positive Power Supply, +5V 10ꢀ
DAC D Output Voltage
13
–
17
18
19
20
14
15
16
V
DD
OUTD
OUTC
DAC C Output Voltage
8
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
between updates. DOUT does not go into a high-
impedance state if the clock or CS is high.
_______________Detailed Description
Serial Interface
At power-on, the serial interface and all DACs are
cleared and set to code zero. The serial data output
(DOUT) is set to transition on SCLK's rising edge.
Serial data is clocked into the data registers in MSB-
first format, with the address and configuration infor-
mation preceding the actual DAC data. Data is
clocked in on SCLK's rising edge while CS is low. Data
at DOUT is clocked out 12 clock cycles later, either at
SCLK's rising edge (default or mode 1) or falling edge
(mode 0).
The MAX509/MAX510 communicate with microproces-
sors through a synchronous, full-duplex, 3-wire inter-
face (Figure 1). Data is sent MSB first and can be
transmitted in one 4-bit and one 8-bit (byte) packet or
in one 12-bit word. If a 16-bit control word is used, the
first four bits are ignored. A 4-wire interface adds a line
for LDAC and allows asynchronous updating. The serial
clock (SCLK) synchronizes the data transfer. Data is
transmitted and received simultaneously.
Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CS must go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the first bit. With CS low, data is clocked into the
MAX509/MAX510's internal shift register on the rising
edge of the external serial clock. SCLK can be driven
at rates up to 12.5MHz.
Figure 2 shows a detailed serial interface timing.
Please note that the clock should be low if it is stopped
INSTRUCTION
EXECUTED
CS
• • •
• • •
SCLK
DIN
• • •
A1
A1
A1
A1
C1
A1
C0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
A1 A0 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
A0
DACA
DACD
DOUT
MODE 1
(DEFAULT)
• • •
A0 C1 C0
D7
D0
D6 D5 D4 D3 D2 D1
A1 A0 C1 C0 D7
D6 D5 D4 D3 D2 D1 D0
A1
DATA FROM PREVIOUS DATA INPUT
DATA FROM PREVIOUS DATA INPUT
DOUT
MODE 0
• • •
D0
A1 A0 C1 C0 D7
D6 D5 D4 D3 D2 D1 D0
A1
A1 A0 C1 C0
D7
D6 D5 D4 D3 D2 D1
A1
Figure 1. MAX509/MAX510 3-Wire Interface Timing
_______________________________________________________________________________________
9
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
t
CLL
CS
t
CSH2
• • •
t
t
CSS
CH
t
CSH0
• • •
SCLK
DIN
t
CL
t
t
CSH1
DS
t
DH
• • •
t
DO
9/MAX510
• • •
• • •
DOUT
LDAC
NOTE: TIMING SPECIFICATION t IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
CLL
t
LDW
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Inꢃerface Programming Commands
12-Biꢃ Serial Word
LDAC
Funcꢃion
A1
A0
C1
C0
D7 . . . . . . . . D0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
1
1
1
1
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
1
1
1
1
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
X
X
0
1
0
0
0
0
8-Bit DAC Data
X X X X X X X X
X
X
Update all DACs from shift register.
No Operation (NOP), shifts data in shift register.
“LDAC” Command, all DACs updated from respective
input registers.
0
1
1
X
1
0
1
1
1
0
0
0
X X X X X X X X
X X X X X X X X
X X X X X X X X
X
X
X
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
10 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
Serial Input Data Format and Control Codes
The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0) and eight bits of data (D0...D7).
Update All DACs from Shift Registers
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
x
0
0
0
8-Bit DAC Data
(LDAC = x)
The 4-bit address/control code configures the DAC as
shown in Table 1.
All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro-
grammed, which clears all DACs.
This is the first bit shifted in
MSB
LSB
D1 D0
● ● ●
A1 A0 C1 C0 D7 D6
DOUT
DIN
No Operation (NOP)
Control and
Address bits
8-bit DAC data
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
x
1
0
0
x
x
x
x
x
x
x
x
Figure 3. Serial Input Format
(LDAC = x)
Load Input Register, DAC Registers Unchanged
(Single Update Operation)
The NOP command (no operation) allows data to be shift-
ed through the MAX509/MAX510 shift register without
affecting the input or DAC registers. This is useful in daisy
chaining (also see the Daisy-Chaining Devices section).
For this command, the data bits are "Don't Cares." As an
example, three MAX509/MAX510s are daisy-chained (A, B
and C), and DAC A and DAC C need to be updated. The
36-bit-wide command would consist of one 12-bit word for
device C, followed by an NOP instruction for device B and
a third 12-bit word with data for device A. At CS's rising
edge, only device B is not updated.
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address
0
1
8-Bit Data
(LDAC = H)
When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
“LDAC” Command (Software)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Load Input and DAC Registers
0
x
1
0
x
x
x
x
x
x
x
x
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
(LDAC = x)
Address
1
1
8-Bit Data
All DAC registers are updated with the contents of their
respective input registers at CS's rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.
(LDAC = H)
This command directly loads the selected DAC register
at CS's rising edge. A1 and A0 set the DAC address.
Current shift-register data is placed in the selected
input and DAC registers.
Set DOUT Phase – SCLK Rising (Mode 1, Default)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 1V, DAC B = 2V, DAC
C = 3V and DAC D = 4V), five commands are required.
First, perform four single input register update opera-
tions. Next, perform an “LDAC” command as a fifth
command. All DACs will be updated from their respec-
tive input registers at the rising edge of CS.
1
1
1
0
x
x
x
x
x
x
x
x
(LDAC = x)
Mode 1 resets the serial output DOUT to transition at
SCLK's rising edge. This is the MAX509/MAX510’s
default setting after the supply voltage has been
applied.
The command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “LDAC” command.
______________________________________________________________________________________ 11
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Set DOUT Phase – SCLK Falling (Mode 0)
A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
DIN
SK
SO
1
0
1
0
x
x
x
x
x
x
x
x
MAX509
MAX510
(LDAC = x)
MICROWIRE
PORT
DOUT
CS
SI
This command resets DOUT to transition at SCLK's falling
edge. Once this command is issued, the phase of DOUT is
latched and will not change except on power-up or if the
specific command is issued that sets the phase to rising
edge.
I/0
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
The same command also updates all DAC registers with
the contents of their respective input registers, identical to
the “LDAC” command.
Figure 4. Connections for MICROWIRE
LDAC Operation (Hardware)
LDAC is typically used in 4-wire interfaces (Figure 7).
LDAC allows asynchronous hardware control of the DAC
outputs and is level-sensitive. With LDAC low, the DAC reg-
isters are transparent and any time an input register is
updated, the DAC output immediately follows.
9/MAX510
DOUT
DIN
MISO
MOSI
MAX509
MAX510
SPI
PORT
Clear DACs with CLR
Strobing the CLR pin low causes an asynchronous clear of
input and DAC registers and sets all DAC outputs to zero.
Similar to the LDAC pin, CLR can be invoked at any time,
typically when the device is not selected (CS = H). When
the DAC data is all zeros, this function is equivalent to the
"Update all DACs from Shift Registers" command.
SCLK
CS
SCK
I/0
CPOL = 0, CPHA = 0
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.
Digital Inputs and Outputs
Figure 5. Connections for SPI
Digital inputs and outputs are compatible with both TTL and
5V CMOS logic. The power-supply current (I ) depends
DD
The MAX509/MAX510 can interface with Intel's
80C5X/80C3X family in mode 0 if the SCLK clock polarity is
inverted. More universally, if a serial port is not available,
three lines from one of the parallel ports can be used for bit
manipulation.
on the input logic levels. Using CMOS logic to drive CS,
SCLK, DIN, CLR and LDAC turns off the internal level trans-
lators and minimizes supply currents.
Serial Data Output
DOUT is the output of the internal shift register. DOUT can be
programmed to clock out data on SCLK's falling edge (mode
0) or rising edge (mode 1). In mode 0, output data lags the
input data by 12.5 clock cycles, maintaining compatibility with
Microwire, SPI, and QSPI. In mode 1, output data lags the input
by 12 clock cycles. On power-up, DOUT defaults to mode 1
timing. DOUT never three-states; it always actively drives either
high or low and remains unchanged when CS is high.
Digital feedthrough at the voltage outputs is greatly mini-
mized by operating the serial clock only to update the regis-
ters. Also see the Clock Feedthrough photo in the Typical
Operating Characteristics section. The clock idle state is low.
Daisy-Chaining Devices
Any number of MAX509/MAX510s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin of the
following device in the chain. The NOP instruction (Table 1)
allows data to be passed from DIN to DOUT without chang-
ing the input or DAC registers of the passing device. A three-
wire interface updates daisy-chained or individual
MAX509/MAX510s simultaneously by bringing CS high.
Interfacing to the Microprocessor
The MAX509/MAX510 are Microwire, SPI, and QSPI compati-
ble. For SPI and QSPI, clear the CPOL and CPHA configura-
tion bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA
= 1 configuration can also be used if the DOUT output is
ignored.
12 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
MAX509
MAX510
MAX509
MAX510
MAX509
MAX510
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
DOUT
DOUT
DOUT
TO OTHER
SERIAL DEVICES
MAX509
MAX510
SCLK
DIN
CS
SCLK
DIN
CS
Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are
required.
DIN
SCLK
LDAC
CS1
TO OTHER
SERIAL
DEVICES
CS2
CS3
CS
CS
CS
MAX509
MAX510
MAX509
MAX510
MAX509
MAX510
LDAC
LDAC
LDAC
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by
enabling individual CS.
______________________________________________________________________________________ 13
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
dependent: 15pF typical for the MAX509 and 30pF
typical for the MAX510.
The output voltage for any DAC can be represented by
a digitally programmable voltage source as:
R
R
R
OUT_
VOUT = (NB x VREF) / 256
where NB is the numerical value of the DAC's binary
input code.
2R
2R
D0
2R
D5
2R
D6
2R
D7
Output Buffer Amplifiers
All MAX509/MAX510 voltage outputs are internally
buffered by precision unity-gain followers that slew at
REF_
up to 1V/µs. The outputs can swing from V to V
.
DD
AGND
SS
With a 0V to +4V (or +4V to 0V) output transition, the
amplifier outputs will settle to 1/2LSB in typically 6µs
when loaded with 10kΩ in parallel with 100pF.
SHOWN FOR ALL 1 ON DAC
Figure 8. DAC Simplified Circuit Diagram
9/MAX510
The buffer amplifiers are stable with any combination of
resistive loads ≥ 2kΩ and capacitive loads ≤ 300pF.
If multiple devices share a common DIN line, Figure 7's
configuration provides simultaneous update by strob-
ing LDAC low. CS1, CS2, CS3... are driven separately,
thus controlling which data are written to devices 1, 2, 3....
__________Applications Information
Power Supply and
Reference Operating Ranges
The MAX509/MAX510 are fully specified to operate with
Analog Section
DAC Operation
The MAX509/MAX510 contain four matched voltage-
output DACs. The DACs are inverted R-2R ladder net-
works that convert 8-bit digital words into equivalent
analog output voltages in proportion to the applied ref-
erence voltages. Each DAC in the MAX509 has a sepa-
rate reference input, while the two reference inputs in
the MAX510 each share a pair of DACs. The two refer-
ence inputs permit different full-scale output voltage
ranges for each pair of DACs. A simplified diagram of
one of the four DACs is shown in Figure 8.
V
= 5V 10ꢀ and V
= 0V to -5.5V. 8-bit perfor-
SS
DD
mance is guaranteed for both single- and dual-supply
operation. The zero-code output error is less than 14mV
when operating from a single +5V supply.
The DACs work well with reference voltages from V
SS
to V . The reference voltage is referred to AGND.
DD
The preferred power-up sequence is to apply V and
SS
then V , but bringing up both supplies at the same
DD
time is also acceptable. In either case, the voltage
applied to REF should not exceed V
during power-
DD
up or at any other time. If proper power sequencing is
not possible, connect an external Schottky diode
Reference Input
The MAX509/MAX510 can be used for multiplying
applications. The reference accepts both DC and AC
signals. The voltage at each REF input sets the full-
scale output voltage for its respective DAC(s). If the ref-
erence voltage is positive, both the MAX509 and
MAX510 can be operated from a single supply. If dual
supplies are used, the reference input can vary from
between V and AGND to ensure compliance with the
SS
Absolute Maximum Ratings. Do not apply signals to
the digital inputs before the device is fully powered up.
Power-Supply Bypassing
and Ground Management
In single-supply operation (AGND = DGND = V
=
SS
V
to V , but is always referred to AGND. The input
DD
0V), AGND, DGND and V
should be connected
SS
SS
impedance at REF is code dependent, with the lowest
value (16kΩ for the MAX509 and 8kΩ for the MAX510)
occurring when the input code is 55 hex or 0101 0101.
The maximum value, practically infinity, occurs when
the input code is 00 hex. Since the REF input imped-
ance is code dependent, the DAC's reference sources
must have a low output impedance (no more than 32Ω
for the MAX509 and 16Ω for the MAX510) to maintain
output linearity. The REF input capacitance is also code
together in a "star" ground at the chip. This ground
should then return to the highest quality ground avail-
able. Bypass V
with a 0.1µF capacitor, located as
DD
close to V
and DGND as possible. In dual-supply
DD
operation, bypass V to AGND with 0.1µF.
SS
Careful PC board layout minimizes crosstalk among
DAC outputs, reference inputs, and digital inputs.
Figures 9 and 10 show suggested circuit board layouts
to minimize crosstalk.
14 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
SYSTEM GND
SYSTEM GND
OUTC
OUTD
OUTB
OUTA
OUTB
OUTA
OUTC
OUTD
V
V
DD
V
DD
SS
V
SS
REFCD
REFAB
AGND
REFC
REFD
REFB
REFA
AGND
Figure 9. Suggested MAX509 PC Board Layout for Minimizing
Crosstalk (Bottom View)
Figure 10. Suggested MAX510 PC Board Layout for Minimizing
Crosstalk (Bottom View)
Unipolar-Output, 2-Quadrant Multiplication
In unipolar operation, the output voltages and the refer-
ence input(s) are the same polarity. Figures 11 and 12
show the MAX509/MAX510 unipolar configurations.
Both devices can be operated from a single supply if
the reference inputs are positive. If dual supplies are
Bipolar-Output, 2-Quadrant Multiplication
Bipolar-output, 2-quadrant multiplication is achieved by
offsetting AGND positively or negatively. Table 3 shows
the bipolar code.
AGND can be biased above DGND to provide an arbi-
trary nonzero output voltage for a 0 input code, as
shown in Figure 13. The output voltage at OUTA is:
used, the reference input can vary from V
Table 2 shows the unipolar code.
to V
.
DD
SS
V
OUTA
= V
+ (NB/256)(V ),
IN
BIAS
Table 3. Biꢀolar Code Table
Table 2. Uniꢀolar Code Table
DAC CꢂNTENTS
DAC CꢂNTENTS
ANALꢂG
ꢂUTPUT
ANALꢂG
ꢂUTPUT
MSB
LSB
MSB
LSB
127
255
256
1 1 1 1
1 1 1 1
+V
+V
(
––––
128
)
)
1 1 1 1
1 1 1 1
+V
(
––––
)
)
REF
REF
REF
REF
1
128
129
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
(
––––
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
+V
(
––––
256
0V
V
REF
128
256
––––
2
+V
(
–––– = +
)
REF
1
-V
(
––––
128
)
REF
127
+V
(
––––
)
)
REF
256
127
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
-V
(
––––
)
REF
128
1
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
-8
+V
(
––––
REF
256
128
128
-V
(
––––
)
= -V
REF
REF
0V
1
256
Noꢃe: 1LSB = (V
) (2 ) = +VREF (––––)
REF
______________________________________________________________________________________ 15
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
REFERENCE INPUTS (V TO V
)
+5V
18
SS
DD
+5V
18
5
4
17
16
5
V
DD
REFA REFB REFC REFD
V
REFA
DD
2
OUTA
DAC A
2
OUTA
DAC A
V
IN
1
6
AGND
OUTB
OUTC
OUTD
DAC B
DAC C
DAC D
MAX509
SERIAL
INTERFACE
NOT SHOWN
V
BIAS
V
DGND
8
SS
3
20
-5V (OR GND)
+5V
9/MAX510
14
4
V
DD
19
REFAB
DGND
V
AGND
6
2
SS
OUTA
3
8
DAC A
V
IN
-5V (OR GND)
MAX509
5
AGND
MAX510
Figure 11. MAX509 Unipolar Output Circuit
V
DGND
6
V
SS
BIAS
3
-5V (OR GND)
SERIAL INTERFACE NOT SHOWN
REFERENCE INPUTS (V TO V
SS
)
+5V
14
DD
4
V
DD
REFAB
Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive
Offset)
2
OUTA
DAC A
where NB represents the digital input word. Since
AGND is common to all four DACs, all outputs will be
1
offset by V
in the same manner. Do not bias AGND
BIAS
OUTB
OUTC
OUTD
DAC B
DAC C
DAC D
more than +1V above DGND, or more than 2.5V below
DGND.
SERIAL
INTERFACE
NOT SHOWN
Figures 14 and 15 illustrate the generation of negative
offsets with bipolar outputs. In these circuits, AGND is
biased negatively (up to -2.5V with respect to DGND) to
provide an arbitrary negative output voltage for a 0
input code. The output voltage at OUTA is:
16
15
OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1)
where NB represents the digital input word. Since
AGND is common to all four DACs, all outputs will be
DGND
V
REFCD
AGND
5
SS
offset by V
in the same manner. Table 3, with
3
13
6
BIAS
V
= 2.5V, shows the digital code vs. output voltage
-5V (OR GND)
REF
MAX510
for Figure 14 and 15's circuits with R1 = R2. The
ICL7612 op amp is chosen because its common-mode
range extends to both supply rails.
Figure 12. MAX510 Unipolar Output Circuit
16 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
REFERENCE INPUTS
+5V
0.1μF
5
4
17
16
18
V
DD
+5V
SERIAL
INTERFACE
NOT SHOWN
MAX509
0.1μF
2
1
OUTA
OUTB
DAC A
R1
330k
0.1%
R2
330k
0.1%
MAX873
DAC B
DAC C
DAC D
+2.5V
+5V
20
19
0.1μF
0.1μF
OUTC
OUTD
7
2
6
3
8
1
ICL7611A
DGND
V
AGND
6
SS
3
8
-5V
0.1μF
-5V
Figure 14. MAX509 AGND Bias Circuit (Negative Offset)
4-Quadrant Multiplication
Each DAC output may be configured for 4-quadrant
multiplication using Figure 16 and 17's circuit. One op
amp and two resistors are required per channel. With
R1 = R2:
VOUT = VREF [2(NB/256)-1]
where NB represents the digital word in DAC register A.
The recommended value for resistors R1 and R2 is
330kΩ ( 0.1ꢀ). Table 3 shows the digital code vs. out-
put voltage for Figure 16 and 17's circuit.
______________________________________________________________________________________ 17
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
+5V
14
REFERENCE INPUTS
13
4
+5V
0.1μF
V
DD
SERIAL
INTERFACE
MAX510
0.1μF
2
1
NOT SHOWN
OUTA
DAC A
2
R1
330k
0.1%
R2
330k
0.1%
6
MAX873
OUTB
DAC B
DAC C
DAC D
+2.5V
4
+5V
16
15
0.1μF
0.1μF
OUTC
OUTD
7
2
3
6
9/MAX510
8
1
ICL7611A
V
AGND
5
DGND
6
SS
3
-5V
0.1μF
-5V
Figure 15. MAX510 AGND Bias Circuit (Negative Offset)
REFERENCE INPUTS (V TO V
)
SS
DD
+5V
0.1μF
+5V
18
V
5
4
17 16
R2
R1
0.1μF
DD
MAX509
ICL7612A*
V
OUT
2
DAC A
OUTA
0.1μF
+5V
-5V
1
SERIAL
INTERFACE
NOT SHOWN
DAC B
DAC C
OUTB
0.1μF
R2
20
OUTC
R1
ICL7612A*
V
OUT
19
OUTD
DAC D
V
0.1μF
AGND
6
DGND
SS
-5V
3
8
0.1μF
*CONNECT ICL7612A PIN 8 TO AGND
AGND OR -5V
Figure 16. MAX509 Bipolar Output Circuit
18 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
REFERENCE INPUTS
+5V
+5V
14
V
4
13
0.1μF
0.1μF
DD
R1
MAX510
R2
ICL7612A*
V
OUT
2
DAC A
OUTA
0.1μF
-5V
+5V
1
SERIAL
INTERFACE
NOT SHOWN
DAC B
DAC C
DAC D
OUTB
0.1μF
0.1μF
16
R1
OUTC
R2
ICL7612A*
V
15
OUT
OUTD
V
DGND
SS
AGND
5
-5V
3
6
0.1μF
AGND OR -5V
*CONNECT ICL7612A PIN 8 TO AGND
Figure 17. MAX510 Bipolar Output Circuit
____Pin Configurations (continued)
__Functional Diagrams (continued)
CLR
DOUT LDAC
DGND
AGND
V
SS
V
REFAB
DD
TOP VIEW
MAX510
DECODE
CONTROL
OUTA
INPUT
REG A
DAC
REG A
OUTB
OUTA
OUTC
OUTD
V
DAC A
DAC B
DAC C
1
2
3
4
5
6
7
8
16
15
V
SS
14 DD
OUTB
OUTC
OUTD
12-BIT
SHIFT
REGISTER
INPUT
REG B
DAC
REG B
REFAB
REFCD
MAX510
13
12
11
10
9
AGND
DGND
LDAC
DOUT
CS
SCLK
DIN
INPUT
REG C
DAC
REG C
CLR
INPUT
REG D
DAC
REG D
SR
CONTROL
DIP/Wide SO
DAC D
REFCD
SCLK
CS DIN
______________________________________________________________________________________ 19
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Package Information
_Ordering Information (continued)
For the latest package outline information and land patterns, go
to www.maxim-ic.com/ꢀackages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
TUE
(LSB)
PART
TEMP RANGE
PIN-PACKAGE
MAX509BCAP+
MAX509AEPP+
MAX509BEPP+
MAX509AEWP+
MAX509BEWP+
MAX509AEAP+
MAX509BEAP+
MAX509AMJP
MAX509BMJP
MAX510ACPE+
MAX510BCPE+
MAX510ACWE+
MAX510BCWE+
MAX510AEPE+
MAX510BEPE+
MAX510AEWE+
MAX510BEWE+
MAX510AMJE
MAX510BMJE
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
20 SSOP
20 PDIP
20 PDIP
20 Wide SO
20 Wide SO
20 SSOP
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
PACKAGE
TYPE
20 PDIP
20 Wide SO
20 SSOP
PACKAGE
CꢂDE
ꢂUTLINE
Nꢂ.
LAND
PATTERN Nꢂ.
P20+3
W20+3
A20A+1
J20-2
21-0043
21-0042
21-0056
21-0045
21-0043
21-0042
21-0045
—
90-0108
90-0094
—
20 SSOP
20 CERDIP**
20 CERDIP**
16 PDIP
20 CERDIP
16 PDIP
P16+2
W16+3
J16-3
—
16 PDIP
16 Wide SO
16 Wide SO
16 PDIP
16 Wide SO
16 CERDIP
90-0107
—
9/MAX510
16 PDIP
16 Wide SO
16 Wide SO
16 CERDIP**
16 CERDIP**
1.5
1
1.5
**Contact factory for availability and processing to MIL-STD-883.
+Denotes a lead(Pb)-free/RoHS-compliant package.
20 ______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
9/MAX510
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
Updated Ordering Information, added soldering temperature to Absolute
Maximum Ratings, updated Figure 17 and Functional Diagrams
3
12/10
1, 2, 19, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Package Information
_Ordering Information (continued)
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
TUE
(LSB)
PART
TEMP RANGE
PIN-PACKAGE
MAX509BCAP+
MAX509AEPP+
MAX509BEPP+
MAX509AEWP+
MAX509BEWP+
MAX509AEAP+
MAX509BEAP+
MAX509AMJP
MAX509BMJP
MAX5±0ACPE+
MAX5±0BCPE+
MAX5±0ACWE+
MAX5±0BCWE+
MAX5±0AEPE+
MAX5±0BEPE+
MAX5±0AEWE+
MAX5±0BEWE+
MAX5±0AMJE
MAX5±0BMJE
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +±25°C
-55°C to +±25°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +±25°C
-55°C to +±25°C
20 SSOP
20 PDIP
20 PDIP
20 Wide SO
20 Wide SO
20 SSOP
±±.5
±±
±±.5
±±
±±.5
±±
±±.5
±±
±±.5
±±
±±.5
±±
±±.5
±±
±±.5
±±
PACKAGE
TYPE
20 PDIP
20 Wide SO
20 SSOP
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
P20+3
W20+3
A20A+±
J20-2
21-0043
21-0042
21-0056
21-0045
21-0043
21-0042
21-0045
—
90-0108
90-0094
—
20 SSOP
20 CERDIP**
20 CERDIP**
±6 PDIP
20 CERDIP
±6 PDIP
P±6+2
W±6+3
J±6-3
—
±6 PDIP
±6 Wide SO
±6 Wide SO
±6 PDIP
±6 Wide SO
±6 CERDIP
90-0107
—
9/MAX510
±6 PDIP
±6 Wide SO
±6 Wide SO
±6 CERDIP**
±6 CERDIP**
±±.5
±±
±±.5
**Contact factory for availability and processing to MIL-STD-883.
+Denotes a lead(Pb)-free/RoHS-compliant package.
20 ______________________________________________________________________________________
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