MAX5102BEUE+ [MAXIM]

D/A Converter, 1 Func, Parallel, 8 Bits Input Loading, 6us Settling Time, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153AC, TSSOP-16;


型号：	MAX5102BEUE+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	D/A Converter, 1 Func, Parallel, 8 Bits Input Loading, 6us Settling Time, PDSO16, 4.40 MM, 0.65 MM PITCH, MO-153AC, TSSOP-16
文件：	总8页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-1565; Rev 0; 10/99

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

General Description

Features

The MAX5102 parallel-input, voltage-output, dual 8-bit

digital-to-analog converter (DAC) operates from a single

+2.7V to +5.5V supply and comes in a space-saving

16-pin TSSOP package. Internal precision buffers

ꢀ +2.7V to +5.5V Single-Supply Operation

ꢀ Ultra-Low Supply Current

0.2mA while Operating

1nA in Shutdown Mode

swing Rail-to-Rail , and the reference input range

includes both ground and the positive rail. Both DACs

share a common reference input.

ꢀ Ultra-Small 16-Pin TSSOP Package

ꢀ Ground to V

Reference Input Range

The MAX5102 has separate input latches for each of its

DACs. Data is transferred to the input latches from a

common 8-bit input port. The DACs are individually

selected through address input A0 and are updated by

bringing WR low.

ꢀ Output Buffer Amplifiers Swing Rail-to-Rail

ꢀ Power-On Reset Sets All Registers to Zero

The MAX5102 features a shutdown mode that reduces

current to 1nA, as well as a power-on reset mode that

resets all registers to code 00 hex on power-up.

Ordering Information

INL

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

Applications

MAX5102AEUE -40°C to +85°C 16 TSSOP

MAX5102BEUE -40°C to +85°C 16 TSSOP

Digital Gain and Offset Adjustment

Programmable Attenuators

Portable Instruments

Power-Amp Bias Control

Functional Diagram

Pin Configuration

TOP VIEW

16 OUTA

15 OUTB

14 GND

OUTA

OUTB

INPUT

LATCH A

DAC A

DAC B

REF

SHDN

D0–D7

MAX5102

13 A0

12 D0

11 D1

10 D2

INPUT

LATCH B

CONTROL

LOGIC

MAX5102

TSSOP

REF SHDN

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

________________________________________________________________ Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ABSOLUTE MAXIMUM RATINGS

to GND..............................................................-0.3V to +6V

Operating Temperature Range

D_, A0, WR, SHDN to GND ......................................-0.3V to +6V

REF to GND................................................-0.3V to (V + 0.3V)

MAX5102_EUE ..............................................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

OUT_ to GND ...........................................................-0.3V to V

Maximum Current into Any Pin ......................................... 50mA

Continuous Power Dissipation (T = +70°C)

16-Pin TSSOP (derate 5.7mW/°C above +70°C) .......457mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

= V

= +2.7V to +5.5V, GND = 0V, R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at

MAX

= V

REF

MIN

= +3V and T = +25°C.)

REF A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY

Resolution

Bits

MAX5102A

MAX5102B

Integral Nonlinearity (Note 1)

INL

LSB

Differential Nonlinearity (Note 1)

Zero-Code Error

DNL

ZCE

Guaranteed monotonic

Code = 00 hex

LSB

Zero-Code-Error Supply

Rejection

Code = 00 hex, V

= 2.7V to 5.5V

Zero-Code Temperature

Coefficient

Code = 00 hex

Code = F0 hex

µV/°C

Gain Error (Note 2)

Gain-Error Temperature

Coefficient

0.001

LSB/°C

= 2.7V to 3.6V,

= 2.5V

REF

Power-Supply Rejection

Code = FF hex

LSB

= 4.5V to 5.5V,

= 4.096V

REF

REFERENCE INPUT

Input Voltage Range

Input Resistance

Input Capacitance

DAC OUTPUTS

320

460

600

kΩ

Output Voltage Range

R = ∞

REF

DIGITAL INPUTS

= 2.7V to 3.6V

Input High Voltage

= 3.6V to 5.5V

Input Low Voltage

Input Current

0.8

1.0

= V or GND

µA

Input Capacitance

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ELECTRICAL CHARACTERISTICS (continued)

= V

= +2.7V to +5.5V, GND = 0V, R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at

MAX

= V

REF

MIN

= +3V and T = +25°C.)

REF A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE

Output Voltage Slew Rate

Output Settling Time (Note 3)

From code 00 to code F0 hex

0.6

V/µs

µs

To 1/2LSB, from code 00 to code F0 hex

Channel-to-Channel Isolation

(Note 4)

Code 00 to code FF hex

500

0.5

nVs

Digital Feedthrough (Note 5)

Code 00 to code FF hex

Digital-to-Analog Glitch Impulse

Code 80 hex to code 7F hex

REF = 2.5Vp-p at 1kHz, V

= 1.5V,

REF(DC)

= 3V, code FF hex

Signal-to-Noise plus Distortion

Ratio

SINAD

REF = 2.5Vp-p at 10kHz, V

= 1.5V,

REF(DC)

= 3V, code FF hex

REF = 0.5Vp-p, V

= 1.5V,

REF(DC)

Multiplying Bandwidth

650

kHz

= 3V, -3dB bandwidth

Wideband Amplifier Noise

Shutdown Recovery Time

Time to Shutdown

µV

RMS

To 1/2LSB of final value of V

µs

SDR

OUT

< 5µA

SDN

POWER SUPPLIES

Power-Supply Voltage

2.7

5.5

360

Supply Current (Note 6)

Shutdown Current

190

µA

0.001

DIGITAL TIMING (Figure 1) (Note 7)

Address to WR Setup

Address to WR Hold

Data to WR Setup

Data to WR Hold

WR Pulse Width

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.

Note 2: Gain error is: [100 (V - ZCE - V ) / V ]. Where V is the DAC output voltage with input code F0 hex,

F0,meas

F0,ideal

REF

F0,meas

and V

is the ideal DAC output voltage with input code F0 hex (i.e., V_REF· 240 / 256).

F0,ideal

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of V

’s final value.

OUT

Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at V

Note 6: R = ∞, digital inputs at GND or V

Note 7: Timing measurement reference level is (V + V ) / 2.

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ADDRESS

ADDRESS VALID

AH-

DH-

DS-

DATA

DATA VALID

Figure 1. Timing Diagram

Typical Operating Characteristics

= V

= +3V, R = 10kΩ, C = 100pF, code = FF hex, T = +25°C, unless otherwise noted.)

REF

DAC FULL-SCALE OUTPUT VOLTAGE

vs. SOURCE CURRENT

DAC ZERO-CODE OUTPUT VOLTAGE

vs. SINK CURRENT

SUPPLY CURRENT vs. TEMPERATURE

1.2

200

190

180

170

160

150

140

130

120

110

100

1 DAC AT CODE 00 OR F0

1 DAC AT CODE 00 (R = ∞)

= V = 5V

REF

1.0

0.8

0.6

0.4

0.2

= V = 3V

REF

= 5V; CODE = F0 HEX

= 3V; CODE = F0 HEX

= V = 3V

REF

= V = 5V

REF

= 5V; CODE = 00

= 3V; CODE = 00

= 3.0V

-40 -20

80 100

SOURCE CURRENT (mA)

SINK CURRENT (mA)

TEMPERATURE (°C)

TOTAL HARMONIC DISTORTION

PLUS NOISE AT DAC OUTPUT

vs. REFERENCE AMPLITUDE

SUPPLY CURRENT vs.

REFERENCE VOLTAGE

SUPPLY CURRENT vs.

REFERENCE VOLTAGE

200

180

160

140

120

100

200

180

160

140

120

100

-10

-20

-30

-40

-50

-60

-70

-80

-90

DAC CODE = FF HEX

1 DAC AT CODE 00 OR F0

= SINE WAVE CENTERED AT 1.5V

REF

1 DAC AT CODE 00 (R = ∞)

80kHz FILTER

CODE = F0 HEX

CODE = 00 HEX

20kHz REF SIGNAL

10kHz REF SIGNAL

CODE = 00 HEX

= 5.0V

1 DAC AT CODE 00 OR F0

1 DAC AT CODE 00. (R = ∞)

= 3.0V

0.5

1kHz REF SIGNAL

0.5 1.0

REFERENCE AMPLITUDE (V

1.0

1.5

2.0

2.5

3.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5. 5.0

REFERENCE VOLTAGE (V)

1.5

2.0

2.5

REFERENCE VOLTAGE (V)

)

p-p

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Typical Operating Characteristics (continued)

= V

= +3V, R = 10kΩ, C = 100pF, code = FF hex, T = +25°C, unless otherwise noted.)

REF

REFERENCE INPUT

FREQUENCY RESPONSE

WORST-CASE 1LSB DIGITAL STEP CHANGE

(NEGATIVE)

TOTAL HARMONIC DISTORTION

PLUS NOISE AT DAC OUTPUT

vs. REFERENCE FREQUENCY

DAC CODE FROM 80 TO 7F HEX

DAC CODE = FF HEX

= SINE WAVE CENTERED AT 1.5V

REF

-10

1kHz FREQUENCY

500kHz FILTER

-20

-30

-20

-30

-40

-50

-60

-70

-80

-40

-50

REF = 0.5V

p-p

REF = 1V

p-p

-60

-70

CODE = FF HEX REF IS IV SIGNAL

REF

p-p

-80

-90

REF = 2V

= 1.5V

p-p

2µs/div

0.01

0.1

100

FREQUENCY (MHz)

CH1 = WR, 1V/div, CH2 = V

, 50mV/div, AC-COUPLED

OUTA

FREQUENCY (kHz)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(1 TO 0 DIGITAL TRANSITION)

WORST-CASE 1LSB DIGITAL STEP CHANGE

(POSITIVE)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(0 TO 1 DIGITAL TRANSITION)

1 TO 0 DIGITAL TRANSITION ON

ALL DATA BITS (WITH WR HIGH)

DAC CODE FROM 7F TO 80 HEX

0 TO 1 DIGITAL TRANSITION ON

ALL DATA BITS (WITH WR HIGH)

20ns/div

1µs/div

20ns/div

CH1 = WR, 1V/div, CH2 = V

, 50mV/div, AC-COUPLED

OUTA

CH1 = D7, 2V/div, CH2 = V

, 1mV/div

OUTA

CH1 = D7, 2V/div, CH2 = V

, 1mV/div

OUTA

INTEGRAL AND DIFFERENTIAL

NONLINEARITY vs. DIGITAL CODE

POSITIVE SETTLING TIME

NEGATIVE SETTLING TIME

0.5

0.4

R = ∞

DAC CODE FROM 10 TO F0 HEX

DAC CODE FROM F0 TO 10 HEX

0.3

0.2

DNL

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

INL

1µs/div

32 64 96 128 160 192 224 256

DIGITAL CODE

CH1 = WR = 2V/div, CH2 = V

= 2V/div

CH1 = WR, 2V/div, CH2 = V

, 2V/div

OUTA

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Pin Description

NAME

FUNCTION

Positive Supply Voltage. Bypass V

to GND using a 0.1µF capacitor.

REF

SHDN

Reference Voltage Input

Shutdown. Connect SHDN to GND for normal operation.

Write Input (active low). Use WR to load data into the DAC input latch selected by A0.

5–12

D7–D0

Data Inputs

DAC Address Select Bit

Ground

GND

OUTB

OUTA

DAC B Voltage Output

DAC A Voltage Output

Reference Input

Detailed Description

Digital-to-Analog Section

The MAX5102 provides a code-independent input

impedance on the REF input. Input impedance is typi-

cally 460kΩ in parallel with 15pF, and the reference

The MAX5102 uses a matrix decoding architecture for the

DACs. The external reference voltage is divided down by

a resistor string placed in a matrix fashion. Row and col-

umn decoders select the appropriate tab from the resistor

string to provide the needed analog voltages. The resistor

network converts the 8-bit digital input into an equivalent

analog output voltage in proportion to the applied refer-

ence voltage input. The resistor string presents a code-

independent input impedance to the reference and

guarantees a monotonic output.

input voltage range is 0 to V . The reference input

accepts positive DC signals, as well as AC signals with

peak values between 0 and V . The voltage at REF

sets the full-scale output voltage for the DAC. The out-

put voltage (V

) for any DAC is represented by a

OUT

digitally programmable voltage source as follows:

OUT

= (N · V ) / 256

REF

where N is the numeric value of the DAC binary input

These devices can be used in multiplying applications.

Their voltages are buffered by rail-to-rail op amps con-

nected in a follower configuration to provide a rail-to-rail

output (see Functional Diagram).

code.

Digital Inputs and Interface Logic

In the MAX5102, address line A0 selects the DAC that

receives data from D0–D7, as shown in Table 1. When

WR is low, the addressed DAC’s input latch is transpar-

ent. Data is latched when WR is high. The DAC outputs

(OUTA, OUTB) represent the data held in the two 8-bit

Low-Power Shutdown Mode

The MAX5102 features a shutdown mode that reduces

current consumption to 1nA. A high voltage on the

SHDN pin shuts down the DACs and the output ampli-

fiers. In shutdown mode, the output amplifiers enter a

high-impedance state. When bringing the device out of

shutdown, allow 13µs for the output to stabilize.

Table 1. MAX5102 Addressing Table

(partial list)

Output Buffer Amplifiers

The DAC outputs are internally buffered by precision

amplifiers with a typical slew rate of 0.6V/µs. The typical

settling time to 1/2LSB at the output is 6µs when

loaded with 10kΩ in parallel with 100pF.

LATCH STATE

Input data latched

DAC A input latch transparent

DAC B input latch transparent

H = High state, L = Low state, X = Don’t care

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

input latches. To avoid output glitches in the MAX5102,

connect an external Schottky diode between REF and

V to ensure compliance with the absolute maximum

ratings. Do not apply signals to the digital inputs before

the device is fully powered up.

ensure that data is valid before WR goes low. When the

device powers up (i.e., V

ramps up), all latches are

internally preset with code 00 hex.

Applications Information

Power-Supply Bypassing and

Ground Management

External Reference

The reference source resistance must be considerably

less than the reference input resistance. To keep within

Digital or AC transient signals on GND can create noise

at the analog output. Return GND to the highest-quality

ground available. Bypass V

with a 0.1µF capacitor,

1LSB error in an 8-bit system, R must be less than

located as close to V

and GND as possible.

/256. Hence, maintain a value of R < 1kΩ to

REF

Careful PC board ground layout minimizes crosstalk

between the DAC outputs and digital inputs.

ensure 8-bit accuracy. If V

is DC only, bypass REF

REF

to GND with a 0.1µF capacitor. Values greater than this

improve noise rejection.

Power Sequencing

Chip Information

The voltage applied to REF should not exceed V

TRANSISTOR COUNT: 6848

any time. If proper power sequencing is not possible,

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Dual, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.

MAX5102BEUE+ [MAXIM]

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