MAX5123BEEE [MAXIM]
+5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/∑C Internal Reference; + 5V / + 3V ， 12位，串行，加载/感应DAC与为10ppm / ° C内部参考
| 型号： | MAX5123BEEE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +5V/+3V, 12-Bit, Serial, Force/Sense DACs with 10ppm/∑C Internal Reference |
| 文件： | 总20页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1446; Rev 0; 3/99
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX5122/MAX5123 low-power, 12-bit, voltage-out-
put, digital-to-analog converters (DACs) feature an inter-
nal precision bandgap reference and output amplifier.
♦ Single-Supply Operation
+5V (MAX5122)
+3V (MAX5123)
The MAX5122 operates on a single +5V supply with an
internal +2.5V reference, and offers a configurable output
amplifier. If necessary, the user can override the on-chip,
<10ppm/°C voltage reference with an external reference.
The MAX5123 has the same features as the MAX5122 but
operates from a single +3V supply and has an internal
+1.25V precision reference. The user-accessible inverting
input and output of the amplifier allows specific gain con-
figurations, remote sensing, and high output drive capa-
bility for a wide range of force/sense applications. Both
d e vic e s d ra w only 500µA of s up p ly c urre nt, whic h
reduces to 3µA in power-down mode. In addition, their
power-up reset feature allows for a user-selectable initial
output state of either 0V or midscale and reduces output
glitches during power-up.
♦ Built-In 10ppm/°C max Precision Bandgap Reference
+2.5V (MAX5122)
+1.25V (MAX5123)
♦ SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
♦ Pin-Programmable Shutdown Mode and Power-
Up Reset (0 or Midscale Output Voltage)
♦ Buffered Output Capable of Driving 5kΩ 100pF
or 4–20mA Loads
♦ Space-Saving 16-Pin QSOP Package
♦ Pin-Compatible 13-Bit Upgrades Available
The serial interface is compatible with SPI™, QSPI™, and
MICROWIRE™, which makes the MAX5122/MAX5123
suitable for cascading multiple devices. Each DAC has
a double-buffered input organized as an input register
followed by a DAC register. A 16-bit shift register loads
data into the input register. The DAC register may be
updated independently or simultaneously with the input
register.
(MAX5132/MAX5133)
♦ Pin-Compatible 14-Bit Upgrades Available
(MAX5171/MAX5173)
Ord e rin g In fo rm a t io n
PIN-
PACKAGE
INL
(LSB)
Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) operating temperature range. For pin-compatible
14-bit upgrades, see the MAX5171/MAX5173 data sheet;
for the pin-compatible 13-bit version, see the MAX5132/
MAX5133 data sheet.
PART
TEMP. RANGE
MAX5122AEEE
MAX5122BEEE
MAX5123AEEE
MAX5123BEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
16 QSOP
±0.5
±1
±1
±2
Ap p lic a t io n s
Industrial Process Control
P in Co n fig u ra t io n
Automatic Test Equipment
TOP VIEW
FB
1
2
3
4
5
6
7
8
16 V
DD
Digital Offset and Gain Adjustment
Motion Control
OUT
15 REFADJ
14 REF
RSTVAL
PDL
Microprocessor-Controlled Systems
MAX5122
MAX5123
13 AGND
12 PD
CLR
CS
11 UPO
10 DOUT
DIN
SCLK
9 DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND...............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
QSOP (derate 8.00mW/°C above +70°C).....................667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V + 0.3V)
DD
FB, OUT to AGND ......................................-0.3V to (V + 0.3V)
DD
REF, REFADJ to AGND ..............................-0.3V to (V + 0.3V)
DD
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5122 (+5V)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier configured
DD
L
L
in unity-gain, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
/MAX5123
N
12
-0.5
-1
Bits
MAX5122A
MAX5123B
0.5
1
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
OS
-10
-3
10
3
GE
-0.2
3
MAX5122A
MAX5123B
10
30
250
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
4.5V ≤ V ≤ 5.5V
DD
Output Voltage
V
T
= +25°C
2.475
2.5
3
2.525
V
REF
A
MAX5122A
MAX5122B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
10
0.1
4
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
1
7
µV/µA
mA
OUT OUT
OUT
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
3
V
V
IH
Input Low Voltage
V
IL
0.8
1
Input Hysteresis
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
IN
= 0 or V
-1
DD
C
IN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
2
_______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
ELECTRICAL CHARACTERISTICS—MAX5122 (+5V) (continued)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier configured
DD
L
L
in unity-gain, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SYMBOL
CONDITIONS
MIN
-0.1
4.5
TYP
MAX
UNITS
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 2.5V
STEP
Output Voltage Swing (Note 4)
Current into FB
0 to V
V
DD
0
2
0.1
µA
ms
Time Required to Exit Shutdown
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-sec
V
SCLK
= 5Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
V
DD
5.5
600
20
V
I
DD
500
3
µA
µA
I
SHDN
ELECTRICAL CHARACTERISTICS—MAX5123 (+3V)
(V = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connected
DD
L
L
in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
12
-1
Bits
MAX5123A
MAX5123B
1
2
Integral Nonlinearity (Note 1)
INL
LSB
-2
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
OS
-10
-5
10
5
GE
-0.2
3
MAX5123A
MAX5123B
10
30
250
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
2.7V ≤ V ≤ 3.3V
DD
Output Voltage
V
T
= +25°C
1.237
1.25
3
1.263
V
REF
A
MAX5123A
MAX5123B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
10
0.1
4
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
1
7
µV/µA
mA
OUT OUT
OUT
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
2.2
V
V
IH
Input Low Voltage
V
IL
0.8
Input Hysteresis
V
HYS
200
mV
_______________________________________________________________________________________
3
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
ELECTRICAL CHARACTERISTICS—MAX5123 (+3V) (continued)
(V = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connected
DD
L
L
in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
Input Leakage Current
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
0.001
8
MAX
UNITS
µA
I
IN
V
IN
= 0 or V
DD
-1
1
C
pF
IN
DIGITAL OUTPUTS
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.4
0.1
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 1.25V
STEP
Output Voltage Swing (Note 4)
Current into FB
0 to V
V
DD
-0.1
0
2
µA
ms
Time Required to Exit Shutdown
/MAX5123
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-sec
V
SCLK
= 3Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
V
2.7
3.6
600
20
V
DD
I
DD
500
3
µA
µA
I
SHDN
TIMING CHARACTERISTICS—MAX5122 (+5V)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connected
DD
L
L
in unity-gain, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
PARAMETER
SCLK Clock Period
SYMBOL
CONDITIONS
MIN
100
40
40
40
0
TYP
MAX
UNITS
ns
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
t
ns
CH
t
ns
CL
t
ns
CSS
CSH
t
ns
t
DS
40
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation Delay Time
t
C
C
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay Time
t
= 200pF
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
100
CSW
4
_______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
TIMING CHARACTERISTICS—MAX5123 (+3V)
(V = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connected
DD
L
L
in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SCLK Clock Period
SYMBOL
CONDITIONS
MIN
150
75
75
60
0
TYP
MAX
UNITS
ns
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
t
ns
CH
t
ns
CL
t
ns
CSS
CSH
t
ns
t
DS
60
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation Delay Time
t
C
C
= 200pF
200
200
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay Time
t
= 200pF
t
10
75
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
150
CSW
Note 1: Accuracy is guaranteed by the following table:
Accuracy Guaranteed
From Code: To Code:
16 4095
33 4095
V
DD
(V)
5
3
Note 2: Offset is measured at the code closest to 10mV.
Note 2: The temperature coefficient is determined by the “box” method, in which the maximum ∆V
over the temperature range
OUT
is divided by ∆T and the typical reference voltage.
Note 4: Accuracy is better than 1.0LSB for V = 10mV to (V - 180mV). Guaranteed by PSR test on end points.
OUT
DD
Note 5: R
= ∞and digital inputs are at either V or DGND.
DD
LOAD
_______________________________________________________________________________________
5
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, R = 5kΩ, C = 100pF, output amplifier in unity-gain configuration, T = +25°C, unless otherwise noted.)
DD
L
L
A
MAX5122
MAX5122
MAX5122
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
REFERENCE VOLTAGE vs. TEMPERATURE
0.20
2.510
2.505
2.500
2.495
2.490
0.20
0.15
0.10
0.05
0
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
-0.15
-0.20
0
1,000
2,000
3,000
4,000
5,000
-60 -40 -20
0
20 40 60 80 100
0
1,000
2,000
3,000
4,000
5,000
/MAX5123
DIGITAL INPUT CODE
TEMPERATURE (°C)
DIGITAL INPUT CODE
MAX5122
MAX5122
MAX5122
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
500
450
400
350
300
250
200
2.00
1.75
1.50
1.25
500
450
400
350
300
250
(CODE = AAA HEX)
(CODE = 000 HEX)
(CODE = AAA HEX)
(CODE = 000 HEX)
1.00
0.75
0.50
0.25
0
-60 -40 -20
0
20 40 60 80 100
4.0
4.5
5.0
5.5
6.0
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
MAX5122
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5122
MAX5122
FULL-SCALE OUTPUT ERROR vs. RESISTIVE LOAD
DYNAMIC RESPONSE RISE TIME
MAX5122/23-09
2.510
2.505
R = 5kΩ
L
0.25
CS
5V/div
C = 100pF
L
-0.50
2.500
2.495
2.490
OUT
1V/div
-1.25
-2.00
2µs/div
0.1
1
10
100
-60 -40 -20
0
20 40 60 80 100
R (kΩ)
L
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, R = 5kΩ, C = 100pF, output amplifier in unity-gain configuration, T = +25°C, unless otherwise noted.)
DD
L
L
A
MAX5122
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5122
MAJOR CARRY TRANSITION
MAX5122
DYNAMIC RESPONSE FALL TIME
MAX5122/23-11
MAX5122/23-12
MAX5122/23-10
SCLK
2V/div
CS
2V/div
CS
5V/div
OUT
1V/div
OUT
OUT
1mV/div
AC COUPLED
100mV/div
AC COUPLED
2µs/div
5µs/div
2µV/div
MAX5123
MAX5123
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
MAX5123
REFERENCE VOLTAGE vs. TEMPERATURE
0.25
0.15
0.10
0.05
0
1.260
1.255
1.250
1.245
1.240
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
0
1,000
2,000
3,000
4,000
5,000
0
1,000
2,000
3,000
4,000
5,000
-60 -40 -20
0
20 40 60 80 100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (°C)
MAX5123
MAX5123
MAX5123
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
400
350
300
250
0.5
0.4
400
350
300
(CODE = AAA HEX)
(CODE = AAA HEX)
0.3
0.2
0.1
(CODE = 000 HEX)
(CODE = 000 HEX)
250
200
200
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
2.50
2.75
3.00
3.25
3.50
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, R = 5kΩ, C = 100pF, output amplifier in unity-gain configuration, T = +25°C, unless otherwise noted.)
DD
L
L
A
MAX5123
MAX5123
MAX5123
DYNAMIC-RESPONSE RISE TIME
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
FULL-SCALE OUTPUT ERROR
vs. RESISTIVE LOAD
MAX5122/23-21
1.260
0
-1
-2
CS
2V/div
1.255
1.250
1.245
1.240
OUT
400mV/div
-3
-4
/MAX5123
-60 -40 -20
0
20 40 60 80 100
1µs/div
0.01
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
MAX5123
DYNAMIC-RESPONSE FALL TIME
MAX5123
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5123
MAJOR CARRY TRANSITION
MAX5122/23-22
MAX5122/23-23
MAX5122/23-24
SCLK
2V/div
CS
2V/div
CS
2V/div
OUT
500µV/div
AC COUPLED
OUT
100mV/div
AC COUPLED
OUT
400mV/div
1µs/div
2µs/div
5µV/div
8
_______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
P in De s c rip t io n
PIN
1
NAME
FUNCTION
FB
Amplifier Inverting Sense Input (Analog Input)
2
OUT
Analog Output Voltage. High impedance if part is in shutdown.
Reset Value Input (Digital Input).
3
RSTVAL
1: Connect to V to select midscale as the output reset value.
DD
0: Connect to DGND to select 0V as the output reset value.
Power-Down Lockout (Digital Input).
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
4
5
PDL
CLR
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
6
7
Active-Low Chip-Select Input (Digital Input)
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Clock Input
CS
DIN
8
SCLK
DGND
DOUT
UPO
9
Digital Ground
10
11
Serial Data Output
User-Programmable Output (Digital Output)
Power-Down Input (Digital Input). Pulling PD high when PDL = V places the IC into shutdown with a maxi-
mum shutdown current of 20µA.
DD
12
13
PD
AGND
Analog Ground
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5122) or +1.25V (MAX5123) nominal output, externally adjustable at REFADJ. In external reference
14
REF
mode, disable the internal reference by pulling REFADJ to V and applying the external reference to REF.
DD
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to V when using an
DD
external reference.
15
16
REFADJ
V
DD
Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.
_______________________________________________________________________________________
9
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
DIN
V
DD
AGND DGND
CS
SCLK
PDL
PD
SR
CONTROL
16-BIT
SHIFT REGISTER
DOUT
UPO
LOGIC
OUTPUT
RSTVAL
CLR
DECODE
CONTROL
FB
12
INPUT
REGISTER
DAC
REGISTER
MAX5122
MAX5123
DAC
OUT
/MAX5123
2X
(X1)
2.5V (1.25V)
BANDGAP 1.25V
REFERENCE
4k
REFERENCE
BUFFER
REFADJ
REF
( ) ARE FOR MAX5123 ONLY.
Figure 1. Simplified Functional Diagram
_______________De t a ile d De s c rip t io n
The MAX5122/MAX5123 12-bit, force/sense DACs are
easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have
a double-buffered digital input consisting of an input
register and a DAC register. In addition, these devices
employ precision bandgap references, as well as an
output amplifier with accessible feedback and output
pins that can be used to set the gain externally (Figure
1) or for forcing and sensing applications. These DACs
are designed with an inverted R-2R ladder network
(Figure 2) that produces a weighted voltage proportion-
al to the digital input code.
FB
OUT
R
R
R
2R
D0
2R
D9
2R
D10
2R
2R
D11
REF*
In t e rn a l Re fe re n c e
Both devices use an on-board precision bandgap ref-
e re nc e with a low te mp e ra ture c oe ffic ie nt of only
10ppm/°C (max) to generate an output voltage of +2.5V
(MAX5122) or +1.25V (MAX5123). The REF pin can
source up to 100µA and may become unstable with
capacitive loads exceeding 100pF. REFADJ can be
used for minor adjustments to the reference voltage.
AGND
*INTERNAL REFERENCE: +2.5V (MAX5122),
+1.25V (MAX5123); OR EXTERNAL REFERENCE
NOTE: SHOWN FOR ALL 1s ON DAC.
Figure 2. Simplified Inverted R-2R DAC Structure
10 ______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
The circuit in Figure 3 achieves a nominal reference
Ou t p u t Am p lifie r
The MAX5122/MAX5123’s DAC outp ut is inte rna lly
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
inp ut (FB) p rovid e s the us e r g re a te r fle xib ility with
a mp lifie r g a in s e tting a nd s ig na l c ond itioning (s e e
Applications Information).
adjustment range of ±1%. Connect a 33nF capacitor
from REFADJ to AGND to establish low-noise DAC
operation. Larger capacitor values may be used, but
will result in increased start-up delay. The time constant
(τ) for the start-up delay is determined by the REFADJ
input impedance of 4kΩ and C
:
REFADJ
τ= 4kΩ · C
The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20µs when it is connected in
REFADJ
Ex t e rn a l Re fe re n c e
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
unity gain and loaded with 5kΩ
100pF. Loads less
than 1kΩ may result in degraded performance.
V
. This allows an external reference signal (AC- or
P o w e r-Do w n Mo d e
DD
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of 0
to (V - 1.4V) for V
These devices feature software- and hardware-pro-
grammable (PD pin) shutdown modes that reduce the
typical supply current to 3µA. To enter software shut-
down mode, program the control sequence for the DAC
as shown in Table 1.
.
DD
REF
Determine the output voltage using the following equa-
tion (REFADJ = V ):
DD
In shutdown mode, the amplifier output becomes high-
impedance and the serial interface remains active.
Da ta in the inp ut re g is te rs is s a ve d , a llowing the
MAX5122/MAX5123 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC regis-
ters simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
V
= V
[(NB / 4096) G]
OUT
REF
whe re NB is the nume ric va lue of the MAX5122/
MAX5123 input code (0 to 4095), V is the external
re fe re nc e volta g e , a nd G is the g a in of the outp ut
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40kΩ and is
code-dependent.
REF
+3V
+5V
15k
MAX5123
90k
MAX5122
400k
400k
100k
100k
REFADJ
REFADJ
33nF
33nF
Figure 3a. MAX5122 Reference Adjust Circuit
Figure 3b. MAX5123 Reference Adjust Circuit
______________________________________________________________________________________ 11
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
S0*
S0*
FUNCTION
C2
C1
C0
D11 ............... D0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
0
1
1
XXXXXXXXXXXX
12-Bit DAC Data
12-Bit DAC Data
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
1XXXXXXXXXXX
00XXXXXXXXXX
0
0
0
0
0
0
0
0
0
No operation.
Load input register; DAC register unchanged.
Simultaneously load input and DAC registers; exit shutdown.
Update DAC register from input register; exit shutdown.
Shutdown DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1; DOUT clocked out on SCLK’s rising edge.
Mode 0; DOUT clocked out on SCLK’s falling edge (default).
X = Don’t care * S0 is a sub-bit and always zero.
/MAX5123
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
V
DD
SS
DIN
MOSI
SCK
Power-Down Input (PD)
Pulling PD high places the MAX5122/MAX5123 in shut-
d own. Pulling PD low will not re turn the MAX5122/
MAX5123 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down mode.
SPI/QSPI
PORT
(PIC16/PIC17)
MAX5122
MAX5123
SCLK
CS
I/O
S e ria l-In t e rfa c e Co n fig u ra t io n
(S P I/QS P I/MICROWIRE/P IC1 6 /P IC1 7 )
The MAX5122/MAX5123 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-
byte-long serial input word contains three control bits,
12 data bits in MSB-first format, and one sub-bit, which
is always zero (Table 2).
CPOL = 0, CPHA = 0
(CKE = 1, CKP = 0, SMP= 0
SSPM3 - SSPM0 = 0001)
( ) ARE FOR PIC16/PIC17 ONLY.
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
The MAX5122/MAX5123’s digital inputs are double
buffered, which allows the user to:
SK
SO
I/O
SCLK
DIN
CS
•
•
•
Load the input register without updating the DAC
register,
MICROWIRE
PORT
MAX5122
MAX5123
Update the DAC register with data from the input
register,
Update the input and DAC registers concurrently.
Figure 5. MICROWIRE Interface Connections
12 ______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
The 16-bit input word may be sent in two 1-byte pack-
MAX5122 a nd 6.6MHz for the MAX5123. Fig ure 7
depicts a more detailed timing diagram of the serial
interface.
ets (SPI-, MICROWIRE-, and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (table 1) determine:
P IC1 6 w it h S S P Mo d u le
a n d P IC1 7 In t e rfa c e
• The clock edge on which DOUT transitions,
• The state of the user-programmable logic output,
• The configuration of the device after shutdown.
The MAX5122/MAX5123 a re c omp a tib le with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module. To establish SPI commu-
nication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by ini-
tializing its synchronous serial port control register (SSP-
CON) a nd s ync hronous s e ria l p ort s ta tus re g is te r
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the regis-
ter on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC regis-
ters, depending on the setting of the three control bits
C2, C1, and C0. The maximum serial clock frequency
g ua ra nte e d for p rop e r op e ra tion is 10MHz for the
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure
6) are necessary to feed the DAC with three control bits,
12 data bits, and one sub-bit. DIN data transitions on
the serial clock’s falling edge and is clocked into the
DAC on SCLK’s rising edge. The first eight bits of DIN
contain the three control bits (C2, C1, C0) and the first
five data bits (D11–D7). The second 8-bit data stream
contains the remaining bits (D6–D0), and the sub-bit S0.
Table 2. Serial Data Format
MSB ............................................................................... LSB
16 BITS OF SERIAL DATA
Control Bits
C2, C1, C0
MSB ..... Data Bits ..... LSB
D11................................D0
Sub-Bit
S0
CS
COMMAND
EXECUTED
SCLK
DIN
1
8
9
16
D5 D4 D3 D2 D1 D0 S0
C1
C0
D10 D9
C2
D11
D8 D7
D6
Figure 6. Serial-Interface Timing
t
CSW
CS
t
CSH
t
t
CSS
CS0
t
CS1
SCLK
t
CH
t
CL
t
CP
DIN
t
DS
t
DH
t
t
DO1
DO2
DOUT
Figure 7. Detailed Serial-Interface Timing
______________________________________________________________________________________ 13
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Table 3. Detailed SSPCON Register Contents
MAX5122/MAX5123
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
CONTROL BIT
WCOL
BIT7
BIT6
X
X
Write Collision Detection Bit
Receive Overflow Detect Bit
SSPOV
Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as serial-
port pins.
SSPEN
BIT5
1
CKP
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f
= f
/ 16
CLK
OSC
X = Don’t care
/MAX5123
Table 4. Detailed SSPSTAT Register Contents
MAX5130/MAX5131
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
CONTROL BIT
SETTINGS
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
SMP
CKE
BIT7
BIT6
0
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
D/A
P
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care
S e ria l Da t a Ou t p u t
Us e r-P ro g ra m m a b le Ou t p u t (UP O)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1) there-
by reducing the number of microcontroller I/O ports
required. During power-down, this output will retain the
last digital state before shutdown. With CLR pulled low,
UPO will reset to the default state after wake-up.
The contents of the internal shift-register are output
serially on DOUT which allows for daisy-chaining of
multiple devices (see Applications Information) as well
as data readback. The MAX5122/MAX5123 may be
programmed to shift data out of DOUT on the serial
clock’s rising edge (Mode 1) or on the falling edge
(Mode 0). The latter is the default during power-up and
provides a lag of 16 clock cycles, maintaining SPI,
QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In
Mode 1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
14 ______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
1LSB. If the magnitude of the DNL is less than or equal
to 1LSB, the DAC guarantees no missing codes and is
monotonic.
__________Ap p lic a t io n s In fo rm a t io n
De fin it io n s
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
a lte rs the s lop e of the tra ns fe r func tion a nd c orre -
sponds to the same percentage error in each step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
7
6
ACTUAL
DIAGRAM
3
2
1
0
5
4
IDEAL DIAGRAM
OFFSET ERROR
AT STEP
O11 (1/2 LSB )
3
2
1
0
(+1 1/4 LSB)
AT STEP
001 (1/4 LSB )
ACTUAL
OFFSET POINT
IDEAL OFFSET
POINT
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
DIGITAL INPUT CODE
Figure 8a. Integral Nonlinearity
Figure 8c. Offset Error
IDEAL FULL-SCALE OUTPUT
6
5
4
7
GAIN ERROR
(-1 1/4 LSB)
1 LSB
6
5
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
IDEAL DIAGRAM
3
ACTUAL
FULL-SCALE
OUTPUT
1 LSB
2
1
0
DIFFERENTIAL
4
0
LINEARITY ERROR (+1/4 LSB)
000
001
010
011
100
101
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 8b. Differential Nonlinearity
______________________________________________________________________________________ 15
Figure 8d. Gain Error
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Settling Time
The settling time is the amount of time required from the
+5V/+3V
start of a transition until the DAC output settles to its
REF
new output value within the converter’s specified accu-
racy.
V
DD
50k
50k
MAX5122
MAX5123
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
la yout a nd g round ing will s ig nific a ntly re d uc e this
nois e , b ut the re will a lwa ys b e s ome fe e d throug h
caused by the DAC itself.
FB
DAC
OUT
AGND
DGND
Un ip o la r Ou t p u t
Figure 9 shows the MAX5122/MAX5123 setup for unipo-
lar, Rail-to-Rail operation with a closed- loop gain of
NOTE: GAIN = +2V/V
®
2V/V. With its internal reference of +2.5V, the MAX5122
provides a convenient unipolar output range of 0 to
+4.99878V, while the MAX5123 offers an output range of
0 to +2.49939V with its on-board +1.25V reference.
Table 5 lists example codes for unipolar output voltages.
Figure 9. Unipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to V
/MAX5123
.
DD
Bip o la r Ou t p u t
The MAX5122/MAX5123 can be configured for unity-
gain bipolar operation (FB = OUT) using the circuit
+5V/+3V
50k
FB
50k
V+
REF
V
DD
shown in Figure 10. The output voltage V
is then
OUT
given by the following equation:
MAX5122
MAX5123
V
OUT
= V [{G (NB / 4096)} - 1]
REF
where NB is the numeric value of the DAC’s binary
input code, V is the voltage of the internal (or exter-
V
OUT
DAC
REF
OUT
nal) precision reference, and G is the overall gain. The
application circuit in Figure 10 uses a low-cost op amp
(MAX4162) e xte rna l to the MAX5122/MAX5123.
Together with the MAX5122/MAX5123 this circuit offers
an overall gain of +2V/V. Table 6 lists example codes
for bipolar output voltages.
MAX4162
V-
AGND
DGND
Figure 10. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
Re s e t (RS TVAL) a n d
pull REFADJ to V
.
DD
CLR
Cle a r (
) Fu n c t io n s
The MAX5122/MAX5123 DACs feature a clear pin (CLR),
which resets the output to a certain value, depending
upon how RSTVAL is set. RSTVAL = DGND selects an
Da is y-Ch a in in g De vic e s
Any number of MAX5122/MAX5123s may be daisy-
chained by simply connecting the serial data output pin
(DOUT) of one device to the serial data input pin (DIN)
of the following device in the chain (Figure 11).
output of 0, and RSTVAL = V selects a midscale out-
DD
put when CLR is pulled low.
The CLR pin has a minimum input resistance of 40kΩ in
series with a diode to the supply voltage (V ). If the
DD
Anothe r c onfig ura tion (Fig ure 12) a llows s e ve ra l
MAX5122/MAX5123 DACs to share one common DIN
signal line. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy-chain.
However, more I/O lines are required in this configura-
tion, because each IC needs a dedicated CS line.
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
be limited to (V
- V - 0.5V) / 40kΩ.
CLR
DD
Note: Clearing the DAC will also cause the part to exit
a software shutdown (PD = 0).
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
16 ______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
Table 5. Unipolar Code Table (Gain = +1.6384V/V)
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
MAX5122 MAX5123
SUB-BIT
S0
EXTERNAL REFERENCE
MAX5122/MAX5123
MSB
LSB
1111 1111 1111
0
0
0
0
0
0
+4.99878V
+2.50122V
+2.5V
+2.49939V
+1.25061V
+1.25V
V
(4095 / 4096) 2
(2049 / 4096) 2
(2048 / 4096) 2
(2047 / 4096) 2
REF
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
V
REF
V
REF
+2.49878V
+1.2207mV
0V
+1.24939V
+610.35µV
0V
V
REF
V
(1 / 4096) 2
0
REF
Table 6. Bipolar Code Table (Figure 10)
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
SUB-BIT
S0
EXTERNAL REFERENCE
MAX5122/MAX5123
MSB
LSB
MAX5122
+2.49878V
+1.2207mV
0V
MAX5123
+1.24939V
+610.35µV
0V
1111 1111 1111
0
0
0
0
0
0
V
[ {2 (4095 / 4096)} - 1]
[ {2 (2049 / 4096)} - 1]
[ {2 (2048 / 4096)} - 1]
[ {2 (2047 / 4096)} - 1]
REF
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
V
REF
V
REF
-1.2207mV
-2.49878V
-2.5V
-610.35µV
-1.24939V
-1.25V
V
REF
V
REF
[ {2 (1 / 4096)} - 1]
-V
REF
SCLK
SCLK
SCLK
I
II
III
MAX5122
MAX5123
MAX5122
MAX5123
MAX5122
MAX5123
DIN
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
CS
TO OTHER
SERIAL DEVICES
Figure 11. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
______________________________________________________________________________________ 17
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
V
). Bypass the power supply (V ) with a 4.7µF
DD
Us in g a n Ex t e rn a l Re fe re n c e
w it h AC Co m p o n e n t s
The MAX5122/MAX5123 have multiplying capabilities
within the reference input voltage range specifications.
Figure 13 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.
DD
capacitor in parallel with a 0.1µF capacitor to AGND.
Minimize lead lengths to reduce lead inductance.
La yo u t Co n s id e ra t io n s
Digital and AC signals coupling to AGND can create
noise at the output. Connect AGND to the highest quali-
ty ground available. Use proper grounding techniques,
s uc h a s a multila ye r b oa rd with a low-ind uc ta nc e
ground plane. Wire-wrapped boards and sockets are
not recommended. If noise becomes an issue, shield-
ing may be required.
P o w e r-S u p p ly a n d Byp a s s in g
Co n s id e ra t io n s
On power-up, the input and DAC registers are cleared to
either zero (RSTVAL = DGND) or midscale (RSTVAL =
DIN
SCLK
CS1
/MAX5123
CS2
TO OTHER
SERIAL DEVICES
CS3
I
II
III
CS
CS
CS
MAX5122
MAX5123
MAX5122
MAX5123
MAX5122
MAX5123
SCLK
SCLK
SCLK
DIN
DIN
DIN
Figure 12. Multiple Devices Share One Common Digital Input (DIN)
___________________Ch ip In fo rm a t io n
+5V/
+3V
TRANSISTOR COUNT: 3308
+5V/+3V
26k
AC
REFERENCE
SUBSTRATE CONNECTED TO AGND
MAX495
INPUT
10k
500mVp-p
V
DD
REF
FB
DAC
OUT
MAX5122
MAX5123
AGND
DGND
Figure 13. External Reference with AC Components
18 ______________________________________________________________________________________
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
/MAX5123
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 19
+5 V/+3 V, 1 2 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
NOTES
/MAX5123
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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