MAX5130BEEE+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX5130BEEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1429; Rev 0; 2/99
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX5130/MAX5131 are low-power, 13-bit, voltage-
output digital-to-analog converters (DACs) with an inter-
nal precision bandgap reference and output amplifier.
The MAX5130 operates on a single +5V supply with an
internal reference of +2.5V, and is capable of a +4.0955V
full-scale output. If necessary, the user can override the
on-chip, <10ppm/°C voltage reference with an external
reference. The MAX5131, operating on +3V, delivers its
+2.04775V full-scale output with an internal precision ref-
erence of +1.25V. Both devices draw only 500µA of sup-
ply current, which reduces to 3µA in power-down mode.
In addition, their power-up reset feature allows for a user-
selectable initial output state of either 0V or midscale and
minimizes output voltage glitches during power-up.
♦ Single-Supply Operation
+5V (MAX5130)
+3V (MAX5131)
♦ Full-Scale Output Range
+4.0955V (MAX5130)
+2.04775V (MAX5131)
♦ Built-In 10ppm/°C (max) Precision Bandgap
Reference
+2.5V (MAX5130)
+1.25V (MAX5131)
♦ Adjustable Output Offset
The serial interface is compatible with SPI™, QSPI™, and
MICROWIRE™, which makes the MAX5130/MAX5131
suitable for cascading multiple devices. Each DAC has a
double-buffered input organized as an input register fol-
lowed by a DAC register. A 16-bit shift register loads data
into the input register. The DAC register may be updated
independently or simultaneously with the input register.
♦ SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
♦ Pin-Programmable Shutdown Mode and Power-
Up Reset (0V or Midscale Output Voltage)
♦ Buffered Output Capable of Driving 5kΩ || 100pF
Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) temperature range. For pin-compatible 14-bit
up g ra d e s , s e e the MAX5170/MAX5172 d a ta s he e t;
for pin-compatible 12-bit versions, see the MAX5120/
MAX5121 data sheet.
or 4–20mA Loads
♦ Space-Saving 16-Pin QSOP Package
♦ Pin-Compatible Upgrades to the 12-Bit
MAX5120/MAX5121
♦ Pin-Compatible 14-Bit Upgrades Available
Ap p lic a t io n s
(MAX5170/MAX5172)
Industrial Process Control
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Motion Control
µP-Controlled Systems
P in Co n fig u ra t io n
Ord e rin g In fo rm a t io n
PIN-
PACKAGE
INL
(LSB)
PART
TEMP. RANGE
TOP VIEW
OS
OUT
1
2
3
4
5
6
7
8
16 V
DD
MAX5130AEEE
MAX5130BEEE
MAX5131AEEE
MAX5131BEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
16 QSOP
±0.5
±1
15 REFADJ
14 REF
RSTVAL
PDL
±1
±2
MAX5130
MAX5131
13 AGND
12 PD
CLR
CS
11 UPO
10 DOUT
DIN
SCLK
9 DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND...............................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
QSOP (derate 8.00mW/°C above +70°C).....................667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V + 0.3V)
DD
OUT to AGND.............................................-0.3V to (V + 0.3V)
DD
OS to AGND ...................................(AGND - 4V) to (V + 0.3V)
DD
REF, REFADJ to AGND ..............................-0.3V to (V + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5130 (+5V)
(V = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
0/MAX531
Resolution
N
13
-0.5
-1
Bits
MAX5130A
MAX5130B
0.5
1
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
V
OS
-10
-3
10
3
GE
-0.2
Full-Scale Voltage
V
FS
Code = 1FFF hex, T = +25°C
A
4.0463 4.0955 4.1447
MAX5130A
MAX5130B
3
30
50
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
4.5V ≤ V ≤ 5.5V
250
DD
Output Voltage
V
T
= +25°C
2.5
16
24
0.1
4
V
REF
A
MAX5130A
MAX5130B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
1
7
µV/µA
mA
OUT OUT
OUT
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
3
V
V
IH
Input Low Voltage
V
IL
0.8
1
Input Hysteresis
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
IN
= 0 or V
-1
DD
C
IN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
2
_______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
ELECTRICAL CHARACTERISTICS—MAX5130 (+5V) (continued)
(V = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 4V
STEP
Output Voltage Swing (Note 4)
OS Input Resistance
0 to V
V
DD
R
83
121
2
kΩ
ms
OS
Time Required to Exit Shutdown
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
V
SCLK
= 5Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
V
4.5
5.5
600
20
V
DD
I
DD
500
3
µA
µA
I
SHDN
ELECTRICAL CHARACTERISTICS—MAX5131 (+3V)
(V = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
13
-1
Bits
MAX5131A
MAX5131B
1
2
Integral Nonlinearity (Note 1)
INL
LSB
-2
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
V
OS
-10
-5
10
5
R
= ∞
GE
-0.2
L
Full-Scale Voltage
V
FS
Data = 1FFF hex, T = +25°C
A
2.02317 2.04775 2.07232
MAX5131A
MAX5131B
3
10
30
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
2.7V ≤ V ≤ 3.3V
250
DD
Output Voltage
V
T
= +25°C
1.25
3
V
REF
A
MAX5131A
MAX5131B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
10
0.1
4
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
1
7
µV/µA
mA
OUT OUT
OUT
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
2.2
V
V
IH
Input Low Voltage
V
IL
0.8
Input Hysteresis
V
HYS
200
mV
_______________________________________________________________________________________
3
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
ELECTRICAL CHARACTERISTICS—MAX5131 (+3V) (continued)
(V = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.001
8
MAX
UNITS
µA
Input Leakage Current
Input Capacitance
I
IN
V
IN
= 0 or V
-1
1
DD
C
pF
IN
DIGITAL OUTPUTS
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.4
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 2V
STEP
Output Voltage Swing (Note 4)
OS Input Resistance
0 to V
V
DD
R
83
121
2
kΩ
ms
OS
Time Required to Exit Shutdown
0/MAX531
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
V
SCLK
= 3Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
V
2.7
3.6
60
20
V
DD
I
DD
500
3
µA
µA
I
SHDN
TIMING CHARACTERISTICS—MAX5130 (+5V)
(V = +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
100
40
40
40
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
t
ns
CH
t
ns
CL
t
ns
CSS
CSH
t
ns
t
DS
40
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation Delay Time
t
C
C
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay Time
t
= 200pF
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
100
CSW
4
_______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
TIMING CHARACTERISTICS—MAX5131 (+3V)
(V = +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, T = T
DD
to
L
L
A
MIN
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
150
75
75
60
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
t
ns
CH
t
ns
CL
t
ns
CSS
CSH
t
ns
t
DS
60
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation Delay Time
t
C
= 200pF
200
200
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay Time
t
C
= 200pF
t
10
75
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
150
CSW
Note 1: Accuracy is guaranteed as shown in the following table:
Accuracy Guaranteed
From Code: To Code:
20 8191
40 8191
V
DD
(V)
5
3
Note 2: Offset is measured at the code closest to 10mV.
Note 3: The temperature coefficient is determined by the “box” method in which the maximum ∆V
over the temperature range is
OUT
divided by ∆T.
Note 4: Accuracy is better than 1.0LSB for V
= 10mV to (V - 180mV). Guaranteed by PSR test on end points.
OUT
DD
Note 5: R
= ∞ and digital inputs are at either V or DGND.
DD
LOAD
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V (MAX5130), V = +3V (MAX5131), R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, unless otherwise noted.)
DD
DD
L
L
A
MAX5130
MAX5130
MAX5130
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
REFERENCE VOLTAGE
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
2.510
2.505
2.500
2.495
2.490
0.20
0.20
0.15
0.10
0.05
0
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
-0.15
-0.20
-60 -40 -20
0
20 40 60 80 100
0
2000
4000
6000
8000 10,000
0
2000
4000
6000
8000 10,000
TEMPERATURE (°C)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
_______________________________________________________________________________________
5
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V (MAX5130), V = +3V (MAX5131), R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, unless otherwise noted.)
DD
DD
L
L
A
MAX5130
MAX5130
MAX5130
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. TEMPERATURE
500
500
450
400
350
300
250
4.0
3.5
3.0
2.5
2.0
1.5
1.0
450
400
350
300
250
200
(CODE = 1555 HEX)
(CODE = 1555 HEX)
(CODE = 0000 HEX)
(CODE = 0000 HEX)
-60 -40 -20
0
20 40 60 80 100
4.0
4.5
5.0
5.5
6.0
-60 -40 -20
0
20 40 60 80 100
0/MAX531
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
MAX5130
MAX5130
MAX5130
FULL-SCALE OUTPUT vs. TEMPERATURE
DYNAMIC RESPONSE RISE TIME
FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5130/31-09
4.099
4.098
4.097
4.096
4.095
4.094
4.093
0.5
0
CS
5V/div
R = 5kΩ
L
C = 100pF
L
-0.5
-1.0
OUT
1V/div
-1.5
-2.0
-2.5
-3.0
-60 -40 -20
0
20 40 60 80 100
0.1
1
10
100
5µs/div
TEMPERATURE (°C)
RESISTOR (kΩ)
MAX5130
MAJOR CARRY TRANSITION
MAX5130
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5130
DYNAMIC RESPONSE FALL TIME
MAX5130/31-12
MAX5130/31-11
MAX5130/31-10
SCLK
2V/div
CS
2V/div
CS
5V/div
OUT
1V/div
OUT
OUT
100mV/div
AC COUPLED
1mV/div
AC COUPLED
5µs/div
2µs/div
5µV/div
6
_______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V (MAX5130), V = +3V (MAX5131), R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, unless otherwise noted.)
DD
DD
L
L
A
MAX5131
MAX5131
MAX5131
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
REFERENCE VOLTAGE
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
0.25
0.15
1.250
1.248
1.246
1.244
1.242
1.240
0.3
0.2
0.1
0
0.05
-0.05
-0.15
-0.25
-0.1
-0.2
-0.3
0
2000
4000
6000
8000 10,000
0
2000
4000
6000
8000 10,000
-60 -40 -20
0
20 40 60 80 100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (°C)
MAX5131
MAX5131
MAX5131
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. TEMPERATURE
400
350
1.0
0.8
0.6
0.4
0.2
0
400
375
350
325
300
275
250
CODE = 1555 HEX
CODE = 1555 HEX
300
250
200
CODE = 0000 HEX
150
100
CODE = 0000 HEX
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
2.5
2.7
2.9
3.1
3.3
3.5
3.7
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
MAX5131
MAX5131
MAX5131
FULL-SCALE OUTPUT vs. TEMPERATURE
FULL-SCALE OUTPUT vs. RESISTIVE LOAD
DYNAMIC RESPONSE RISE TIME
MAX5130/31-21
2.046
2.044
2.042
2.040
2.038
2.036
0.5
0
R = 5kΩ
C = 100pF
L
L
CS
2V/div
-0.5
-1.0
-1.5
OUT
500mV/div
-60 -40 -20
0
20 40 60 80 100
0.1
1
10
100
2µs/div
TEMPERATURE (°C)
RESISTOR (kΩ)
_______________________________________________________________________________________
7
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V (MAX5130), V = +3V (MAX5131), R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, unless otherwise noted.)
DD
DD
L
L
A
MAX5131
MAJOR CARRY TRANSITION
MAX5131
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5131
DYNAMIC RESPONSE FALL TIME
MAX5130/31-24
MAX5130/31-23
MAX5130/31-22
CS
2V/div
SCLK
2V/div
CS
2V/div
OUT
OUT
OUT
100mV/div
AC COUPLED
500µV/div
AC COUPLED
500mV/div
0/MAX531
5µs/div
2µs/div
2µs/div
P in De s c rip t io n
PIN
NAME
FUNCTION
1
2
OS
Offset Adjust (Analog Input)
OUT
Analog Output Voltage. High impedance if part is in shutdown.
Reset Value Input (Digital Input)
3
RSTVAL
1: Tie to V to select midscale as the output reset value.
DD
0: Tie to DGND to select 0V as the output reset value.
Power-Down Lockout (Digital Input)
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
4
5
PDL
CLR
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
6
7
Active-Low Chip-Select Input (Digital Input)
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Clock Input
CS
DIN
8
SCLK
DGND
DOUT
UPO
9
Digital Ground
10
11
Serial Data Output
User-Programmable Output (Digital Output)
Power-Down Input (Digital Input). Pulling PD high when PDL = V places the IC into shutdown with a
maximum shutdown current of 20µA.
DD
12
13
PD
AGND
Analog Ground
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5130) or +1.25V (MAX5131) nominal output, externally adjustable at REFADJ. In external reference
14
REF
mode, disable the internal reference by pulling REFADJ to V and applying the external reference to REF.
DD
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to V when using an
DD
external reference.
15
16
REFADJ
V
DD
Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.
8
_______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
CS DIN SCLK
V
DD
AGND DGND
PDL
PD
SR
CONTROL
16-BIT
SHIFT REGISTER
DOUT
LOGIC
OUTPUT
UPO
OS
R
RSTVAL
CLR
DECODE
CONTROL
13
0.6384R
INPUT
REGISTER
DAC
REGISTER
MAX5130
MAX5131
OUT
DAC
GAIN = 1.6384X
2X
(1X)
2.5V, (1.25V)
BANDGAP 1.25V
REFERENCE
4k
REFERENCE
BUFFER
( ) FOR MAX5131 ONLY
REFADJ
REF
Figure 1. Simplified Functional Block Diagram
_______________De t a ile d De s c rip t io n
The MAX5130/MAX5131 13-bit, voltage-output DACs
are easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have
a double-buffered input consisting of an input register
and a DAC register. In addition, these devices employ
precision bandgap references and trimmed internal
resistors to produce a gain of 1.6384V/V, maximizing
the output voltage swing (Figure 1). The MAX5130/
MAX5131 output amplifier’s offset-adjust pin allows for
a DC shift in the DAC outputs. The full-scale output volt-
age is +4.0955V for the MAX5130 and +2.04775V for
the MAX5131. These DACs are designed with an invert-
ed R-2R ladder network (Figure 2) that produces a
weighted output voltage proportional to the digital input
code.
OS
R
0.6384R
OUT
R
R
R
2R
D0
2R
D10
2R
D11
2R
2R
D12
REF*
In t e rn a l Re fe re n c e
Both the MAX5130 and MAX5131 use an on-board pre-
cision bandgap reference to generate an output volt-
age of +2.5V (MAX5130) or +1.25V (MAX5131). With a
low temperature coefficient of only 10ppm/°C (max),
the REF pin can source up to 100µA and may become
uns ta b le with c a p a c itive loa d s e xc e e d ing 100p F.
REFADJ can be used for minor adjustments (1%) to the
AGND
SHOWN FOR ALL 1s ON DAC
*INTERNAL 2.5V (MAX5130) AND 1.25V (MAX5131) OR EXTERNAL REFERENCE.
Figure 2. Simplified Inverted R-2R DAC Structure
_______________________________________________________________________________________
9
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
reference voltage. Use the circuits shown in Figure 3a
(MAX5130) and Figure 3b (MAX5131) to achieve these
adjustments. Connect a 33nF capacitor from REFADJ
to AGND to establish low-noise operation of the DAC.
Larger capacitor values may be used, but will result in
increased start-up delay. The time constant (τ) for the
s ta rt-up d e la y is d e te rmine d b y the REFADJ inp ut
buffer gain, the MAX5131 achieves a full-scale output
of +2.04775V, while the MAX5130 provides a +4.0955V
full-scale output with a +2.5V reference.
The output amplifier has a typical slew rate of 0.6V/µs
and settles to ±0.5LSB within 20µs, with a load of 5kΩ
in parallel with 100pF. Loads less than 1kΩ may result
in degraded performance.
impedance of 4kΩ and C
:
REFADJ
The OS pin may be used to adjust the output offset volt-
a g e . For ins ta nc e , to a c hie ve a + 1V offs e t, a p p ly
τ = 4kΩ · C
REFADJ
-1.566V (Offset = -[Output Buffer Gain - 1] · V ) to OS
to produce an output voltage range from +1V to (1V +
OS
Ex t e rn a l Re fe re n c e
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
V
REF
· 1.6384V/V). Note that the DAC’s output range is
still limited by the maximum output voltage specification.
V
DD
. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of
P o w e r-Do w n Mo d e
The MAX5130/MAX5131 feature software- and hard-
ware-programmable (PD pin) shutdown modes that
reduce the typical supply current to 3µA. To enter soft-
ware shutdown mode, program the control sequence
for the DAC as shown in Table 1.
0V to (V - 1.4V) for V
.
DD
REF
Determine the output voltage using the following equa-
tion (REFADJ = V ; OS = AGND):
0/MAX531
DD
V
OUT
= [V
· (NB / 8192)] · 1.6384V/V
REF
In shutdown mode, the amplifier output becomes high-
impedance and the serial interface remains active.
Da ta in the inp ut re g is te rs is s a ve d , a llowing the
MAX5130/MAX5131 to recall the output state prior to
entering shutdown when returning to normal operation
mode. To exit shutdown mode, load both input and
DAC registers simultaneously or update the DAC regis-
ter from the input register. When returning from shut-
down mode, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
whe re NB is the nume ric va lue of the MAX5130/
MAX5131 input code (0 to 8191), V is the external
reference voltage, and 1.6384V/V is the gain of the
internal output amplifier. The REF pin has a minimum
input resistance of 40kΩ and is code-dependent.
REF
Ou t p u t Am p lifie r
The outp ut a mp lifie r of the MAX5130/MAX5131
employs a trimmed resistor-divider to set a gain of
+1.6384V/V and minimize the gain error. With its on-
board laser-trimmed +1.25V reference and the output
+3V
+5V
15k
MAX5131
90k
MAX5130
400k
400k
100k
100k
REFADJ
REFADJ
33nF
33nF
Figure 3a. MAX5130 Reference Adjust Circuit
Figure 3b. MAX5131 Reference Adjust Circuit
10 ______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
C2
C1
C0
D12 ............... D0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
0
1
1
XXXXXXXXXXXXX
13-Bit DAC Data
13-Bit DAC Data
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
1XXXXXXXXXXXX
00XXXXXXXXXXX
No operation.
Load input register; DAC register unchanged.
Simultaneously load input and DAC registers; exit shutdown.
Update DAC register from input register; exit shutdown.
Shutdown DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1; DOUT clocked out on SCLK’s rising edge.
Mode 0; DOUT clocked out on SCLK’s falling edge (default).
X = Don’t care
Power-Down Lockout Input (PDL)
V
DD
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
SS
Power-Down Input (PD)
Pulling PD high places the MAX5130/MAX5131 in shut-
down mode. Pulling PD low will not return the MAX5130/
MAX5131 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down.
DIN
MOSI
SCK
SPI/QSPI
PORT
(PIC16/PIC17)
MAX5130
MAX5131
SCLK
CS
I/O
S e ria l-In t e rfa c e Co n fig u ra t io n
(S P I/QS P I/MICROWIRE/P IC1 6 /P IC1 7 )
The MAX5130/MAX5131 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-byte-
long serial input word contains three control bits and 13
data bits in MSB-first format (Table 2).
( ): PIC16/PIC17 ONLY
CPOL = 0, CPHA = 0
(CHE = 1, CKP = 0, SMP = 0,
SSPM3–SSPM0 = 0001)
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
The MAX5130/MAX5131’s digital inputs are double
buffered, which allows the user to:
•
•
•
Load the input register without updating the DAC
register,
SK
SO
I/O
SCLK
DIN
CS
MICROWIRE
PORT
Update the DAC register with data from the input
register,
MAX5130
MAX5131
Update the input and DAC registers concurrently.
Figure 5. MICROWIRE Interface Connections
______________________________________________________________________________________ 11
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
The 16-bit input word may be sent in two 1-byte pack-
ets (SPI-, MICROWIRE- and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (Table 1) determine:
P IC1 6 w it h S S P Mo d u le a n d
P IC1 7 In t e rfa c e
The MAX5130/MAX5131 a re c omp a tib le with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by
initializing its synchronous serial port control register
(SSPCON) and synchronous serial port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
•
The clock edge on which DOUT is to be clocked out
via the serial interface,
•
•
The state of the user-programmable logic output,
The configuration of the device after shutdown.
The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the regis-
ter on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC registers,
depending on the setting of the three control bits C2,
C1, and C0. The maximum serial clock frequency guar-
anteed for proper operation is 10MHz for the MAX5130
and 6.6MHz for the MAX5131. Figure 7 depicts a more
detailed timing diagram of the serial interface.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be transmitted synchronously and received simulta-
neously. Two consecutive 8-bit writings (Figure 6) are
necessary to feed the DAC with three control bits and
13 data bits. DIN data transitions on the serial clock’s
falling edge and is clocked into the DAC on SCLK’s ris-
ing edge. The first 8 bits on DIN contain the three con-
trol bits (C2, C1, and C0) and the first five data bits
(D12–D8). The second 8-bit word contains the remain-
ing bits (D7–D0).
0/MAX531
Table 2. Serial Data Format
MSB ............................................................................... LSB
16 BITS OF SERIAL DATA
Control Bits
C2, C1, C0
MSB ..... Data Bits ..... LSB
D12................................D0
CS
COMMAND
EXECUTED
SCLK
DIN
1
8
9
16
D6 D5 D4 D3 D2 D1 D0
C1
C0
D11 D10
D9 D8
C2
D12
D7
Figure 6. Serial-Interface Timing
t
CSW
CS
t
CSH
t
t
CSS
CS0
t
CS1
SCLK
t
CH
t
CL
t
CP
DIN
t
DS
t
DH
t
t
DO1
DO2
DOUT
Figure 7. Detailed Serial-Interface Timing
12 ______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
Table 3. Detailed SSPCON Register Contents
MAX5130/MAX5131
SETTING
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
CONTROL BIT
WCOL
BIT7
BIT6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detection Bit
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as
serial-port pins.
SSPEN
BIT5
1
CKP
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f
= f
/ 16.
CLK
OSC
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
MAX5130/MAX5131
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPSTAT)
CONTROL BIT
SETTINGS
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
SMP
CKE
BIT7
BIT6
0
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
D/A
P
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care
S e ria l Da t a Ou t p u t
Us e r-P ro g ra m m a b le Ou t p u t (UP O)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after
wake-up.
The contents of the internal shift register are output
s e ria lly on DOUT, a llowing for d a is y-c ha ining (s e e
Applications Information) of multiple devices as well as
data readback. The MAX5130/MAX5131 may be pro-
g ra mme d to s hift d a ta out on DOUT on the s e ria l
clock’s rising edge (Mode 1) or falling edge (Mode 0).
The latter is the default during power-up and provides a
la g of 16 c loc k c yc le s , ma inta ining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the outp ut d a ta la g s DIN b y 15.5 c loc k c yc le s .
During power-down, DOUT retains its last digital state
prior to shutdown.
______________________________________________________________________________________ 13
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
__________Ap p lic a t io n s In fo rm a t io n
De fin it io n s
Offset Error
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
values on an actual transfer function from a straight
set point is the step value when the digital input is zero.
line. This straight line can be either a best-straight-line
This error affects all codes by the same amount and
fit (closest approximation to the actual transfer curve)
can usually be compensated for by trimming.
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
a lte rs the s lop e of the tra ns fe r func tion a nd c orre -
sponds to the same percentage error in each step.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
0/MAX531
7
6
6
1 LSB
5
4
5
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
AT STEP
011 (1/2 LSB )
3
2
3
2
1
0
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
AT STEP
001 (1/4 LSB )
1
0
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 8a. Integral Nonlinearity
Figure 8b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT
ACTUAL
3
7
6
5
DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
ACTUAL
OFFSET
POINT
2
1
0
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
OFFSET ERROR
(+1 1/4 LSB)
4
0
IDEAL OFFSET
POINT
000
001
010
011
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 8c. Offset Error
Figure 8d. Gain Error
14 ______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
Settling Time
OS
+5V/+3V
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
REF
V
DD
R
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
la yout a nd g round ing will s ig nific a ntly re d uc e this
nois e , b ut the re will a lwa ys b e s ome fe e d throug h
caused by the DAC itself.
MAX5130
MAX5131
0.6384R
DAC
OUT
AGND
DGND
Un ip o la r Ou t p u t
Fig ure 9 s hows the MAX5130/MAX5131 s e tup for
unip ola r, Ra il-to-Ra il® op e ra tion with a g a in of
1.6384V/V. With its + 2.5V inte rna l re fe re nc e , the
MAX5130 can generate a unipolar output range of 0 to
+4.0955V. The MAX5131 produces a range of 0 to
+2.04775V with its on-board +1.25V reference. Table 5
lists example codes for unipolar output voltages. An off-
set to the output voltage can be achieved by simply
connecting the appropriate voltage to the OS pin, as
shown in Figure 10.
GAIN = 1.638V/V
Figure 9. Unipolar Output Circuit (OS = AGND) Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to V
.
DD
OS
+5V/+3V
REF
+
REFADJ
V
OS
V
DD
Bip o la r Ou t p u t
The MAX5130/MAX5131 can be configured for unity-
gain bipolar operation (OS = OUT) using the circuit
R
MAX5130
MAX5131
0.6384R
shown in Figure 11. The output voltage V
given by the following equation:
is thereby
OUT
DAC
OUT
V
OUT
= V · [ {G · (NB / 8192)} - 1]
REF
AGND
DGND
where NB is the numeric value of the DAC’s binary
input code, V is the voltage of the internal (or exter-
REF
nal) precision reference, and G is the overall gain. The
application circuit in Figure 11 uses a low-cost opera-
tional amplifier (MAX4162) external to the MAX5130/
MAX5131 in a unity-gain configuration. This provides
an overall circuit gain of 2V/V. Table 6 lists example
codes for bipolar output voltages.
Figure 10. Circuit for Adding Offset to the DAC’s Output
+5V/+3V
50k
OS
50k
V+
REF
V
DD
Re s e t (RS TVAL) a n d Cle a r (CLR) Fu n c t io n s
The MAX5130/MAX5131 DACs offer a clear pin (CLR),
which resets the output to a certain value, depending
upon how RSTVAL is set. RSTVAL = DGND sets the
R
MAX5130
MAX5131
0.6384R
V
OUT
output to 0, and RSTVAL = V sets the output to mid-
scale when CLR is pulled low.
DD
DAC
OUT
MAX4162
The CLR pin has a minimum input resistance of 40kΩ in
V-
DGND
AGND
series with a diode to the supply voltage (V ). If the
DD
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
be limited to (V
- V - 0.5V) / 40kΩ.
CLR
DD
Figure 11. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
Note: Clearing the DAC will also cause the part to exit
software shutdown (PD = 0).
pull REFADJ to V
.
DD
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
______________________________________________________________________________________ 15
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
Table 5. Unipolar Code Table (Gain = +1.6384V/V)
ANALOG OUTPUT
DAC CONTENTS
INTERNAL REFERENCE
MSB
LSB
EXTERNAL REFERENCE
MAX5130
+4.0955V
+2.0485V
+2.0480V
+2.0475V
+0.5mV
0V
MAX5131
+2.04775V
+1.02425V
+1.02400V
+1.02375V
+0.25mV
0V
1 1111 1111 1111
+V
(8191 / 8192) · 1.6384
(4097 / 8192) · 1.6384
(4096 / 8192) · 1.6384
(4095 / 8192) · 1.6384
(1 / 8192) · 1.6384
REF
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
+V
REF
+V
REF
+V
REF
+V
REF
0V
Table 6. Bipolar Code Table for Figure 11
ANALOG OUTPUT
INTERNAL REFERENCE
DAC CONTENTS
MSB
LSB
EXTERNAL REFERENCE
0/MAX531
MAX5130
MAX5130
+1.24969V
+305.18µV
0V
1 1111 1111 1111
+2.49939V
+610.35µV
0V
V
REF · [ {2 · (8191 / 8192)} - 1]
REF · [ {2 · (4097 / 8192)} - 1]
REF · [ {2 · (4096 / 8192)} - 1]
REF · [ {2 · (4095 / 8192)} - 1]
REF · [ {2 · (1 / 8192)} - 1]
-V
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
V
V
-610.35µV
-2.49939V
-2.5V
-305.18µV
-1.24969V
-1.25V
V
V
REF
SCLK
SCLK
SCLK
I
II
III
MAX5130
MAX5131
MAX5130
MAX5131
MAX5130
MAX5131
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 12. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
Anothe r c onfig ura tion a llows s e ve ra l MAX5130/
MAX5131 DACs to share one common DIN signal line
(Fig ure 13). In this c onfig ura tion, the d a ta b us is
common to all devices; data is not shifted through a
daisy-chain. However, more I/O lines are required in
this configuration, because each IC needs a dedicated
CS line.
Da is y-Ch a in in g De vic e s
Any numb e r of MAX5130/MAX5131s c a n b e d a isy-
chained simply by connecting the serial data output pin
(DOUT) of one device to the digital input pin (DIN) of
the following device in the chain (Figure 12).
16 ______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
= V ). Bypass the power supply with a 4.7µF capaci-
DD
tor in parallel with a 0.1µF capacitor to AGND. Minimize
lead lengths to reduce lead inductance.
Us in g a n Ex t e rn a l Re fe re n c e
w it h AC Co m p o n e n t s
The MAX5130/MAX5131 have multiplying capabilities
within the reference input voltage range specifications.
Figure 14 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.
La yo u t Co n s id e ra t io n s
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. If noise becomes an
issue, shielding may be required.
P o w e r-S u p p ly a n d Byp a s s in g
Co n s id e ra t io n s
On power-up, the input and DAC registers are cleared
to either zero (RSTVAL = DGND) or midscale (RSTVAL
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
I
II
III
CS
CS
CS
MAX5130
MAX5131
MAX5130
MAX5131
MAX5130
MAX5131
SCLK
SCLK
SCLK
DIN
DIN
DIN
Figure 13. Multiple Devices Share One Common Digital Input (DIN)
+5V/+3V
+5V/+3V
26k
10k
AC
REFERENCE
INPUT
MAX495
500mVp-p
V
DD
REF
R
OS
0.6384R
DAC
OUT
MAX5130
MAX5131
AGND
DGND
Figure 14. External Reference with AC Components
______________________________________________________________________________________ 17
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 3308
SUBSTRATE CONNECTED TO AGND
P a c k a g e In fo rm a t io n
0/MAX531
18 ______________________________________________________________________________________
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
0/MAX531
NOTES
______________________________________________________________________________________ 19
+3 V/+5 V, 1 3 -Bit , S e ria l Vo lt a g e -Ou t p u t DACs
w it h In t e rn a l Re fe re n c e
NOTES
0/MAX531
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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