MAX515EPA+ [MAXIM]

D/A Converter, 1 Func, Serial Input Loading, 25us Settling Time, PDIP8, 0.300 INCH, PLASTIC, DIP-8;


型号：	MAX515EPA+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	D/A Converter, 1 Func, Serial Input Loading, 25us Settling Time, PDIP8, 0.300 INCH, PLASTIC, DIP-8 光电二极管转换器
文件：	总16页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-0280; Rev 2; 11/96

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

_______________Ge n e ra l De s c rip t io n

___________________________Fe a t u re s

♦ Operate from Single +5V Supply

♦ Buffered Voltage Output

The MAX504/MAX515 are low-power, voltage-output,

10-bit digital-to-analog converters (DACs) specified for

single +5V power-supply operation. The MAX504 can

a ls o b e op e ra te d with ± 5V s up p lie s . The MAX515

draws only 140µA, and the MAX504 (with internal refer-

ence) draws only 260µA. The MAX515 comes in 8-pin

DIP and SO packages, while the MAX504 comes in 14-

p in DIP a nd SO p a c ka g e s . Both p a rts ha ve b e e n

trimmed for offset voltage, gain, and linearity, so no fur-

ther adjustment is necessary.

♦ Internal 2.048V Reference (MAX504)

♦ 140µA Supply Current (MAX515)

♦ INL = ±1/2LSB (max)

♦ Guaranteed Monotonic Over Temperature

♦ Flexible Output Ranges:

The MAX515’s buffer is fixed at a gain of 2. The MAX504’s

internal op amp may be configured for a gain of 1 or 2, as

we ll a s for unip ola r or b ip ola r outp ut volta g e s . The

MAX504 can also be used as a four-quadrant multiplier

without external resistors or op amps.

0V to V

(MAX504/MAX515)

to V

(MAX504)

♦ 8-Pin SO/DIP (MAX515)

♦ Power-On Reset

For parallel data inputs, see the MAX503 data sheet.

For a ha rd wa re a nd s oftwa re c omp a tib le 12-b it

upgrade, refer to the MAX531/MAX538/MAX539 data

sheet.

♦ Serial Data Output for Daisy-Chaining

______________Ord e rin g In fo rm a t io n

_______________________Ap p lic a t io n s

Battery-Powered Test Instruments

PART

MAX504CPD

MAX504CSD

MAX504EPD

MAX504ESD

MAX515CPA

MAX515CSA

MAX515EPA

MAX515ESA

TEMP. RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

14 Plastic DIP

14 SO

Digital Offset and Gain Adjustment

Battery-Operated/Remote Industrial Controls

Machine and Motion Control Devices

Cellular Telephones

14 Plastic DIP

14 SO

8 Plastic DIP

8 SO

________________Fu n c t io n a l Dia g ra m

8 Plastic DIP

8 SO

REFIN

REFOUT*

BIPOFF*

Refer to the MAX531/MAX538/MAX539 data sheet for military tem-

perature or die equivalents.

MAX504

MAX515

_________________P in Co n fig u ra t io n s

2.048V

REFERENCE*

RFB*

TOP VIEW

VOUT

DAC

AGND

POWER-UP

RESET

DIN

SCLK

DGND*

10-BIT DAC REGISTER

VOUT

REFIN

AGND

CLR*

MAX515

CONTROL

LOGIC

V *

DOUT

(LSB)

(MSB)

SCLK

DIN

DUMMY

BITS

DOUT

10 DATA BITS

DIP/SO

16-BIT SHIFT REGISTER

MAX504 appears at end of data sheet.

* MAX504 ONLY

________________________________________________________________ Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t

S e ria l 1 0 -Bit DACs

ABSOLUTE MAXIMUM RATINGS

to DGND and V to AGND ................................-0.3V, +6V

Continuous Power Dissipation (T = +70°C)

to DGND and V to AGND .................................-6V, +0.3V

8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW

8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW

14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ..... 800mW

14-Pin SO (derate 8.33mW/°C above +70°C)................667mW

Operating Temperature Ranges

to V .................................................................-0.3V, +12V

AGND to DGND........................................................-0.3V, +0.3V

Digital Input Voltage to DGND ......................-0.3V, (V + 0.3V)

REFIN ..................................................(V - 0.3V), (V + 0.3V)

REFOUT to AGND .........................................-0.3V, (V + 0.3V)

MAX5_ _C_ _.........................................................0°C to +70°C

MAX5_ _E_ _......................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10sec) .............................+300°C

RFB .....................................................(V - 0.3V), (V + 0.3V)

BIPOFF................................................(V - 0.3V), (V + 0.3V)

OUT

(Note 1) ................................................................V , V

SS DD

Continuous Current, Any Pin................................-20mA, +20mA

Note 1: The output may be shorted to V , V , or AGND if the package power dissipation limit is not exceeded.

DD SS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

04/MAX15

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V = 5V, V = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX504), C

= 33µF (MAX504),

REFOUT

R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

Bits

LSB

Relative Accuracy (Note 2)

Differential Nonlinearity

Unipolar Offset Error

Unipolar Offset Tempco

Unipolar Offset-Error

INL

DNL

±0.5

±1

Guaranteed monotonic

LSB

TCV

ppm/°C

PSRR

4.5V ≤ V ≤ 5.5V

0.1

LSB/V

Power-Supply Rejection Ratio

Gain Error (Note 2)

±1

LSB

Gain-Error Tempco

ppm/°C

Gain-Error Power-Supply

Rejection Ratio

PSRR

4.5V ≤ V ≤ 5.5V

0.1

LSB/V

VOLTAGE OUTPUT (V

)

OUT

MAX504 (G = 1)

- 2

Output Voltage Range

MAX504 (G = 2), MAX515

- 0.4

Output Load Regulation

Short-Circuit Current

VOUT = 2V, R = 2kΩ

0.5

LSB

REFERENCE INPUT (REFIN)

Voltage Range

- 2

Input Resistance

Code dependent, minimum at code 0101...

Code dependent (Note 3)

kΩ

Input Capacitance

AC Feedthrough

REFIN = 1kHz, 2Vp-p

-80

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V = 5V, V = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX504), C

= 33µF (MAX504),

REFOUT

R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

REFERENCE OUTPUT (REFOUT—MAX504 Only)

= +25°C

2.024

2.015

2.011

2.048

2.072

2.081

2.085

Reference Output Voltage

MAX504C

MAX504E

Temperature Coefficient

Resistance

ppm/°C

Ω

REFOUT

(Note 4)

0.5

REFOUT

Power-Supply Rejection Ratio

Noise Voltage

PSRR

4.5V ≤ V ≤ 5.5V

200

400

µV/V

µVp-p

µF

0.1Hz to 10kHz

Required External Capacitor

3.3

2.4

REFOUT

DIGITAL INPUTS (DIN, SCLK, CS, CLR)

Input High

Input Low

0.8

±1

Input Current

= 0V or V

µA

Input Capacitance

DIGITAL OUTPUT (DOUT)

Output High

= 2mA

- 1

SOURCE

Output Low

= 2mA

0.4

SINK

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

Voltage-Output Settling Time

Digital Feedthrough

= +25°C

0.15

0.25

V/µs

µs

To ±1/2LSB, VOUT = 2V

nV-s

CS = V , DIN = 100kHz

REFIN = 1kHz, 2Vp-p (G = 1 or 2),

code = 1111...

Signal-to-Noise Plus Distortion

SINAD

POWER SUPPLY

Positive Supply Voltage

4.5

5.5

400

300

MAX504

MAX515

260

140

All inputs = 0V or V

output = no load

Power-Supply Current

µA

SWITCHING CHARACTERISTICS (Note 5)

CS Setup Time

CSS

SCLK Fall to CS Fall Hold Time

SCLK Fall to CS Rise Hold Time

SCLK High Width

CSH0

CSH1

SCLK Low Width

DIN Setup Time

DIN Hold Time

DOUT Valid Propagation Delay

CS High Pulse Width

CLR Pulse Width

= 50pF

CSW

CLR

CS Rise to SCLK Rise Setup Time

CS1

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (MAX504 Only)

(V = 5V, V = -5V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C

= 33µF, R = 10kΩ,

REFOUT

= 100pF, T = T

to T , unless otherwise noted.)

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

Resolution

Relative Accuracy

Differential Nonlinearity

Bipolar Offset Error

Bipolar Offset Tempco

INL

±0.5

±1

LSB

DNL

Guaranteed monotonic

BIPOFF = REFIN

LSB

±3

LSB

TCV

ppm/°C

Offset-Error Power-Supply

Rejection Ratio

PSRR

4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V

0.1

LSB/V

Gain Error (Unipolar or Bipolar)

Gain-Error Tempco

±1

LSB

ppm/°C

04/MAX15

Gain-Error Power-Supply

Rejection Ratio

PSRR

4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V

0.1

LSB/V

REFERENCE INPUT (REFIN)

Voltage Range

+ 2

- 2

Input Resistance

Code dependent, minimum at code 0101...

Code dependent (Note 3)

kΩ

Input Capacitance

AC Feedthrough

REFIN = 1kHz, 2.0Vp-p

-80

REFERENCE OUTPUT (REFOUT—MAX504 Only)

= +25°C

2.024

2.015

2.011

2.048

2.072

2.081

2.085

MAX504C

MAX504E

Reference Output Voltage

Temperature Coefficient

Resistance

ppm/°C

Ω

REFOUT

PSRR

(Note 4)

0.5

Power-Supply Rejection Ratio

Noise Voltage

4.5V ≤ V ≤ 5.5V

200

400

µV/V

µVp-p

µF

0.1Hz to 10kHz

Required External Capacitor

DIGITAL INPUTS (DIN, SCLK, CS)

Input High

3.3

2.4

REFOUT

Input Low

0.8

±1

Input Current

= 0V or V

µA

Input Capacitance

DIGITAL OUTPUT (DOUT)

Output High

= 2mA

V - 1

SOURCE

Output Low

= 2mA

0.4

SINK

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (MAX504 Only) (continued)

(V = 5V, V = -5V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C

= 33µF, R = 10kΩ,

REFOUT

= 100pF, T = T

to T , unless otherwise noted.)

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

VOLTAGE OUTPUT (VOUT)

(G = 1)

(G = 2)

+ 2

- 2

Output Voltage Range

+ 0.4

- 0.4

Output Load Regulation

Short-Circuit Current

VOUT = 2V, R = 2kΩ

0.5

LSB

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

Voltage-Output Settling Time

Digital Feedthrough

0.15

0.25

V/µs

µs

To ±1/2LSB, VOUT = 2V

Step all 0s to all 1s

nV-s

REFIN = 1kHz, 2Vp-p (G = 1)

REFIN = 1kHz, 2Vp-p (G = 2)

Signal-to-Noise Plus Distortion

SINAD

POWER SUPPLY

Positive Supply Voltage

Negative Supply Voltage

Positive Supply Current

Negative Supply Current

SWITCHING CHARACTERISTICS

CS Setup Time

4.5

5.5

-5.5

All inputs = 0V or V , no load

260

400

-200

µA

All inputs = 0V or V , no load

-120

CSS

SCLK Fall to CS Fall Hold Time

SCLK Fall to CS Rise Hold Time

SCLK High Width

CSH0

CSH1

SCLK Low Width

DIN Setup Time

DIN Hold Time

DOUT Valid Propagation Delay

CS High Pulse Width

= 50pF

CSW

CLR Pulse Width

CLR

CS Rise to SCLK Rise Setup Time

CS1

Note 2: In single-supply operation, INL and GE calculated from Code 3 to Code 1023.

Note 3: Guaranteed by design.

Note 4: Tested at I

= 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics).

OUT

Note 5: The timing characteristics limits for the MAX515 are guaranteed by design.

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = +5V, V

= 2.048V, T = +25°C, unless otherwise noted.)

REFIN

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

ANALOG FEEDTHROUGH vs.

FREQUENCY

-110

-100

-90

CODE = all 0s

-80

-70

-60

-50

-40

-30

-20

-10

04/MAX15

0.2

0.4

0.6

0.8

1.0

-5

-4

-3

-2

-1

V -0

100

10k 100k 1M

OUTPUT PULL-DOWN VOLTAGE (V)

OUTPUT PULL-UP VOLTAGE (V)

FREQUENCY (Hz)

MAX504

REFERENCE VOLTAGE vs.

TEMPERATURE

MAX504

GAIN vs. FREQUENCY

SUPPLY CURRENT vs.

TEMPERATURE

300

2.055

2.050

REFIN = 4Vp-p

280

260

240

220

200

180

160

140

120

MAX504

-2

-4

-6

-8

-10

-12

MAX515

-14

2.045

-60 -40 -20

20 40 60 80 100 120 140

100

FREQUENCY (Hz)

10k

100k

-60 -40 -20

20 40 60 80 100 120

TEMPERATURE (°C)

MAX504 REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

MAX504

GAIN AND PHASE vs.FREQUENCY

MAX504

AMPLIFIER SIGNAL-TO-NOISE RATIO

2.0520

2.0515

180

RFB CONNECTED TO AGND (G=2)

RFB CONNECTED TO VOUT (G=1)

REFIN = 4Vp-p

GAIN

2.0510

2.0505

2.0500

2.0495

2.0490

-10

-20

PHASE

-180

-30

100

800

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REFERENCE LOAD CURRENT (mA)

100

10k

100k

FREQUENCY (kHz)

FREQUENCY (Hz)

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

= +5V, V = 2.048V, T = +25°C, unless otherwise noted.)

REFIN A

DIGITAL FEEDTHROUGH

2µs/div

CS = HIGH

A: DIN = 4Vp-p, 100kHz

B: VOUT, 10mV/div

NEGATIVE SETTLING TIME (MAX504)

POSITIVE SETTLING TIME (MAX504)

5µs/div

A: CS RISING EDGE, 5V/div

B: VOUT, NO LOAD, 1V/div

DUAL SUPPLY ±5V

BIPOLAR CONFIGURATION

V = 2V

REFIN

A: CS RISING EDGE, 5V/div

B: VOUT, NO LOAD, 1V/div

DUAL SUPPLY ±5V

BIPOLAR CONFIGURATION

REFIN

= 2V

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t

S e ria l 1 0 -Bit DACs

____________________P in De s c rip t io n

_______________De t a ile d De s c rip t io n

Ge n e ra l DAC Dis c u s s io n

The MAX504/MAX515 use an “inverted” R-2R ladder net-

work with a single-supply CMOS op amp to convert 10-bit

digital data to analog voltage levels (see Functional

Diagram). The term “inverted” describes the ladder net-

work because the REFIN pin in current-output DACs is the

summing junction, or virtual ground, of an op amp.

However, such use would result in the output voltage

b e ing the inve rs e of the re fe re nc e volta g e . The

MAX504/MAX515’s topology makes the output the same

polarity as the reference input.

NAME

FUNCTION

MAX504

MAX515

Bipolar offset/gain

resistor

—

BIPOFF

DIN

Serial data input

Clear. Asynchronously sets

DAC register to all 0s.

—

CLR

An internal reset circuit forces the DAC register to reset

to all 0s on power-up. Additionally, a clear (CLR) pin,

when held low, sets the DAC register to all 0s. CLR

operates asynchronously and independently from the

chip select (CS) pin.

SCLK

Serial clock input

Chip select, active low

04/MAX15

Serial data output for

daisy-chaining

DOUT

Bu ffe r Am p lifie r

—

DGND

AGND

REFIN

Digital ground

The output buffer is a unity-gain stable, rail-to-rail output,

BiCMOS op amp. Input offset voltage and CMRR are

trimmed to achieve better than 10-bit performance.

Settling time is 25µs to 0.01% of final value. The output is

short-circuit protected and can drive a 2kΩ load with more

than 100pF load capacitance.

Analog ground

Reference input

Reference output,

2.048V. Connect to V

if not used.

—

REFOUT

—

Negative power supply

DAC output

VOUT

Positive power supply

Feedback resistor

—

RFB

CSH0

CSW

CSH1

CSS

SCLK

CS1

DIN

DOUT

Figure 1. Timing Diagram

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

code 0000.... REFIN’s input capacitance is also code

dependent and has a 50pF maximum value at several

codes.

REFOUT

TOTAL

REFERENCE

NOISE

If an upgrade to the internal reference is required, the 2.5V

REFOUT

MAX873A is suitable: ±15mV initial accuracy, TCV

7ppm/°C (max).

TEK 7A22

OUT

300

250

200

150

100

1.8

1.6

1.4

1.2

1.0

0.8

SINGLE POLE ROLLOFF

Logic Inte rfa c e

= 3.3µF

REFOUT

The MAX504/MAX515 logic inputs are designed to be

compatible with TTL or CMOS logic levels. However, to

achieve the lowest power dissipation, drive the digital

inputs with rail-to-rail CMOS logic. With TTL logic levels,

the power requirement increases by a factor of approxi-

mately 2.

0.6

0.4

0.2

0.0

= 47µF

REFOUT

Serial Clock and Update Rate

Figure 1 shows the MAX504/MAX515 timing. The maxi-

mum serial clock rate is given by 1/(t +t ), approxi-

0.1

100

1000

CH CL

mately 14MHz. The digital update rate is limited by the

FREQUENCY (kHz)

chip-select period, which is 16 x (t

+ t ) + t

CSW

Figure 2. Reference Noise vs. Frequency

This equals a 1.14µs, or 877kHz, update rate. However,

the DAC settling time to 10 bits is 25µs, which may limit

the update rate to 40kHz for full-scale step transitions.

Inte rna l Re fe re nc e (MAX504 only)

The on-chip reference is laser trimmed to generate 2.048V

at REFOUT. The output stage can source and sink current

so REFOUT can settle to the correct voltage quickly in

response to code-dependent loading changes. Typically,

source current is 5mA and sink current is 100µA.

____________Applic a tions Inform a tion

Refer to Figures 3a and 3b for typical operating con-

nections.

Se ria l Inte rfa c e

REFOUT connects the internal reference to the R-2R DAC

ladder at REFIN. The R-2R ladder draws 50µA maximum

load current. If any other connection is made to REFOUT,

ensure that the total load current is less than 100µA to

avoid gain errors.

The MAX504/MAX515 use a three-wire serial interface that

is compatible with SPI™, QSPI™ (CPOL = CPHA = 0), and

Microwire™ standards as shown in Figures 4 and 5. The

DAC is programmed by writing two 8-bit words (see Figure

1 and the Functional Diagram). 16 bits of serial data are

clocked into the DAC in the following order: 4 fill (dummy)

bits, 10 data bits, and 2 sub-LSB 0s. The 4 dummy bits are

not normally needed, and are required only when DACs

are daisy chained. The 2 sub-LSB 0s, however, are always

needed, and allow hardware and software compatibility

with the 12-bit MAX531/MAX538/MAX539. Transitions at

CS should occur while SCLK is low. Data is clocked in on

SCLK’s rising edge while CS is low. The serial input data is

held in a 16-bit serial shift register. On CS’s rising edge, the

10 data-bits are transferred to the DAC register and update

the DAC. With CS high, data cannot be clocked into the

MAX504/MAX514.

For applications requiring very low-noise performance, con-

nect a 33µF capacitor from REFOUT to AGND. If noise is

not a concern, a lower value (3.3µF min) capacitor may be

used. To reduce noise further, insert a buffered RC filter

between REFOUT and REFIN (Figure 2). The reference

bypass capacitor C

is still required for reference sta-

REFOUT

bility. In applications not requiring the reference, connect

REFOUT to V (to save power and to eliminate the need

for C

) or use the MAX515 (no internal reference).

REFOUT

Exte rna l Re fe re nc e

An external reference in the range (V + 2V) to (V - 2V)

may be used with the MAX504 in dual-supply operation.

With the MAX515 or the MAX504 in single-supply use, the

The MAX504/MAX515 inputs data in 16-bit blocks. The SPI

and Microwire interfaces output data in 8-bit blocks, there-

by requiring two write cycles to input data to the DAC. The

QSPI interface allows variable data input from 8 to 16 bits,

and can be loaded into the DAC in one write cycle.

reference must be positive and may not exceed V - 2V.

The reference voltage determines the DAC’s full-scale out-

put. The DAC input resistance is code dependent and is

minimum (40kΩ) at code 0101... and virtually infinite at

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

_______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

DIN SCLK CS DOUT

DIN DOUT SCLK CS

REFIN

CLR

REFIN

VOUT

INVERTED

R-2R DAC

INVERTED

R-2R DAC

REFOUT

RFB

2.048V

MAX504

CONNECT BIPOFF

TO VOUT FOR G=1,

TO AGND FOR G=2,

OR TO REFIN FOR

BIPOLAR GAIN

MAX515

BIPOFF

MAX515

ONLY

33µF

AGND DGND

AGND

0.1µF

+5V

0V to -5V

0.1µF

+5V

04/MAX15

Figure 3a. MAX504 Typical Operating Circuit

Figure 3b. MAX515 Typical Operating Circuit

Da is y-Ch a in in g De vic e s

Bip o la r Co n fig u ra t io n

The serial output, DOUT, allows cascading of two or more

DACs. The data at DIN appears at DOUT, delayed by 16

clock cycles plus one clock width. For low power, DOUT is

a CMOS output that does not require an external pull-up

resistor. DOUT does not go into a high-impedance state

when CS is high. DOUT changes on SCLK’s falling edge

when CS is low. When CS is high, DOUT remains in the

state of the last data bit.

A bipolar range is set up by connecting BIPOFF to

REFIN a nd RFB to VOUT, a nd op e ra ting from d ua l

(±5V) supplies (Figure 8). Table 3 shows the DAC-latch

c onte nts (inp ut) vs . VOUT (outp ut). In this ra ng e ,

-9

1LSB = V

(2 ).

REFIN

Fo u r-Qu a d ra n t Mu lt ip lic a t io n

The MAX504 can be used as a four-quadrant multiplier

by connecting BIPOFF to REFIN and RFB to VOUT, and

using (1) an offset binary digital code, (2) bipolar power

supplies, and (3) a bipolar analog input at REFIN within

Any number of MAX504/MAX515 DACs can be daisy-

chained by connecting the DOUT of one device to the DIN

of the next device in the chain. For proper timing, ensure

the range V + 2V to V - 2V, as shown in Figure 9.

that t (SCLK low) is greater than t + t .

In general, a 10-bit DAC’s output is (D)(V

(G),

REFIN)

Un ip o la r Co n fig u ra t io n

The MAX504 is configured for a gain of 1 (0V to V

where “G” is the gain (1 or 2) and “D” is the binary rep-

resentation of the digital input divided by 2 or 1,024.

REFIN

unipolar output) by connecting BIPOFF and RFB to VOUT

(Figure 6). The converter operates from either single or

dual supplies in this configuration. See Table 1 for the

This formula is precise for unipolar operation. However,

for bipolar, offset binary operation, the MSB is really a

polarity bit. No resolution is lost because the number of

steps is the same. The output voltage, however, has

been shifted from a range of, for example, 0V to 4.096V

(G = 2) to a range of -2.048V to +2.048V.

DAC-latch contents (input) vs. the analog VOUT (output).

-10

In this range, 1LSB = V

), where V

is the

REFIN

REF

voltage on REFIN.

A gain of 2 (0V to 2V

unipolar output) is set up by

Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. Negative full scale

REFIN

connecting BIPOFF to AGND and RFB to VOUT (Figure

7). Table 2 shows the DAC-latch contents vs. VOUT. The

MAX504 operates from either single or dual supplies in

this mode. In this range,

is -V

, while positive full scale is +V

- 1LSB.

REFIN

-10

-9

1LSB = (2)(V )(2

REFIN

) = (V

)(2 ).

REFIN

The MAX515 is internally configured for unipolar gain of

2 operation.

10 ______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

SCLK

DIN

SCLK

DIN

SCK

MICROWIRE

PORT

SPI

PORT

MOSI

MAX504

MAX515

MAX504

MAX515

I/O

DOUT

MISO

CPOL = 0, CPHA = 0

THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .

THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX504/MAX515, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .

Figure 4. Microwire Connection

Figure 5. SPI/QSPI Connection

+5V

REFIN

BIPOFF

REFOUT

33µF

MAX504

BIPOFF

AGND

DGND

AGND

DGND

RFB

OUT

VOUT

OUT

VOUT

G = 2

G = 1

0V TO -5V

Figure 6. Unipolar Configuration (0V to +2.048V Output)

Figure 7. Unipolar Configuration (0V to +4.096V Output)

Table 2. Unipolar Binary Code Table

Table 1. Unipolar Binary Code Table

(0V to 2V

Output), Gain = 2

(0V to V

Output), Gain = 1

REFIN

OUTPUT

INPUT*

OUTPUT

INPUT*

1023

1024

1023

1024

+2 (V )

REFIN

1111 1111

1000 0000

11(00)

01(00)

)

1111 1111

1000 0000

11(00)

01(00)

REFIN

513

1024

513

1024

+2 (V

)

REFIN

)

REFIN

512

1024

512

1024

= +V

+2 (V

)

1000 0000

0111 1111

00(00)

11(00)

REFIN

)

= +V

REFIN

1000 0000

0111 1111

00(00)

11(00)

REFIN

511

1024

511

+2 (V

)

REFIN

1024

0000 0000

)

01(00)

00(00)

REFIN

0000 0000

+2 (V

01(00)

00(00)

REFIN

1024

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

______________________________________________________________________________________ 11

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

Table 3. Bipolar (Offset Binary) Code

Table (-V to +V Output)

+5V

REFIN

OUTPUT

INPUT*

REFIN

BIPOFF

REFOUT

511

512

(+V

)

1111 1111

1000 0000

11(00)

01(00)

REFIN

33µF

MAX504

512

RFB

(+V

)

REFIN

AGND

DGND

1000 0000

0111 1111

00(00)

11(00)

OUT

VOUT

512

(-V

)

REFIN

511

512

0000 0000

(-V

01(00)

00(00)

REFIN

04/MAX15

-5V

512

)

= -V

REFIN

Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

DGND and AGND should be connected together at the

chip. For the MAX504 in single-supply applications,

S in g le -S u p p ly Lin e a rit y

As with any amplifier, the MAX504/MAX515’s output

buffer offset can be positive or negative. When the off-

set is positive, it is easily accounted for (Figure 10).

However, when the offset is negative, the buffer output

cannot follow linearly when there is no negative supply.

In that case, the amplifier output (VOUT) remains at

ground until the DAC voltage is sufficient to overcome

the offset and the output becomes positive.

connect V to AGND at the chip. The best ground

connection may be achieved by connecting the DAC's

DGND and AGND pins together and connecting that

point to the system analog ground plane. If the DAC's

DGND is connected to the system digital ground, digi-

tal noise may get through to the DAC’s analog portion.

Bypass V

(and V in dual-supply mode) with a

0.1µF ceramic capacitor connected between V

and

Normally, linearity is measured after accounting for

zero error and gain error. Since, in single-supply opera-

tion, the actual value of a negative offset is unknown, it

cannot be accounted for during test. Additionally, the

output buffer amplifier exhibits a nonlinearity near-zero

output when operating with a single supply. To account

for this nonlinearity in the MAX504/MAX515, linearity

a nd g a in e rror a re me a s ure d from c od e 3 to c od e

1023. The output buffer’s offset and nonlinearity do not

affect monotonicity, and these DACs are guaranteed

monotonic starting with code zero. In dual-supply oper-

ation, linearity and gain error are measured from code

0 to 1023.

AGND (and between V and AGND). Mount it with

short leads close to the device. Ferrite beads may also

be used to further isolate the analog and digital power

supplies.

Fig ure s 11a a nd 11b illus tra te the g round ing a nd

bypassing scheme described.

S a vin g P o w e r

When the DAC is not being used by the system, mini-

mize power consumption by setting the appropriate

code to minimize load current. For example, in bipolar

mode, with a resistive load to ground, set the DAC

code to mid-scale (see Table 3). If there is no output

load, minimize internal loading on the reference by set-

ting the DAC to a ll 0s (on the MAX504, us e CLR).

Under this condition, REFIN is high impedance and the

op amp operates at its minimum quiescent current.

P o w e r-S u p p ly Byp a s s in g a n d

Gro u n d Ma n a g e m e n t

Best system performance is obtained with printed cir-

c uit b oa rd s tha t us e s e p a ra te a na log a nd d ig ita l

ground planes. Wire-wrap boards are not recommend-

e d . The two g round p la ne s s hould b e c onne c te d

together at the low-impedance power-supply source.

Due to these low currents, the output settling time for a

zero input code typically increases to 60µs (100µs

max).

12 ______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

CS CLR DIN DOUT REFOUT V

2.048V

POSITIVE OFFSET

NEGATIVE OFFSET

SIGNAL

REFIN

VOUT

INVERTED

R-2R DAC

RFB

BIPOFF

MAX504

Figure 9. MAX504 Connected as Four-Quadrant Multiplier. The

unused REFOUT is connected to V

DAC CODE (LSBs)

Figure 10. Single-Supply Offset

AC Co n s id e ra t io n s

ANALOG GROUND PLANE

Digital Feedthrough

High-speed serial data at any of the digital input or output

pins may couple through the DAC package and cause

internal stray capacitance to appear at the DAC output as

noise, even though CS is held high (see Typical Operating

Characteristics). This digital feedthrough is tested by hold-

ing CS high transmitting 0101... from DIN to DOUT.

0.1µF

Analog Feedthrough

Because of internal stray capacitance, higher frequency

analog input signals may couple to the output as shown in

the Analog Feedthrough vs. Frequency graph in the

Typical Operating Characteristics. It is tested by holding

CS high, setting the DAC code to all 0s, and sweeping

REFIN.

0.1µF

(a) MAX504 BYPASSING

0.1µF

(b) MAX515 BYPASSING

Figure 11. Power-Supply Bypassing

______________________________________________________________________________________ 13

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

___________________Ch ip In fo rm a t io n

____P in Co n fig u ra t io n s (c o n t in u e d )

TRANSISTOR COUNT: 922

TOP VIEW

BIPOFF

DIN

RFB

MAX504

CLR

VOUT

SCLK

REFOUT

REFIN

DOUT

DGND

AGND

DIP/SO

04/MAX15

14 ______________________________________________________________________________________

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

04/MAX15

________________________________________________________P a c k a g e In fo rm a t io n

______________________________________________________________________________________ 15

5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,

S e ria l 1 0 -Bit DACs

___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )

04/MAX15

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.

MAX515EPA+ [MAXIM]

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