MAX5174BEEE-T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 18us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX5174BEEE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 18us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1475; Rev 0; 4/99
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX5174/MAX5176 low-power, serial, voltage-out-
put, 12-bit digital-to-analog converters (DACs) feature a
precision output amplifier in a space-saving 16-pin
QSOP package. The MAX5174 operates from a single
+5V supply, and the MAX5176 operates from a single
+3V supply. Both devices draw only 280µA of supply
current, which reduces to 1µA in shutdown. In addition,
the programmable power-up reset feature allows for a
user-selectable output voltage state of either 0 or mid-
scale.
♦ ±1 LSB INL
♦ 1µA Shutdown Current
♦ “Glitch Free” Output Voltage at Power-Up
♦ Single-Supply Operation
+5V (MAX5174)
+3V (MAX5176)
♦ Full-Scale Output Range
+2.048V (MAX5176, V
+4.096V (MAX5174, V
= +1.25V)
= +2.5V )
REF
REF
The 3-wire, digital, serial interface is compatible with
SPI™/QSPI™, and MICROWIRE™ standards. An input
register followed by a DAC register provides a double-
buffered input, allowing the input and DAC registers to
be updated independently or simultaneously with a 16-
bit serial word. Additional features include software and
hardware shutdown, shutdown lockout, a hardware
clear pin, and a reference input capable of accepting
DC and offset AC signals. These devices provide a pro-
grammable digital output pin for added functionality
and a serial-data output pin for daisy-chaining. All logic
inputs are TTL/CMOS compatible and are internally
buffered with Schmitt triggers to allow direct interfacing
to optocouplers.
♦ Rail-to-Rail® Output Amplifier
♦ Adjustable Output Offset
♦ Low THD (-80dB) in Multiplying Operation
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦ Programmable Shutdown Mode and Power-Up
Reset
♦ Buffered Output Capable of Driving 5kΩ || 100pF
Loads
♦ User-Programmable Digital Output Pin Allows
Serial Control of External Components
The MAX5174/MAX5176 incorporate a proprietary on-
c hip c irc uit tha t ke e p s the outp ut volta g e virtua lly
“glitch free,” limiting the glitches to a few millivolts dur-
ing power-up.
♦ 14-Bit Upgrades Available (MAX5170/MAX5172)
Ord e rin g In fo rm a t io n
Both devices are available in 16-pin QSOP packages
and are specified for the extended (-40°C to +85°C)
temperature range. The MAX5170/MAX5172 are pin-
compatible 14-bit upgrades to the MAX5174/MAX5176.
For 100% pin-compatible DACs with internal reference,
s e e the 13-b it MAX5130/MAX5131 a nd the 12-b it
MAX5120/MAX5121 data sheets.
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX5174AEEE
MAX5174BEEE
MAX5176AEEE
MAX5176BEEE
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
±1
±2
±2
±4
Ap p lic a t io n s
Industrial Process Controls
P in Co n fig u ra t io n
TOP VIEW
Digital Offset and Gain Adjustment
Motion Control
OS
OUT
RS
1
2
3
4
5
6
7
8
16 V
DD
15 N.C.
14 REF
13 AGND
Automatic Test Equipment (ATE)
Remote Industrial Controls
MAX5174
MAX5176
PDL
CLR
CS
µP-Controlled Systems
12
SHDN
11 UPO
DIN
SCLK
10 DOUT
Functional Diagram appears at end of data sheet.
9
DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND............................................-0.3V to +6.0V
Continuous Power Dissipation (T = +70°C)
A
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND..........................................-0.3V to +6.0V
16-Pin QSOP (derate 8mW/°C above +70°C)..............667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DOUT, UPO to DGND ................................-0.3V to (V + 0.3V)
DD
OUT, REF to AGND ...................................-0.3V to (V + 0.3V)
DD
OS to AGND ...............................(AGND - 4.0V) to (V + 0.3V)
DD
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5174
(V
= +5V ±10%, V
= 2.5V, OS = AGND = DGND, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4/MAX5176
12
Bits
MAX5174A
MAX5174B
±1
±2
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
±1
LSB
mV
V
OS
±10
±4
R
R
= ∞
-0.6
-1.6
10
L
L
Gain Error
GE
LSB
= 5kΩ
±8
Power-Supply Rejection Ratio
Output Noise Voltage
PSRR
120
µV/V
LSBp-p
nV/√Hz
f = 100kHz
1
Output Thermal Noise Density
REFERENCE
80
Reference Input Range
Reference Input Resistance
V
0
V
DD
- 1.4
V
REF
R
18
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
V
= 0.5Vp-p + 1.5V , slew-rate limited
350
-80
kHz
dB
REF
DC
V
= 3.6Vp-p + 1.8V , f = 1kHz,
DC
REF
Reference Feedthrough
code = all 0s
Signal-to-Noise Plus Distortion
Ratio
V
REF
code = FFF hex
= 2Vp-p + 1.5V , f = 10kHz,
DC
SINAD
82
dB
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
3
V
V
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
I
IN
V
= 0 or V
IN DD
C
IN
V
OH
I
= 2mA
V - 0.5
DD
V
V
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
2
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
ELECTRICAL CHARACTERISTICS—MAX5174 (continued)
(V
= +5V ±10%, V
= 2.5V, OS = AGND = DGND, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SR
0.6
18
V/µs
µs
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
OS Pin Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
0
V
DD
V
80
120
40
1
kΩ
µs
nV-s
CS = V , f
= 100kHz, V
= 5Vp-p
DD
SCLK
SCLK
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current (Note 4)
Shutdown Current (Note 4)
TIMING CHARACTERISTICS
SCLK Clock Period
V
4.5
5.5
0.4
10
V
DD
I
DD
0.35
1
mA
µA
t
CP
100
40
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise Setup
Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise Hold
Time
t
CSH
SDI Setup Time
SDI Hold Time
t
40
0
ns
ns
DS
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
CS1
t
t
100
CSW
_______________________________________________________________________________________
3
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
ELECTRICAL CHARACTERISTICS—MAX5176
(V = +2.7V to +3.6V, V
= 1.25V, OS = AGND = DGND, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C).
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
MAX5176A
MAX5176B
±2
±4
Integral Nonlinearity (Note 5)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
±1
LSB
mV
V
OS
±10
±4
R
R
= ∞
-0.6
-1.6
10
L
L
Gain Error
GE
LSB
= 5kΩ
±8
Power-Supply Rejection Ratio
Output Noise Voltage
PSRR
120
µV/V
LSBp-p
nV/√Hz
f = 100kHz
2
Output Thermal Noise Density
REFERENCE
80
4/MAX5176
Reference Input Range
Reference Input Resistance
V
0
V
DD
- 1.4
V
REF
R
18
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
V
= 0.5Vp-p + 0.75V , slew-rate limited
350
-80
kHz
dB
REF
DC
V
= 1.6Vp-p + 0.8V , f = 1kHz,
DC
REF
Reference Feedthrough
code = all 0s
Signal-to-Noise Plus Distortion
Ratio
V
REF
code = FFF hex
= 0.6Vp-p + 0.9V , f = 10kHz,
DC
SINAD
78
dB
DIGITAL INPUT
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.2
V
V
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
DIGITAL OUTPUT
Output High Voltage
Output Low Voltage
I
IN
V
= 0 or V
IN DD
C
IN
V
OH
I
= 2mA
V - 0.5
DD
V
V
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
4
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
ELECTRICAL CHARACTERISTICS—MAX5176 (continued)
(V = +2.7V to +3.6V, V
= 1.25V, OS = AGND = DGND, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C).
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
18
V/µs
µs
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
OS Pin Input Resistance
Time Required to Exit Shutdown
0
V
DD
V
80
120
40
kΩ
µs
CS = V , DIN = 50kHz; f
= 100kHz,
DD
SCLK
Digital Feedthrough
1
nV-s
V
SCLK
= 3Vp-p
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current (Note 4)
Shutdown Current (Note 4)
TIMING CHARACTERISTICS
SCLK Clock Period
V
2.7
3.6
0.4
10
V
DD
I
DD
0.35
1
mA
µA
t
150
75
ns
ns
ns
CP
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
75
CL
CSB Fall to SCLK Rise Setup
Time
t
60
0
ns
ns
CSS
t
SCLK Rise to CS Rise Hold Time
CSH
SDI Setup Time
SDI Hold Time
t
60
0
ns
ns
DS
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
C
C
= 200pF
= 200pF
200
200
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
t
10
75
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
150
CSW
n
Note 2: Offset is measured at the code that comes closest to 10mV.
Note 3: Accuracy is better than 1 LSB for V = 10mV to V - 180mV. Guaranteed by PSR test on end points.
OUT
DD
Note 4: R = open and digital inputs are either V or DGND.
L
DD
Note 5: INL guaranteed between codes 20 and 4095.
_______________________________________________________________________________________
5
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(MAX5174: V = +5V, V
= 2.5V; MAX5176: V = +3V, V
= +1.25V; C = 100pF, OS = AGND, code = FFF hex,
DD
REF
DD
REF L
T
A
= +25°C, unless otherwise noted.)
MAX5174
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
1.4
1.3
1.2
1.1
1.0
0.9
0.8
290
288
286
284
282
280
278
276
274
272
270
268
330
320
310
300
290
280
270
260
250
240
230
4/MAX5176
-50 -30 -10
10
30
50
70
90
4.4
4.6
4.8
5.0
5.2
5.4
5.6
-50 -30 -10 10
30
50
70
90
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DYNAMIC RESPONSE
OUTPUT VOLTAGE vs. TEMPERATURE
OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX5174/6 toc06
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0970
5V
V
5V/div
CS
4.0968
4.0966
4.0964
4.0962
4.0960
0
4.096V
V
OUT
1V/div
10mV
-50 -30 -10 10
30
50
70
90
2µs/div
10
100
1k
10k
100k
R (Ω)
L
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
-75
REFERENCE FEEDTHROUGH
DYNAMIC RESPONSE
MAX5174/6 toc07
0
V
REF
= 1.8 V + 3.6Vp-p at f = 1kHz
DC
-76
-77
-78
-79
-80
-81
-82
-83
-84
5V
V
CS
0
5V/div
4.096V
V
/V
OUT REF
12.5dB/div
V
OUT
1V/div
10mV
10
100
1k
10k
100k
20
10k
2µs/div
FREQUENCY (Hz)
FREQUENCY (Hz)
6
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5174: V = +5V, V
= 2.5V; MAX5176: V = +3V, V
= +1.25V; C = 100pF, OS = AGND, code = FFF hex,
DD
REF
DD
REF L
T
A
= +25°C, unless otherwise noted.)
MAX5174
FFT PLOT
DIGITAL FEEDTHROUGH
MAJOR-CARRY TRANSITION
MAX5174/6 toc12
MAX5174/6 toc11
0
V
REF
= 1.25V + 1.13Vp-p at f = 10kHz
DC
V
OUT
V
CS
2mV/div
V/div
AC-COUPLED
V
/V
OUT REF
12.5dB/div
V
SCLK
V
OUT
5V/div
100mV/div
20
100k
400ns/div
5µs/div
FREQUENCY (Hz)
START-UP GLITCH
REFERENCE INPUT FREQUENCY RESPONSE
MAX5174/6 toc14
5
V
1V/div
0
-5
DD
-10
-15
-20
-25
V
OUT
10mV/div
AC-COUPLED
V
REF
= 0.67Vp-p + 1.5V
DC
5Oms/div
0
500 1000 1500 2000 2500 3000
FREQUENCY (kHz)
MAX5176
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
300
295
290
285
280
275
270
265
260
255
250
295
290
285
280
275
270
265
260
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
SUPPLY VOLTAGE (V)
-50 -30 -10 10
30
50
70
90
-50 -30 -10 10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5174: V = +5V, V
= 2.5V; MAX5176: V = +3V, V
= +1.25V; C = 100pF, OS = AGND, code = FFF hex,
DD
REF
DD
REF L
T
A
= +25°C, unless otherwise noted.)
MAX5176
OUTPUT VOLTAGE vs. LOAD RESISTANCE
OUTPUT VOLTAGE vs. TEMPERATURE
DYNAMIC RESPONSE
MAX5174/6 toc20
2.5
2.0
1.5
1.0
0.5
0
2.0490
2.0488
2.0486
2.0484
2.0482
2.0480
3V
V
3V/div
CS
0
2.048V
V
OUT
500mV/div
10mV
4/MAX5176
-0.5
10
100
1k
R (Ω)
10k
100k
-50 -30 -10 10
30
50
70
90
2µs/div
L
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
DYNAMIC RESPONSE
REFERENCE FEEDTHROUGH
MAX5174/6 toc21
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
0
V
REF
= 0.8V + 1.6Vp-p at f = 1kHz
DC
3V
V
3V/div
CS
0
2.048V
V
/V
OUT REF
12.5dB/div
V
OUT
500mV/div
10mV
20
10k
2µs/div
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
MAJOR-CARRY TRANSITION
FFT PLOT
MAX5174/6 toc25
0
V
REF
= 0.9V + 0.424Vp-p at f = 10kHz
DC
CS
2V/div
V
/V
OUT REF
12.5dB/div
OUT
100mV/div
20
100k
5µs/div
FREQUENCY (Hz)
AC-COUPLED
8
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5174: V = +5V, V
= 2.5V; MAX5176: V = +3V, V
= +1.25V; C = 100pF, OS = AGND, code = FFF hex,
DD
REF
DD
REF L
T
A
= +25°C, unless otherwise noted.)
MAX5176
REFERENCE INPUT
FREQUENCY RESPONSE
DIGITAL FEEDTHROUGH (SCLK, OUT)
START-UP GLITCH
MAX5174/6 toc26
MAX5174/6 toc28
5
0
V
DD
SCLK
1V/div
2V/div
-5
-10
-15
-20
-25
-30
V
OUT
OUT
500µV/div
10mV/div
V
REF
= 0.67Vp-p + 0.75V
DC
0
500 1000 1500 2000 2500 3000
FREQUENCY (kHz)
2µs/div
50ms/div
AC-COUPLED
AC-COUPLED
P in De s c rip t io n
PIN
1
NAME
OS
FUNCTION
Offset Adjustment. Connect to AGND for no offset.
Voltage Output. High impedance when in shutdown. The output voltage is limited to V
2
OUT
.
DD
Reset Mode Select (digital input). Connect to V to select midscale reset output voltage. Connect to
DD
DGND to select 0 reset output voltage.
3
4
RS
Power-Down Lockout. (digital input). Connect to V to allow shutdown. Connect to DGND to disable
DD
software and hardware shutdown.
PDL
5
6
Clear DAC. (digital input) Clears the DAC to either zero or midscale as determined by RS.
Chip-Select Input (digital input). DIN ignored when CS is high.
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
Serial Clock Input (digital input).
CLR
CS
7
DIN
8
SCLK
DGND
DOUT
UPO
9
Digital Ground
10
11
Serial-Data Output
User-Programmable Output. State is set by the serial input.
Shutdown (digital input). Pulling SHDN high when PDL = V places the chip in shutdown with a maximum
shutdown current of 10µA.
DD
12
SHDN
13
14
15
16
AGND
REF
Analog Ground
Reference Input. Maximum V
is V - 1.4V.
DD
REF
N.C.
No Connection
V
DD
Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.
_______________________________________________________________________________________
9
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
De t a ile d De s c rip t io n
OS_
The MAX5174/MAX5176 12-bit, serial, voltage-output
DACs op e ra te with a 3-wire s e ria l inte rfa c e . The s e
devices include a 16-bit shift register and a double-
buffered input composed of an input register and a
DAC register (see Functional Diagram). In addition,
these devices employ a rail-to-rail output amplifier and
inte rna l trimme d re s is tors to p rovid e a g a in of
+1.638V/V, maximizing the output voltage swing. The
MAX5174/MAX5176’s offset adjust pin allows for a DC
shift in DAC outputs. The DACs are designed with an
inverted R-2R ladder network (Figure 1) that produces
a weighted voltage proportional to the reference volt-
age.
R
R
OUT_
R
R
R
2R
D0
2R
D9
2R
D10
2R
D11
2R
REF_
AGND
Re fe re n c e In p u t s
The reference input accepts both AC and DC values
SHOWN FOR ALL 1s ON DAC
with a voltage range extending from 0 to V
The following equation represents the resulting output
voltage:
- 1.4V.
DD
Figure 1. Simplified DAC Circuit Diagram
4/MAX5176
reloading the DAC register from the shift register, by
simultaneously loading the input and DAC registers, or
by toggling PDL. When returning from shutdown wait
40µs for the output to settle.
V
N
Gain
REF
V
=
OUT
4096
Power-Down Lockout
Power-down lockout disables the software/hardware
shutdown mode. A high-to-low transition on PDL brings
the device out of shutdown and returns the output to its
previous state.
where N is the numeric value of the DAC’s binary input
code (0 to 4095), V is the reference voltage, and
Gain is the internally set voltage gain (1.638V/V if OS =
REF
AGND). The maximum output voltage is V . The refer-
DD
ence pin has a minimum impedance of 18kΩ and is
code dependent.
Shutdown
Pulling SHDN hig h while PDL is hig h p la c e s the
MAX5174/MAX5176 in shutdown. Pulling SHDN low will
not return the device to normal operation. A high-to-low
transition on PDL or an appropriate command from the
serial data line (see Table 1 for commands) is required
to exit shutdown.
Ou t p u t Am p lifie r
With OS c onne c te d to AGND, the outp ut a mp lifie r
employs an internal trimmed resistor-divider, setting the
gain to 1.638V/V and minimizing gain error. The output
amplifier has a typical slew rate of 0.6V/µs, and settles
to ±0.5LSB from a full-scale transition within 18µs when
loaded with 5kΩ in parallel with 100pF. Loads less than
2kΩ d e g ra d e p e rforma nc e . For a lte rna tive outp ut
amplifier setups, refer to the Applications Information
section.
S e ria l-In t e rfa c e
The MAX5174/MAX5176 3-wire serial interface is com-
patible with SPI and QSPI (Figure 2), and MICROWIRE
(Figure 3) interface standards. The 16-bit serial input
word consists of two control bits, 12 bits of data (MSB
to LSB), and two sub-bits.
S h u t d o w n Mo d e
The MAX5174/MAX5176 feature a software- and hard-
ware-programmable shutdown mode that reduces the
typical supply current to 1µA. Enter shutdown by writing
the appropriate input-control word as shown in Table 1
or by using the hardware shutdown. In shutdown mode,
the reference input and amplifier output both become
hig h imp e d a nc e , a nd the s e ria l inte rfa c e re ma ins
active. Data in the input register is saved, allowing the
MAX5174/MAX5176 to re c a ll the p rior outp ut s ta te
when returning to normal operation. Exit shutdown by
The control bits determine the MAX5174/MAX5176’s
re s p ons e a s outline d in Ta b le 1. The MAX5174/
MAX5176’s digital inputs are double buffered, which
allows any of the following:
• Loading the input register without updating the DAC
register.
• Updating the DAC register from the input register.
• Updating the input and DAC registers simultaneously.
10 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
The MAX5174/MAX5176 accepts one 16-bit packet or
+5V
two 8-b it p a c ke ts s e nt while CS re ma ins low. The
MAX5174/MAX5176 allow the following to be config-
ured:
• Clock edge on which serial data output (DOUT) is
SS
clocked.
• State of the user-programmable logic output.
DIN
MOSI
SCK
• Configuration of the reset state.
SPI/QSPI
PORT
Sp e c ific c omma nd s for s e tting the s e a re s hown in
Table 1.
MAX5174
MAX5176
SCLK
The general timing diagram in Figure 4 illustrates how
CS
I/O
the MAX5174/MAX5176 acquires data. CS must go low
at least t
before the rising edge of the serial clock
CSS
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for the MAX5174 a nd 6MHz for the MAX5176. Se e
Figure 5 for a detailed timing diagram of the serial inter-
face.
CPOL = 0, CPHA = 0
Figure 2. Connections for SPI and QSPI Standards
S e ria l Da t a Ou t p u t (DOUT)
The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
SK
SO
I/O
SCLK
DIN
CS
MICROWIRE
PORT
MAX5174
MAX5176
Figure 3. Connections for MICROWIRE
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
S1, S0
FUNCTION
C1
C0
D11..................D0
0
0
12-bit DAC data
0 0
0 0
Load input register; DAC registers are unchanged.
Load input register; DAC registers are updated (start-up DAC with
new data).
0
1
1
0
12-bit DAC data
xxxxxxxxxxxx
Update DAC register from input register (start-up DAC with data
previously stored in the input registers).
xx
1
1
1
1
1
1
1
1
1
1
1
1
0 0 x x xxxx xxxx
0 1 x x xxxx xxxx
1 0 0 x xxxx xxxx
1 0 1 x xxxx xxxx
1 1 0 x xxxx xxxx
1 1 1 x xxxx xxxx
xx
xx
xx
xx
xx
xx
No operation (NOP).
Shut down DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
______________________________________________________________________________________ 11
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
D3 D2 D1 D0 S2 S1 S0
C1
DIN
C2
C0 D9 D8 D7 D6 D5
D4
Figure 4. Serial-Interface Timing Diagram
t
CSW
CS
t
t
CSS
CSO
t
CSH
4/MAX5176
t
CS1
SCLK
t
t
CL
CH
t
CP
DIN
t
DS
t
DH
t
t
D02
D01
DOUT
Figure 5. Detailed Serial-Interface Timing Diagram
Table 2 lists the codes for unipolar output voltages. The
Us e r-P ro g ra m m a b le Lo g ic Ou t p u t (UP O)
The user-programmable logic output (UPO) allows con-
trol of an external device through the serial interface,
thereby reducing the number of microcontroller I/O pins
required. During power-down, this output will retain its
digital state prior to shutdown. When CLR is pulled low,
UPO will reset to its programmed default state. See
Table 1 for specific commands to control the UPO.
output voltage is limited to V . Use the OS pin to intro-
DD
d uc e a n offs e t volta g e a s s hown in Fig ure 7 a nd
described in the Offset and Buffer Configurations section.
Bip o la r Ou t p u t
Figure 8 shows the MAX5174/MAX5176 configured for
bipolar output operation. The output voltage is given by
the following equation (OS = AGND):
Re s e t (RS ) a n d Cle a r (CLR)
The MAX5174/MAX5176 offers a clear pin (CLR), which
resets the output voltage. If RS = DGND, then CLR
2
N
V
= V
− 1
OUT
REF
4096
resets the output voltage to 0. If RS = V , then CLR
DD
where N represents the numeric value of the DAC’s
binary input code and V is the voltage of the exter-
nal reference. Table 3 shows digital codes and the cor-
responding output voltage for Figure 8’s circuit.
resets the output voltage to mid-scale. In either case,
CLR will reset UPO to its programmed default state.
REF
Ap p lic a t io n s In fo rm a t io n
Un ip o la r Ou t p u t
Figure 6 shows the MAX5174/MAX5176 configured for
unipolar, rail-to-rail operation with a gain of 1.638V/V.
12 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
Offs e t a n d Bu ffe r Co n fig u ra t io n s
The simple circuit of Figure 7 illustrates how to intro-
duce an offset to the output voltage. The amount of off-
OS
+5V/+3V
REF
set introduced by a voltage at the OS pin is shown in
the following equation:
V
DD
V
= V · (1- Gain)
OS
OFFSET
MAX5174
MAX5176
where Gain = 1.638.
However, the total output voltage of the device cannot
DAC
OUT
exceed V , regardless of the voltage on the OS pin.
DD
AGND
DGND
To set the gain of the output amplifier to 1, connect OS
to OUT.
Da is y-Ch a in in g De vic e s
The s e ria l-d a ta outp ut p in (DOUT) a llows multip le
MAX5174/MAX5176s to be daisy-chained together as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs. The disadvan-
tage is that it takes n commands to program the DACs.
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
OS
+5V/+3V
Figure 10 shows several MAX5174/MAX5176s sharing
one common DIN signal line. In this configuration the
data bus is common to all devices; however, more I/O
lines are required because each device needs a dedi-
cated CS line. The advantage of this configuration is
that only one command is needed to program any DAC.
REF
V
OS
V
DD
MAX5174
MAX5176
DAC
OUT
Table 2. Unipolar Code Table
(Circuit of Figure 6)
AGND
DGND
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
11 1111 1111 11 (00)
+V
(4095/4096) · 1.638
(2049/4096) · 1.638
(2048/4096) · 1.638
(2047/4096) · 1.638
(1/4096) · 1.638
REF
10 0000 0000 01 (00)
10 0000 0000 00 (00)
01 1111 1111 11 (00)
00 0000 0000 01 (00)
00 0000 0000 00 (00)
+V
Figure 7. Setting OS for Output Offset
REF
+V
REF
+V
REF
+V
REF
+5V/+3V
REF
10k
10k
V+
0
OS
V
DD
Table 3. Bipolar Code Table
(Circuit of Figure 8)
MAX5174
MAX5176
DAC CONTENTS
V
OUT
ANALOG OUTPUT
MSB
LSB
DAC
OUT
11 1111 1111 11 (00)
+V
[(2 · 4095/4096) - 1]
[(2 · 2049/4096) - 1]
[(2 · 2048/4096) - 1]
[(2 · 2047/4096) - 1]
REF
V-
10 0000 0000 01 (00)
10 0000 0000 00 (00)
01 1111 1111 11 (00)
00 0000 0000 01 (00)
00 0000 0000 00 00
+V
REF
DGND
AGND
+V
REF
+V
REF
TOLERANCES: 10kΩ ±0.1%
+V
[(2 · 1/4096) - 1]
REF
-V
REF
Figure 8. Bipolar Output Circuit
________________________________________________________________________________________13
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
pins together and connecting that point to the system
Us in g a n AC Re fe re n c e
The MAX5174/MAX5176 accept references with AC
components, as long as the reference voltage remains
analog ground plane. This is useful because if the
DAC’s DGND is c onne c te d to the s ys te m d ig ita l
ground, digital noise may infiltrate the DAC’s analog
portion.
between 0 and V
- 1.4V. Figure 11 shows a tech-
DD
nique for applying a sine-wave signal to the reference
input where the AC signal is offset before being applied
to REF. The re fe re nc e volta g e mus t re ma in a b ove
AGND.
Bypass the power supply with a 4.7µF capacitor in par-
allel with a 0.1µF capacitor to AGND. Minimize capaci-
tor le a d le ng ths to re d uc e ind uc ta nc e . If nois e
becomes an issue, use shielding and/or ferrite beads to
increase isolation.
P o w e r-S u p p ly a n d La yo u t Co n s id e ra t io n s
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect
the two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
tog e the r a t the IC. The b e s t g round c onne c tion is
achieved by connecting the DAC’s DGND and AGND
To maintain INL and DNL performance as well as gain
drift, it is extremely important to provide the lowest pos-
sible reference output impedance at the DAC reference
input pin. INL degrades if the series resistance on REF
pin exceeds 0.1Ω. The same consideration must be
made for the AGND pin.
4/MAX5176
SCLK
SCLK
SCLK
MAX5174
MAX5176
MAX5174
MAX5176
MAX5174
MAX5176
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 9. Daisy-Chaining MAX5174/MAX5175 Devices
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5174
MAX5176
SCLK
MAX5174
MAX5176
SCLK
MAX5174
MAX5176
SCLK
DIN
DIN
DIN
Figure 10. Multiple MAX5174/MAX5176s Sharing Common DIN and SCLK Lines
14 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
4/MAX5176
+5V/
+3V
Ch ip In fo rm a t io n
+5V/+3V
TRANSISTOR COUNT: 3457
R
1
AC
MAX495
REFERENCE
INPUT
R
2
V
DD
REF
500mVp-p
OS
OUT
DAC
MAX5174
MAX5176
AGND
GND
Figure 11. AC Reference Input Circuit
Fu n c t io n a l Dia g ra m
V
DD
CS DIN SCLK
AGND DGND
PDL
DOUT
SERIAL
16-BIT
CONTROL
SHIFT REGISTER
SHDN
LOGIC
UPO
OS
OUTPUT
RS
DECODE
CONTROL
CLR
INPUT
REGISTER
DAC
REGISTER
DAC
REF
OUT
MAX5174
MAX5176
______________________________________________________________________________________ 15
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs
w it h Vo lt a g e Ou t p u t
P a c k a g e In fo rm a t io n
4/MAX5176
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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