MAX5175AEEE+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 12us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX5175AEEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 12us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1477; Rev 0; 4/99
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX5175/MAX5177 low-power, serial, voltage-out-
put, 12-bit digital-to-analog converters (DACs) feature a
precision output amplifier in a space-saving 16-pin
QSOP package. The MAX5175 operates from a single
+5V supply, and the MAX5177 operates from a single
+3V supply. The output amplifier’s inverting input is
available to allow specific gain configurations, remote
sensing, and high output current capability. This makes
the MAX5175/MAX5177 ideal for a wide range of appli-
c a tions , inc lud ing ind us tria l p roc e s s c ontrol. Both
d e vic e s d ra w only 260µA of s up p ly c urre nt, whic h
reduces to 1µA in shutdown mode. In addition, the pro-
grammable power-up reset feature allows for a user-
selectable output voltage state of either 0 or midscale.
♦ ±1 LSB INL
♦ 1µA Shutdown Current
♦ “Glitch Free” Output Voltage at Power-Up
♦ Single-Supply Operation
+5V (MAX5175)
+3V (MAX5177)
♦ Full-Scale Output Range
+2.048V (MAX5177, V
+4.096V (MAX5175, V
= +1.25V)
= +2.5V)
REF
REF
®
♦ Rail-to-Rail Output Amplifier
♦ Adjustable Output Offset
♦ Low THD (-80dB) in Multiplying Operation
The 3-wire serial interface is compatible with SPI™,
QSPI™, and MICROWIRE™ standards. An input register
followed by a DAC register provides a double-buffered
input, allowing the registers to be updated independent-
ly or simultaneously with a 16-bit serial word. Additional
features include software and hardware shutdown, shut-
down lockout, a hardware reset pin, and a reference
input capable of accepting DC and offset AC signals.
These devices provide a programmable digital output
pin for added functionality and a serial-data output pin
for daisy-chaining. All logic inputs are TTL/CMOS com-
patible and are internally buffered with Schmitt triggers
to allow direct interfacing to optocouplers.
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial Interface
♦ Programmable Shutdown Mode and Power-Up
Reset (0 or midscale)
♦ Buffered Output Capable of Driving 4–20mA or
5kΩ || 100pF Loads
♦ User-Programmable Digital Output Pin Allows
Serial Control of External Components
♦ 14-Bit Upgrades Available (MAX5171/MAX5173)
The MAX5175/MAX5177 incorporate a proprietary on-chip
circuit that keeps the output voltage virtually “glitch free,”
limiting the glitches to a few millivolts during power-up.
Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
Both devices come in 16-pin QSOP packages and are
specified for the extended (-40°C to +85°C) temperature
range. The MAX5171/MAX5173 are 14-bit pin-compatible
upgrades to the MAX5175/MAX5177. For pin-compatible
DACs with a n inte rna l re fe re nc e , s e e the 13-b it
MAX5132/MAX5133 and 12-bit MAX5122/MAX5123.
MAX5175AEEE
MAX5175BEEE
MAX5177AEEE
MAX5177BEEE
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
-40°C to +85°C 16 QSOP
±1
±2
±2
±4
P in Co n fig u ra t io n
Ap p lic a t io n s
Digitally Programmable 4–20mA Current Loops
Industrial Process Controls
TOP VIEW
FB
OUT
RS
1
2
3
4
5
6
7
8
16 V
DD
15 N.C.
Digital Offset and Gain Adjustment
Motion Control
14 REF
PDL
CLR
CS
MAX5175
MAX5177
13 AGND
12 SHDN
11 UPO
10 DOUT
Automatic Test Equipment (ATE)
Remote Industrial Controls
µP-Controlled Systems
DIN
Functional Diagram appears at end of data sheet.
SCLK
9 DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND...............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
16-Pin QSOP (derate 8mW/°C above +70°C)...............667mW
Operating Temperature Range .............................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DOUT, UPO to DGND ................................-0.3V to (V + 0.3V)
DD
FB, OUT REF to AGND...............................-0.3V to (V + 0.3V)
DD
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5175
(V = +5V ±10%, V
= 2.5V, AGND = DGND, FB = OUT, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
/MAX517
12
Bits
MAX5175A
MAX5175B
±1
±2
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
±1
LSB
mV
V
OS
±10
±4
R
R
= ∞
-0.6
-1.6
10
LSB
L
L
Gain Error
GE
= 5kΩ
±8
Power-Supply Rejection Ratio
Output Noise Voltage
PSRR
120
µV/V
LSBp-p
nV/√Hz
f = 100kHz
1
Output Thermal Noise Density
REFERENCE INPUT
50
Reference Input Range
V
REF
0
V
DD
- 1.4
V
Reference Input Resistance
R
18
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
V
= 0.5Vp-p + 2.5V , slew-rate limited
350
-84
kHz
dB
REF
DC
V
= 3.6Vp-p + 1.8V , f = 1kHz,
DC
REF
Reference Feedthrough
code = all 0s
Signal-to-Noise Plus Distortion
Ratio
V
REF
code = FFF hex
= 1.4Vp-p + 2.5V , f = 10kHz,
DC
SINAD
84
dB
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
3
V
V
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
I
IN
V
= 0 or V
IN DD
C
IN
V
OH
I
= 2mA
V - 0.5
DD
V
V
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
2
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
ELECTRICAL CHARACTERISTICS—MAX5175 (continued)
(V = +5V ±10%, V
= 2.5V, AGND = DGND, FB = OUT, R = 5kΩ, C = 100pF referenced to ground, T = T
to T , unless
MAX
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SR
0.6
12
V/µs
µs
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
Current into FB
0
V
V
DD
-0.1
0
40
1
0.1
µA
µs
Time Required to Exit Shutdown
Digital Feedthrough
nV-s
CS = V ; f
= 100kHz, V
= 5Vp-p
DD
SCLK
SCLK
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current (Note 4)
Shutdown Current (Note 4)
TIMING CHARACTERISTICS
SCLK Clock Period
V
4.5
5.5
0.35
10
V
DD
I
DD
0.26
1
mA
µA
t
CP
100
40
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise Setup
Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise Hold
Time
t
CSH
SDI Setup Time
SDI Hold Time
t
40
0
ns
ns
DS
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
CS1
t
t
100
CSW
_______________________________________________________________________________________
3
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
ELECTRICAL CHARACTERISTICS—MAX5177
(V = +2.7V to +3.6V, V
= 1.25V, AGND = DGND, FB = OUT, R = 5kΩ, C = 100pF referenced to ground, T = T
to T
,
DD
REF
L
L
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
MAX5177A
MAX5177B
±2
±4
Integral Nonlinearity (Note 5)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
DNL
±1
LSB
mV
V
OS
±10
±4
R
R
= ∞
-0.6
-1.6
10
LSB
L
L
Gain Error
GE
= 5kΩ
±8
Power-Supply Rejection Ratio
Output Noise Voltage
PSRR
120
µV/V
LSBp-p
nV/√Hz
f = 100kHz
2
Output Thermal Noise Density
REFERENCE
50
/MAX517
Reference Input Range
Reference Input Resistance
V
0
V
DD
- 1.4
V
REF
R
18
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
V
= 0.5Vp-p + 1.25V , slew-rate limited
350
-84
kHz
dB
REF
DC
V
= 1.6Vp-p + 0.8V , f = 1kHz,
DC
REF
Reference Feedthrough
code = all 0s
Signal-to-Noise Plus Distortion
Ratio
V
REF
code = FFF hex
= 0.9Vp-p + 1.25V , f = 10kHz,
DC
SINAD
78
dB
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.2
V
V
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
I
IN
V
= 0 or V
IN DD
C
IN
V
OH
I
= 2mA
V - 0.5
DD
V
V
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
4
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
ELECTRICAL CHARACTERISTICS—MAX5177 (continued)
(V = +2.7V to +3.6V, V
= 1.25V, AGND = DGND, FB = OUT, R = 5kΩ, C = 100pF referenced to ground, T = T
to T
,
DD
REF
L
L
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SR
0.6
12
V/µs
µs
To ±0.5LSB, from 10mV to full-scale
Output Voltage Swing (Note 3)
Current into FB
0
V
V
DD
-0.1
0
0.1
µA
µs
Time Required to Exit Shutdown
40
CS = V , DIN = 50kHz, f
= 100kHz,
DD
SCLK
Digital Feedthrough
1
nV-s
V
SCLK
= 3Vp-p
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current (Note 4)
Shutdown Current (Note 4)
TIMING CHARACTERISTICS
SCLK Clock Period
V
2.7
3.6
0.35
10
V
DD
I
DD
0.26
1
mA
µA
t
CP
150
75
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
75
CL
CS Fall to SCLK Rise Setup
Time
t
60
0
ns
ns
CSS
SCLK Rise to CS Rise Hold
Time
t
CSH
SDI Setup Time
SDI Hold Time
t
60
0
ns
ns
DS
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
t
C
C
= 200pF
= 200pF
200
200
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
10
75
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
CS1
t
t
150
CSW
Note 1: INL guaranteed between codes 16 and 4095.
Note 2: Offset is measured at the code that comes closest to 10mV.
Note 3: Accuracy is better than 1LSB for V = 10mV to V - 180mV. Guaranteed by PSR test on end points.
OUT
DD
Note 4: R = open and digital inputs are either V or DGND.
L
DD
Note 5: INL guaranteed between codes 32 and 4095.
_______________________________________________________________________________________
5
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(MAX5175: V = +5V, V
= 2.5V; MAX5177: V = +3V, V
= 1.25V; C = 100pF, FB = OUT, code = FFF hex, T = +25°C,
DD
REF
DD
REF
L
A
unless otherwise noted.)
MAX5175
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
310
300
290
280
270
260
250
240
230
220
210
1.4
1.3
1.2
1.1
1.0
0.9
0.8
266
264
262
260
258
256
254
252
250
248
/MAX517
4.4
4.6
4.8
5.0
5.2
5.4
5.6
-50 -30 -10 10
30
50
70
90
-50 -30 -10 10
30
50
70
90
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
DYNAMIC RESPONSE
OUTPUT VOLTAGE vs. TEMPERATURE
OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX5175-06
2.49950
2.49946
2.49942
2.49938
2.49934
2.49930
3.0
2.5
2.0
1.5
1.0
0.5
0
5V
0
V
(5V/div)
CS
2.5V
V
OUT
(1V/div)
10mV
-50 -30 -10 10
30
50
70
90
10
100
1k
R (Ω)
10k
100k
2µs/div
TEMPERATURE (°C)
L
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
DYNAMIC RESPONSE
REFERENCE FEEDTHROUGH
MAX5175-07
-78
-80
-82
-84
-86
-88
-90
-92
0
V
REF
= 1.8V + 3.6Vp-p at f = 1kHz
DC
5V
0
V
(5V/div)
V
/V
CS
OUT REF
(12.5dB/div)
2.5V
V
OUT
(1V/div)
10mV
10
100
1k
10k
100k
2µs/div
20
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
6
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5175: V = +5V, V
= 2.5V; MAX5177: V = +3V, V
= 1.25V; C = 100pF, FB = OUT, code = FFF hex, T = +25°C,
DD
REF
DD
REF
L
A
unless otherwise noted.)
MAX5175
FFT PLOT
MAJOR-CARRY TRANSITION
DIGITAL FEEDTHROUGH
MAX5175-11
MAX5175-12
0
V
REF
= 2.5 V + 1.414Vp-p at f = 10kHz
DC
V
/V
OUT REF
V
CS
(2V/div)
(12.5dB/div)
V
OUT
(2mV/div)
V
OUT
(100mV/div)
V/SCLK
(5V/div)
20
100k
400ns/div
FREQUENCY (Hz)
AC-COUPLED
START-UP GLITCH
REFERENCE INPUT FREQUENCY RESPONSE
MAX5175-14
0
-5
V
DD
(1V/div)
-10
-15
-20
-25
V
OUT
(10mV/div)
V
REF
= 0.67Vp-p + 1.25V
DC
50ms/div
0
500 1000 1500 2000 2500 3000
FREQUENCY (kHz)
AC-COUPLED
MAX5177
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
280
275
270
265
260
255
250
245
240
235
230
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
268
266
264
262
260
258
256
254
252
-50 -30 -10 10
30
50
70
90
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
SUPPLY VOLTAGE (V)
-50 -30 -10 10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5175: V = +5V, V
= 2.5V; MAX5177: V = +3V, V
= 1.25V; C = 100pF, FB = OUT, code = FFF hex, T = +25°C,
DD
REF
DD
REF
L
A
unless otherwise noted.)
MAX5177
OUTPUT VOLTAGE vs. TEMPERATURE
OUTPUT VOLTAGE vs. RESISTANCE LOAD
DYNAMIC RESPONSE
MAX5175-20
1.24980
1.24970
1.24960
1.24950
1.24940
1.24930
1.4
3V
0
1.2
1.0
0.8
0.6
0.4
0.2
V
CS
(3V/div)
1.25V
10mV
V
OUT
(500mV/div)
0
-50 -30 -10 10
30
50
70
90
5
10
100
1k
R (Ω)
10k
100k
2µs/div
TEMPERATURE (°C)
L
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
REFERENCE FEEDTHROUGH
DYNAMIC RESPONSE
MAX5175-21
-72
-74
-76
-78
-80
-82
-84
-86
-88
0
3V
0
V
= 0.8V + 1.6Vp-p at f = 1kHz
REF DC
V
(3V/div)
V
/V
CS
OUT REF
(12.5dB/div)
1.25V
10mV
V
OUT
(500mV/div)
20
10k
10
100
1k
10k
100k
2µs/div
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT PLOT
MAJOR-CARRY TRANSITION
DIGITAL FEEDTHROUGH (SCLK, OUT)
0
V
REF
= 1.5V + 0.848V at f = 10kHz
DC p-p
V
CS
SCLK
(2V/div)
(2V/div)
V
/V
OUT REF
(12.5dB/div)
V
OUT
OUT
(100mV/div)
(500µV/div)
20
100k
5µs/div
2µs/div
FREQUENCY (Hz)
AC-COUPLED
AC-COUPLED
8
_______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(MAX5175: V = +5V, V
= 2.5V; MAX5177: V = +3V, V
= 1.25V; C = 100pF, FB = OUT, code = FFF hex, T = +25°C,
DD
REF
DD
REF L A
unless otherwise noted.)
MAX5177
REFERENCE INPUT FREQUENCY RESPONSE
START-UP GLITCH
MAX5175-28
0
-5
V
DD
(1V/div)
-10
-15
-20
-25
V
OUT
(10mV/div)
AC-COUPLED
V
REF
= 0.67Vp-p + 1.25V
DC
0
500 1000 1500 2000 2500 3000
FREQUENCY (kHz)
50ms/div
P in De s c rip t io n
PIN
1
NAME
FB
FUNCTION
Feedback Input
2
OUT
Voltage Output. High impedance in shutdown. Output voltage is limited to V
.
DD
Reset Mode Select (digital input). Connect to V to select midscale reset output value. Connect to DGND
DD
to select 0 reset output value.
3
4
RS
Power-Down Lockout (digital input). Connect to V to allow shutdown. Connect to DGND to disable shut-
DD
down.
PDL
5
6
Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS.
Chip-Select Input (digital input). DIN is ignored when CS is high.
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
Serial Clock Input (digital input)
CLR
CS
7
DIN
8
SCLK
DGND
DOUT
UPO
9
Digital Ground
10
11
Serial-Data Output
User-Programmable Output. State is set by the serial input.
Shutdown (digital input). Pulling SHDN high when PDL = V places the chip in shutdown with a maximum
shutdown current of 10µA.
DD
12
SHDN
13
14
15
16
AGND
REF
Analog Ground
Reference Input. Maximum V
is V - 1.4V.
DD
REF
N.C.
No Connect
V
DD
Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.
_______________________________________________________________________________________
9
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
De t a ile d De s c rip t io n
FB
The MAX5175/MAX5177 12-bit, serial, voltage-output
DACs op e ra te with a 3-wire s e ria l inte rfa c e . The s e
devices include a 16-bit shift register and a double-
OUT
R
R
R
buffered input composed of an input register and a
DAC register (see Functional Diagram). In addition, the
negative terminal of the output amplifier is available.
The DACs are designed with an inverted R-2R ladder
network (Figure 1) that produces a weighted voltage
proportional to the reference voltage.
2R
2R
2R
2R
MSB
2R
REF
Re fe re n c e In p u t s
The reference input accepts both AC and DC values with
AGND
a voltage range extending from 0 to V - 1.4V. The fol-
DD
lowing equation represents the resulting output voltage:
SHOWN FOR ALL 1s ON DAC
V
N
GAIN
Figure 1. Simplified DAC Circuit Diagram
REF
V
=
OUT
4096
/MAX517
Power-Down Lockout
Power-down lockout disables the software/hardware
shutdown mode. A high-to-low transition on PDL brings
the device out of shutdown, returning the output to its
previous state.
where N is the numeric value of the DAC’s binary input
code (0 to 4095), V is the reference voltage, and
Gain is the externally set voltage gain. The maximum
REF
output voltage is V . The reference pin has a mini-
DD
mum impedance of 18kΩ and is code dependent.
Shutdown
Pulling SHDN hig h while PDL is hig h p la c e s the
MAX5175/MAX5177 in shutdown. Pulling SHDN low does
not take the device out of shutdown. A high-to-low transi-
tion on PDL or an appropriate command from the serial
data line (see Table 1 for commands) is required to exit
shutdown.
Ou t p u t Am p lifie r
The MAX5175/MAX5177’s DAC outp ut is inte rna lly
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
input provides flexibility in output gain setting and sig-
nal conditioning (see Applications Information).
The output amplifier settles to ±0.5LSB from a full-scale
transition within 12µs, when loaded with 5kΩ in parallel
with 100p F. Loa d s le s s tha n 2kΩ d e g ra d e p e rfor-
mance.
S e ria l In t e rfa c e
The 3-wire serial interface is compatible with SPI, QSPI
(Figure 2), and MICROWIRE (Figure 3) interface stan-
dards. The 16-bit serial input word consists of two con-
trol bits, 12 bits of data (MSB to LSB), and two sub-bits.
S h u t d o w n Mo d e
The MAX5175/MAX5177 feature a software- and hard-
ware-programmable shutdown mode that reduces the
typical supply current to 1µA. Enter shutdown by writing
the appropriate input-control word as shown in Table 1
or by using the hardware shutdown function. In shut-
down mode, the reference input and the amplifier out-
put become high impedance and the serial interface
remains active. Data in the input register is saved,
allowing the MAX5175/MAX5177 to recall the prior out-
put state when returning to normal operation. Exit shut-
d own b y re loa d ing the DAC re g is te r from the s hift
register, by simultaneously loading the input and DAC
registers, or by toggling PDL. When returning from
shutdown, wait 40µs for the output to settle.
The control bits determine the MAX5175/MAX5177’s
response as outlined in Table 1. The digital inputs are
double buffered, which allows any of the following:
•
Loading the input register without updating the DAC
register
•
•
Updating the DAC register from the input register
Updating the input and DAC registers simultaneously.
10 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
The MAX5175/MAX5177 accept one 16-bit packet or
The general timing diagram in Figure 4 illustrates how
two 8-b it p a c ke ts s e nt while CS re ma ins low. The
devices allow the following to be configured:
the MAX5175/MAX5177 acquire data. CS must go low
at least t
before the rising edge of the serial clock
CSS
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for the MAX5175 a nd 6MHz for the MAX5177. Se e
Figure 5 for a detailed timing diagram of the serial inter-
face.
•
Clock edge on which serial data output (DOUT) is
clocked out
•
•
State of the user-programmable logic output
Reset state.
Sp e c ific c omma nd s for s e tting the s e a re s hown in
Table 1.
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
C1
C0
D11..................D0
S1, S0
0
0
12-bit DAC data
00
Load input register; DAC registers are unchanged.
Load input register; DAC registers are updated (start up DAC with
new data).
0
1
1
0
12-bit DAC data
xxxx xxxx xxxx
00
xx
Update DAC register from input register (start up DAC with data
previously stored in the input registers).
1
1
1
1
1
1
1
1
1
1
1
1
0 0 x x xxxx xxxx
0 1 x x xxxx xxxx
1 0 0 x xxxx xxxx
1 0 1 x xxxx xxxx
1 1 0 x xxxx xxxx
1 1 1 x xxxx xxxx
xx
xx
xx
xx
xx
xx
No operation (NOP).
Shut down DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
+5V
SS
DIN
MOSI
SCLK
DIN
SK
SO
SPI/QSPI
PORT
MICROWIRE
PORT
MAX5175
MAX5177
MAX5175
MAX5177
SCLK
CS
SCK
I/O
CS
I/O
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 0
Figure 2. Connections for SPI/QSPI Standards
Figure 3. Connections for MICROWIRE
______________________________________________________________________________________ 11
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
D3 D2 D1 D0 S2 S1 S0
C1
DIN
C2
C0 D9 D8 D7 D6 D5
D4
Figure 4. Serial-Interface Timing Diagram
t
CSW
CS
/MAX517
t
t
CSS
CSO
t
CSH
t
CS1
SCLK
t
t
CL
CH
t
CP
DIN
t
DS
t
DH
t
t
D02
D01
DOUT
Figure 5. Detailed Serial-Interface Timing Diagram
S e ria l-Da t a Ou t p u t (DOUT)
The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
Whe n CLR is p ulle d low, UPO will re s e t to its p ro-
grammed default state. See Table 1 for specific com-
mands to control the UPO.
CLR
Re s e t (RS ) a n d Cle a r (
)
The MAX5175/MAX5177 offers a clear pin (CLR) which
resets the output voltage. If RST = DGND, then CLR
resets the output voltage to the minimum voltage (0 if
no offset is introduced). If RST = V , then CLR resets
DD
the output voltage to midscale. In either case, CLR will
reset UPO to its programmed default state.
Us e r-P ro g ra m m a b le Lo g ic Ou t p u t (UP O)
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
microcontroller I/O pins required. During power-down,
this output will retain its digital state prior to shutdown.
12 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
where N represents the numeric value of the DAC’s
Ap p lic a t io n s In fo rm a t io n
binary input code and V
is the voltage of the exter-
REF
Un ip o la r Ou t p u t
Figure 6 shows the MAX5175/MAX5177 configured for
unipolar, rail-to-rail operation with a gain of +2V/V.
Table 2 lists the codes for unipolar output voltages. The
nal reference. Table 3 shows digital codes and the cor-
responding output voltage for Figure 7’s circuit.
Da is y-Ch a in in g De vic e s
The s e ria l d a ta outp ut p in (DOUT) a llows multip le
MAX5175/MAX5177s to be daisy-chained together as
shown in Figure 8. The advantage of this is that only
two lines are needed to control all of the DACs on the
line. The disadvantage is that it takes n commands to
program the DACs. Figure 9 shows several MAX5175/
MAX5177s sharing one common DIN signal line. In this
configuration the data bus is common to all devices;
however, more I/O lines are required because each
device needs a dedicated CS line. The advantage of
this configuration is that only one command is needed
to program any DAC.
output voltage is limited to V
.
DD
Bip o la r Ou t p u t
Figure 7 shows the MAX5175/MAX5177 configured for
bipolar output operation. The output voltage is given by
the following equation (FB = OUT):
2N
V
= V
− 1
OUT
REF
4096
10k
10k
REF
MAX5175
MAX5177
+5V/+3.3V
+5V/+3.3V
REF
V
DD
V+
V
DD
FB
10k
10k
OUT
FB
V
OUT
DAC
DAC
OUT
V-
GND
MAX5175
MAX5177
R1 = R2 = 10kΩ ± 0.1%
GND
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
Figure 7. Bipolar Output Circuit
Table 2. Unipolar Code Table (Circuit of
Figure 6)
Table 3. Bipolar Code Table (Circuit of
Figure 7)
DAC CONTENTS
ANALOG OUTPUT
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
MSB
LSB
11 1111 1111 11 (00)
+V
[(2 · 4095/4096) - 1]
[(2 · 2049/4096) - 1]
[(2 · 2048/4096) - 1]
[(2 · 2047/4096) - 1]
REF
11 1111 1111 11 (00)
2 · V
(4095/4096)
(2049/4096)
(2048/4096)
(2047/4096)
REF
10 0000 0000 01 (00)
10 0000 0000 00 (00)
01 1111 1111 11 (00)
00 0000 0000 01 (00)
00 0000 0000 00 (00)
+V
REF
10 0000 0000 01 (00)
10 0000 0000 00 (00)
01 1111 1111 11 (00)
00 0000 0000 01 (00)
00 0000 0000 00 (00)
2 · V
REF
+V
REF
2 · V
REF
+V
REF
2 · V
REF
+V
[(2 · 1/4096) - 1]
REF
2 · V
(1/4096)
REF
-V
REF
0
______________________________________________________________________________________ 13
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
SCLK
SCLK
SCLK
MAX5175
MAX5177
MAX5175
MAX5177
MAX5175
MAX5177
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
/MAX517
Figure 8. Daisy-Chaining MAX5175/MAX5177s
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5175
MAX5177
MAX5175
MAX5177
MAX5175
MAX5177
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 9. Multiple MAX5175/MAX5177s Sharing Common DIN and SCLK Lines
14 ______________________________________________________________________________________
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
/MAX517
power-supply source. Connect DGND and AGND pins
tog e the r a t the IC. The b e s t g round c onne c tion is
achieved by connecting the DAC’s DGND and AGND
pins together and connecting that point to the system
analog ground plane. If the DAC’s DGND is connected
to the system digital ground, digital noise may infiltrate
the DAC’s analog portion.
Us in g a n AC Re fe re n c e
The MAX5175/MAX5177 accept reference voltages
containing AC components, as long as the reference
voltage remains between 0 and V
- 1.4V. Figure 10
DD
shows a technique for applying a sine-wave signal to
REF. The reference voltage must remain above AGND.
Dig it a lly P ro g ra m m a b le
Cu rre n t S o u rc e
The c irc uit of Fig ure 11 p la c e s a n NPN tra ns is tor
(2N3904 or similar) within the op amp feedback loop to
implement a digitally programmable, unidirectional cur-
rent source. The output current is calculated with the
following equation:
Bypass the power supply with a 4.7µF capacitor in par-
allel with a 0.1µF capacitor to AGND. Minimize capaci-
tor le a d le ng ths to re d uc e ind uc ta nc e . If nois e
becomes an issue, use shielding and/or ferrite beads to
increase isolation.
In order to maintain INL and DNL performance, as well
as gain drift, it is extremely important to provide the
lowest possible reference output impedance at the
DAC reference input pin. INL degrades if the series
resistance on the REF pin exceeds 0.1Ω. The same
consideration must be made for the AGND pin.
V
N
REF
I
=
OUT
R
4096
where N is the numeric value of the DAC’s binary input
code and R is the sense resistor shown in Figure 11.
P o w e r-S u p p ly a n d La yo u t Co n s id e ra t io n s
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect
the two ground planes together at the low-impedance
+5V/
+3.3V
+5V/+3.3V
REF
+5V/+3.3V
R
1
AC
MAX495
REFERENCE
INPUT
V
DD
V
L
MAX5175
MAX5177
I
OUT
DAC
500mVp-p
R
1
OUT
FB
V
DD
REF
2N3904
DAC
OUT
GND
R
MAX5175
MAX5177
GND
Figure 11. Digitally Programmable Current Source
Figure 10. AC Reference Input Circuit
______________________________________________________________________________________ 15
Lo w -P o w e r, S e ria l, 1 2 -Bit DACs w it h
Fo rc e /S e n s e Vo lt a g e Ou t p u t
Fu n c t io n a l Dia g ra m
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 3457
AGND DGND
V
DD
CS
SCLK
DIN
PDL
16-BIT
SHIFT
REGISTER
DOUT
UPO
SERIAL
CONTROL
LOGIC
OUTPUT
SHDN
RS
DECODE
CONTROL
MAX5175
MAX5177
CLR
FB
INPUT
REGISTER REGISTER
DAC
OUT
DAC
REF
/MAX517
P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明